INTEGRATED CIRCUITS DATA SHEET TDA8786; TDA8786A 10-bit analog-to-digital interface for CCD cameras Product specification Supersedes data of 1997 May 20 File under Integrated Circuits, IC02 1997 Nov 17 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras TDA8786; TDA8786A FEATURES GENERAL DESCRIPTION • Correlated Double Sampling (CDS), AGC, soft clipper, pre-blanking, 10-bit ADC and reference regulator included The TDA8786; TDA8786A is a 10-bit analog-to-digital interface for CCD cameras. The device includes a correlated double sampling circuit, AGC, a soft clipper circuit and a low power 10-bit Analog-to-Digital Converter (ADC) together with its reference voltage regulator. • Fully programmable via a 3-wire serial interface • Sampling frequency up to 18 MHz The AGC and soft clipper circuits are controlled by on-chip DACs via a serial interface. • AGC gain from 3.5 to 33.5 dB (in 0.1 dB steps) • Programmable soft clipper for white compression (starting at 40% of the input signal) A 10-bit DAC controls the ADC input clamp level. • Standby mode available for each block for power saving applications (19 mW) A pre-blanking function is also included. An additional DAC is provided for additional system controls; its output voltage range is 1.4 V (p-p) which is available at pin OFDOUT. • 6 dB fixed gain analog output for analog iris control • 8-bit and 10-bit DAC included for analog settings • Low power consumption of only 475 mW (typ.) • 5 V operation and 2.5 to 5 V operation for the digital outputs APPLICATIONS • CCD camera systems. • CDS control pulse: TDA8786 = HIGH; TDA8786A = LOW • TTL compatible inputs, TTL and CMOS compatible outputs. QUICK REFERENCE DATA SYMBOL PARAMETER VCCA VCCD VCCO ICCA ICCD ICCO analog supply voltage digital supply voltage digital outputs supply voltage analog supply current digital supply current digital outputs supply current ADCres Vi(CDS)(p-p) GCDS fCLK(max) AGCdyn Ntot(rms) ADC resolution CDS input voltage (peak-to-peak value) CDS output amplifier gain maximum clock frequency AGC dynamic range total noise from CDS input to ADC output (RMS value) total power consumption Ptot CONDITIONS fCLK = 18 MHz; CL = 20 pF; ramp input gain = 3.5 dB MIN. TYP. MAX. UNIT 4.5 4.5 2.5 − − − 4.75 4.75 2.6 83 16 1 5.5 5.5 5.5 − − − V V V mA mA mA − − − 18 − − 10 400 6 − 30 0.5 − 1200 − − − − bits mV dB MHz dB LSB − 475 − mW ORDERING INFORMATION TYPE NUMBER TDA8786G TDA8786AG 1997 Nov 17 PACKAGE NAME LQFP48 DESCRIPTION plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm 2 VERSION SOT313-2 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras TDA8786; TDA8786A BLOCK DIAGRAM VCCA3 handbook, full pagewidth IN2 47 IN1 DGND2 AGND3 46 48 CDSP2 CDSP1 44 43 45 CLPCDS CLK 42 41 VCCD2 40 39 VCCO OE 38 37 36 TRACKAND-HOLD STGE AGND1 TRACKAND-HOLD TRACKAND-HOLD TRACKAND-HOLD TRACKAND-HOLD CLOCK GENERATOR 35 34 19 CLAMP 5 CLAMP 33 ref2 TDA8786 TDA8786A AMPOUT PBK 32 4 +6 dB 31 2 OUTPUTS BUFFER 10-BIT ADC AGCOUT CLPOPB 7 SOFT CLIPPER 1 30 AGC 1 29 ref1 PBIN VCCA1 8 OPTICAL BLACK CLAMP 9-BIT DAC 28 ADCIN 9 27 10 26 10-BIT DAC 11 8-BIT DAC D7 D6 D5 D4 D3 D2 D1 Vref 13 14 15 VCCA2 DACOUT AGND2 16 VRB 17 VRT 18 23 Fig.1 Block diagram. 21 20 24 SDATA SCLK VCCD1 22 STDBY SEN DEC1 3 3 D0 DGND1 OFDOUT SERIAL INTERFACE REGULATOR CLAMP 12 1997 Nov 17 D8 1 25 CLPADC D9 6 4-BIT DAC PBOUT OGND MGE361 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras TDA8786; TDA8786A PINNING SYMBOL PIN DESCRIPTION CLPOPB 1 optical black clamp control pulse input (active HIGH for TDA8786, active LOW for TDA8786A) PBK 2 pre-blanking control pulse input; if PBK is HIGH (LOW) the signal is replaced by the optical black level for TDA8786 (TDA8786A) OFDOUT 3 analog output of the additional 8-bit control DAC (controlled via the serial interface) AMPOUT 4 CDS amplifier output (fixed gain = +6 dB) AGND1 5 analog ground 1 VCCA1 6 analog supply voltage 1 AGCOUT 7 AGC and soft clipper amplifier signal output PBIN 8 optical black clamp and pre-blanking block signal input (from AGCOUT via a capacitor) PBOUT 9 optical black clamp and pre-blanking block signal output ADCIN 10 ADC analog signal input (from PBOUT or AGCOUT via a capacitor) CLPADC 11 clamp control input for ADC analog input signal clamp (active HIGH for TDA8786 and active LOW for TDA8786A) Vref 12 ADC input clamp reference voltage (normally connected to pin VRB or DACOUT) DACOUT 13 DAC output for ADC clamp level AGND2 14 analog ground 2 VCCA2 15 analog supply voltage 2 VRB 16 ADC reference voltage (BOTTOM) code 0 VRT 17 ADC reference voltage (TOP) code 1023 DEC1 18 decoupling 1 (decoupled to ground via a capacitor) STGE 19 CDS offset storage SDATA 20 serial data input for the 4 control DACs (9-bit DAC for AGC gain, 4-bit DAC for soft clipper; additional 8-bit DAC for OFD output voltage; 10-bit DAC for ADC clamp level and the stand-by mode per block; see Table 1) SCLK 21 serial clock input for the control DACs and their serial interface; see Table 1 SEN 22 enable input for the serial interface shift register (active when SEN = logic 0); see Table 1 STDBY 23 stand-by control pin (active HIGH); all the output bits are logic 0 when stand-by is enabled VCCD1 24 digital supply voltage 1 DGND1 25 digital ground 1 D0 26 ADC digital output 0 (LSB) D1 27 ADC digital output 1 D2 28 ADC digital output 2 D3 29 ADC digital output 3 D4 30 ADC digital output 4 D5 31 ADC digital output 5 D6 32 ADC digital output 6 D7 33 ADC digital output 7 D8 34 ADC digital output 8 D9 35 ADC digital output 9 (MSB) OGND 36 digital output ground 1997 Nov 17 4 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras SYMBOL VCCO TDA8786; TDA8786A PIN 37 DESCRIPTION digital output supply voltage output enable (LOW: digital outputs active; HIGH: digital outputs high impedance) 39 digital supply voltage 2 DGND2 40 digital ground 2 CLK 41 ADC clock input CLPCDS 42 CDS clamp control input (active HIGH for TDA8786; active LOW for TDA8786A) CDSP1 43 CDS control pulse input 1 (active HIGH for TDA8786; active LOW for TDA8786A) CDSP2 44 CDS control pulse input 2 (active HIGH for TDA8786; active LOW for TDA8786A) 39 VCCD2 analog ground 3 40 DGND2 48 41 CLK AGND3 42 CLPCDS input signal 2 from CCD (usually video channel) 43 CDSP1 47 44 CDSP2 IN2 45 VCCA3 input signal 1 from CCD (usually black channel) 46 IN1 analog supply voltage 3 46 47 IN2 45 IN1 48 AGND3 VCCA3 37 VCCO 38 VCCD2 38 OE OE CLPOPB 1 36 OGND PBK 2 35 D9 OFDOUT 3 34 D8 AMPOUT 4 33 D7 AGND1 5 32 D6 VCCA1 6 AGCOUT 7 PBIN 8 29 D3 PBOUT 9 28 D2 ADCIN 10 27 D1 31 D5 TDA8786 TDA8786A 30 D4 26 D0 CLPADC 11 Vref 12 Fig.2 Pin configuration. 1997 Nov 17 5 VCCD1 24 STDBY 23 SEN 22 SCLK 21 SDATA 20 STGE 19 VRT 17 DEC1 18 VRB 16 VCCA2 15 AGND2 14 DACOUT 13 25 DGND1 MGE360 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras TDA8786; TDA8786A LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCCA analog supply voltage note 1 −0.3 +7.0 V VCCD digital supply voltage note 1 −0.3 +7.0 V VCCO output stages supply voltage note 1 −0.3 +7.0 V ∆VCC supply voltage difference between VCCA and VCCD −1.0 +1.0 V between VCCA and VCCO −1.0 +4.0 V between VCCD and VCCO −1.0 +4.0 V Vi input voltage referenced to VSSA −0.3 +7.0 V VCLK(p-p) AC input voltage for switching (peak-to peak-value) referenced to VSSD − VCCD V Io output current − 10 mA Tstg storage temperature −55 +150 °C Tamb operating ambient temperature −20 +75 °C Tj junction temperature − 150 °C Note 1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 and +7.0 V provided that the supply voltage difference ∆VCC remains as indicated. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 1997 Nov 17 PARAMETER CONDITIONS thermal resistance from junction to ambient in free air 6 VALUE UNIT 76 K/W Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras TDA8786; TDA8786A CHARACTERISTICS VCCA = VCCD = 4.75 V; VCCO = 2.6 V; fCLK = 18 MHz; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VCCA analog supply voltage 4.5 4.75 5.5 V VCCD digital supply voltage 4.5 4.75 5.5 V VCCO digital outputs supply voltage 2.5 2.6 5.5 V ICCA analog supply current − 83 − mA ICCD digital supply current − 16 − mA ICCO digital outputs supply current − 1 − mA CL = 20 pF on all data outputs; ramp input Digital inputs CLOCK INPUT: CLK (REFERENCED TO DGND) VIL LOW-level input voltage 0 − 0.8 V VIH HIGH-level input voltage 2.0 − VCCD V IIL LOW-level input current VCLK = 0.8 V −1 − +1 µA IIH HIGH-level input current VCLK = 2.0 V − − 20 µA Zi input impedance fCLK = 18 MHz − 2 − kΩ Ci input capacitance fCLK = 18 MHz − 2 − pF INPUTS: CDSP1 AND CDSP2 VIL LOW-level input voltage 0 − 0.6 V VIH HIGH-level input voltage 2.2 − VCCD V IIL LOW-level input current VIL = 0.6 V − −100 − µA IIH HIGH-level input current VIH = 2.2 V − 0 − µA INPUTS: SEN, STDBY, CLPCDS, CLPOPB, PBK AND CLPADC VIL LOW-level input voltage 0 − 0.6 V VIH HIGH-level input voltage 2.2 − VCCD V Ii input current −2 − +2 µA INPUTS: SEN, SDATA AND SCLK (see Fig.14) tsu1 SEN set-up time compared to SCLK rising edge − 4 − ns tsu2 SDATA set-up time compared to SCLK rising edge − 4 − ns tsu3 SEN set-up time compared to SCLK falling edge − 4 − ns thd3 SEN hold time compared to SCLK rising edge − 4 − ns thd4 SDATA hold time compared to SCLK rising edge − 4 − ns 1997 Nov 17 7 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras SYMBOL PARAMETER TDA8786; TDA8786A CONDITIONS MIN. TYP. MAX. UNIT Correlated Double Sampling; CDS Vi(CDS)(p-p) CDS input amplitude (peak-to-peak value) − 400 1200 mV ISTGE,IN1,IN2 input current pins 19, 46 and 47 −2 − +2 µA tCDS(min) CDS control pulses minimum active time (HIGH for TDA8786, LOW for TDA8786A) fi(CDS1,2) = fCLK(pix) Vi(CDS)(p-p) = 1200 mV black-to-white transition in one pixel (±1 LSB typ.) 12 − − ns thd1 hold time IN1 compared to control pulse CDSP1 see Fig.15 − 1 − ns thd2 hold time of IN2 compared to control pulse CDSP2 see Fig.15 − −0.5 − ns Amplifier outputs GAMPOUT output amplifier gain − 6 − dB ZAMPOUT output amplifier impedance − 300 − Ω VAMPOUT(p-p) output amplifier dynamic voltage level (peak-to-peak value) − 2.4 − V VAMPOUT(bl) output amplifier black level voltage − 1.1 − V VAGCOUT(p-p) AGC output amplifier dynamic voltage level (peak-to-peak value) − 1800 − mV VAGCOUT AGC output amplifier black level voltage − 1.1 − V ZAGCOUT AGC output amplifier output impedance at 10 kHz − 5 − Ω IAGCOUT AGC output static drive current static − − 1 mA VOPB(p-p) optical black clamp and blanking block output dynamic voltage (peak-to-peak value) − 1.8 − V VOPB optical black clamp and blanking block output black level voltage − 1.4 − V ZOPB optical black clamp and blanking block output impedance at 10 kHz − − 5 Ω IOPB OPB output current drive static − − 1 mA IPBIN input current pin 8 −2 − +2 µA GAGC(min) minimum gain of AGC circuit − 3.5 − dB 1997 Nov 17 AGC DAC input code = 00 (9-bit control) 8 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras SYMBOL PARAMETER TDA8786; TDA8786A CONDITIONS MIN. MAX. UNIT 33.5 − dB − 1.1 − V soft clipper 4-bit control DAC input code = 00 − 40% − VAGCOUT(p-p) V soft clipper 4-bit control DAC input code = 15 − 100% − VAGCOUT(p-p) V soft clipper compression ratio Vi(sc) < Vinflex − 1.0 − Vi(sc) > Vinflex − 0.66 − gmADC ADC clamps transconductance at clamp level − 60 − mS gmPBK PBK clamp transconductance at clamp level − 60 − mS gmCDS CDS clamps transconductance at clamp level − 5.5 − mS VPBIN(clamp) clamp voltage at PBIN input − 1.4 − V GAGC(max) maximum gain of AGC circuit VAGCOUT AGC output amplifier black level voltage Vinflex(p-p) voltage at soft clipper inflexion point (peak-to-peak value) CRsc AGC DAC input − code = ≥319 (9-bit control) TYP. CLAMPS Analog-to-Digital Converter; ADC fCLK(max) maximum clock frequency 18 − − MHz tCPH clock pulse width HIGH 15 − − ns tCPL clock pulse width LOW 15 − − ns SRCLK clock input slew rate (rising and falling edge) 0.5 − − V/ns Vi(ADC)(p-p) ADC input voltage level (peak-to-peak value) − 1.8 − V VRB ADC reference voltage output code 0 − 1.4 − V VRT ADC reference voltage output code 1023 − 3.2 − V IADCIN input current pin 10 −2 − +2 µA ILE integral linearity error fCLK = 18 MHz; ramp input − ±1.0 ±2.0 LSB DLE differential linearity error fCLK = 18 MHz; ramp input td(s) sampling delay time 1997 Nov 17 10 to 90% 9 − ±0.4 ±0.75 LSB − − 5 ns Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras SYMBOL PARAMETER TDA8786; TDA8786A CONDITIONS MIN. TYP. MAX. UNIT Total chain timing (CDS + ADC + SOFT CLIPPER + PRE BLANKING + ADC) td time delay between CDSP1 and CLK 50% at rising edges of CLK and CDSP1: transition full-scale code 0 to code 1023; Vi(CDS)(p-p) = 1200 mV − 40 − ns N(rms) noise (RMS value) gain = 3.5 dB − 0.5 − LSB Digital-to-Analog Converters (OFDOUT DAC) VOFDOUT(p-p) additional 8-bit control DAC (OFD) output voltage (peak-to-peak value) − 1.4 − V VOFDOUT(0) DC output voltage for code 0 − 2.0 − V VOFDOUT(255) DC output voltage for code 255 − 3.4 − V ZOFDOUT additional 8-bit control DAC (OFD) output impedance − 2000 − Ω IOFDOUT OFD output current drive − − 50 µA − 0.9 − V − 1.4 − V static ADC clamp control DAC (see Fig.5) VDACOUT(p-p) ADC clamp 10-bit control DAC output voltage (peak-to-peak value) VDACOUT DC output voltage ZDACOUT ADC clamp control DAC output impedance IDACOUT DAC output current drive OFELOOP maximum offset error of DAC + ADC clamp loop code 0 − 2.3 − V − − 250 Ω static − − 50 µA code 0 − ±5 − LSB code 1023 − ±5 − LSB code 1023 1997 Nov 17 10 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras SYMBOL PARAMETER TDA8786; TDA8786A CONDITIONS MIN. TYP. MAX. UNIT Digital outputs (fCLK = 18 MHz; CL = 20 pF) VOH HIGH-level output voltage IOH = −1 mA VCCO − 0.5 − VCCO V VOL LOW-level output voltage IOL = 1 mA 0 − 0.5 V IOZ output current in 3-state mode 0.5 V < Vo < VCCO −20 − +20 µA to(h) output hold time 5 − − ns to(d) output delay Ci = 20 pF; VCCO = 4.75 V − 12 15 ns Ci = 20 pF; VCCO = 3.15 V − 17 20 ns Ci = 20 pF; VCCO = 2.7 V − 21 24 ns 5 − − MHz Serial interface fSCLK(max) maximum frequency of serial interface MGE365 handbook, halfpage 33.5 GAGC (dB) 3.5 0 319 511 AGC control DAC input code Fig.3 AGC gain as a function of DAC input code. 1997 Nov 17 11 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras TDA8786; TDA8786A handbook, full pagewidth MGE364 AGCOUT control DAC input code = 15 100% control DAC input code = 00 (1) (2) 40% 0 0 40% 100% 130% soft clipper input V (1) -----o- = 1 Vi V (2) -----o- = 0.66 Vi Fig.4 Soft clipper output voltage as a function of soft clipper input voltage. MGE366 handbook, halfpage MGD599 handbook, halfpage 2.3 3.4 ADC CLAMP DAC voltage output (V) OFD DAC voltage output (V) 2.0 1.4 0 1023 ADC CLAMP control DAC input code 0 255 OFD control DAC input code Fig.5 DAC voltage output as a function of DAC input code. 1997 Nov 17 12 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras TDA8786; TDA8786A handbook, full pagewidth 8 × fSC = 2fCLK >12 ns CDSP1 >12 ns CDSP2 MGE370 Fig.6 CCD high band control signal timing (TDA8786). handbook, full pagewidth 8 × fSC = 3fCLK >12 ns CDSP1 >12 ns CDSP2 MGE369 Fig.7 CCD normal band control signal timing (TDA8786). 1997 Nov 17 13 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras TDA8786; TDA8786A handbook, full pagewidth 8 × fSC = 2fCLK CDSP1 >12 ns CDSP2 MGE371 >12 ns Fig.8 CCD high band control signal timing (TDA8786A). handbook, full pagewidth 8 × fSC = 3fCLK CDSP1 >12 ns CDSP2 MGE372 >12 ns Fig.9 CCD normal band control signal timing (TDA8786A). 1997 Nov 17 14 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras TDA8786; TDA8786A IPBIN handbook, halfpage handbook,I halfpage (µA) (µA) 450 350 0 0 1.4 2.85 VPBIN (V) −450 V (V) −350 MBK058 30 mV 200 mV MBK057 Fig.11 Typical clamp currents for pins IN1, IN2 and STGE. Fig.10 Typical PBK clamp current. ADC clamping When pin CLPADC is HIGH (TDA8786) (LOW for TDA8786A), the ADC input is clamped to voltage level Vref. Vref should normally be connected to VRB (ADC reference voltage code 0) or to DACOUT (10-bit DAC output). The DAC is controlled via the serial interface, its output covers the lower half of the ADC input range. IADCIN handbook, halfpage (µA) slope = 1 kΩ 450 Vref 0 VADCIN (V) −450 30 mV 500 mV MBK059 Fig.12 Typical ADC clamp current. 1997 Nov 17 15 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras handbook, full pagewidth TDA8786; TDA8786A SDATA SHIFT REGISTER D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 A0 A1 A2 SCLK LSB MSB 10 LATCH SELECTION SEN 8 (D7 to D0) 9 (D8 to D0) 4 (D3 to D0) 4 (D3 to D0) OFD LATCHES AGC GAIN LATCHES SOFT CLIP LATCHES PARTIAL STANDBY 8-bit DAC AGC control soft clip control standby control 10 (D9 to D0) CLAMP REFERENCE LATCHES 10-bit DAC MGD526 Fig.13 Serial interface block diagram. tsu2 handbook, full pagewidth thd4 MSB SDATA A2 A1 A0 D9 D8 D7 LSB D6 D5 D4 D3 D2 D1 D0 SCLK SEN MGE373 tsu1 thd3 tsu3 tsu = 4 ns (min.); thd3 = thd4 = 4 ns (min.). Fig.14 Loading sequence of control DACs input data via the serial interface. 1997 Nov 17 16 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras Table 1 TDA8786; TDA8786A Serial interface programming (see note 1) ADDRESS BITS DATA BITS D9 to D0 A2 A1 A0 0 0 0 OFDOUT output control (D7 to D0). 0 0 1 Soft clipper control. Only the 4 LSBs (D3 to D0) are used. Bits D9 to D4 should be set to logic 0. 0 1 0 AGC gain control (D8 to D0). 0 1 1 Partial standby controls for power consumption optimization. Only the 4 LSBs (D3 to D0) are used. Bits D9 to D4 should be set to logic 0: D0 = 1: CDS + AGC + soft clipper block in standby; ICCA + ICCD = 48 mA D1 = 1: optical black clamp + blanking block in standby; ICCA + ICCD = 92 mA D2 = 1: OFD DAC in standby; ICCA + ICCD = 98 mA D3 = 1: 6 dB amplifier (output on AMPOUT pin) in standby; ICCA + ICCD = 98.5 mA. 1 0 0 Clamp reference DAC (D9 to D0). Note 1. At the end of each programming sequence (usually during the video vertical blanking), the soft clipper register must be reloaded (for example if the soft clipper is not used, code 15 must be entered in the soft clipper register at the end of each TDA8786(A) programming sequence). Table 2 Standby selection STDBY D9 to D0 ICCA + ICCD 1 LOW 4 mA (typ.) 0 active 99 mA (typ.) 1997 Nov 17 17 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras TDA8786; TDA8786A thd1 handbook, full pagewidth IN1 and IN2 PIXEL N CDSP1 (active HIGH) ,,,,,,, ,,,,, ,, ,,, sample N PIXEL N+1 PIXEL N+2 PIXEL N+3 PIXEL N+4 thd2 CDSP2 (active HIGH) td CLK th DATA OUTPUT D0 to D7 PIXEL N − 4 PIXEL N − 3 PIXEL N − 2 PIXEL N − 1 PIXEL N td (OUT) MGE367 The hatched areas represent active video. Fig.15 Pixel frequency timing diagram. handbook, full pagewidth AGCOUT VIDEO OPTICAL BLACK HORIZONTAL FLYBACK DUMMY VIDEO CLPCDS (active HIGH) CLPOPB (active HIGH) PBK (active HIGH) PREBLANKING OUTPUT VIDEO BLACK LEVEL VIDEO CLPADC (active HIGH) MGE368 Fig.16 Line frequency timing diagram. 1997 Nov 17 18 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras TDA8786; TDA8786A APPLICATION INFORMATION TDA8786 and SAA8110 can be used with Sharp CCDs. TDA8786A and SAA8110 can be used with Sony CCDs. Table 3 gives as an example some references of ICs which may be used with Philips TDA8786(A)/SAA8110. This overview is not restrictive, both devices are compatible with other CCD/V-driver/PPG combinations including the more recent ones. Table 3 Possible components for the application of Figs 17 and 18 NTSC CCD TYPE Sony CCDs COMPONENT TYPE CCD MEDIUM RESOLUTION HIGH RESOLUTION MEDIUM RESOLUTION HIGH RESOLUTION LZ2313H5 LZ2353A LZ2323H5 LZ2363 V-driver Sharp CCDs PAL LR36683N timing generator LZ95G55 LZ95G71 LZ95G55 LZ95G71 CCD ICX056AK ICX068AK ICX057AK ICXo69AK V-driver timing generator CXD1250MN, CXD1267N CXD1257AR CXD1265R CXD1257AR CXD1265R Notes to the application diagram 1. In the configuration of Figs 17 and 18, the microcontroller reads and writes data from/to the DSP using the SNERT-bus (UART mode 0). Optional external control is available via the I2C-bus. 2. Free I/O pins of the microcontroller can be used to control PGG, or for other purposes. 3. 83Cxxx processing is synchronized by VD interruption. Depending on VD polarity, it can be necessary to invert VD. 4. A customized 83Cxxx is available for this application. Please contact your nearest Philips sales office. 1997 Nov 17 19 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras TDA8786; TDA8786A handbook, full pagewidth P0 P0 (optional, PPG setting) P1 P1 (optional, PPG settings) CDACOUT (optional, can be used for frequency tuning) CDACOUT CLK1 (to ADC and DSP) CLK2 CLK2 (to DSP, CLK2 = 2 × CLK1) CDSPULSE1 CDSPULSE1 CDSPULSE2 CDSPULSE2 VERTICAL DRIVER (PPG) analog ground CLAMPCDS CLAMPCDS (CLAMP CDS, OPB, ADC can be the same) CLAMPOPB CLAMPOPB CLAMPADC CLAMPADC PreBlank (optional) PreBlank Horizontal Drive HD (to DSP and µC) Vertical Drive VD (to DSP and µC) V1 H1 H2 CDSPULSE1 CDSPULSE2 OEN (optional) (from microcontroller) 1 µF CLPOPB OFDOUT AGND1 PBIN 5V 220 nF VDDA3 PBOUT ADCIN CLPADC Vref 220 nF VDDD P1.0 10 kΩ P1.1 P1.2 P1.3 OEN (optional) (to ADC) P1.4 P1.5 P1.6/SCL VDDD P1.7/SDA JB JB RST P3.0/RxD P3.1/TxD 1 JB VDDD P3.2/INT0 SDA 2 SCL 3 4 +5 V GND JB 4.7 µF P3.3/INT1 A0/SNDA P3.4/T0 SCL/SNCL P3.5/T1 HD (opt.) FIIN A1/SNRES 18 pF 12 MHz P3.6/WR P3.7/RD XTAL2 XTAL1 VSS 2 44 3 4 5 43 40 39 CLAMPADC (from PPG) 8 38 9 37 10 11 13 14 36 5 SCL 4.7 kΩ P0.4/AD4 P0.6/AD6 VSS 4 EPROM A2 6 PCF8598 3 NC VDDD PTC PCF8594 2 7 4.7 VDD WP kΩ 8 PCF8582 1 SDA P0.3/AD3 P0.5/AD5 DGND2 VCCD2 CLK CLPCDS CDSP1 31 7 30 TDA8786G or TDA8786AG 8 9 29 28 10 27 11 26 12 25 16 30 17 29 VDDD VDDD 100 nF 1 nF 2.2 nF 200 nF 18 28 19 27 20 26 21 25 22 24 P2.7/A15 P2.5/A13 RESET_DSP (to DSP) P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 MGK393 18 pF Fig.17 SAA8110G system configuration for camera application (continued in Fig.18). 1997 Nov 17 D6 D5 D4 D3 D2 D1 D0 DGND1 A B C D E F G H I J K 100 nF L 1 nF P0.7/AD7 P2.6/A14 D7 100 nF 32 31 D8 VDDD 83C54/ 35 EA VDDD 83C654 ALE (OM-XXX) 33 PSEN 15 D9 VDDA1 41 7 32 6 VDDD P0.0/AD0 33 5 1 nF VDD P0.1/AD1 MICRO42 CONTROLLER P0.2/AD2 6 4 DACOUT VD (from PPG) 10 µF ANALOG-TO-DIGITAL INTERFACE OGND 13 14 15 16 17 18 19 20 21 22 23 24 10 kΩ BC848C 34 SEN VDDA2 3 SCLK VDDA1 VCCA1 AGCOUT 35 SDATA 100 nF VDDD 36 2 STGE AMPOUT AMPOUT 48 47 46 45 44 43 42 41 40 39 38 37 DEC1 SMP_CLK (from DSP) VDDA1 100 nF 1 VRT SWITCH MODE POWER SUPPLIES (optional) 5V PBK 100 nF VRB +xxV CDSP2 PreBlank VCCA3 CLAMPOPB IN1 VDDD OFD level (optional) IN2 Reset CCDout VCCA2 Shutter AGND3 H2 AGND2 H1 CCD 5V VDDA1 100 nF V4 V3 V2 V1 −xxV 100 nF VDDA1 VERTICAL DRIVER BUFFER VCCO V2 OE V3 CLAMPCDS Electrical Reset Shutter Pulse STBY V4 CLK1 FI (to DSP and µC) Field Id VCCD1 digital ground CLK1 20 M Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras TDA8786; TDA8786A handbook, full pagewidth 25 24 23 DIGITAL OUTPUT CONNECTOR 26 22 A1/SNRES 20 A0/SNDA 18 SDA 16 14 SCL/SNCL VDDD 12 10 100 nF 8 VDDD 6 optional 4 VDDD 19 17 15 13 11 9 7 5 3 2 1 VDDD UV0 Y6 Y7 VDDD(P2) Y4 Y5 Y2 49 48 47 46 45 UV1 UV2 UV3 UV4 UV5 UV6 UV7 VSSD(P1) LLC CREF/PXQ HREF VSYNCOUT FIOUT CLK2 VDDD(P1) VDDA(BG) RBIAS CLK2 (from PPG) VDDD VDDA3 47 kΩ 100 nF DECOUPL VSSA(BG) 100 nF 42 VDDA(DC) VDDA3 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 100 nF 44 100 nF 43 OUT1 VDDA(O1) 10 nF 50 OUT2 VDDA(O2) CDACOUT SAA8110G OUT3 VDDA(O3) K 51 T0 VSSA(OB) J 52 T1 I 53 T2 H 55 54 RESET F G DIGITAL SIGNAL PROCESSOR SIS E 56 VDDD(C2) D Y3 57 P1 C Y0 4 P0 B Y1 58 CDACRBIAS A A1/SNRES VDDD(C3) VSSD(P2) 3 FIIN 5 VSSD(C1) 6 CCD9 7 CCD8 8 CCD7 9 CCD6 10 CCD5 11 CCD4 12 CCD3 13 CCD2 14 CCD1 15 CCD0 16 VSSD(C2) 17 SCLK 18 VSSA(CD) 19 CDACOUT 20 FI SDA A0/SNDA 59 SMP HSYNCIN HD 60 2 SDATA VSYNCIN VD 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 STROBE CLK1 CLK1 VDDA(CD) VDDD 100 nF V DDD(C1) SCL/SNCL VSSD(C3) XOUT XIN VSSD(C4) 100 nF 21 150 kΩ L(1) L(1) 100 nF 100 nF VDDA3 4 2 7 Y L(1) Green 6 11 7 100 nF 2 L(1) RESET_DSP (from µC) SMP_CLK (to power supply) 68 Ω VDDA3 VDDD L M 1 6 5 1 100 nF VDDA2 3 SVHS L(1) 68 Ω C 12 8 3 13 9 14 4 L(1) 10 5 15 U, Blue P0 P1 VDDD L(1) digital ground L(1) analog ground 68 Ω V, Red L(1) CVBS CVBS-RCA MGK394 (1) Values depend on DSP output configuration. Fig.18 SAA8110G system configuration for camera application (continued from Fig.17). 1997 Nov 17 21 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras TDA8786; TDA8786A PACKAGE OUTLINE LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M pin 1 index θ bp Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 7.1 6.9 0.5 9.15 8.85 9.15 8.85 1.0 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) θ 0.95 0.55 7 0o 0.95 0.55 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 94-12-19 97-08-01 SOT313-2 1997 Nov 17 EUROPEAN PROJECTION 22 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras TDA8786; TDA8786A If wave soldering cannot be avoided, for LQFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Reflow soldering Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering techniques are suitable for all LQFP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Wave soldering Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all LQFP packages with a pitch (e) equal or less than 0.5 mm. 1997 Nov 17 23 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras TDA8786; TDA8786A DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1997 Nov 17 24 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras TDA8786; TDA8786A NOTES 1997 Nov 17 25 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras TDA8786; TDA8786A NOTES 1997 Nov 17 26 Philips Semiconductors Product specification 10-bit analog-to-digital interface for CCD cameras TDA8786; TDA8786A NOTES 1997 Nov 17 27 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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