INTEGRATED CIRCUITS DATA SHEET TDA8043 Satellite Demodulator and Decoder (SDD) Product specification Supersedes data of 1997 Nov 07 File under Integrated Circuits, IC02 1998 Feb 13 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD) TDA8043 FEATURES • One-chip Digital Video Broadcasting (DVB) compliant demodulator and concatenated Viterbi/Reed-Solomon decoder with de-interleaver and de-randomizer • 3.3 V supply voltage (up to 5 V allowed) • Internal clock divider • Reed-Solomon (RS) decoder: • On-chip crystal oscillator – (204, 188 and T = 8) Reed Solomon code • QPSK/BPSK demodulator: – Automatic (I2C-bus configurable) synchronization of bytes, transport packets and frames – Interpolator to handle variable symbol rates without an external anti-aliasing filter – Internal convolutional de-interleaving (I = 12; using internal memory) – On-chip Automatic Gain Control (AGC) of the analog input I and Q baseband signals or tuner AGC control – De-randomizer based on Pseudo Random Binary Sequence (PRBS) – Two on-chip matched Analog-to-Digital Converters (ADCs; 7 bits) – External indication of RS decoder sync lock – Square-Root Raised-Cosine Nyquist filter with programmable roll-off factor – External indication of uncorrectable errors (transport error indicator is set) – High maximum symbol frequency: 32 Msymbols/s – Indication of the number of lost blocks – Can be used at low channel Es/No (Symbol energy-to-noise ratio) – Indication of the number of corrected blocks/bytes. • I2C-bus interface: – Internal carrier recovery, clock recovery and AGC loops with programmable loop filters – I2C-bus interface initializes and monitors the demodulator and Forward Error Correction (FEC) decoder with standby mode; when no I2C-bus is used, default mode is defined – Two carrier recovery loops enabling phase tracking of the incoming symbols – Different modulation schemes: Quadrature Phase Shift Keying (QPSK) and Binary-Phase Shift Keying (BPSK) – 4-bit I/O expander for flexible access to and from the I2C-bus – I2C-bus configurable interrupt pin – Signal-to-noise ratio (S/N) estimation – Standby mode for reduced power consumption. – External indication of demodulator lock. • Package: QFP100 • Viterbi decoder: • Boundary scan test. – Rate 1⁄2 convolutional code based – Constraint length K = 7 with G1 = 171oct and G2 = 133oct APPLICATIONS • Demodulation and FEC for digital satellite TV. – Supported puncturing code rates: 1⁄2, 2⁄3, 3⁄4, 4⁄5, 5⁄6, 6⁄ , 7⁄ and 8⁄ 7 8 9 – 4 bits ‘soft decision’ inputs for both I and Q – Truncation length: 144 – Automatic synchronization to correct puncturing rate and spectral inversion – Channel Bit Error Rate (BER) estimation from 10−2 to 10−8 – External indication of Viterbi synchronization lock – Differential decoding supported. 1998 Feb 13 2 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD) TDA8043 For evaluation purposes, the output can also be used to monitor internal data, for example I/Q after demodulation. GENERAL DESCRIPTION This document specifies a DVB compliant demodulator and forward error correction decoder IC for reception of QPSK and BPSK modulated signals for satellite applications. The SDD requires a single clock frequency which is independent of the received symbol rate, providing the clock frequency is slightly higher than twice the highest symbol frequency. The TDA8043 can handle variable symbol rates without adapting the analog filters within the tuner. Typical applications for this device are: All loops to recover the data from the received symbols are internal. No external loop components are required. Loop parameters for the clock, carrier recovery and AGC can be controlled via the I2C-bus. • Single Carrier Per Channel (SCPC): two or more QPSK or BPSK modulated signals in a single satellite channel (transponder) The Forward Error Correction (FEC) unit has a built-in state machine to achieve lock without knowing the system parameters (depuncturing rate, spectral inversion, etc.). Once lock is achieved, all necessary parameters can be read via the I2C-bus. By programming these parameters in advance lock can be achieved more quickly. • Multi-Carrier Per Channel (MCPC): one QPSK or BPSK modulated signal in a single satellite channel (transponder) • Simul-cast: QPSK or BPSK modulated signal together with a Frequency Modulated (FM) signal in a single satellite channel. The SDD can be controlled and monitored via the I2C-bus. An I2C-bus default mode is specified which makes it possible to use the device by software control. A 4-bit bidirectional I/O expander and an interrupt line are available. By sending an interrupt signal, the SDD can inform the microcontroller of its internal status (lock). The SDD requires the analog in-phase (I) and quadrature (Q) components as an input and provides 8-bit wide MPEG2 transport packet data at the output. The outputs of the SDD can be directly connected to a descrambler (SAA7206) or a demultiplexer (SAA7205). ORDERING INFORMATION TYPE NUMBER TDA8043H 1998 Feb 13 PACKAGE NAME QFP100 DESCRIPTION plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 × 20 × 2.8 mm 3 VERSION SOT317-2 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD) TDA8043 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDDA analog supply voltage 3.0 3.3 3.6 V VDDD digital supply voltage 3.0 3.3 3.6 V IDD(tot) total supply current 390 − mA fclk clock frequency − − 65 MHz rs symbol rate 0.5 − 32 Msymbols/s α nyquist roll-off (selectable) − 35 or 50 − % IL implementation loss note 3 − 0.3 − dB S/N signal-to-noise ratio for locking the SDD QPSK mode; note 1 2 − − dB Ptot total power dissipation Tamb = 70°C; note 1 − 1285 1650 mW Tstg IC storage temperature −55 − +150 °C Tamb operating ambient temperature Tj operating junction temperature VDDD = 3.3 V; note 1 − note 2 Tamb = 70 °C 0 − 70 °C − − 125 °C Notes 1. These values are specified for a symbol rate of 27.5 Msymbols/s, a puncturing rate of 3⁄4 and a clock frequency of 65 MHz. 2. A range from 3 to 32 Msymbols/s can be achieved with one SAW filter. By using an internal clock divider and reducing the external SAW filter bandwidth, symbol rates down to 0.5 Msymbols/s can be achieved by using a 65 MHz crystal clock. 3. This data was measured in a laboratory environment at a symbol rate of 27.5 Msymbols/s, a clock frequency of 65 MHz, a signal-to-noise ratio of 4.5 dB and including a tuner. PINNING SYMBOL I2 I3 VSSD1 n.c. n.c. I4 I5 I6 Q0 VDDD1 Q1 Q2 Q3 Q4 VSSD2 Q5 Q6 1998 Feb 13 PIN I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 I I − − − I I I I − I I I I − I I DESCRIPTION digital I-input bit 2 (ADC bypass); note 1 digital I-input bit 3 (ADC bypass); note 1 digital ground 1 not connected not connected digital I-input bit 4 (ADC bypass); note 1 digital I-input bit 5 (ADC bypass); note 1 digital I-input bit 6 (ADC bypass: MSB); note 1 digital Q-input bit 0 (ADC bypass: LSB); note 1 digital supply voltage 1 digital Q-input bit 1 (ADC bypass); note 1 digital Q-input bit 2 (ADC bypass); note 1 digital Q-input bit 3 (ADC bypass); note 1 digital Q-input bit 4 (ADC bypass); note 1 digital ground 2 digital Q-input bit 5 (ADC bypass); note 1 digital Q-input bit 6 (ADC bypass: MSB); note 1 4 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD) SYMBOL PIN I/O VSSD3 VDDD2 PRESET P3 P2 P1 P0 VDDD3 n.c. n.c. PDOCLK PDO0 PDO1 PDO2 VSSD4 PDO3 PDO4 PDO5 n.c. n.c. PDO6 n.c. VDDD4 VDDD5 VSSD5 VDDD6 VDDD7 PDO7 n.c. n.c. PDOERR PDOVAL PDOSYNC VSSD6 SCL SDA INT A0 RSLOCK VLOCK DLOCK VDDD8 VDDD9 TEST 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 − − I I/O I/O I/O I/O − − − O O O O − O O O − − O − − − − − − O − − O O O − I I/O O I O O O − − I 1998 Feb 13 TDA8043 DESCRIPTION digital ground 3 digital supply voltage 2 set device into default mode quasi-bidirectional I/O port (bit 3) quasi-bidirectional I/O port (bit 2) quasi-bidirectional I/O port (bit 1) quasi-bidirectional I/O port (bit 0) digital supply voltage 3 not connected not connected output clock for transport stream bytes parallel data output (bit 0) parallel data output (bit 1) parallel data output (bit 2) digital ground 4 parallel data output (bit 3) parallel data output (bit 4) parallel data output (bit 5) not connected not connected parallel data output (bit 6) not connected digital supply voltage 4 digital supply voltage 5 digital ground 5 digital supply voltage 6 digital supply voltage 7 parallel data output (bit 7) not connected not connected transport error indicator data valid indicator transport packet synchronization signal digital ground 6 serial clock of I2C-bus; note 1 serial data of I2C-bus; note 1 interrupt output (active LOW); note 1 I2C hardware address; note 1 Reed-Solomon lock indicator Viterbi lock indicator demodulator lock indicator digital supply voltage 8 digital supply voltage 9 test pin (normally connected to ground); note 1 5 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD) SYMBOL TRST TCK n.c. n.c. VDDD10 VSSD7 VSSD8 TMS TDO TDI VDDD11 VSSD9 VSSD(AD) VDDD(AD) Vref(B) VSSA1 QA Vref(Q) IA VSSA2 Vref(I) VDDA VDDXTAL XTALI XTALO VSSXTAL VDDD12 VDDD13 VSSD10 n.c. n.c. n.c. VAGC n.c. VDDD14 VDDD15 OUTSD I0 I1 PIN I/O 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 I I − − − − − I O I − − − − O − I O I − O − − I O − − − − − − − O − − − O I I DESCRIPTION BST optional asynchronous reset (normally connected to ground); note 1 BST dedicated test clock (normally connected to ground); note 1 not connected not connected digital supply voltage 10 digital ground 7 digital ground 8 BST input control signal (normally connected to ground); note 1 BST serial test data out BST serial test data in (normally connected to ground); note 1 digital supply voltage 11 digital ground 9 digital ground for ADC digital supply for ADC bottom reference voltage for ADC analog ground 1 analog input Q AGC decoupling for Q path analog input I analog ground 2 AGC decoupling for I path analog supply voltage supply voltage for crystal oscillator crystal oscillator input crystal oscillator output ground for crystal oscillator digital supply voltage 12 digital supply voltage 13 digital ground 10 not connected not connected not connected AGC output voltage; note 1 not connected digital supply voltage 14 digital supply voltage 15 general purpose sigma-delta output digital I-input bit 0 (ADC bypass: LSB); note 1 digital I-input bit 1 (ADC bypass); note 1 Note 1. This pin is 5 V tolerant. 1998 Feb 13 TDA8043 6 Philips Semiconductors Product specification 82 Vref(I) 81 VSSA2 84 VDDXTAL 83 VDDA 85 XTALI 86 XTALO TDA8043 88 VDDD12 87 VSSXTAL 90 VSSD10 89 VDDD13 91 n.c. 92 n.c. 94 VAGC 93 n.c. 95 n.c. 98 OUTSD 99 I0 100 I1 handbook, full pagewidth 97 VDDD15 96 VDDD14 Satellite Demodulator and Decoder (SDD) I2 1 80 IA I3 2 79 Vref(Q) VSSD1 3 78 QA n.c. 4 n.c. 5 77 VSSA1 76 Vref(B) I4 6 75 VDDD(AD) I5 7 74 VSSD(AD) I6 8 Q0 9 73 VSSD9 72 VDDD11 VDDD1 10 71 TDI Q1 11 70 TDO Q2 12 69 TMS Q3 13 68 VSSD8 Q4 14 67 VSSD7 VSSD2 15 66 VDDD10 TDA8043H Q5 16 65 n.c. Q6 17 64 n.c. VSSD3 18 63 TCK VDDD2 19 62 TRST PRESET 20 61 TEST P3 21 60 VDDD9 P2 22 59 VDDD8 P1 23 58 DLOCK P0 24 57 VLOCK VDDD3 25 56 RSLOCK n.c. 26 55 A0 n.c. 27 54 INT Fig.1 Pin configuration. 1998 Feb 13 7 PDOSYNC 50 PDOVAL 49 PDOERR 48 n.c. 47 n.c. 46 PDO7 45 VDDD7 44 VDDD6 43 VSSD5 42 VDDD5 41 n.c. 39 VDDD4 40 PDO6 38 n.c. 37 n.c. 36 PDO5 35 PDO4 34 51 VSSD6 PDO3 33 52 SCL PDO1 30 PDO2 31 53 SDA PDO0 29 VSSD4 32 PDOCLK 28 MGM102 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD) TDA8043 APPLICATION INFORMATION handbook, full pagewidth 4-Mbit EPROM MICROCONTROLLER 4-Mbit DRAM 16-Mbit SDRAM data 16 16 8+3 address I TUNER Q TDA8043 (SDD) 8 Ctrl SAA7205 AND SAA7206 I2S-bus 8 Ctrl 27 MHz SAA7201 H, V valid AUDIO DAC YUV H, V CVBS TTX/TTXRQ I2C-bus high speed data CVBS SAA7183 Y/C RGB MGM104 Fig.2 Satellite set-top box concept. 1998 Feb 13 8 L R Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD) TDA8043 handbook, full pagewidth TSA5522 × Vtune SYNTHESIZER switch output TDA8010 ADC SAW × AGC control × AGC DETECTOR TDA8042 TUNER SWITCH XTAL OSCILLATOR ADC ADC I2C-bus AGC QPSK/BPSK DEMODULATOR FORWARD ERROR CORRECTION TDA8043 (SDD) MGM105 data control Note: Control for external AGC is also available using the internal AGC sigma-delta converter (indicated with the dashed line). Fig.3 Application of satellite demodulator and decoder including tuner. 1998 Feb 13 9 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD) VDDD1 L(1) 10 Ω tuner AGC (optional) 15 µF 470 Ω 10 kΩ +5V VDDD2 L(1) 330 nF 15 µF 15 pF (4) C(3) VDDD2 VDDA L 4.7 pF VDDD2 +3.3 V 10 nF 10 nF XTAL(2) handbook, full pagewidth +3.3 V TDA8043 C(3) C(3) 390 kΩ(5) 100 nF n.c. n.c. n.c. n.c. 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 2 79 3 78 4 77 n.c. 5 76 6 75 7 74 8 73 9 72 10 71 TDI 11 70 TDO 12 69 TMS 13 68 14 67 C(3) VDDD1 100 nF 15 VDDD2 C(3) VDDD2 65 VDDD2 64 n.c. 63 TCK 19 62 TRST 20 61 P3 21 60 P2 22 59 P1 23 58 P0 24 57 25 56 n.c. 26 55 n.c. 27 54 28 53 29 52 VDDD1 C(3) 30 C(3) n.c. 18 C(3) packet data and control outputs Q 100 nF 17 VDDD1 100 nF 66 TDA8043H 16 470 kΩ C(3) I 100 nF n.c. VDDD 390 kΩ(5) 100 nF 1 VDDD1 C(3) +5 V 2.2 kΩ 2.2 kΩ 1.6 kΩ interrupt I2C-bus 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 n.c. n.c. n.c. n.c. n.c. C(3) C(3) VDDD1 B = SMD bead type CBD8.9/3/3 Grade 4S2. XTAL = 65 MHz, 3rd overtone. C = 6.8 nF, SMD. L = 560 nH, Taiyo Yuden LAL02. (5) Value specified for a 65 MHz clock. For other clock frequencies, refer to “Application note AN96108”. Fig.4 Application diagram. 1998 Feb 13 10 L(1) VDDA 15 µF VDDD1 packet data and control outputs (1) (2) (3) (4) +3.3 V MGM103 If possible, connect ‘n.c.’ pins to ground to ease power dissipation. TRST, TCK, TMS, and TDI pins can be connected to ground if they are not used. Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD) TDA8043 PACKAGE OUTLINE QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT317-2 c y X 80 A 51 81 50 ZE e E HE A A2 (A 3) A1 θ wM pin 1 index Lp bp L 31 100 detail X 30 1 wM bp e ZD v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 3.20 0.25 0.05 2.90 2.65 0.25 0.40 0.25 0.25 0.14 20.1 19.9 14.1 13.9 0.65 24.2 23.6 18.2 17.6 1.95 1.0 0.6 0.2 0.15 0.1 Z D (1) Z E(1) 0.8 0.4 1.0 0.6 θ o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-02-04 97-08-01 SOT317-2 1998 Feb 13 EUROPEAN PROJECTION 11 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD) If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Reflow soldering Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm. 1998 Feb 13 TDA8043 12 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD) TDA8043 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1998 Feb 13 13 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD) NOTES 1998 Feb 13 14 TDA8043 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD) NOTES 1998 Feb 13 15 TDA8043 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1998 SCA57 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545104/1200/03/pp16 Date of release: 1998 Feb 13 Document order number: 9397 750 03267