PHILIPS UAA3522HL

INTEGRATED CIRCUITS
DATA SHEET
UAA3522HL
Low power dual-band GSM
transceiver with an image rejecting
front-end
Objective specification
File under Integrated Circuits, IC17
2000 Feb 18
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
FEATURES
The input Low Noise Amplifier (LNA) can be switched off
via the bus to allow accurate calibration in the offset
cancellation mode.
• Dual-band application for Global System for Mobile
communication (GSM) and Digital Cellular
communication Systems (DCS)
The transmitter comprises a high precision I/Q modulator
and modulation loop architecture. The I/Q modulator
converts the baseband modulation frequency to the
transmit IF. The modulation loop architecture, which
includes an on-chip offset mixer and phase detector,
controls an external transmit RF VCO which converts the
transmit modulated IF signal to RF.
• Low noise and wide dynamic range single Intermediate
Frequency (IF) transceiver
• More than 30 dB on-chip image rejection in the receiver
• More than 60 dB gain control range
• I/Q demodulator with high performance integrated
baseband channel filter
A receive RF VCO provides the Local Oscillator (LO)
signal to the image rejection mixers in the RF receiver. An
IF VCO provides the LO signal to the I/Q demodulator and
I/Q modulator in the receiver and transmitter sections
respectively.
• High precision I/Q modulator
• Transmit modulation loop architecture including offset
mixer and phase detector
• Dual Phase-Locked Loop (PLL) with on-chip IF Voltage
Controlled Oscillator (VCO)
The frequencies of the RF VCO and the IF VCO are set by
internal PLL circuits, which are programmable via the
3-wire serial bus. The RF and IF PLL comparison
frequencies are 200 kHz and 1 MHz respectively, derived
from a 13 MHz reference signal which has to be supplied
externally. The quadrature RF LO signals required by the
image rejection mixers are obtained using on-chip
Resistor Capacitor (RC) networks. The quadrature IF LO
signals required by the I/Q modulator and I/Q demodulator
are obtained by dividing the frequency of the IF VCO
signal.
• Fully differential design minimizing cross-talk and spurii
• 3-wire serial bus interface
• Functional down to 2.7 V and up to 3.3 V
• LQFP48 package.
APPLICATIONS
• GSM 900 MHz hand-held transceiver
• GSM/DCS dual-band solution with the UAA2077CM
(down to 3.2 V) or UAA2077TS/D (down to 2.7 V).
The IC can be powered on in either receiver (RX),
transmitter (TX) or synthesizer (SYN) operating mode
depending on the logic level at pins RXON, TXON and
SYNON, respectively. Alternatively, an operating mode
can be selected by software using the 3-wire serial
programming bus. In RX or TX mode, only those sections
of the IC which are required are switched on.
GENERAL DESCRIPTION
The UAA3522HL integrates the receiver and most of the
transmitter section of a GSM hand-held transceiver. It also
integrates the receiver IF and the transmitter section of a
DCS transceiver.
The GSM or DCS band is selected by the 3-wire serial
programming bus. When activating RX mode for DCS
applications, the receiver RF section can be disabled by
software so that only the receiver IF section is
powered-on.
The receiver comprises an RF and an IF section. The RF
(GSM) front-end amplifies the aerial signal, converts the
chosen channel frequency to an IF of 200 MHz, and also
provides more than 30 dB of image suppression. Some
selectivity is provided at this stage by an off-chip bandpass
pre-filter. The IF section further amplifies the chosen
channel, maintains the gain at the required level,
demodulates the signal into I and Q components, and
provides channel selectivity at a baseband stage using a
high performance integrated low-pass filter. The IF gain
can be varied over a range of more than 60 dB. The offset
at the I and Q outputs can be cancelled out by software
using the 3-wire serial programming bus.
2000 Feb 18
UAA3522HL
The SYN mode is used to power-on the synthesizer prior
to activating the RX or TX mode. In SYN mode, some
internal LO buffers are also powered-on to minimize the
‘pulling’ effect of the VCO when either the receiver or the
transmitter are switched on.
2
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
fi(RF)(RX)
GSM band RF input frequency in RX mode
925
−
960
MHz
fo(RF)(TX)(GSM)
GSM band RF output frequency in TX mode
880
−
915
MHz
fo(RF)(TX)(DCS)
DCS band RF output frequency in TX mode
1710
−
1785
MHz
fIF
IF frequency in all modes
−
200
−
MHz
ORDERING INFORMATION
TYPE
NUMBER
UAA3522HL
2000 Feb 18
PACKAGE
NAME
LQFP48
DESCRIPTION
plastic low profile quad flat package; 48 leads; body
7 × 7 × 1.4 mm
3
VERSION
SOT313-2
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+
PHASE
SHIFTER
BALUN
0°
ADDER
×
SAW
UAA2077XM
46, 47
×
925 to 960 MHz
×
90°
41,
42
BALUN
8, 9
PHASE 90°
SHIFTER
+
PHASE
SHIFTER
0°
4, 5
I
0°
IF VCO
400 MHz
×
ADDER
×
2, 3 Q
B
A
S
E
B
A
N
D
90°
÷2
DIVIDER &
PHASE
SHIFTER
13,
14
IF VCO
XTAL
4
UAA3522HL
DCS RF
RX VCO
1510 to 1680
MHz
GSM RF
RX VCO
1080 to 1160
MHz
RX/TX
SWITCH
880 to 915 MHz
GSM BAND
IF PHASE/
FREQUENCY
DETECTOR
PROGRAMMABLE
DIVIDER
26
RF PHASE/
FREQUENCY
DETECTOR
CHARGE
PUMP
DIVIDER
÷5
DIVIDER
÷13
×
ADDER
GSM TX RF VCO
880 to 915 MHz
23
REF OSC.
13 MHz
×
90°
2, 3 Q
44, 45
DCS TX RF VCO
1710 to 1785 MHz
FCA004
Fig.1 Block diagram.
Objective specification
CHARGE
PUMP
4, 5 I
I
N
T
E
R
F
A
C
E
UAA3522HL
1710 to 1785 MHz
POWER
DCS BAND
AMPLIFIER
+
PHASE
DETECTOR
0°
A
U
D
I
O
CHARGE 16
PUMP
×
38, 39
35
&
PROGRAMMABLE
DIVIDER
30, 31
Philips Semiconductors
90°
Low power dual-band GSM transceiver
with an image rejecting front-end
PHASE 90°
SHIFTER
BLOCK DIAGRAM
1805 to1880 MHz
handbook, full pagewidth
2000 Feb 18
×
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
PINNING
SYMBOL
UAA3522HL
SYMBOL
PIN
DESCRIPTION
PIN
DESCRIPTION
VCCCPRF
25
RF charge pump and phase
detector supply voltage
VCCIF1
1
IF section of RF receiver supply
voltage 1
CPORF
26
RF charge pump output
QA
2
Q path A baseband input/output
GNDCP
27
RF charge pump ground
QB
3
Q path B baseband input/output
SYNON
28
SYN mode control pin
IA
4
I path A baseband input/output
VCCRFLO
29
RF LO section supply voltage
IB
5
I path B baseband input/output
RFLOC
30
LO signal input from RF VCO
REFAGC
6
AGC reference resistor
RFLOE
31
LO signal input from RF VCO
GNDIF2
7
I/Q modulator and I/Q demodulator
ground 2
GNDRFLO
32
RF LO section ground
RXON
33
RX mode control pin
RXIIFA
8
RX IF input A to AGC amplifier
GNDPHD
34
RXIIFB
9
RX IF input B to AGC amplifier
transmit modulation loop charge
pump ground
VCCIF2
10
I/Q modulator and I/Q demodulator
supply voltage 2
PHDOUT
35
charge pump output
VCCPHD
36
TXON
11
TX mode control pin
transmit modulation loop charge
pump supply voltage
VCCIFLO
12
IF LO supply voltage
RESEXT
37
IFLOC
13
IF LO signal input from
IF VCO resonator
reference resistor for transmit
modulation loop
TXIRFA
38
TX RF VCO signal input
IFLOE
14
IF LO signal input from
IF VCO resonator
TXIRFB
39
TX RF VCO signal input
VCCRF
40
GNDIFLO
15
IF LO ground
RF receiver and transmit
modulation loop supply voltage
CPOIF
16
IF charge pump output
RXIRFA
41
RF receiver input A
GNDCPIF
17
IF charge pump and phase
detector ground
RXIRFB
42
RF receiver input B
GNDRF
43
VCCCPIF
18
IF charge pump and phase
detector supply voltage
RF receiver and transmit
modulation loop ground
TXIFA
44
transmit IF external filter A
EN
19
serial programming bus enable
control pin
TXIFB
45
transmit IF external filter B
DATA
20
serial programming bus data input
RXOIFA
46
receiver IF output A
CLK
21
serial programming bus clock input
RXOIFB
47
receiver IF output B
GNDSYN
22
synthesizer ground
GNDIF1
48
IF section of RF receiver ground 1
REFIN
23
13 MHz reference input
VCCSYN
24
synthesizer supply voltage
2000 Feb 18
5
Philips Semiconductors
Objective specification
37 RESEXT
38 TXIRFA
39 TXIRFB
40 VCCRF
UAA3522HL
41 RXIRFA
42 RXIRFB
43 GNDRF
44 TXIFA
45 TXIFB
46 RXOIFA
48 GNDIF1
handbook, full pagewidth
47 RXOIFB
Low power dual-band GSM transceiver
with an image rejecting front-end
VCCIF1
1
36 VCCPHD
QA
2
35 PHDOUT
QB
3
34 GNDPHD
IA
4
33 RXON
IB
5
32 GNDRFLO
REFAGC
6
31 RFLOE
UAA3522HL
GNDIF2
7
30 RFLOC
RXIIFA
8
29 VCCRFLO
RXIIFB
9
28 SYNON
VCCIF2 10
27 GNDCP
TXON 11
26 CPORF
VCCIFLO 12
Fig.2 Pin configuration.
2000 Feb 18
6
VCCSYN 24
REFIN 23
GNDSYN 22
CLK 21
DATA 20
EN 19
VCCCPIF 18
GNDCPIF 17
CPOIF 16
GNDIFLO 15
IFLOE 14
IFLOC 13
25 VCCPRF
FCA043
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
FUNCTIONAL DESCRIPTION
UAA3522HL
The phase detector output transfers the modulation of the
I/Q IF signal to the off-chip transmit RF VCO making the
analog PLL act as a tracking filter. A PLL of at least
third-order is needed to meet noise requirements at
20 MHz offset from the carrier.
RF receiver
The receiver front-end converts the aerial RF signal, in the
GSM band (925 to 960 MHz), to an IF signal of
approximately 200 MHz. The first stage of the receiver is a
symmetrical LNA that is matched to 50 Ω by an external
balun. The LNA is followed by an image rejection mixer
which suppresses the image by more than 30 dB.
It comprises two mixers in parallel driven by 0° and 90°
quadrature LO signals respectively. The IF signal from
one mixer is shifted by 90° with respect to the IF signal
from the other mixer, then both signals are added together
to cancel out the image signal. The resultant IF signal is
fed to the output via a high output impedance
open-collector stage which drives an external Surface
Acoustical Wave (SAW) filter which selects the required
channel.
RF and IF LO sections
The active components required for the design of a low
noise IF VCO are provided on-chip. Pins IFLOC and
IFLOE connect the on-chip IF VCO components to an
external resonator and feedback circuit.
A divider and phase shifter divides the frequency of the
IF VCO signal by 2 and splits it into two signals having
phases of respectively 0° and 90° which are both fed to the
I/Q modulator and to the I/Q demodulator. The IF VCO
frequency is twice the IF to suppress the effects of
self-mixing and parasitic VCO modulation.
I/Q demodulator
Pins TXIRFA and TXIRFAB connect an external receive
RF VCO module to the on-chip RF LO section. This
section includes a RC phase shifter which splits the
RF VCO signal into two signals having phases of
respectively 0° and 90° which are both fed to the RX
image rejection mixer.
The signal from the SAW filter enters the I/Q demodulator
section. In addition to I/Q demodulation, this section
performs Automatic Gain Control (AGC) over a range of
60 dB to maintain a constant output level irrespective of
the antenna input level, and also applies additional
channel selectivity at the baseband stage using an
integrated high-order low-pass filter.
Dual PLL
An on-chip high performance dual PLL synthesizes the
frequencies of the receive RF VCO and IF VCO signals.
Very low close-in phase noise is achieved which provides
a wide PLL bandwidth with a short settling time.
The AGC amplifier output can be adjusted for a static
offset of less than 50 mV. Its design prevents the offset
from varying by more than ±5 mV. To allow a more
accurate offset calibration, the RF LNA can be switched off
to ensure that no IF signal is present at the AGC amplifier
input during the offset measurement.
A dual programmable divider chain reduces the frequency
of the receive RF and IF LO signals to 200 kHz and 1 MHz
respectively. A digital phase/frequency detector compares
their phases to a reference signal derived from an external
13 MHz clock signal. Phase error information is fed back
to both VCOs via the dual charge pump circuit which
adjusts the phase of each VCO signal by either ‘sinking’
current into, or ‘sourcing’ current from, its loop filter
capacitor, phase locking both RF and IF loops. The very
low leakage current of the dual charge pump circuit
ensures that any spurii are negligible.
I/Q modulator
Baseband I and Q signals are applied to the I/Q modulator
which shifts the modulation spectrum up to the transmit IF.
The I/Q modulator is designed for low harmonic distortion,
low carrier leakage and high image rejection to keep the
phase error as small as possible. Its IF output is loaded by
an integrated low-pass filter and by an external
LC tuned-circuit to prevent unwanted spurii from entering
the phase detector in the transmit modulation loop.
Operating modes
BASIC OPERATING MODES
Transmit modulation loop
The circuit can be powered on in one of four operating
modes in which different parts of the device are enabled or
disabled. The four operating modes are called Idle, RX,
TX and SYN, and are selected by the hardware control
voltage level applied to pins RXON, TXON and SYNON.
The analog transmit modulation loop comprises an on-chip
offset mixer and simple phase detector in switching mode
(triangular transfer function) forming an analog PLL with
an off-chip loop filter and transmit RF VCO.
2000 Feb 18
7
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
Table 2
The synthesizer, receiver and transmitter cannot all be on
at the same time. Table 1 shows which parts of the device
are enabled (on) or disabled (off) in each mode.
Table 1
UAA3522HL
Bit LNA status
BIT LNA STATUS
POWER STATUS OF BIT
LNA
0
off
1
on
Operating modes
POWER STATUS
MODE
SYNTHESIZER RECEIVER TRANSMITTER
Idle
off
off
off
SYN
on
off
off
RX
on
on
off
TX
on
off
on
Table 3
The synthesizer includes the oscillators and LO buffers
common to the receive and transmit sections. The receiver
includes the RF section and the I/Q demodulator. When
the receiver is on, the LNA can be switched off to allow
DC offset compensation to be performed. The RF section
can also be switched off for DCS applications. See Section
“Receiver power status control”.
BIT RF STATUS
POWER STATUS OF
RECEIVER RF SECTION
IN RX MODE
1
on (GSM)
0
off (DCS)
Programming
SERIAL PROGRAMMING BUS
A simple 3-wire unidirectional serial bus is used for
programming the IC. The lines are called DATA, CLK
and EN (enable). Programming data is sent to the IC in
bursts which are separated from each other by EN.
Programming clock edges are ignored until EN goes
active LOW. The data is loaded into the addressed register
when EN returns inactive HIGH, and when the CLK is in
either state, without affecting the data in the register.
The register only holds the last 18 bits that are serially
clocked into the IC.
RECEIVER POWER STATUS CONTROL
• DC offset compensation: This feature allows the DC
offset of the receiver output to be set accurately. When
the receiver is on, the LNA can be switched off to isolate
the antenna input from the I/Q demodulator input.
The offset at the I and Q outputs can be independently
reduced to less than 50 mV by adequately programming
two 5-bit data registers, see Table 4 “Register bit
allocation”. The LNA is switched on or off by the status
of bit LNA (see Table 2).
Additional leading bits are ignored, and no check is made
on the number of clock pulses received. The fully static
CMOS design uses virtually no current when the bus is
inactive. It can always accept new programming data even
when both synthesizers are powered-off.
• Disabling RF section: For DCS applications, the RF
section can be disabled in RX mode. The same
IF circuits are used for both GSM and DCS applications
to avoid duplication. For DCS applications using the
UAA2077XM, for example, the RF section of the
UAA3522HL does not have to be powered on.
The RF section is enabled or disabled by the status of
bit RF when the RX mode is activated (see Table 3).
2000 Feb 18
Bit RF status
DATA FORMAT
Data is loaded into the register with the most significant bit
(MSB) first. The first 14 bits are data, while the last 4 bits
are the register address. The address bits are decoded on
the rising edge of EN. This internally generates a load
pulse to store the data in the addressed register.
To ensure that data loads correctly after the device has
powered-up, EN should be held LOW and only taken HIGH
after the appropriate register has been loaded.
The EN pulse is inhibited during the period when data is
read by the frequency dividers to prevent divider ratio data
from being read incorrectly. This state is guaranteed by
always allowing for a minimum EN pulse width after data
transfer.
8
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ADDRESS BITS
FIRST
BIT
LAST
BIT
13
12
11
10
9
8
7
X
X
X
X
X
X
MSB
MSB
6
5
4
3
2
1
0
3
2
1
0
LSB
0
1
1
0
LSB
0
1
0
0
LSB
0
0
1
1
LSB
I sign(2)
0
0
1
0
RX ON
TX ON
0
0
0
1
0
0
0
0
IF LO frequency divider ratio
RF LO frequency divider ratio
X
X
X
X
X
MSB
X
X
X
Q output offset adjust
LNA(1)
X
MSB
AGC amplifier gain (RX mode)
see Table 5
LSB
Q sign
MSB
I output offset adjust
(2)
X
X
X
X
X
IF RD
IF VCO
(3)
(4)
0
0
RF(5)
X
SYN ON
For test purposes only(6)
Notes
9
1. Bit LNA: 1 = LNA ON in RX mode; 0 = LNA OFF in RX mode.
Philips Semiconductors
DATA BITS
Low power dual-band GSM transceiver
with an image rejecting front-end
2000 Feb 18
Table 4 Register bit allocation
X = don’t care; MSB = Most Significant Bit; LSB = Least Significant Bit.
2. Bits Q sign and I sign = polarity of offset at Q/I channel outputs: 0 = negative offset step (output A with respect to output B); 1 = positive offset step
(output A with respect to output B).
3. Bit IF RD: 0 = frequency dividers programmed for GSM applications; 1 = frequency dividers programmed for DCS applications.
4. Bit IF VCO: 0 = IF LO buffer ON (external IF LO source connected); 1 = IF VCO ON (external IF LO source not connected).
5. Bit RF: 1 = RF section ON when RX mode is activated; 0 = RF section OFF when RX mode is activated.
6. This address must not be used. Data bits to be defined.
Objective specification
UAA3522HL
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
Table 5 AGC amplifier gain register look-up table
All codes not included in the table are forbidden.
BIT 5 (MSB)
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
AGC AMPLIFIER
GAIN (dB)(1)
0
0
0
0
1
1
−1
0
0
0
1
0
0
+1
0
0
0
1
0
1
+3
0
0
0
1
1
0
+5
0
0
0
1
1
1
+7
0
0
1
0
0
0
+9
0
0
1
0
0
1
+11
0
0
1
0
1
0
+13
0
0
1
0
1
1
+15
0
0
1
1
0
0
+17
0
0
1
1
0
1
+19
0
1
0
1
1
0
+21
0
1
0
1
1
1
+23
0
1
1
0
0
0
+25
0
1
1
0
0
1
+27
0
1
1
0
1
0
+29
0
1
1
0
1
1
+31
1
0
0
1
1
1
+33
1
0
1
0
0
0
+35
1
0
1
0
0
1
+37
1
0
1
0
1
0
+39
1
0
1
0
1
1
+41
1
1
0
1
0
0
+43
1
1
0
1
0
1
+45
1
1
0
1
1
0
+47
1
1
0
1
1
1
+49
1
1
1
0
0
0
+51
1
1
1
0
0
1
+53
1
1
1
0
1
0
+55
1
1
1
0
1
1
+57
1
1
1
1
0
0
+59
1
1
1
1
0
1
+61
Note
1. Voltage gain is defined as the differential baseband output voltage (either at pins IA/IB or pins QA/QB) divided by the
differential input voltage at pins RXIIFA and RXIIFB.
2000 Feb 18
10
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VCCn
supply voltage
−0.3
−
+6
V
Ptot
total power dissipation
−
−
1
W
Tstg
storage temperature
−40
−
+150
°C
Tamb
ambient temperature
−30
−
+70
°C
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take
normal precautions appropriate to handling MOS devices (see “Handling MOS devices” ).
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
VALUE
UNIT
65
K/W
in free air
DC CHARACTERISTICS
All parameters are guaranteed at VCC = 2.8 V; Tamb = 25 °C.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply pins VCCIF1, VCCIF2, VCCIFLO, VCCRFLO, VCCSYN, and VCCRF
VCC
supply voltage
note 1
2.7
−
3.3
V
note 1
2.7
−
4
V
note 1
2.7
−
5.5
V
Supply pins VCCCPIF and VCCCPRF
VCCCPIF;
VCCCPRF
supply voltage
Supply pin VCCPHD
VCCPHD
supply voltage for charge pump of
phase detector in transmit
modulation loop
Supply pins VCCIF1, VCCIF2, VCCIFLO, VCCRFLO, VCCSYN, VCCCPIF, VCCCPRF, VCCPHD and VCCRF
ICC(pd)(tot)
total power-down supply current
−
40
100
µA
RX mode active
−
16.9
21.9
mA
pins TXON,
RXON, SYNON = LOW-level;
pins EN, DATA, CLK = HIGH-l
evel; note 2
RF receiver IF section (pins VCCIF1, RXOIFA and RXOIFB)
ICC(RFIF)(RX)
RF receiver and IF section total
supply current
IF section supply (pin VCCIF2)
ICCIF(RX)
I/Q demodulator supply current
RX mode active
−
10.1
14.1
mA
ICCIF(TX)
I/Q modulator supply current
TX mode active
−
7.4
9.6
mA
2000 Feb 18
11
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
SYMBOL
PARAMETER
UAA3522HL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
IF LO section supply (pin VCCIFLO)
ICCIFLO(SYN)
IF LO section supply current
SYN mode active
−
5.5
6.6
mA
SYN mode active; phase
locked
−
1.2
1.5
mA
SYN mode active
−
5
6.7
mA
SYN mode active; phase
locked
−
1.4
1.7
mA
SYN mode active; RX mode
active
−
8.6
10.9
mA
−
9.8
12.6
mA
TX mode active; phase locked −
5.6
7.5
mA
IF charge pump supply (pin VCCCPIF)
ICCCPIF(SYN)
IF LO charge pump supply current
Synthesizer supply (pin VCCSYN)
ICCSYN(SYN)
synthesizer supply current
RF LO charge pump and phase detector supply (pin VCCCPRF)
ICCCPRF(SYN) RF LO charge pump supply current
RF LO supply (pin VCCRFLO)
ICCRFLO(RX)
RF LO buffer receive section supply
current
ICCRFLO(TX)
RF LO buffer transmit section supply TX mode active
current
Closed-loop charge pump supply (pin VCCPHD)
ICCPHD(TX)
closed-loop charge pump supply
current
RF receiver and transmit modulation loop supply (pin VCCRF)
ICCRF(RX)on
supply current of RF receiver
(receive IF section disconnected)
with RX image rejection mixer and
LNA ON
RX mode active; LNA ON
−
17.9
23.6
mA
ICCRF(RX)off
supply current of RF receiver
(receive IF section disconnected)
with RX image rejection mixer and
LNA OFF
RX mode active; LNA OFF
−
11.2
14.6
mA
ICCRF(TX)
supply current of transmit
modulation loop (charge pump
disconnected)
TX mode active
−
6.1
7.6
mA
Pins VCCIF1, VCCIF2, VCCIFLO, VCCCPIF, VCCSYN, VCCCPRF, VCCPHD, VCCRF and RXOIFA, RXOIFB
ICC(RX)
supply current in RX mode
RX mode active; note 3
−
44.9
59.6
mA
ICC(TX)
supply current in TX mode
TX mode active; note 3
−
20.3
26.4
mA
ICC(SYN)
supply current in SYN mode
SYN mode active; note 3
−
21.7
27.4
mA
Pins IA IB, QA and QB
VO(IQ)
DC voltage at I/Q baseband outputs
TX mode active
1.125
1.25
1.325
V
VI(IQ)
DC voltage at I/Q baseband inputs
RX mode active
1.175
1.25
1.35
V
Logic levels (pins EN, DATA, CLK, TXON, RXON and SYNON)
VIH
HIGH-level input voltage
1.9
−
−
V
VIL
LOW-level input voltage
−
−
0.7
V
2000 Feb 18
12
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
Notes:
1. VCCCPRF, VCCCPIF and VCCPHD must be equal to, or greater than, the other supply voltages. The other supply
voltages must be equal.
2. ‘HIGH-level’ means the control pin voltage must be equal to the supply voltage VCC. ‘LOW-level’ means the control
pin voltage must be equal to the supply ground.
3. ICC(RX) = ICC(RFIF)(RX) + ICCIF(RX) + ICCRF(RX); ICC(TX) = ICCIF(TX) + [ICCRFLO(TX) − ICCRFLO(RX)] + ICCPHD(TX) + ICCRF(TX);
ICC(SYN) = ICCIFLO(SYN) + ICCCPIF(SYN) + ICCPLL(SYN) + ICCCPRF(SYN) + ICCRFLO(SYN).
AC CHARACTERISTICS
All parameters are guaranteed at VCC = 2.8 V; Tamb = 25 °C; unless specified otherwise.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
RF receiver section; measured in a 50 Ω impedance system, including external input/output baluns and
matching networks to 50 Ω (see Fig.3)
RF RECEIVER INPUTS (PINS RXIRFA AND RXIRFB)
fi(RF)(GSM)
GSM band RF input
frequency
925
−
960
MHz
Ri(dif)
differential input
resistance
−
146
−
Ω
Ci(dif)
differential input
capacitance
−
0.85
−
pF
S11
input power matching
−
−15
−10
dB
Pi(spur)
level of spurious input
power due to
LO leakage
−
−50
−40
dBm
note 1
RECEIVER IF OUTPUT (PINS RXOIFA AND RXOIFB)
fo(IF)
IF output frequency
LO > RF
−
200
−
MHz
RL(m)
matched load
resistance
differential; note 2
−
1
−
kΩ
Gconv(p)
power conversion gain
into specified matched load
resistance; note 1
23
24.5
27
dB
Gripple
gain ripple
over specified frequency range;
note 3
−0.5
−
+0.5
dB
∆G/∆T
gain variation
note 6
−60
−30
−
dBm/K
−
3.45
3.85
dB
with temperature
F
noise figure
for Ri(dif); notes 1, 3 and 4
CP1
−1 dB input
compression point
referenced to input
note 1
IP3
third-order intercept
point referenced to
input
DES3dB
3 dB desensitization
point referenced to
input
2000 Feb 18
at Tamb = 25 °C
−23.5 −
−
dBm
over temperature range
−24.2 −
−
dBm
note 1
−18
−
−
dBm
∆fi(RF) = 3 MHz RF input power =
−101 dBm; note 1
−25
−
−
dBm
13
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
SYMBOL
PARAMETER
CONDITIONS
UAA3522HL
MIN.
TYP.
MAX.
UNIT
IR
image rejection
fo(IF) = 200 MHz; note 1
30
35
−
dB
Goff
output isolation in
off-state
bit LNA = 0; notes 1 and 5
60
70
−
dB
Receiver IF section (AGC and baseband filter); the impedance of the source, input balun, matching network
and specified input is 50 Ω
IF INPUT TO AGC AMPLIFIER (PINS RXIIFA AND RXIIFB)
fi(IF)
IF input frequency
−
200
−
MHz
Ri(dif)
differential input
resistance
−
1
−
kΩ
Pi(m)
input power matching
−
−15
−10
dB
−2.5
−0.5
+1.5
dB
note 1
BASEBAND INPUT/OUTPUT; RX MODE (PINS IA, IB, QA AND QB)
Gconv(dif)(min)
differential voltage
conversion gain per
channel; gain set to
minimum
Gconv(dif)(max)
differential voltage
conversion gain per
channel; gain set to
maximum
59.5
61.5
63.5
dB
Gconv(step)
voltage conversion step note 1
gain
−
2
−
dB
∆GI-Q
gain difference
between I and Q paths
−
−
0.8
dB
∆ϕ
quadrature-phase error
between I and Q paths
−5
−
+5
deg
GL
gain control linearity
notes 1 and 7
note 1
note 1
−2
−
+2
dB
notes 1 and 11
−3
−
+3
dB
within any 20 dB gain range
−1
−
+1
dB
Gconv(dif)(max); notes 1 and 9
−
−
9
dB
F
noise figure
Gconv(dif)(min); notes 1 and 9
−
−
61
dB
IP3
third-order intercept
point referenced to
input
Gconv(dif)(max) = 61 dB; note 8
−42
−38
−
dBm
CP1
−1 dB compression
point referenced to
input
Gconv(dif)(min); note 8
−4
0
−
dBm
CP1adjacent
−1 dB compression
point for adjacent
channels referenced to
input
Gconv = 49 dB; notes 7 and 6
∆fmod = n × 200 kHz; n = 1, 2, 3
−45
−40
−
dBm
Bbf(-1dB)
−1 dB baseband filter
bandwidth
note 10
67.7
−
−
kHz
∆td(g)
group delay variation
DC < ∆fmod < 67.7 kHz
−
1.5
−
µS
2000 Feb 18
14
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
SYMBOL
αbf5
PARAMETER
CONDITIONS
baseband filter
note 10;
attenuation
∆fmod = 140 kHz
(fifth-order Butterworth)
∆fmod = 200 kHz
∆fmod = 400 kHz
∆fmod = 600 kHz
Vo(pin)(peak)(max) maximum peak output
voltage per pin giving a
total harmonic
distortion of less
than 3% at Gconv >7
VOO
output offset voltage
adjustment
LSBoffset
LSB offset adjustment
∆Voffset
offset variation
UAA3522HL
MIN.
TYP.
MAX.
UNIT
8
11
−
dB
19
25
−
dB
36
55
−
dB
44
−
−
dB
differential resistance between
QA/QB or IA/IB > = 180 kΩ; note 1
0.75
−
−
V
Gconv = 31 dB
−60
−
+60
mV
−
50
100
mV
−10
−
+10
mV
gain from Gconv(dif)(min)
to Gconv(dif)(max)
Transmit IF section; general conditions: Vmod(peak) = 0.25 V; VI(IQ) = VO(IQ) = 1.25 V; fmod = 67.7 kHz
BASEBAND INPUT/OUT; TX MODE (PINS IA, IB, QA AND QB)
∆fmod
modulation frequency
gain = −3 dB gain
0
Vmod(peak)
modulation level (peak
value)
single-ended
DRi
dynamic input
resistance
single-ended per pin
−
2
MHz
0.225 0.25
0.275
V
−
−
kΩ
12.5
TRANSMITTER IF LC TUNED CIRCUIT (PINS TXIFA AND TXIFB)
fo(IF)
IF output frequency
−
200
−
MHz
LOout
local oscillator
feedthrough level
fo(IF) = 200 MHz
−
−40
−30
dBc
Po
transmit power without
LC tuned circuit
fo(IF) = 200 MHz
± 67.7 kHz; measured through a
balun; note 12
−
−16
−
dBm
IM2o
level of second-order
image products
fo(IF) = 200 MHz
± 2 × 67.7 kHz; note 12
−
−48
−45
dBc
IM3o
level of third-order
image products
fo(IF) = 200 MHz
± 3 × 67.7 kHz; note 12
−
−55
−50
dBc
IMo
image level
fo(IF) = 200 MHz
− 67.7 kHz; note 12
−
−34
−
dBc
ϕN
phase noise output
power density
foffset = 400 kHz
−
−
−125
dBc/Hz
foffset = 10 MHz
−
−140 −133
dBc/Hz
Transmit modulation loop section; General conditions: Vmod(peak) = 0.25 V; VI(IQ) = VO(IQ) = 1.25 V;
fmod = 67.7 kHz
OFFSET MIXER; GSM BAND (PINS TXIRFA AND TXIRFB)
fi(RF)(TX)
2000 Feb 18
TX RF VCO input
frequency
880
15
−
915
MHz
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
SYMBOL
PARAMETER
CONDITIONS
UAA3522HL
MIN.
TYP.
MAX.
UNIT
Ri(pin)
input resistance per pin note 13
−
100
−
Ω
Ci(pin)
input capacitance per
pin
−
1
−
pF
Pi
input power
S11
input power matching
LOL
reverse isolation local
oscillator leakage
symmetrical
−14.5 −10
−5.5
dBm
single-ended
−11.5 −7
−2.5
dBm
note 1
−
−15
−10
dB
−
−
−40
dBm
OFFSET MIXER; DCS BAND (PINS TXIRFA AND TXIRFB)
fi(RF)(TX)
TX RF VCO input
frequency
1710
−
1785
MHz
Ri(pin)
input resistance per pin note 13
−
100
−
Ω
Ci(pin)
input capacitance per
pin
−
1
−
pF
Pi
input power
S11
input power matching
LOL
reverse isolation local
oscillator leakage
symmetrical
−14.5 −10
−5.5
dBm
single-ended
−11.5 −7
−2.5
dBm
note 1
−
−15
−10
dB
−
−
−40
dBm
PHASE DETECTOR; DCS AND GSM BAND (PIN PHDOUT)
Icp(max)
charge pump maximum R = 270 Ω, 1%; VO = 1⁄2VCCPHD
sink or source current
2.2
2.4
2.6
mA
GPHD
phase detector gain
−
2
−
mA/rad
−20
−
+20
%
∆GPHD
phase detector gain
variation
VO =
1⁄ V
2 CCPHD;
note 11
VO
output voltage
0.5
−
VCCPHD − 0.5 V
Ro
output resistance
VO = 1⁄2VCCPHD
−
10
−
kΩ
No
output noise current
density
20 kHz < foffset < 20 MHz in lock;
note 1
−
−
200
pA/√Hz
Isweep
VCO sweeping source
current
VO = 1⁄2VCCPHD
0.4
0.55
0.7
mA
Ro(off)
output resistance to
ground when powered
down
TX mode disabled
−
1
−
kΩ
SPUR4fm
level of spurious signal
at four times the
wanted fmod signal
−
−48
dBc
SPUR8fm
level of spurious signal
at eight times the
wanted fmod signal
fmod = 67.7 kHz;
−
fo(RF)(GSM) = 880 MHz
to 915 MHz; fo(RF)(DCS) = 1710 MHz
to 1785 MHz
−
−
−55
dBc
LOout
local oscillator
feedthrough level
at fRF
−
−40
−32
dBc
IMo
image level
at fRF; note 1
−
−38
−35
dBc
2000 Feb 18
16
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
SYMBOL
PARAMETER
CONDITIONS
UAA3522HL
MIN.
TYP.
MAX.
UNIT
RF LO buffer; measured and guaranteed on evaluation board
RF LO SOURCE CONNECTED TO PIN RFLOE (see Fig.7)
Ri
input resistance
−
50
−
Ω
Ci
input capacitance
−
1
−
pF
S11
input power matching
−
−15
−10
dB
Pi(LO)
input power acceptable
from the RF LO source
−7
−3
2
dBm
IF LO; measured and guaranteed on evaluation board
EXTERNAL RESONATOR CIRCUIT CONNECTED TO PINS IFLOC AND IFLOE
fosc
oscillation frequency
note 1
−
400
−
MHz
Vosc(peak)
peak voltage excursion
limit at IFLOC
(collector)
VCCIFLO = 2.8 V; see Fig.5
1
−
1.5
V
ϕN
phase noise
foffset = 400 kHz; fLO(IF) = 400 MHz
−
−
−125
dBc/Hz
∆fTROFF
frequency variation with note 14
supply voltage
(pushing)
−
−
1
MHz/V
∆fTRON
frequency variation
between RX on and
RX off (pulling)
−
−
10
kHz
IF LO buffer; measured and guaranteed on evaluation board
IF SOURCE CONNECTED TO PIN IFLOE
Ri
input resistance
−
50
−
Ω
Ci
input capacitance
−
1
−
pF
Pi(m)
input power matching
−
−15
−10
dB
PIF
power available from
the IF source
−8
−5
−2
dBm
see Fig.5
RF and IF synthesizer VCOs
REFERENCE FREQUENCY INPUT (PIN REFIN)
fref
reference frequency
−
13
−
MHz
Vi(fref)(rms)
input voltage level
(RMS value)
80
−
250
mV
Ri
input resistance
Ci
input capacitance
fref = 13 MHz
−
10
−
kΩ
−
1
−
pF
RF SYNTHESIZER; GSM AND DCS MODES (PINS RXIRFA, RXIRFB AND CPORF)
fLO(RF)
RF LO frequency
1040
−
1720
MHz
fph(comp)
phase comparator
frequency
−
200
−
kHz
ϕN(GSM)
GSM close-in phase
noise
−
−82
−75
dBc/Hz
2000 Feb 18
within the closed-loop bandwidth
Pxtal = 0 dBm; fLO(RF) = 1.1 GHz
17
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
SYMBOL
PARAMETER
CONDITIONS
UAA3522HL
MIN.
TYP.
MAX.
UNIT
ϕN(DCS)
DCS close-in phase
noise
within the closed-loop bandwidth
Pxtal = 0 dBm; fLO(RF) = 1.6 GHz
−
−79
−74
dBc/Hz
Vfph(comp)(spur)
phase comparator
frequency spurii
breakthrough level
foffset = 200 kHz; second-order loop
filter closed-loop
bandwidth = 11 kHz
−
−75
−60
dBc
Io(cp)
charge pump output
current
sink or source current; at Vo(cp)
1.8
2.2
2.6
mA
IL(cp)(off)
charge pump leakage
current in off-state
−5
−
+5
nA
Vo(cp)
charge pump output
voltage
0.4
−
VCC − 0.4
V
Io(cp) within specified values
IF SYNTHESIZER (PINS IFLOC, IFLOE AND CPOIF)
fLO(IF)
IF LO frequency
380
400
440
MHz
fph(comp)
phase comparator
frequency
−
1
−
MHz
ϕN
close-in phase noise
within the closed-loop bandwidth
Pxtal = 0 dBm; fLO(IF) = 400 MHz
−
−95
−85
dBc/Hz
Vfph(comp)(spur)
phase comparator
frequency spurii
breakthrough level
foffset = 1 MHz; second order loop
filter closed-loop
bandwidth = 25 kHz
−
−75
−60
dBc
Io(cp)
charge pump output
current
sink or source current; at Vo(cp)
0.75
1.1
1.35
mA
IL(cp)(off)
charge pump leakage
current in off-state
−5
−
+5
nA
Vo(cp)
charge pump output
voltage
0.4
−
VCC − 0.4
V
Frequency dividers
D/DfLO(RF)
RF frequency
programmable divider
ratio
5200
−
8600
D/DfLO(IF)
IF frequency
programmable divider
ratio
−
200
−
D/Dfref(RF)
RF reference frequency fixed ratio
divider ratio
−
65
−
D/Dfref(IF)
IF reference frequency
divider ratio
−
13
−
−
−
10
General IC specification
tON
2000 Feb 18
switch-on time
90% of the final current
18
µs
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
Notes
1. Measured and guaranteed only on UAA3522 evaluation board.
2. The IF output has open collectors which are supplied via external inductors. External resistors are also needed to
set the output impedance and to match the IF output to the specified load resistance RL (see Fig.3).
3. Value includes losses due to the printed circuit board and balun.
4. Value is guaranteed only for the Pi(LO) typ.
5. For a given RF input power, the value is the difference in the power measured at the IF output when the LNA is
switched on and when it is switched off.
6. This value is guaranteed within the temperature range −10 to +70 °C.
7. Voltage gain is defined as the differential baseband output voltage (either at pins IA/IB or pins QA/QB) divided by the
differential input voltage at pins RXIIFA and RXIIFB.
8. Value refers to differential voltage at pins RXIIFA and RXIIFB (1 kΩ input impedance).
9. Value includes printed circuit board and balun losses.
10. RREFAGC = 18 kΩ, 1%.
11. Guaranteed at Tamb = −30 to +70 °C.
12. With specified LC tuned circuit (33 nH, 15 pF) connected as shown in Fig.4.
13. Defined for the typical input power.
14. Oscillator configured as shown in the evaluation board diagram Fig.7.
VCC
handbook, full pagewidth
50 Ω
RXIRFA
LOW
LOSS
BALUN
RF
RECEIVER
RXIRFB
RXOIFA
Z = 1 kΩ
BALUN
1 kΩ/50 Ω
RL
50 Ω
RXOIFB
output port
input port
FCA047
Fig.3 RF receiver test principle.
2000 Feb 18
19
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
handbook, full pagewidth
VCC
15 pF
UAA3522HL
EXTERNAL
IF FILTER
33 nH
330 Ω
330 Ω
TXIFA
TXIFB
2 kΩ
FCA045
Fig.4 I/Q modulator output.
handbook, full pagewidth
VCCIFLO
VCC
1 kΩ
UAA3522HL
IFLOC
IF VCO
XTAL
IFLOE
IF SOURCE
GNDIFLO
FCA048
Fig.5 Evaluating IF LO buffer.
2000 Feb 18
20
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
SERIAL TIMING CHARACTERISTICS
General conditions: VCC = 2.8 V; Tamb = 25 °C; see Fig.6; unless otherwise specified.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Serial programming clock (pin CLK)
tr
rise time
−
10
tf
fall time
−
10
40
ns
Tcy(clk)
clock cycle time
100
−
−
ns
40
ns
Enable programming (pin EN)
td(ENL-CLKH)
delay from enable active to rising clock edge
40
−
−
ns
td(CLKL-ENH)
delay from enable inactive to last falling clock edge
20
−
−
ns
tW(reg)(min)
minimum inactive pulse width when consecutively programming
two different registers
150
−
−
ns
tW(IFLO)(min)
minimum inactive pulse width when consecutively programming
two IF divider ratios
150
−
−
ns
tW(RFLO)(min)
minimum inactive pulse width when consecutively programming
two RF divider ratios
500
−
−
ns
tsu(ENH-CLKH)
enable set-up time to next rising clock edge
20
−
−
ns
Register serial input data (pin DATA)
tsu(DATA-CLK)
set-up time DATA to CLK
20
−
−
ns
th(DATA-CLK)
hold time DATA to CLK
20
−
−
ns
t d(CLKL-ENH)
handbook, full pagewidth
t su(DATA-CLK)
t h(DATA-CLK)
tf
Tcy(CLK)
tr
tsu(ENH-CLKH)
CLK
DATA
MSB
LSB
ADDRESS
INACTIVE
EN
ACTIVE
FCA042
t d(ENL-CLKH)
Fig.6 Serial bus timing diagram.
2000 Feb 18
21
tW
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3.9 pF
150 nH
VCC
10 pF
12 nH
27 pF
27 pF
150 nH
3.9 pF
18 pF
ATTENUATOR
18 pF
22 nH
10 pF
47 nH
100 nH
12 nH
1.5 kΩ
12 pF
48
46
45
44
43
42
41
40
39
38
1
36
2
35
QB
3
34
IA
4
33
IB
5
32
18 kΩ
TX RF
VCO
37
QA
VCC
VCC
220 Ω
100 pF
1.8 nF
18 Ω
RXON
27 nF
22 pF
31
6
7
30
RXIIFA
8
29
RXIIFB
9
28 SYNON
10
27
11
26
12
25
470 nH
3.9 pF
VCC
120 pF
150 nH
TXON
VCC
13
14
15
16
19
20
21
22
1 nF
33 pF
22 nH
10 kΩ
470
pF
SERIAL
PROGRAMMING
BUS LINES
VCC
24
RX RF
VCO
3.3
kΩ
12 nF
VCC
1 nF
VCC(chip)
27
pF
100
pF
1
nF
200 mV
13 MHz
10 kΩ
SERIAL
PROGRAMMING
BUS LINES
(chip)
39 pF
SERIAL
PROGRAMMING
BUS LINES
(board)
This schematic represents the UAA3522HL characterisation board for GSM application and does not guarantee full specification for any particular application.
Fig.7 Evaluation board.
VCC(board)
FCA044
UAA3522HL
BB149
3.3
kΩ
6.8
nF
23
22 pF
VCC
Objective specification
330 Ω
100 pF
18
VCC
8.2 pF
100 pF
17
CLK
150 nH
DATA
120 pF
EN
22
UAA3522HL
3.9 pF
RX IF
47
27 pF
270 Ω
VCC
Philips Semiconductors
2.2 pF
100
nH
Low power dual-band GSM transceiver
with an image rejecting front-end
VCC
RX IF
APPLICATION INFORMATION
andbook, full pagewidth
2000 Feb 18
RX RF
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0°
ADDER
×
SAW
UAA2077XM
46, 47
×
925 to 960 MHz
×
90°
41,
42
BALUN
8, 9
PHASE 90°
SHIFTER
+
PHASE
SHIFTER
0°
4, 5
0°
IF VCO
400 MHz
×
ADDER
×
23
UAA3522HL
RX/TX
SWITCH
880 to 915 MHz
GSM BAND
CHARGE
PUMP
RF PHASE/
FREQUENCY
DETECTOR
DIVIDER
÷5
DIVIDER
÷13
×
ADDER
GSM TX RF VCO
880 to 915 MHz
IF VCO
XTAL
&
+
PHASE
DETECTOR
CHARGE 16
PUMP
23
REF OSC.
13 MHz
×
90°
4, 5 I
I
N
T
E
R
F
A
C
E
2, 3 Q
44, 45
DCS TX RF VCO
1710 to 1785 MHz
FCA004
Fig.8 Typical application block diagram of a GSM dual-band solution using the UAA2077XM DCS front-end and the UAA3522HL transceiver.
Objective specification
CHARGE
PUMP
0°
A
U
D
I
O
UAA3522HL
1710 to 1785 MHz
POWER
DCS BAND
AMPLIFIER
13,
14
×
38, 39
35
DIVIDER &
PHASE
SHIFTER
IF PHASE/
FREQUENCY
DETECTOR
PROGRAMMABLE
DIVIDER
26
B
A
S
E
B
A
N
D
PROGRAMMABLE
DIVIDER
30, 31
GSM RF
RX VCO
1080 to 1160
MHz
2, 3 Q
90°
÷2
DCS RF
RX VCO
1510 to 1680
MHz
I
Philips Semiconductors
+
PHASE
SHIFTER
BALUN
Low power dual-band GSM transceiver
with an image rejecting front-end
PHASE 90°
SHIFTER
90°
Typical application
1805 to1880 MHz
handbook, full pagewidth
2000 Feb 18
×
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
PACKAGE OUTLINE
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
37
24
ZE
e
E HE
A A2
(A 3)
A1
w M
pin 1 index
θ
bp
Lp
L
13
48
detail X
12
1
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.60
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
7.1
6.9
0.5
9.15
8.85
9.15
8.85
1.0
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
0.95
0.55
7
0o
0.95
0.55
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT313-2
136E05
MS-026
2000 Feb 18
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
00-01-19
24
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
The footprint must incorporate solder thieves at the
downstream end.
SOLDERING
Introduction to soldering surface mount packages
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
2000 Feb 18
UAA3522HL
25
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
2000 Feb 18
26
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
NOTES
2000 Feb 18
27
UAA3522HL
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Internet: http://www.semiconductors.philips.com
SCA 69
© Philips Electronics N.V. 2000
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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403506/01/pp28
Date of release: 2000
Feb 18
Document order number:
9397 750 06451