INTEGRATED CIRCUITS DATA SHEET TDA8742; TDA8742H Satellite sound circuit with noise reduction Product specification Supersedes data of November 1992 File under Integrated Circuits, IC02 Philips Semiconductors October 1994 Philips Semiconductors Product specification Satellite sound circuit with noise reduction FEATURES APPLICATIONS • Demodulation of main audio signal using wide band PLL (lock range selectable) • Satellite receivers • HF input selection: two-out-of-eight secondary audio signals can be selected • Video recorders. TDA8742; TDA8742H • TV sets • Demodulation of secondary audio signals using wide band PLL GENERAL DESCRIPTION The TDA8742; TDA8742H is a multi-function sound IC for use in satellite receivers, television sets and video recorders. The pin numbers given in parenthesis throughout this document refer to the QFP44 package. • Noise reduction of the secondary audio signals • Output selection: stereo, language 1, language 2, main audio and external • Mute control • Line outputs (SCART level). QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VP supply voltage 8 12 13.2 V S/N(A) = 40 dB − 1.0 2.0 mV MHz Main channel VIN3(rms) input sensitivity pin 18 (14) (RMS value) ∆fOM lock range PLL demodulator either 5.5 − 7.5 or 10.0 − 11.5 MHz −9 −6 −4 dBV 62 70 − dB 0.8 1.5 mV − 11.5 MHz VOM output voltage pin 23 (19) S/N(A) signal-to-noise ratio A-weighted Secondary channels VIN1,IN2(rms) input sensitivity pins 2, 4, 6, 8, 10, 12, 14 and 16 (1, 3, 5, 7, 9, 11, 40 and 42) (RMS value) ∆fOS1,2 S/N(A) = 40 dB − lock range PLL demodulators VOR,OL output voltage pins 24 and 25 (20 and 21) S/N(A) signal-to-noise ratio 10.0 A-weighted −8 −6 −4 dBV 72 80 − dB Crosstalk αS/M crosstalk from secondary to main channel − 74 − dB αM/S crosstalk from main to secondary channel − 74 − dB αS/S crosstalk between secondary channels − 74 − dB October 1994 2 Philips Semiconductors Product specification Satellite sound circuit with noise reduction TDA8742; TDA8742H ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8742 SDIP42 TDA8742H QFP44(1) DESCRIPTION VERSION plastic shrink dual in-line package; 42 leads (600 mil) SOT270-1 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm SOT307-2 Note 1. When using IR reflow soldering it is recommended that the Drypack instructions in the “Quality Reference Handbook” (order number 9398 510 63011) are followed. BLOCK DIAGRAM The pin numbers in parenthesis refer to the QFP44 package. Fig.1 Block diagram. October 1994 3 Philips Semiconductors Product specification Satellite sound circuit with noise reduction TDA8742; TDA8742H PINNING SYMBOL PIN SDIP42 PIN QFP44 DESCRIPTION n.c. 1 39 not connected IN-1A 2 40 intercarrier input A for Channel 1 (left) Isel 1 3 41 input select switch bit 1 IN-1B 4 42 intercarrier input B for Channel 1 (left) Isel 2 5 43 input select switch bit 2 IN-1C 6 1 intercarrier input C for Channel 1 (left) MCS 7 2 main channel PLL lock-in range select/disable IN-1D 8 3 intercarrier input D for Channel 1 (left) HFGND 9 4 ground for HF section IN-2A 10 5 intercarrier input A for Channel 2 (right) SCD 11 6 secondary channels PLLs disable IN-2B 12 7 intercarrier input B for Channel 2 (right) MUTE 13 8 mute switch IN-2C 14 9 intercarrier input C for Channel 2 (right) Osel L 15 10 output select switch bit 1 (left) IN-2D 16 11 intercarrier input D for Channel 2 (right) Osel R 17 13 output select switch bit 2 (right) IN-3 18 14 intercarrier input for main channel VREF 19 15 decoupling capacitor for reference voltage CD M 20 16 de-emphasis capacitor for main channel CC M 21 17 audio pass-through capacitor input for main channel VP 22 18 positive supply voltage OM 23 19 main channel output OR 24 20 right channel output OL 25 21 left channel output EXT/INT 26 22 output switch bit 3 (external/internal) EXTR 27 23 external audio input (right) EXTL 28 24 external audio input (left) CATT/REC R 29 25 attack/recovery capacitor (right) RECTR 30 26 rectifier DC decoupling (right) CNR D R 31 27 noise reduction de-emphasis capacitor (right) CD R 32 28 fixed de-emphasis capacitor (right) CC R 33 29 audio pass-through capacitor input for right channel AFGND 34 30 ground for AF section CC L 35 31 audio pass-through capacitor input for left channel CD L 36 32 fixed de-emphasis capacitor (left) CNR D L 37 33 noise reduction de-emphasis capacitor (left) RECTL 38 34 rectifier DC decoupling (left) CATT/REC L 39 35 attack/recovery capacitor (left) October 1994 4 Philips Semiconductors Product specification Satellite sound circuit with noise reduction TDA8742; TDA8742H PIN SDIP42 PIN QFP44 CDC L 40 36 DC decoupling capacitor (left) CDC M 41 37 DC decoupling capacitor (main) CDC R 42 38 DC decoupling capacitor (right) n.c. − 12 not connected n.c. − 44 not connected SYMBOL DESCRIPTION Fig.2 Pin configuration (SDIP42). October 1994 5 Philips Semiconductors Product specification Satellite sound circuit with noise reduction Fig.3 Pin configuration (QFP44). October 1994 6 TDA8742; TDA8742H Philips Semiconductors Product specification Satellite sound circuit with noise reduction channel input, pin 18 (14) via a 10.7 MHz ceramic bandpass filter. FUNCTIONAL DESCRIPTION Satellite sound The filtered signal is AC-coupled to a limiter/amplifier and then to a PLL demodulator. The PLL FM demodulator ensures that the demodulator is alignment-free. High gain and DC error signals from the PLL, which are superimposed on the demodulator output, require DC decoupling. A buffer amplifier is used to amplify the signal to the same level as the secondary channels and decouples DC using an electrolytic capacitor connected to pin 41 (37). The demodulator output signal is fed to pin 20 (16) via an internal resistor. The output signal can be de-emphasized by means of this resistor and an external capacitor connected to ground. The baseband signal coming from a satellite tuner contains the demodulated video signal plus a number of sound carriers to facilitate reception of a PAL/NTSC/SECAM satellite signal. Nearest to the video signal is the main sound carrier which carries the single channel sound related to the video. This is an FM modulated carrier with a fixed pre-emphasis. The carrier frequency can be in the range of 5.8 to 6.8 MHz. Additionally, a number of optional secondary sound carriers may be present which can be used for stereo or multi-language sound related to the video, or for unrelated radio sound. These carriers are also FM modulated, but for better sound quality (improved signal-to-noise performance) broadcast satellites (e.g. ‘ASTRA’) use a noise reduction system (adaptive pre-emphasis circuit, combined with a fixed pre-emphasis). Capacitor value = de-emphasis time constant per1500 (for 50 µs: 33 nF). From here the signal is fed to the output selectors. The signal is amplified to 500 mV (RMS) (i.e. −6 dBV) in the output amplifiers. These secondary carrier frequencies can be in the range of 6.30 to 8.28 MHz. Secondary channels Up to eight secondary channels are available at pins 2, 4, 6, 8, 10, 12, 14 and 16 (1, 3, 5, 7, 9, 11, 40 and 42). External ceramic bandpass filters, tuned to the required secondary sound carrier frequencies, route these signals to the inputs. This enables the demodulation of eight different channel; frequencies, which are derived from the baseband, by using an external mixer and oscillator frequency synthesizer. The TDA8742; H contains all circuitry for processing the main channel and for two secondary channels, from baseband signal to line (SCART) output drivers. The desired frequencies can be routed to the device via bandpass filters. Main channel (see Fig.1) The lock-in range of the main channel PLL can be switched between 5.5 to 7.5 MHz, PLL off and 10.0 to 11.5 MHz using the MCS signal at pin 7 (2) [when pin 7 (2) is at logic 0, being a voltage from 0 to 1.2 V, the lock-in range = 5.5 to 7.5 MHz; when pin 7 (2) is at logic 1, being a voltage from 3.5 V until VP, the lock-in range = 10.0 to 11.5 MHz; when pin 7 (2) is in the mid voltage position, being a voltage from 1.8 to 2.8 V, the main channel PLL is switched off]. The voltage is then determined by the resistor divider at this pin between VP and ground. For stereo applications the TDA8742; TDA8742H contains two identical secondary sound processing channels. For each channel it is possible to select from four inputs (IN-A, IN-B, IN-C and IN-D) using the input selector (see Table 1). With the input switch several stereo signals or languages can be selected for demodulation. It should be noted that the inputs are identical and can be freely interchanged Secondary Channel 1 will also be referred to as ‘LEFT’ or ‘LANGUAGE 1’ and secondary Channel 2 will also be referred to as ‘RIGHT’ or ‘LANGUAGE 2’. If only one fixed carrier frequency for the main channel is to be demodulated (e.g. 6.5 MHz), the lock-in range of the PLL should be switched to 5.5 to 7.5 MHz. The baseband signal is applied to the main channel input, pin 18 (14) via a 6.5 MHz ceramic bandpass filter. Alternatively, if there is a requirement to demodulate different main channel frequencies, these frequencies can be transferred to a fixed intermediate frequency (e.g. 10.7 MHz) using an external mixer and oscillator-frequency synthesizer. In this event the lock-in range of the PLL should be switched to 10.0 to 11.5 MHz. The IF signal is applied to the main October 1994 TDA8742; TDA8742H From the input selector switch the signals are coupled to limiter/amplifiers and then to the PLL demodulators. Processing is similar to the main channel. The demodulator output signal is amplified in a buffer amplifier and DC decoupled using electrolytic capacitors connected to pins 40 (36) (left) and 42 (38) (right). The output level is set with a 220 Ω resistor connected in series with the capacitor. 7 Philips Semiconductors Product specification Satellite sound circuit with noise reduction High frequency components in the amplified PLL output signal are filtered out in the audio LPF block (4th order Butterworth low-pass filter) to prevent unwanted influence on the noise reduction. ABBREVIATIONS fMOD = modulating frequency. ∆fM = frequency deviation of the main Channel. ∆fS1 = frequency deviation of secondary Channel 1 (left). NOISE REDUCTION (NR) ∆fS2 = frequency deviation of secondary Channel 2 (right). The noise reduction can be regarded as an input level-dependent low-pass filter (adaptive de-emphasis system) followed by a fixed de-emphasis. With maximum input level (0 dB) the frequency response of the first part (i.e. without the fixed de-emphasis) is virtually flat. As the input level is lowered by x-dB, the higher output frequencies will be reduced an extra x-dB with respect to the lower frequencies (1 : 2 expansion). fOM = carrier frequency of main Channel. fOS1 = carrier frequency of secondary Channel 1. fOS2 = carrier frequency of secondary Channel 2. LPF = Low-Pass Filter. NR = Noise Reduction. The NR output signal is fed to pin 36 (32) (left) and pin 32 (28) (right) via an internal resistor. PLL = Phase-Locked-Loop. Fixed de-emphasis is achieved by these resistors and external capacitors connected to ground. The signals are DC decoupled via pins 36/35 (32/31) and 32/33 (28/29) and then routed to the output selectors. OUTPUT SELECTION With the output selector (see Table 2) the outputs at pins 25 and 24 (21 and 20) can be switched to the different channels. Both outputs can be switched to both secondary channels, to the main channel and to the external inputs at pin 28 and 27 (24 and 23) for IC chaining purposes. Pin 23 (19) is a separate output which delivers the main channel only, thereby creating the possibility of having three different output channels simultaneously e.g. for use in hi-fi VCRs. The outputs at pins 25 and 24 (21 and 20) can be muted by setting the MUTE signal at pin 13 (8) to logic 1 (switch positions 6 and 7). The output at pin 23(19) can be muted by setting the MUTE signal and the EXT/INT signal at pin 26 (22) both logic 1 (switch position 7). All outputs at pins 23, 24 and 25 (19, 20 and 21) are line drivers with SCART level capability and are short-circuit protected by 125 Ω output resistors. Output level of all channels = −6 dBV typical when frequency deviation of FM signal is 54% of maximum frequency deviation (i.e. 0.54 × 85 kHz = 46 kHz for the main channel and 0.54 × 50 kHz = 27 kHz for the secondary channels) at 1 kHz modulation frequency (reference level). October 1994 TDA8742; TDA8742H 8 Philips Semiconductors Product specification Satellite sound circuit with noise reduction TDA8742; TDA8742H LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VP supply voltage note 1 0 13.2 V Vn voltage level on pins 2, 4, 6, 8, 10, 12, 14 and note 2 16 (1, 3, 5, 7, 9, 11, 40 and 42) 0 1 V Vn voltage on pins 3, 5, 11, 13, 15, 17, 20, 21, 23 to 26, 31, 33, 35, 37, 40, 41, and 42 (6, 8, 10, 13, 16, 17, 19, 20 to 22, 27, 29, 31, 33, 36, 37, 38, 41 and 43) note 2 0 9 V Vn voltage on pins 7, 18, 19, 27 to 30, 32, 36, 38 note 1 and 39 (2, 14, 15, 23 to 26, 28, 32, 34 and 35) 0 VP V Tstg storage temperature −55 +150 °C Tamb operating ambient temperature −20 +70 °C Notes 1. All voltages referenced to ground pins 9 and 34 (4 and 30). 2. All voltages referenced to ground pins 9 and 34 (4 and 30). These voltages must not exceed VP or maximum value at any time. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER VALUE UNIT SDIP42 53 K/W QFP44 69 K/W thermal resistance from junction to ambient in free air DC CHARACTERISTICS All voltages referenced to ground at pins 9 and 34 (4 and 30). Measured in test circuit Fig.4; VP = 12 V; Tamb = 25 °C; ∆fM = ∆fS1 = ∆fS2 = 0 kHz (no modulation); fOM = 6.5 MHz; fOS1 = 10.52 MHz; fOS2 = 10.7 MHz; HF level at pin 18 (14): 40 mV (RMS); HF level at selected secondary inputs: 20 mV (RMS); MCS = logic 0 [V7 (V2) = 0 V]; SCD = logic 0 [V11 (V6) = 0 V]; unless otherwise specified. SYMBOL PARAMETER MIN. TYP. MAX. UNIT VP supply voltage 8.0 12 13.2 V IP supply current − 38 45 mA Ptot total power dissipation − − 600 mW Vn voltage on pins 20, 21, 23, 24, 25, 27, 28, 30, 32, 33, 35, 36 and 38 (16, 17, 19, 20, 21, 23, 24, 26, 28, 29, 31, 32 and 34) − 3.8 − V VREF input reference voltage on pin 19 (15) 3.7 3.8 3.9 V Vn voltage on pins 2, 4, 6, 8, 10, 12, 14 and 16 (1, 3, 5, 7, 9, 11, 40 and 42) − 0 − V VCDCL,CDCR voltage on pins 40 and 42 (36 and 38) − 2.7 − V VCDCM voltage on pin 41 (37) − 2.8 − V IIN3 input current at pin 18 (14) − − 1 µA October 1994 9 Philips Semiconductors Product specification Satellite sound circuit with noise reduction TDA8742; TDA8742H AC CHARACTERISTICS All voltages referenced to ground at pins 9 and 34 (4 and 30). Measured in test circuit Fig.4; VP = 12 V; Tamb = 25 °C; fMOD = 1 kHz; fOM = 6.5 MHz; ∆fM = 46 kHz; ∆fS1 = ∆fS2 = 27 kHz (reference levels); fOS1 = 10.52 MHz; fOS2 = 10.7 MHz; HF level at pin 18 (14): 40 mV (RMS); HF level at selected secondary inputs: 20 mV (RMS); MCS = logic 0 [V7 (V2) = 0 V]; SCD = logic 0 [V11 (V6) = 0 V]; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Main channel - HF input pin 18 (14) and limiter VIN3(rms) input sensitivity (RMS value) VIN3(rms) input signal level (RMS value) RIN3 input resistance S/N(A) = 40 dB − 1.0 2.0 mV − − 200 mV − 15 − kΩ Main channel - PLL FM demodulator and DC decoupling amplifier fCCO − 6.5 − MHz MCS = logic 1 − 10.7 − MHz note 1 5.5 − 7.5 MHz free-running frequency ∆fOM lock range of PLL 10.0 − 11.5 MHz RCDM output resistance for 50 µs de-emphasis pin 20 (16) 1.24 1.5 1.7 kΩ VCDM output voltage pin 20 (16) −18.5 −16.0 −14.5 dBV ∆VCDM spread of PLL output voltage over lock range pin 20 (16) − − ±1 dB RCCM input resistance of output amplifier pin 21 (17) 95 150 200 kΩ MCS = logic 1; note 1 Main channel - overall performance (output selector in position 4) VOM,OR,OL output voltage pins 23, 24 and 25 (19, 20 and 21) all PLLs locked −9 −6 −4 dBV UBM unbalance voltage outputs pins 23 to 25 (19 to 21) output selector in position 4 −0.5 − +0.5 dB THD total harmonic distortion all PLLs locked − 0.1 0.5 % S/N(A) signal-to-noise ratio A-weighted; all PLLs locked 62 70 − dB V OM ( 15 kHz ) ------------------------------V OM ( 1 kHz ) 15 kHz frequency response with respect to 1 kHz pin 23 (19) no de-emphasis connected −0.5 0 +0.5 dB ROM,OR,OL output resistance pins 23, 24 and 25 (19, 20 and 21) 92 125 150 Ω αS/M crosstalk attenuation from secondary channels to main note 2 − 74 − dB MUTEatt mute attenuation output selector in position 7 74 − − dB SVRR supply voltage ripple rejection VRR = 100 mV; fi = 70 Hz − 35 − dB October 1994 10 Philips Semiconductors Product specification Satellite sound circuit with noise reduction SYMBOL PARAMETER TDA8742; TDA8742H CONDITIONS MIN. TYP. MAX. UNIT Secondary channels 1 and 2 - HF inputs pins 2, 4, 6, 8, 10, 12, 14 and 16 (1, 3, 5, 7, 9, 11, 40 and 42) and limiters VIN1,IN2(rms) input sensitivity (RMS value) − 0.8 1.5 mV Vi(rms) input signal level (RMS value) − − 200 mV Ri input resistance 260 330 380 Ω S/N(A) = 40 dB Secondary channels 1 and 2 - PLL FM demodulators (input selector in position 1) fCCO1 free running frequency PLL1 − 10.7 − MHz fCCO2 free running frequency PLL2 − 10.52 − MHz ∆fOS1/2 lock range of PLLs 10 − 11.5 MHz RS1, S2 series resistance for optimum frequency response adjustment 0 0.68 2.2 kΩ VCDCL,CDCR(rms) PLL output voltage pins 40 and pins to be left open-circuit − 42 (36 and 38) (RMS value) 9 − mV ∆VCDCL,CDCR spread of PLL output voltage over lock range − − ±1 dB note 3 Secondary channels - overall performance of LPF and NR (output selectors in position 1) Ro output resistance for 75 µs de-emphasis pins 36 and 32 (32 and 28) 1.9 2.3 2.6 kΩ Ri input resistance of output amplifiers pins 35 and 33 (31 and 29) 95 150 200 kΩ VOL,OR output voltage level pins 25 and 24 (21 and 20) note 4 −8 −6 −4 dBV UBS unbalance voltage outputs pins 25 and 24 (21 and 20) note 4 −1 − +1 dB THD total harmonic distortion note 4 − 0.1 0.5 % S/N(A) signal-to-noise ratio A-weighted; note 4 72 80 − dB Ro output resistance pins 25 and 24 (21 and 20) note 4 92 125 150 Ω MUTEatt mute attenuation output selector in position 6; note 4 74 − − dB αS/S crosstalk attenuation between secondary channels note 5 − 74 − dB αM/S crosstalk attenuation from main note 6 channel to secondary − 74 − dB Voffset(DC) DC offset voltage on attack/recovery capacitors pins 29, 39 (25, 35) all PLLs locked; ∆f = 0 14 16 20 mV SVRR supply voltage ripple rejection VRR = 100 mV; fi = 70 Hz − 25 − dB October 1994 11 Philips Semiconductors Product specification Satellite sound circuit with noise reduction SYMBOL PARAMETER TDA8742; TDA8742H CONDITIONS MIN. TYP. MAX. UNIT Secondary channels - low-pass filter pins 38 and 30 (34 and 26) V RECTL, RECTR ( 50 kHz ) ----------------------------------------------------------V RECTL, RECTR ( 1 kHz ) 50 kHz frequency response with respect to 1 kHz note 7 −25 −16 −9 dB Secondary channels - noise reduction pins 25 and 24 (21 and 20); note 4 VOL, OR output voltage at 0 dB noise reduction input level ∆fS1 = ∆fS2 = 50 kHz; no fixed de-emphasis connected −1 +1 +3 dBV V OL, OR ( 15 kHz ) --------------------------------------V OL, OR ( 1 kHz ) 15 kHz frequency response with respect to 1 kHz at 0 dB noise reduction input level ∆fS1 = ∆fS2 = 50 kHz; no fixed de-emphasis connected −2 0 +2 dB VOL,OR output voltage at −20 dB noise reduction input level ∆fS1 = ∆fS2 = 5 kHz; no fixed de-emphasis connected −29 −26 −23 dBV V OL, OR ( 15 kHz ) --------------------------------------V OL, OR ( 1 kHz ) 15 kHz frequency response ∆fS1 = ∆fS2 = 5 kHz; with respect to 1 kHz at −20 dB no fixed de-emphasis connected noise reduction input level −13 −11.5 −10 dB External inputs - pin 28 (24) (left) and pin 27 (23) (right) - overall performance (output selector in position 5) − − 6 95 150 200 kΩ −6.5 −6.0 −5.5 dBV − − 0.1 % A-weighted; VEXTR, EXTL = −6 dBV 80 − − dB fi = 1 kHz − 80 − dB VEXTR,EXTL input signal level Ri input resistance VOL,OR output level VEXTR, EXTL = −6 dBV THD total harmonic distortion VEXTR, EXTL = −6 dBV; fi = 1 kHz S/N(A) signal-to-noise ratio αL/R,αR/L crosstalk dBV Input selector control circuit pins 3 and 5 (41 and 43) (see also Table 1) and secondary channels PLLs disable [SCD pin 11 (6)]; pin 11 (6); pins left open-circuit = logic HIGH VIL LOW level input voltage VIH HIGH level input voltage Ri input resistance October 1994 connected to VP 12 0 − 1.2 V 3.5 − 9 V 65 100 130 kΩ Philips Semiconductors Product specification Satellite sound circuit with noise reduction SYMBOL PARAMETER TDA8742; TDA8742H CONDITIONS MIN. TYP. MAX. UNIT Output selector control circuit (see also Table 2) and main channel PLL lock-in select [MCS pin 7 (2)]; pins 15, 17, 26, 13 and 7 (10, 13, 22, 8 and 2) MOS inputs and should not be left open-circuit VIL LOW level input voltage limits 0 − 1.2 V VIM MID level input voltage limits for MCS pin only 1.8 − 2.8 V VIMF MID level input voltage on MCS pin if MCS pin is floating 17 19 21 %VP VP must be 1.8 to 13.2 V VIH HIGH level input voltage limits 3.5 − VP V RIL low input resistance MCS pin to ground 12 19 26 kΩ RIH high input resistance MCS pin to VP 52 80 108 kΩ IIL LOW level input current (not MCS pin) VIL = 0 V − <−1 − µA IIH HIGH level input current (not MCS pin) VIH = 5 V − <1 − µA Notes 1. At pin 20 (16) the demodulated 1 kHz signal should be present with a typical level of 158 mV (RMS) (−16 dBV), and THD of maximum 0.5%; VP = 8 to 3.2 V; Tamb = −20 to +70 °C. 2. Modulation of main channel is OFF; modulation of secondary channels is ON. 3. The electrolytic capacitors at pins 40 and 42 (36 and 38) are removed and 1500 pF capacitors between pin 40 (36) and ground and between pin 42 (38) and ground are connected. At pins 40 and 42 (36 and 38) the demodulated 1 kHz signals should be present with typical levels of 9 mV (RMS) and THD of maximum 0.5%; VP = 8 to 3.2 V; Tamb = −20 to +70 °C. 4. All PLLs locked; RS1 = RS2 = 0.68 kΩ. 5. Modulation of secondary channel being measured and main channel is OFF; modulation of other secondary channel is ON. 6. Modulation of main channel is ON; modulation of secondary channels is OFF. 7. Measured at pins 38 (34) (left) and 30 (26) (right) and no electrolytic capacitors connected to these pins. October 1994 13 Philips Semiconductors Product specification Satellite sound circuit with noise reduction Table 1 Truth table for input selection SWITCH POSITION Table 2 TDA8742; TDA8742H STATE PIN 3 (41) PIN 5 (43) 1 pins 2 and 10; IN-A (pins 40 and 5) 0 0 2 pins 4 and 12; IN-B (pins 42 and 7) 0 1 3 pins 6 and 14; IN-C (pins 1 and 9) 1 0 4 pins 8 and 16; IN-D (pins 3 and 12 1 1 Truth table for output selection (note 1) SWITCH POSITION PIN 15 (10) PIN 17 (13) PIN 26 (22) PIN 13 (8) OUTSEL L OUTSEL R EXT/INT MUTE STATE 1 stereo 1 1 0 0 2 left 1 0 0 0 3 right 0 1 0 0 4 main 0 0 0 0 5 external X X 1 0 6 mute secondary X X 0 1 7 mute all X X 1 1 Note 1. X = don’t care. October 1994 14 Philips Semiconductors Product specification TDA8742; TDA8742H The pin numbers in parenthesis refer to the QFP44 package. Fig.4 Test circuit. Satellite sound circuit with noise reduction October 1994 15 Philips Semiconductors Product specification Satellite sound circuit with noise reduction APPLICATION INFORMATION General This application is mainly intended to have more than two inputs for secondary channel available. In this event a choice between the same frequency sets e.g. 10.7 and 10.52 MHz but with different bandwidths is possible. A narrow bandwidth can be chosen in the event of a weak signal, however this produces slightly more distortion. A normal signal will be processed using 150 kHz filters thus resulting in a signal with normal distortion. For the main channel either baseband or synthesized signal can be selected. The circuit is illustrated in Fig.5. October 1994 16 TDA8742; TDA8742H Philips Semiconductors Product specification TDA8742; TDA8742H The pin numbers in parenthesis refer to the QFP44 package. Fig.5 Application diagram. Satellite sound circuit with noise reduction October 1994 17 Philips Semiconductors Product specification Satellite sound circuit with noise reduction TDA8742; TDA8742H seating plane PACKAGE OUTLINES handbook, full pagewidth 39.0 38.4 15.80 15.24 4.57 5.08 max max 3.2 2.9 0.51 min 1.73 max 0.53 max 1.778 (40x) 0.18 M 0.32 max 15.24 17.15 15.90 1.3 max 22 42 MSA268 - 1 14.1 13.7 1 21 Dimensions in mm. Fig.6 Plastic shrink dual in-line package; 42 leads (600 mil); SDIP42; SOT270-1. October 1994 18 Philips Semiconductors Product specification Satellite sound circuit with noise reduction TDA8742; TDA8742H handbook, full pagewidth seating plane S 0.1 S 12.9 12.3 44 1.2 (4x) 0.8 34 B 33 1 pin 1 index 0.15 M B 0.8 11 23 12 10.1 9.9 12.9 12.3 0.40 0.20 22 0.8 0.40 0.20 1.2 (4x) 0.8 0.15 M A 10.1 9.9 X A 0.85 0.75 1.85 1.65 0.25 0.14 0.25 0.05 MBB944 - 2 detail X 0.95 0.55 2.10 1.70 0 to 10 o Dimensions in mm. Fig.7 Plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm (QFP44; SOT307-2). October 1994 19 Philips Semiconductors Product specification Satellite sound circuit with noise reduction TDA8742; TDA8742H SOLDERING BY SOLDER PASTE REFLOW Plastic dual in-line packages Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. BY DIP OR WAVE The maximum permissible temperature of the solder is 260 °C; this temperature must not be in contact with the joint for more than 5 s. The total contact time of successive solder waves must not exceed 5 s. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 °C. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 °C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING IRON OR PULSE-HEATED SOLDER TOOL) REPAIRING SOLDERED JOINTS Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 °C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 °C. (Pulse-heated soldering is not recommended for SO packages.) Apply the soldering iron below the seating plane (or not more than 2 mm above it). If its temperature is below 300 °C, it must not be in contact for more than 10 s; if between 300 and 400 °C, for not more than 5 s. Plastic quad flat packages BY WAVE For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement. During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 °C within 6 s. Typical dwell time is 4 s at 250 °C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. October 1994 20 Philips Semiconductors Product specification Satellite sound circuit with noise reduction TDA8742; TDA8742H DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. October 1994 21