INTEGRATED CIRCUITS DATA SHEET SAA7284 Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems Preliminary specification File under Integrated Circuits, IC02 1996 Oct 24 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 FEATURES • Single-chip solution including FM and vision filters, analog demodulator and audio switching • Dual standard with automatic selection between PAL system I and BGH • Suitable for conventional intercarrier PLL-IF (single SAW) TV/VCR systems The SAA7284 takes, as input, a second IF (intercarrier) Terrestrial TV PAL signal, and performs all the Differential Quadrature Phase Shift Keying (DQPSK) demodulation, digital decoding and digital-to-analog conversion necessary to produce a complete NICAM receiver on a single integrated circuit. • Single low-radiation crystal oscillator for improved EMC • Stereo bitstream audio DACs • Programmable attenuator for matching levels of NICAM and FM audio sources at the output of the device • Full EBU specification NICAM 728 demodulation and decoding The demodulator function includes integrated baseband filters for pulse shaping and unwanted signal rejection, automatic gain control, a low jitter integrated VCO, digital monostables for precise data sampling points and a multi-standard controller to enable automatic locking to either a PAL system I or PAL system BGH input signal. • Digital Audio Interface conforming with EBU/IEC 958 • Automatic mute function which switches from NICAM to FM sound when NICAM fails • Compatible with either single-ended or differential DQPSK input signals • Microcomputer controlled via specification). I2C-bus The decoder function performs the descrambling, de-interleaving and reformatting operations required to recover the original data words. (up to 400 kHz The data words are processed through a stereo digital filter, digital de-emphasis network, second order noise shaper and 256 times oversampling Bitstream audio DAC. APPLICATIONS • Television receivers • Video cassette recorders. GENERAL DESCRIPTION Philips Semiconductors have pushed the boundaries of Stereo Sound further with this addition to the successful Terrestrial Digital Sound Decoder family. The SAA7284 device is an application specific version of the existing SAA7283, with guaranteed improved specification on selected parameters, enabling comparable RF performance in conventional intercarrier PLL-IF systems, to that of the SAA7283 in QSS systems. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7284ZP SDIP52 plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1 SAA7284GP QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 × 20 × 2.8 mm SOT319-2 1996 Oct 24 DESCRIPTION 2 VERSION Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDD supply voltage 4.5 5.0 5.5 V IDD supply current − 205 − mA fclk clock frequency − 8.192 − MHz Tamb operating ambient temperature −20 +25 +70 °C 1996 Oct 24 3 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 BLOCK DIAGRAM DQPSK handbook, full pagewidth V DDF1 V SSF1 COFF CEYE VDDF2 VSSF2 REMO REMVE I REF VROF VRCF CLKLPF DATAOUT DATAIN XTAL OSC VSSX SDA SCL ADSEL MIXREF 29 25 28 23 30 31 38 22 QUADRATURE MIXERS, BASEBAND FILTERS AND AGC GAIN STAGE COSINE 21 SOFF SEYE SINE 39 17 16 CARRIER LOOP PHASE DETECTOR AND DATA SLICERS AGC CONTROLLER BITRATE CLOCK RECOVERY CARRIER LOOP QUADRATURE VCO 34 PKDET 36 35 37 41 46 27 24 VCONT VCLK 45 42 43 47 CRYSTAL OSCILLATOR 50 NICAM 728 DECODER AND DEVICE CONTROLLER 44 54 53 55 56 57 14 I2 C 15 PCLK RESET PORT2 MUTE PORM PORA SAA7284GP DOBM 59 VDDD 49 VSSD 48 VSSDAC FML EXTL DIGITAL FILTER, GAIN, J17 DE-EMPHASIS DAI NOISE SHAPER (LEFT CHANNEL) NOISE SHAPER (RIGHT CHANNEL) BITSTREAM DAC (LEFT CHANNEL) BITSTREAM DAC (RIGHT CHANNEL) 8 3 12 13 VDDA 61 VSSA 62 VROA 7 VRCA 63 2 (1) OUTPUT SWITCHES AND BUFFER (LEFT CHANNEL) OUTPUT SWITCHES AND BUFFER (RIGHT CHANNEL) 11 4 MBH216 (1) Represents controller bus. OPL OPR Fig.1 Block diagram (QFP64). 1996 Oct 24 4 FMR EXTR Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 PINNING PIN SYMBOL DESCRIPTION SDIP52 QFP64(1) MUTE 1 57 active LOW mute input; function defined by MUTEDEF (control bit in the I2C-bus register) DOBM 2 59 digital audio interface output that can be 3-stated via I2C-bus VDDA 3 61 analog supply voltage for the audio channels VSSA 4 62 analog ground connection for the audio channels VRCA 5 63 internal audio reference voltage buffer (high-impedance node) EXTR 6 2 external analog input to the right audio channel FMR 7 3 FM sound input to the right audio channel OPR 8 4 analog output from the right audio channel n.c. 9 and 10 9 and 10 not connected; left open-circuit in application VROA 11 7 internal audio reference voltage buffer output VSSDAC 12 8 quiet ground connection to DACs n.c. 13 and 14 − not connected; left open-circuit in application OPL 15 11 analog output from the left audio channel FML 16 12 FM sound input to the left audio channel EXTL 17 13 external analog input to the left audio channel PORM 18 14 active LOW power-on reset mute input; mute cleared by setting silence bit HIGH in I2C-bus (internal pull-up) PORA 19 15 power-on reset audio select input (internal pull-up) REMVE 20 16 carrier loop-filter connection REMO 21 17 carrier loop-filter output SEYE 22 21 sine channel eye pattern output for monitoring SOFF 23 22 sine channel offset compensator capacitor output VSSF1 24 23 demodulator ground connection 1 VCLK 25 24 carrier loop VCO clock output for monitoring VDDF1 26 25 demodulator supply voltage 1 VCONT 27 27 carrier loop VCO control voltage input MIXREF 28 28 mixer voltage reference or input when using differential DQPSK signal DQPSK 29 29 DQPSK input signal COFF 30 30 cosine channel offset compensator capacitor output CEYE 31 31 cosine channel eye pattern output for monitoring PKDET 32 34 AGC peak detector storage capacitor output VROF 33 35 internal demodulator reference voltage buffered output IREF 34 36 internal demodulator reference current output VRCF 35 37 internal demodulator reference voltage unbuffered output VDDF2 36 38 demodulator supply voltage 2 VSSF2 37 39 demodulator ground connection 2 n.c. 38 40 not connected; left open-circuit in application CLKLPF 39 41 clock loop-phase comparator output 1996 Oct 24 5 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 PIN SYMBOL SDIP52 DESCRIPTION QFP64(1) XTAL 40 42 8.192 MHz crystal oscillator input OSC 41 43 8.192 MHz crystal oscillator output VSSX 42 44 crystal oscillator ground connection DATAIN 43 45 serial data input at 728 kbits/s to decoder VSSD 44 48 digital ground connection PCLK 45 47 728 kHz output clock to DQPSK demodulator VDDD 46 49 digital supply voltage RESET 47 50 active LOW power-on reset input DATAOUT 48 46 serial data output at 728 kbits/s from DQPSK demodulator SCL 49 53 serial clock input for I2C-bus SDA 50 54 serial data input/output for I2C-bus ADSEL 51 55 input that defines I2C-bus address bit 0 (internal pull-up) PORT2 52 56 output that is directly controlled from Port 2 bit in I2C-bus Note 1. Pins 1, 5, 6, 18, 19, 20, 26, 32, 33, 51, 52, 58, 60 and 64 are not connected; left open-circuit in application. 1996 Oct 24 6 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 handbook, halfpage MUTE 1 52 PORT2 DOBM 2 51 ADSEL VDDA 3 50 SDA VSSA 4 49 SCL V RCA 5 48 DATAOUT EXTR 6 47 RESET FMR 7 46 V OPR 8 45 PCLK n.c. 9 44 VSSD n.c. 10 43 DATAIN VROA 11 42 VSSX VSSDAC 12 41 OSC 40 XTAL 39 CLKLPF OPL 15 38 n.c. FML 16 37 VSSF2 EXTL 17 36 VDDF2 PORM 18 35 VRCF PORA 19 34 I REF REMVE 20 33 VROF n.c. 13 n.c. 14 DDD SAA7284ZP REMO 21 32 PKDET SEYE 22 31 CEYE SOFF 23 30 COFF VSSF1 24 29 DQPSK VCLK 25 28 MIXREF V DDF1 26 27 VCONT MBH217 Fig.2 Pin configuration for SOT247. 1996 Oct 24 7 Philips Semiconductors Preliminary specification 52 n.c. n.c. 1 51 n.c. EXTR 2 50 RESET FMR 3 49 VDDD OPR 4 48 VSSD n.c. 5 47 PCLK n.c. 6 46 DATAOUT VROA 7 45 DATAIN VSSDAC 8 44 VSSX n.c. 9 43 OSC 42 XTAL OPL 11 41 CLKLPF FML 12 40 n.c. EXTL 13 39 VSSF2 PORM 14 38 VDDF2 15 37 VRCF REMVE 16 36 I REF REMO 17 35 VROF n.c. 18 34 PKDET n.c. 19 33 n.c. Fig.3 Pin configuration for SOT319. 8 n.c. 32 CEYE 31 COFF 30 DQPSK 29 MIXREF 28 VCONT 27 n.c. 26 24 VCLK V SSF1 23 SOFF 22 SEYE 21 n.c. 20 PORA V DDF1 25 SAA7284GP n.c. 10 1996 Oct 24 53 SCL 54 SDA 55 ADSEL SAA7284 56 PORT2 57 MUTE 58 n.c. 59 DOBM 60 n.c. 61 V DDA 62 V SSA 64 n.c. handbook, full pagewidth 63 V RCA Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems MBH218 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 FUNCTIONAL DESCRIPTION NICAM 728 decoding DQPSK demodulation DECODING FUNCTIONS QUADRATURE MIXERS, BASEBAND FILTERS AND AUTOMATIC (AGC) The device performs all decoding functions in accordance with the EBU NICAM 728 specification. After locking to the frame alignment word, the data is de-scrambled by application of the defined pseudo random binary sequence, and the device synchronizes to the periodic frame flag bit C0. GAIN CONTROL The DQPSK signal is fed into two differential input mixers, where it is mixed with quadrature phases generated by the carrier-loop quadrature VCO. The quadrature signals modulated onto the NICAM carrier are thus recovered. The relevant control information and scale factor word is extracted, and with the integrated RAM the data is de-interleaved and the scale factor word is extracted, and expanded to 14 bits. Parity checking on the eleventh bit of each sample word is carried out to reveal any sound sample errors, which if detected are flagged, with the last good sample being held. The mixers can be driven by either a single-ended or differential source. In single-ended mode, the device is driven directly from the sound IF down-converter into the DQPSK input pin, with the MIXREF pin decoupled. In differential mode, the signal is applied between the DQPSK and MIXREF pins. The outputs from the mixers are then fed into a pulse-shaping filter, and FM/vision filter stage with improved colour rejection to allow suitable performance with SAW filters. The signal from the filtering stages is then fed into the AGC, which ensures that the phase comparator gain remains constant, irrespective of the input signal level. This is important to maintain the stability of Costas loop PLL. Automatic muting Enable when AMDIS = LOW. The I2C-bus section has two registers which define an upper and lower limit for the automatic muting function. When the number of errors within a 128 ms period exceeds the number stored in the upper error limit register, then the automatic muting will switch the device output to the FM input, (dependent on the relevant control bits in the I2C-bus) and mute (set to zero) the data input to the filter (in that order). When the error count in a 128 ms period is less than the value stored in the lower error limit register then the data into the filter is uninterrupted, and the device output is switched back to the DAC (dependent on the value of the relevant control bits in the I2C-bus). During the muting operation the open-drain pin MUTE is pulled LOW and the AM bit in the status-byte is set HIGH. Figure 4 shows the dependency of the automatic muting function on error_count, RSSF, C4OV, output state and application mode. The automatic muting function, if enabled, will override user mute via the MUTE pin/bit. AGC CONTROLLER The AGC controller monitors the I and Q channel signals at the input to the carrier loop-phase comparator and generates a reference voltage to set the AGC output level. EYE BUFFER A differential to the single-ended converter provides the baseband signal as an output at the pins CEYE and SEYE for the I and Q channels respectively for eye-height monitoring. BIT RATE CLOCK RECOVERY When the transmission is DATA format or currently undefined format (C3 = logic 1) the device will automatically switch to the FM inputs regardless of RSSF/C4OV states, and whether the automatic muting function AMDIS is enabled or disabled. The I and Q channels are processed using edge detectors and monostables, which generate a signal with a coherent component at the data symbol rate. The outputs from the I and Q channel monostables are each compared with the clock derived from PCLK (364 kHz nominal), the resultant output is used to derive a 3-state control signal used to control two current sources at the CLKLPF output. This error signal is loop filtered and used to control the master clock oscillator. The bit rate clock, PCLK, and symbol clock are derived from the master clock. 1996 Oct 24 9 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 User mute Power-on reset state The error counter is an 8-bit counter which locks at count 255. The counter is reset and its output sent to the I2C-bus every 128 ms. This enables the user to interrogate the number of errors occurring within a 128 ms period. The user can then mute the device by pulling pin MUTE LOW (this function is also provided by the MUTE bit in the I2C-bus) or setting SILENCE bit LOW in I2C-bus to switch input of audio switching buffers to analog ground. Two pins control the initial set-up of the device during power-on reset. PORA (Power-On Reset Audio) When pulled LOW the device will be configured with a 12 dB gain in the oversampling filter and the C4OV bit in the I2C-bus will be set HIGH. This pin when HIGH will configure the device with a 6 dB gain in the oversampling filter and will set C4OV bit in the I2C-bus LOW. Switching buffers PORM (Power-On Reset Mute) The analog switches select between the output of the DACs, the FM input and an external input (EXT). Switching is controlled by bits in the I2C-bus and internal switching function. The external analog inputs should be ≤1.1 V (RMS) at the input pin, and the output buffers have a voltage drive of 1 V (RMS). This pin when LOW will mute the output of the device at power-on by setting the SILENCE bit in the I2C-bus LOW. To put the device back into a normal mode of operation the SILENCE bit in the I2C-bus must be set HIGH. NICAM/FM audio level matching Differing audio headroom and alignment levels occur between systems I and BGH, due to the differing systems and broadcast standards. In order to match the NICAM and FM audio output levels without requiring application changes, the device will automatically switch in 4.6 dB attenuation network in the NICAM path for system BGH (this can be disabled by setting the NICLEV bit LOW in I2C-bus). A programmable attenuation network in the FM path only, controlled by bits in I2C-bus, provides additional flexibility for user to match FM and NICAM audio levels (see Table 9). 1996 Oct 24 10 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 handbook, full pagewidth ERROR_COUNT ERROR_MAX NO Output is unchanged AM bit = LOW MUTEB pin = HIGH YES RSSF = 1 NO C4ov BIT = 0 NO Output is unchanged AM bit = LOW MUTEB pin = HIGH YES EXT or FM INPUT SWITCHED IN YES YES When error_count is less than error_min, AM bit = LOW, MUTEB pin = HIGH Output is unchanged AM bit = HIGH (1) MUTEB pin = LOW (1) NO SOUND APPLICATION DUAL MONO NO Output is switched to FM input AM bit = HIGH MUTEB pin = LOW YES DUAL MONO MODE LEFT = RIGHT = M1 SELECTED YES NO Output is unchanged AM bit = LOW MUTEB pin = HIGH MGB465 When error_count is less than error_min, the output is switched back to NICAM and AM bit = LOW, MUTEB pin = HIGH (1) Indicating that a mute may occur when user returns to NICAM source. Fig.4 Flow diagram showing SAA7284 automatic muting function. 1996 Oct 24 11 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 I2C-BUS FORMATS The SAA7284 contains an I2C-bus slave transceiver (up to 400 kHz) permitting a master device to: • Read decoder status information derived from the transmitted digital audio signal • Read an error count byte to determine the bit error rate for user mute purposes and to indicate quality of NICAM signal • Write control codes to select PAL I or PAL BGH configurations • Write control codes to select the available analog switching configurations • Write upper and lower error count limits for automatic muting function • Read additional transmitted data bits. Their purpose has yet to be defined but accessibility is provided to allow future services to be implemented in receiver software. I2C-bus slave address An address select pin (ADSEL) is provided to allow selection of one of two different slave addresses. The logic state of the ADSEL pin is reflected in the least significant bit of the I2C-bus slave address. Slave address = 101101X (R/W) [ADSEL = 1, address = B6 (R/W) ADSEL = 0, address = B4 (R/W)]. Table 1 SAA7284 slave address BITS A7 A6 A5 A4 A3 A2 A1 A0 1 0 1 1 0 1 selected by ADSEL read/write The SAA7284 does not acknowledge the I2C-bus general call address. Slave receiver format The slave receiver format is shown in Table 2. Table 2 Slave receiver format START Table 3 slave_addr ACK sub_addr ACK data_byte ACK n-bytes data_byte ACK STOP Explanation of Table 2 ITEM DESCRIPTION START I2C-bus Slave_addr 101101XW X logic 0 when ADSEL = 0; logic 1 when ADSEL = 1 W logic 0, I2C-bus write to slave receiver ACK I2C-bus acknowledge condition generated by slave receiver Sub_addr sub-address range 00 to 04 (HEX) Data_byte data byte transmitted to slave receiver STOP I2C-bus stop condition start condition The sub-address is auto-incremented by the SAA7284, for each data byte received. When the sub-address is equal to 04 (HEX), on reception of the next data byte, the sub-address will reset to 00 (HEX). 1996 Oct 24 12 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 I2C-bus slave receiver register map Table 4 Slave receiver data byte SUB-ADDRESS D7 D6 D5 D4 D3 D2 D1 D0 000 M1/M2 DMSEL SSWIT3 SSWIT2 SSWIT1 PORT2 MUTEDEF AMDIS 001 EMAX7 EMAX6 EMAX5 EMAX4 EMAX3 EMAX2 EMAX1 EMAX0 010 EMIN7 EMIN6 EMIN5 EMIN4 EMIN3 EMIN2 EMIN1 EMIN0 011 C4OV MUTE SILENCE DAIE FM3 FM2 FM1 FM0 100 ASYS BG/I NICLEV STLOCK − − − − M1/M2 AMDIS This bit selects either mono channel M1 or M2 to be the output on the left and right channel dependent on the transmitted control bits C1 and C2 indicating a mono transmission and the value of bit DMSEL (see Table 5). Power-on resets to logic 1. This bit enables and disables the automatic mute function. Power-on resets to enabled = LOW. EMAX7 TO EMAX0 This is the upper error limit register which defines the number of errors in 128 ms period which will cause automatic mute to switch IN. User definable, but power-on resets to 50 (HEX). DMSEL DMSEL is the dual mono selection bit, for transmissions consisting of two independent mono signals. Selection is in conjunction with M1/M2 (see Table 5). Power on resets to logic 0. EMIN7 TO EMIN0 This is the lower error limit register which defines the number of errors in 128 ms period which will cause automatic mute to switch OUT. User definable, but power-on resets to 14 (HEX). SSWIT1, SSWIT2 AND SSWIT3 These bits control the analog switching, selecting between the FM, external, and NICAM signals. With the NICAM source the signals select whether the de-emphasis is performed and what gain is applied after the filtering and de-emphasis stage. The signal states and their meaning are listed in Table 7. Power-on resets to 010 with PORA pin HIGH, and to 011 with PORA pin LOW. C4OV When set LOW this bit overrides the status of the transmitted C4-bit when muting. When this bit is HIGH muting takes place in accordance with EBU specification. Power-on resets to HIGH when the PORA pin is held LOW during power-up, and power-on resets to LOW when PORA is HIGH. PORT2 PORT2 controls a bit out, providing direct access to a dedicated output pin (PORT2) via the I2C-bus. See Table 6. Power-on resets to logic 0. MUTE This reflects the function of the MUTEB pin. When this bit is set LOW the external MUTEB pin is pulled LOW and the action is dependent on the MUTEDEF bit (see Table 8). Power-on resets to HIGH. MUTEDEF This defines the operation of the user definable MUTE pin or MUTE I2C-bus bit when it is pulled LOW externally or set LOW in the I2C-bus respectively. SILENCE pin/I2C-bus When this bit is HIGH, pulling the MUTE bit LOW will mute (set to zero) the digital data and switch the output to the FM input, depending on relevant control bits (see Table 8). When this bit is LOW, pulling the MUTE pin/I2C-bus bit LOW will only mute the digital data under the same conditions. Power-on resets to LOW. 1996 Oct 24 When set LOW this bit silences the outputs of the device by switching the input of the audio switching buffers to analog ground. When the PORM pin is held LOW at power-on reset the silence bit is initialized to zero. With PORM bit HIGH the silence bit is initialized HIGH. 13 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems 4.6 dB (if NICLEV is set HIGH). When LOW, the DQPSK demodulator switches to system I (with no 4.6 dB attenuation). Power-on resets to HIGH. DAIE When set HIGH this bit switches in the Digital Audio Interface output to the DOBM pin. When set LOW the DOBM output is 3-stated. Power-on resets to HIGH. NICLEV When this bit is set LOW it overrides the 4.6 dB NICAM audio level compensation, irrespective of whether the device is in automatic or manual system mode. When set HIGH the 4.6 dB compensation level is applied in system BGH. Power-on resets to HIGH. FM3 TO FM0 These bits set the level of attenuation of the FM audio signal (see Table 9). Power-on resets 0000 = 0 dB attenuation. ASYS STLOCK When this bit is HIGH it activates the automatic standard switch mode. When set LOW, the standard must be set by the BG/I bit. Power-on resets to HIGH. When STLOCK is set HIGH it will stop the automatic system switch after the device has achieved an INSYNC condition, should the demodulator lose lock at any time. This minimizes the re-acquisition time. When set LOW the device will be permitted to change system after an INSYNC condition has been reached. Power-on resets to LOW. BG/I When this bit is HIGH it switches the DQPSK demodulator to system BGH and attenuates the digital audio level by Table 5 SAA7284 Output as a function of M1/M2 and DMSEL Table 6 Port 2 control DMSEL M1/M2 FUNCTION PORT2 PIN OUTPUT STATE 0 0 selects DIGITAL; L = M2, R = M2 0 LOW 0 1 selects DIGITAL; L = M1, R = M1 1 HIGH 1 0 selects DIGITAL; L = M2, R = M1 1 1 selects DIGITAL; L = M1, R = M2 Table 7 SSWIT signal states and function SSWIT3 SSWIT2 SSWIT1 FUNCTION 0 0 0 NICAM source de-emphasis switched out, no gain 0 0 1 NICAM source de-emphasis switched in, no gain 0 1 0 NICAM source de-emphasis switched in, +6 dB gain; power-on reset when PORA = HIGH 0 1 1 NICAM source de-emphasis switched in, +12 dB gain; power-on reset when PORA = LOW 1 X(1) 0 external inputs switched in, no change to previous de-emphasis/gain setting 1 X 1 FM inputs switched in, no change to previous de-emphasis/gain setting Note 1. Where X = don’t care. 1996 Oct 24 14 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 Action of pulling MUTE pin/I2C-bus bit LOW Table 8 TRANSMITTED C4 BIT (RSSF) OUTPUT ACTION(1) C4OV TRANSMISSION MODE MUTEDEF = 1 MUTEDEF = 0 1 1 or 0 stereo/mono/dual mono with L and R = M1 mute digital data and switch to FM mute digital data only 1 1 or 0 dual mono with M2 selected in either L or R no action no action 0 1 all modes no action no action 0 0 all modes mute digital data and switch to FM mute digital data only Note 1. With MUTE pin/i2C-bus bit pulled LOW. If user has manually selected FM or NICAM inputs, no switching will occur. Table 9 FM attenuation control FM ATTENUATION (dB) FM3 FM2 FM1 FM0 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 Not defined 1 1 0 1 Not defined 1 1 1 0 Not defined 1 1 1 1 Slave transmitter format The slave transmitter format is shown in Table 10. Table 10 Slave transmitter format START 1996 Oct 24 slave_addr ACK data_byte ACK 15 n-bytes data_byte ACK STOP Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 Table 11 Explanation of Table 10 ITEM DESCRIPTION START I2C-bus start condition Slave_addr 101101XR X logic 0 when ADSEL = 0; logic 1 when ADSEL = 1 R logic 1, I2C-bus read from slave transmitter ACK I2C-bus acknowledge condition generated by slave receiver Data_byte data byte transmitted from slave receiver ACK master device negative acknowledge to indicate last byte STOP I2C-bus stop condition I2C slave transmitter register map The bus master can perform single-byte, two-byte, three-byte, four-byte or five-byte read in the order shown in Table 12. Table 12 Slave transmitter data byte BYTE STATUS BYTE 1 ERROR BYTE D7 D6 D5 D4 D3 D2 D1 D0 PONRES S/M D/S VDSP RSSF OS AM CFC ERR7 ERR6 ERR5 ERR4 ERR3 ERR2 ERR1 ERR0 AD BYTE 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 AD BYTE 1 OVW SAD 0 CI1 CI2 AD10 AD9 AD8 C1 C2 C3 BG/I 0 0 0 0 STATUS BYTE 2 PONRES OS When set HIGH this bit indicates that a power-on reset has occurred. It is cleared after the status byte has been read. When HIGH this bit indicates that the device has both frame and C0 (16 frame) synchronization. S/M AM This bit gives the stereo or mono broadcast indication. Set HIGH indicates stereo transmission. When HIGH this bit indicates that the automatic mute function has switched from NICAM to FM. When LOW the automatic mute function has not activated a switch. D/S CFC When HIGH this bit indicates a dual mono broadcast. When LOW this bit indicates a configuration change at the C0 (16 frame) boundary. It is reset after reading the status byte. VDSP When this bit is HIGH, it indicates that the digital data transmission is a sound source. When LOW the transmission is either data or undefined format. ERR7 TO ERR0 These bits indicate the number of errors occurring in the previous 128 ms period. RSSF This bit reflects the state of the C4 bit in the NICAM transmission. When set LOW, the FM sound content does not match the digital transmission, and switching to FM by automatic mute or setting MUTE LOW is prevented (if C4OV = HIGH). 1996 Oct 24 AD7 TO AD0 These bits contain the eight least significant additional data bits. 16 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 OVW AD10, AD9 AND AD8 This bit is set when new additional data bits are written to the I2C-bus without the previous bits being read. These are the three most significant additional data bits. C1, C2 AND C3 SAD These are the transmitted control bits, see Table 13. This bit is set HIGH when new additional data is written into the I2C-bus, and cleared by the action of reading the data. BG/I When set HIGH this bit indicates that the DQPSK demodulator is switched to system BGH. When LOW, indicates that DQPSK demodulator is switched to system I. CI1 AND CI2 These are the CI bits decoded by majority logic from the parity checks of the last ten samples in a frame. Indicator bits Table 13 is the truth table for the indicator bits. Table 13 Indicator bits functional truth table C1 C2 C3 S/M D/S VDSP OS Stereo 0 0 0 1 0 1 1 M1 + M2 0 1 0 0 1 1 1 M1 + data 1 0 0 0 0 1 1 Transparent data 1 1 0 0 0 0 1 Any currently undefined combination of C1, C2 and C3 0 0 0 1 Decoder unsynchronized (OS = logic 0) 0 0 0 0 TRANSMISSION 1996 Oct 24 17 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 DIGITAL AUDIO INTERFACE IEC/EBU 958 Sub-frame structure Block structure Each frame is divided into 32 time-slots numbered 0 to 31. The output is grouped into a block of 192 consecutive frames providing, for each channel the 192 channel status data bits. The start of a block is designated by a special sub-frame preamble. Time-slots 0 to 3 carry one of three permitted preambles. These are used to affect synchronization of sub-frames, frames and blocks. Time-slots 4 to 27 carry the audio sample word in linear two's complement representation. The most significant bit is carried by time-slot 27. Frame structure Each frame is uniquely composed of two sub-frames. The rate of transmission of frames corresponds exactly to the source sampling frequency. In the 2-channel operation, samples taken from both channels are transmitted by time multiplexing in consecutive sub-frames. Sub-frames related to Channel 1 (left or ‘A’ channel in stereophonic operation and primary channel in monophonic operation) normally use preamble M. However the preamble is changed to preamble B once every 192 frames. This defines the block structure used to organize the channel status information. Sub-frames of Channel 2 (right or ‘B’ channel in stereophonic operation and secondary channel in monophonic operation) always use preamble W. handbook, full pagewidth M W channel 1 channel 2 B Time-slot 28 carries the validity flag associated with the audio sample word. This flag is set to logic 0 if the audio sample is reliable. If set to logic 1 then the sample is unreliable. Time-slot 29 carries one bit of the user data channel. In this application this is not used and so is set to logic 0. Time-slot 30 carries one bit of the channel status word associated with the audio channel transmitted in the same sub-frame. Time-slot 31 carries a parity bit such that time-slots 4 to 31 inclusive will carry an even number of ones and an even number of zeros. channel 1 sub-frame frame 191 W channel 2 M channel 1 W channel 2 sub-frame frame 1 frame 0 start of block MLB155 Fig.5 Frame format. 3 4 0 sync preamble 27 28 11 12 handbook, full pagewidth logical 0 bits L S B M S B audio sample word MLB156 validity flag user data = logic 0 channel status parity bit Fig.6 Sub-frame structure. 1996 Oct 24 18 31 V U C P Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems Channel coding SAA7284 Table 15 Preambles Time-slots are encoded as biphase mark data. Each bit transmitted is represented by a symbol comprising two consecutive binary states. The first state of a symbol is always different from the second state of the previous symbol. The second state of the symbol is identical to the first if the bit being transmitted is logic 0, however it is different if the bit is logic 1 (see Table 14). PRECEDING STATE PREAMBLE 0 TRANSMITTED BIT 1 11 00 1 10 01 CHANNEL CODING B 11101000 00010111 M 11100010 00011101 W 11100100 00011011 • Preamble B indicates the start of Channel A data and the beginning of a block CHANNEL CODING 0 1 The preambles preceding each digital audio sample are used to indicate the beginning of a sample as follows: Table 14 Channel coding PRECEDING STATE 0 • Preamble M indicates the start of Channel A data but not the beginning of a block • Preamble W indicates the start of Channel B data. Preambles Channel status Preambles are specific patterns providing synchronization and identification of the sub-frames and blocks. The channel status information is organized in 192-bit words. The first bit of each word is carried in the frame with Preamble B. The 192-bit word is organized into sections as shown in Table 16. A set of three preambles is used. These preambles are transmitted in the time allocated to four time-slots and are represented by eight successive states. The first state of the preamble is always different from the second state of the previous symbol. Depending on this state the preambles are as shown in Table 15. Table 16 Channel status codes BIT CODE DESCRIPTION 0 0 consumer 1 0 sound data 2 1 digital copy permitted 3 and 4 00 indicates digital de-emphasis switched in 11 indicates digital de-emphasis switched out 0 − 6 and 7 00 − 8 to 15 00110001 16 to 19 0000 source code (don't care) 20 to 23 0000 channel number (don't care) 24 to 27 1100 sampling frequency (32 kHz) 28 and 29 00 30 to 191 all 0s 5 1996 Oct 24 category code clock accuracy (level II) − 19 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 LIMITING VALUES In accordance with the Absolute Maximum Rating Systems (IEC 134). SYMBOL PARAMETER CONDITIONS note 1 MIN. −0.3 MAX. +6.5 UNIT VDDF1, VDDF2, VDDA supply voltage (all supplies) VSSF1, VSSF2, VSSA ground supply voltage VSSD − 0.5 VSSD + 0.5 V VI(max) maximum input voltage (any input) 0 VO(max) maximum output voltage 0 VDD V IIOK DC input or output diode current − ±20 mA IO(max) output current (each output) − ±10 mA Tamb ambient operating temperature −20 +70 °C Tstg storage temperature −55 +125 °C VDD V V electrostatic handling Vstat(HBM) Human Body Model note 2 −2000 +2000 V Vstat(MM) Machine Model note 3 −200 +200 V Notes 1. All VDD and VSS connections must be made externally to the same power supply. 2. Electrostatic handling is equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor with a 15 ns rise time. 3. Electrostatic handling is equivalent to discharging a 200 pF capacitor via a 0 Ω series resistor with a 15 ns rise time. QUALITY AND RELIABILITY This device will meet Philips Semiconductors General Quality Specification for Business group “Consumer Integrated Circuits SNW-FQ-611-Part E”. 1996 Oct 24 20 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 SYSTEM PERFORMANCE Bit Error Rate (BER) Table 17 shows input signal conditions which typically produce bit error rates of less than 10−3. Signal levels given in dB are related to the picture carrier reference level (0 dB) and based on the output level of the set up as shown in Fig.8. All measurements are at RF and using Philips Semiconductors SAA7284 Applications Board. Table 17 System performance SYSTEM I INPUT SIGNAL CONDITIONS(1) Picture carrier RF level (FM deviation = ±50 kHz) SYSTEM BG SAW A(2) SAW B(2) SAW C(3) 35 35 35 UNIT dB NICAM level with respect to picture carrier (FM deviation = ±50 kHz) −35 −34 −32 dB FM overmodulation >120 >100 >100 kHz Notes 1. Measurements made with colour bar at 100% modulation. a) FM level = −10 dB system I; −13 dB system BG. b) NICAM level = −20 dB (unless otherwise specified). 2. 10 dB sound shelf with extended bandwidth for NICAM signal. 3. 14 dB sound shelf with extended bandwidth for NICAM signal. Acquisition time Maximum acquisition time = 1 s, measured from power-on to reset in-sync condition achieved. 1996 Oct 24 21 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 CHARACTERISTICS VDD = 4.5 to 5.5 V; Tamb = −20 to +70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Digital supplies (note 1) VDDD digital supply voltage 4.5 5.0 5.5 V VSSD digital ground supply voltage − 0 − V IDDD digital supply current − 15 − mA Audio supplies (note 1) VDDA audio supply voltage 4.5 5.0 5.5 V VSSA audio ground supply voltage − 0 − V VSSDAC DAC ground supply voltage − 0 − V IDDA audio supply current − 19 − mA Demodulator supplies (note 1) VDDF1 1st front-end supply voltage 4.5 5.0 5.5 V VSSF1 1st front-end ground supply voltage − 0 − V IDDF1 1st front-end supply current − 46 − mA VDDF2 2nd front-end supply voltage 4.5 5.0 5.5 V VSSF2 2nd front-end ground supply voltage − 0 − V IDDF2 2nd front-end supply current − 125 − mA Digital inputs DATAIN (TTL/CMOS COMPATIBLE INPUT LEVELS) VIL LOW level input voltage 0 − 0.8 V VIH HIGH level input voltage 2.0 − VDD V ILI input leakage current −10 − +10 µA Ci input capacitance − − 10 pF V ADSEL, PORM AND PORA (TTL/CMOS COMPATIBLE INPUT LEVELS WITH INTERNAL PULL-UP) VIL LOW level input voltage 0 − 0.8 VIH HIGH level input voltage 2.0 − VDD V Ri(pu) input pull-up resistance − 50 − kΩ Ci input capacitance − − 10 pF RESET AND SCL (CMOS/I2C-BUS INPUT LEVELS WITH SCHMITT TRIGGER) VIL LOW level input voltage 0 − 1.5 V VIH HIGH level input voltage 3.0 − VDD V Vhys hysteresis − 0.05VDD − V ILI input leakage current −10 − +10 µA Ci input capacitance − − 10 pF 1996 Oct 24 22 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SYMBOL PARAMETER SAA7284 CONDITIONS MIN. TYP. MAX. UNIT Digital input/output SDA (I2C-BUS LEVELS WITH SCHMITT TRIGGER/OPEN-DRAIN OUTPUT) VIL LOW level input voltage 0 − 1.5 V VIH HIGH level input voltage 3.0 − VDD V Vhys hysteresis 0.05VDD − − V ILI input leakage current −10 − +10 µA Ci input capacitance − − 10 pF VOL LOW level output voltage 0 − 0.4 V CL load capacitance active pull-up − − 400 pF passive pull-up − − 200 pF IOL = +3 mA MUTE (TTL/CMOS COMPATIBLE INPUT LEVELS/OPEN-DRAIN OUTPUT WITH INTERNAL PULL-UP) VIL LOW level input voltage 0 − 0.8 V VIH HIGH level input voltage 2.0 − VDD V Ci input capacitance − − 10 pF VOL LOW level output voltage IOL = +3 mA 0 − 0.4 V IOH = −3 mA VOH HIGH level output voltage 2.4 − VDD V Ci load capacitance with active pull-up − − 50 pF Zi input impedance − 50 − kΩ Digital outputs PORT2, PCLK AND DATAOUT (PUSH-PULL OUTPUT) VOL LOW level output voltage IOL = +2 mA 0 − 0.4 V VOH HIGH level output voltage IOH = −2 mA 2.4 − VDD V CL load capacitance − − 50 pF DOBM (3-STATE PUSH-PULL OUTPUT) VOL LOW level output voltage IOL = +2 mA 0 − 0.4 V VOH HIGH level output voltage IOH = −2 mA 2.4 − VDD V CL load capacitance − − 50 pF ILI 3-state leakage current VI = 0 to VDD −10 − +10 µA − 0.5VDDF2 − V − − 10 pF − 0.5VDDF2 − V − − 10 pF ANALOG SECTION (measured at VDD = 5 V; Tamb = 25 °C) Demodulator analog references VRCF OUTPUT Vo output signal voltage Ci input capacitance supply dependent VROF OUTPUT Vo output signal voltage Ci input capacitance 1996 Oct 24 defined by VRCF 23 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SYMBOL PARAMETER SAA7284 CONDITIONS MIN. TYP. MAX. UNIT IREF OUTPUT Vo output signal voltage Ci input capacitance Isink output sink current − 0.5VDDF2 − V − − 10 pF with external 10 kΩ resistor from pin to VSSF2 − 250 − µA − 12.5 − kΩ 10 dB SAW sound shelf − 24.5 − mV 14 dB SAW sound shelf − 15.5 − mV with respect to +10 ViDQPSK; 10 dB SAW −15 +10 − dB −20 − dB +10 with respect to ViDQPSK; 14 dB SAW −11 +10 − dB defined by VRCF Signal path analog inputs DQPSK AND MIXREF Ri input resistance ViDQPSK(rms) NICAM input signal voltage Vnom (RMS value) ViDR AGC range ViCUM(rms) cumulative input signal voltage (RMS value) Ci input capacitance −16 − dB − − 464 mV − − 10 pF in-lock; system I; note 3 − 1.25 − V in-lock; system B/G; note 3 − 1.79 − V 20log10 (VCEYE/VSEYE) −2 0 +2 dB defined by VRCF − 0.5VDDF2 − V note 2 Baseband outputs CEYE AND SEYE Vo(p-p) VI/Q eye pattern output signal voltage (peak-to-peak value) channel matching COFF AND SOFF VO offset compensator DC output voltage Baseband filters SYSTEM I Afo pass band cut-off attenuation fi = 6552 MHz + 182 kHz 1.9 3.1 4.6 dB FMr FM rejection fi = 6.0 MHz ± 50 kHz − 65 − dB FMomr FM rejection (overmodulated FM) fi = 6.0 MHz ± 80 kHz 45 50 − dB CCr colour-carrier rejection fi = 4.43 MHz 70 78 − dB 1996 Oct 24 24 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SYMBOL PARAMETER SAA7284 CONDITIONS MIN. TYP. MAX. UNIT SYSTEM BGH Afo pass band cut-off attenuation fi = 5850 MHz + 182 kHz 1.7 3.1 4.5 dB FMr FM rejection fi = 5.5 MHz ± 50 kHz − 50 − dB FMomr FM rejection (overmodulated FM) fi = 5.5 MHz ± 80 kHz 25 30 − dB CCr colour-carrier rejection fi = 4.43 MHz 66 73 − dB 0.2 − VDD − 0.5 V − 1.2 − V/rad Baseband demodulator output REMO Vo output voltage limits Kp carrier loop-phase detector gain fp carrier loop pull-in frequency Φoffset carrier loop-phase detector offset fn carrier loop bandwidth (natural frequency) system I system B/G phase shift = 45° − 0.9 − V/rad 4 − − kHz −4 0 +4 deg 2 − 5 kHz − 0.5VDDF2 − V Baseband remodulator filter feedback REMVE Vo carrier loop filter virtual earth voltage defined by VRCF Fine frequency calibration current (on to REMVE node) Isource output source current − 15 − µA Isink output sink current − 15 − µA ILI 3-state leakage current −0.25 0 +0.25 µA ffstep fine frequency calibration step 0.8 2 8 kHz Voltage controlled oscillator VCONT Vi input signal voltage 0.5 − VDD − 0.5 V Ci input capacitance − − 10 pF fSYS − 75 − fSYS + 75 kHz VCO frequency after fine frequency calibration fSYS = 6552 MHz (system I) or fSYS = 5.85 MHz (system BGH) fSYS − 4 − fSYS + 4 kHz VCO slope system I −139 −186 −232 kHz/V system B/G −191 −255 −319 kHz/V VCO (MEASURED AT VCLK PIN) fVCO KVCO VCO frequency after DAC calibration DACSTEP VCO calibrating DAC step size −50 +30 +50 kHz ItoQ in-phase to quadrature phase accuracy − 90 − deg ϕj VCO phase jitter − − 8.1 ns 1996 Oct 24 note 4 25 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SYMBOL PARAMETER SAA7284 CONDITIONS MIN. TYP. MAX. UNIT Clock recovery loop and crystal oscillator XTAL Ci input capacitance − − 10 pF Vbias DC bias voltage − 3.63 − V Vosc(p-p) oscillator voltage amplitude (peak to peak value) − 1.4 − V Vbias DC bias voltage − 2.33 − V Gv small signal voltage gain − 1.0 − V/V Co output capacitance − − 10 pF OSC CRYSTAL SPECIFICATION (FUNDAMENTAL MODE) fi crystal input frequency − 8.192 − MHz CL load capacitance − 15 − pF C1 series capacitance 21 − − fF C0 parallel capacitance − − 5 pF S pulling sensitivity −26.25 − − 10−6/pF Rr resonance resistance − − 40 Ω RDLD resonance resistance; drive level dependency − − 120 Ω Xa ageing − − ±5 10−6/year Trange temperature range −20 +25 +70 °C Xj adjustment tolerance − − ±30 10−6 Xd drift − − ±30 10−6 0.5 ≤ VCLKLPF ≤ VDD − 0.5; note 5 −5 0 +5 µA 0.5 ≤ VCLKLPF ≤ VDD − 0.5; note 5 57 63.5 70 µA/rad supply dependent − 0.5VDDA − V − − 10 pF − 0.5VDDA − V determined by CL, C1 and C0 across Trange CLOCK RECOVERY LOOP CURRENT SOURCE ILI 3-state leakage current at phase shift ϕgm phase comparator transconductance π⁄ (CLKLPF) 2 Analog references VRCA OUTPUT VO output signal voltage Ci input capacitance VROA OUTPUT VO output signal voltage defined by VRCA Ci input capacitance − − 10 pF fs output sample frequency − 128 − kHz PR pass band ripple at 0 Hz to 15 kHz − − ±0.01 dB SBA stop band attenuation at f ≥ 17 kHz 30 − − dB Digital filter 1996 Oct 24 26 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SYMBOL PARAMETER SAA7284 CONDITIONS MIN. TYP. MAX. UNIT Digital de-emphasis DEV − − ±0.09 dB 0 dB FM attenuation set − 40 − kΩ −12 dB FM attenuation set − 160 − kΩ programmable in 1 dB steps − 0 to 12 − dB deviation from ideal FM audio inputs FML AND FMR (SELECTED VIA I2C-BUS CONTROL) Zi input impedance G output gain Ga output gain accuracy −0.5 0 +0.5 dB Vain(rms) input voltage level (RMS value) − − 1.1 V S/N signal-to-noise ratio 90 95 − dB THD total harmonic distortion − −85 −70 dB EXT audio input EXTL AND EXTR (SELECTED VIA I2C-BUS CONTROL) Zi input impedance − 40 − kΩ G output gain − 0 − dB Ga output gain accuracy − 0 − dB Vain(rms) input voltage level (RMS value) − − 1.1 V S/N signal-to-noise ratio 90 95 − dB THD total harmonic distortion − −85 −70 dB NICAM internal DAC (selected via I2C-bus control) Vo(rms) NICAM output voltage level (RMS value) 0 dB; VROA = 2.5 V 0.94 1 1.06 V THD+N total harmonic distortion plus noise notes 6 and 7 − −80 −75 dB DIGS digital silence level MUTE on − −80 − dB AUDIOS audio silence level SILENCE on = 0 −80 − − dB − − 300 pF Audio outputs OPL AND OPR CL output load capacitance RL output load resistance CHM channel matching PSRR power supply rejection ratio 1996 Oct 24 0 dB, 1 kHz 27 3 − − kΩ −0.5 0 +0.5 dB − 40 − dB Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SYMBOL PARAMETER SAA7284 CONDITIONS MIN. TYP. MAX. UNIT Timing (all timing values refer to VIH and VIL levels) DATAIN WITH RESPECT TO PCLK (see Fig.9) tSU;DAT data set-up time 100 − − ns tHD;DAT data hold time 250 − − ns SDA WITH RESPECT TO SCL(see Fig.10) fSCL SCL clock frequency 0 − 400 kHz tBUF bus free time 1300 − − ns tHD;STA START code hold time 600 − − ns tLOW SCL clock LOW time 1300 − − ns tHIGH SCL clock HIGH time 600 − − ns tSU;STA START code set-up time 600 − − ns tHD;DAT data hold time note 8 0 − − ns tSU;DAT data set-up time note 9 100 − − ns tr SDA and SCL rise time 50 − 300 ns tf SDA and SCL fall time 50 − 300 ns tSU;STO STOP code set-up time 600 − − ns Notes 1. It is assumed that all supplies are externally connected at the same source, and consequently that maximum and minimum values apply simultaneously to each supply. 2. Cumulative input level based on FM at 0 dB and NICAM at −10 dB with respect to picture carrier. 3. The signal amplitude present at the SEYE and CEYE pins depends on whether the demodulator is in or out-of-lock. When out-of-lock, the signal at the pins is √2 times the in-lock situation. 4. VCO jitter is measured in System I over 100 cycles of the VCO clock. 5. With 10 kΩ resistor from IREF to VSSF2. 6. Audio performance is limited by the dynamic range of the NICAM 728 system. Due to compansion, the quantization noise is never lower than −62 dB with respect to the input level. 7. Measured with a −30 dB, 1 kHz NICAM 728 input signal. 8. Note that a transmitter must internally provide at least a hold time to bridge the undefined region (max. 300 ns) of the falling edge of SCL. 9. If a fast I2C-bus device is used in an up to 100 kbit/s I2C-bus system, then the requirement tSU;DAT ≥ 250 ns is always fulfilled if this device cannot stretch the LOW level of the SCL signal. If a device stretches the LOW level of the SCL signal, then data to SDA must be asserted (tRD(max) + tSU;DAT) = 1000 + 250 = 1250 ns before the SCL signal is released to be compatible with the up to 100 kbit/s I2C-bus specification. 1996 Oct 24 28 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems handbook, full pagewidth SAA7284 supply 2.2 Ω 100 nF 47 µF 100 nF V DDF1 47 µF 100 nF V DDF2 10 Ω 22 Ω 2.2 Ω 100 nF VDDD VDDA SAA7284 MBH219 Fig.7 VDD external circuitry. 1996 Oct 24 29 1996 Oct 24 RF input 33.4 MHz B/G 32.9 MHz I FM 33.05 MHz 32.348 MHz Nicam 10 dB/14 dB handbook, full pagewidth 30 Vision 38.9 MHz SAW filter SAA7284 NICAM DECODER DAI 2 I 2C STEREO BITSTREAM DAC AND SWITCHES FM MBH224 DQPSK DEMODULATOR DQPSK VISION PLL-IF DEMODULATOR TDA9800 DOBM I 2 C-bus right audio outputs left external audio inputs CVBS Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems Fig.8 System block diagram showing SAA7284. TUNER U944C Philips Semiconductors Preliminary specification SAA7284 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 handbook, full pagewidth PCLK DATA t SU;DAT MLB158 t HD;DAT Fig.9 Data output timing. handbook, full pagewidth SDA t LOW t BUF tf SCL t HD;STA tr t HD;DAT t HIGH t SU;DAT SDA MBC764 t SU;STA Fig.10 I2C-bus timing. 1996 Oct 24 31 t SU;STO VSSF2 330 nF 2.2 Ω VDDF2 100 nF 22 nF 22 k Ω VSS 680 k Ω VDDD VSSF2 10 µF VSSD 470 nF 100 nF 22 Ω 10 µF VSSF2 VSSF1 VSSF1 10 µF 47 µF 32 31 30 29 28 27 26 25 24 23 22 21 20 10 µF VSSF1 100 nF n.c. n.c. RESET VDDD VSSD PCLK DATAOUT DATAIN VSSX OSC XTAL CLKLPF TEST V SSF2 VDDF2 VRCF I REF VROF PKDET SAA7284 n.c. EXTR FMR OPR n.c. n.c. VROA V SSDAC n.c. n.c. OPL FML EXTL PORM PORA REMVE REMO n.c. n.c. VSSD digital audio interface VDDA Fig.11 Application diagram for QFP64. VSSD SCL SDA VSSA 10 Ω 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 100 nF 100 nF 100 nF VSSA VSSA VSSA 1 MΩ 10 k Ω VSSA VSSA 220 nF 47 µ F 47 µF VSSA 220 nF 1 MΩ 47 µF 10 k Ω 47 VSSA µF 1.8 k Ω 47 nF VSSA 10 11 12 13 14 15 16 17 18 19 33 k Ω audio right FMR EXTR EXTL FML MBH225 68 pF 220 nF 220 nF 68 pF audio left Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems I C bus connector 2 51 50 49 48 47 46 VDDD 100 nF 44 45 43 42 41 40 39 100 pF 1 µF 38 37 36 35 34 33 VSSF1 100 nF VSSF1 100 pF 10 k Ω VSSD BAW62 BB405 6.8 µH 1 MΩ 8.192 MHz 100 nF VSSF2 10 µF 220 pF supply connector VSSF1 VDDF1 PORT2 VDD (5 V) DQPSK MIXREF ADSEL 10 pF 2.2 Ω n.c. n.c. 1 kΩ VCONT MUTE 100 Ω SOFF 390 pF COFF SDA VCLK n.c. n.c. DQPSK input n.c. VSSF1 V DDA V SSA n.c. CEYE SCL V DDF1 DOBM SEYE V RCA 32 n.c. 1996 Oct 24 handbook, full pagewidth Philips Semiconductors Preliminary specification SAA7284 APPLICATION INFORMATION Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 PACKAGE OUTLINES seating plane SDIP52: plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1 ME D A2 L A A1 c e Z b1 (e 1) w M MH b 27 52 pin 1 index E 1 26 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 5.08 0.51 4.0 1.3 0.8 0.53 0.40 0.32 0.23 47.9 47.1 14.0 13.7 1.778 15.24 3.2 2.8 15.80 15.24 17.15 15.90 0.18 1.73 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 90-01-22 95-03-11 SOT247-1 1996 Oct 24 EUROPEAN PROJECTION 33 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT319-2 c y X 51 A 33 52 32 ZE Q e E HE A A2 (A 3) A1 θ wM pin 1 index Lp bp L 20 64 detail X 19 1 ZD w M bp e v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y mm 3.20 0.25 0.05 2.90 2.65 0.25 0.50 0.35 0.25 0.14 20.1 19.9 14.1 13.9 1 24.2 23.6 18.2 17.6 1.95 1.0 0.6 1.4 1.2 0.2 0.2 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-02-04 SOT319-2 1996 Oct 24 EUROPEAN PROJECTION 34 o 7 0o Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary from 50 to 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheat for 45 minutes at 45 °C. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). WAVE SOLDERING Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. SDIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. If wave soldering cannot be avoided, the following conditions must be observed: The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). REPAIRING SOLDERED JOINTS During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. QFP REFLOW SOLDERING A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Reflow soldering techniques are suitable for all QFP packages. REPAIRING SOLDERED JOINTS The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). 1996 Oct 24 Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 35 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems SAA7284 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1996 Oct 24 36 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems NOTES 1996 Oct 24 37 SAA7284 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems NOTES 1996 Oct 24 38 SAA7284 Philips Semiconductors Preliminary specification Terrestrial digital sound decoder for conventional intercarrier PLL-IF systems NOTES 1996 Oct 24 39 SAA7284 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/1200/01/pp40 Date of release: 1996 Oct 24 Document order number: 9397 750 01426