INTEGRATED CIRCUITS PCK857 66–150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver Preliminary specification 1998 Dec 10 Philips Semiconductors Preliminary specification 66–150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver FEATURES PCK857 PIN CONFIGURATION • Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications GND 1 • 1-to-10 differential clock distribution • Very low skew (< 100ps) and jitter (< 100ps) • 3V AVCC and 2.5V Vddq • SSTL_2 interface clock inputs and outputs • CMOS control signal input • Test mode enables buffers while disabling PLL • Low current power-down mode • Tolerant of Spread Spectrum input clock • Full DDR solution provided when used with SSTL16857 and Y0 2 Y0 3 VDDQ 4 Y1 5 Y1 6 45 VDDQ 44 Y6 43 Y6 42 GND 41 GND 40 Y7 39 Y7 VDDQ 11 38 VDDQ VDDQ 12 37 G 36 FBIN CLK 14 VDDQ 15 35 FBIN AVCC 16 33 FBOUT 32 FBOUT AGND 17 GND 18 Zero delay buffer to distribute an SSTL differential clock input pair to 10 SSTL_2 differential output pairs. Outputs are slope controlled. External feedback pin for synchronization of the outputs to the input. A CMOS style Enable/Disable pin is provided for low power disable. 46 Y5 GND 8 CLK 13 DESCRIPTION 47 Y5 GND 7 Y2 9 Y2 10 CBT3857 48 GND 34 VDDQ Y3 19 31 GND 30 Y8 Y3 20 29 Y8 VDDQ 21 Y4 22 Y4 23 GND 24 28 VDDQ 27 Y9 26 Y9 25 GND SW00358 ORDERING INFORMATION PACKAGES 48-Pin Plastic TSSOP TEMPERATURE RANGE 0°C to +70°C OUTSIDE NORTH AMERICA PCK857 DGG NORTH AMERICA PCK857 DGG DRAWING NUMBER SOT362-1 PINS SYMBOL DESCRIPTION 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 GND SSTL_2 ground pins 2, 3, 5, 6, 9, 10, 19, 20, 22, 23, 26, 27, 29, 30, 32, 33, 39, 40, 43, 44, 46, 47 Yn, Ynb, FBOUT, FBOUTb SSTL_2 differential outputs 4, 11, 12, 15, 21, 28, 34 VDDQ SSTL_2 power pins 13, 14, 35, 36 CLKIN, CLKINb, FBIN, FBINb SSTL_2 differential inputs 1998 Dec 10 16 AVCC Analog power 17 AGND Analog ground 37 G Power-down control input 2 Philips Semiconductors Preliminary specification 66–150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver PCK857 FUNCTION TABLE INPUTS G OUTPUTS PLL ON/OFF CLK CLK Y Y FBOUT FBOUT L L H Z Z Z1 Z1 OFF L H L Z Z Z1 Z1 OFF H L H L H L H ON H H L H L H L ON X2 < 20MHz < 20MHz Z Z1 Z1 OFF Z NOTES: H = HIGH voltage level L = LOW voltage level Z = high impedance OFF-state X = don’t care 1. Subject to change. May cause conflict with FBIN pins. 2. Additional feature that senses when the clock input is less than 20MHz and places the part in sleep mode. BLOCK DIAGRAM G/ Y0 Y0/ Y1 Y1/ Y2 Y2/ Y3 Y3/ Y4 CLK CLK/ FBIN FBIN/ AVCC Y4/ PLL Y5 Y5/ Y6 Y6/ Y7 Y7/ Y8 Y8/ Y9 Y9/ FBOUT FBOUT/ SW00395 1998 Dec 10 3 Philips Semiconductors Preliminary specification 66–150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver PCK857 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0V). LIMITS SYMBOL PARAMETER TEST CONDITIONS UNIT AVCC Analog supply voltage MIN 3 TYP 3.3 MAX 3.6 VDDQ I/O supply voltage 2.3 V 2.5 2.7 VIL Input low voltage –0.3 Vref –0.35 V V VIH Input high voltage Vref + 0.35 Vddq + 0.3 V VOL Output low voltage1 0 0.5 V VOH Output high voltage1 2 Vddq V NOTE: 1. This is intended to operate in the SSTL_2 type IV unterminated mode without series resistors on the outputs. AC CHARACTERISTICS GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL fCK fPHASERROR fSK fdifSK fSL Jitterpp Jittercc O/P impedance fDC Cin PARAMETER UNIT Clock frequency MIN 50 TYP 133 MAX 150 MHz Phase error –150 0 150 ps Output clock skew 200 ps Differential clock skew 100 Output clock skew 1 Peak-to-Peak jitter (long term) Cycle-to-cycle jitter (short term) Inherent series resistance Duty cycle 1.5 Input capacitance Sync time 4 ps V/ns –100 100 ps > –100 < 100 ps Ω 25 NOTE: 1. Rise and fall 1998 Dec 10 LIMITS CONDITION WAVEFORM 45 55 % 2.5 4 pF 100 µs Philips Semiconductors Preliminary specification 66–150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver PCK857 SDRAM SDRAM SDRAM SDRAM CBT CBT CBT CBT CBT SDRAM SDRAM SDRAM SDRAM CBT SDRAM SDRAM SDRAM SDRAM CBT SDRAM SDRAM CBT SDRAM SDRAM SDRAM CBT SDRAM 184/200-pin DDR SDRAM DIMM BACK SIDE CBT3857 (9) FRONT SIDE SSTL16857 SSTL16857 PCK857 The PLL clock distribution device and SSTL registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation SW00393 AC WAVEFORMS skew ANY TWO OUTPUTS SW00396 Figure 1. Skew between any two outputs. t1 45% t2 t1 55% t1 t2 SW00397 Figure 2. Duty cycle limits and measurement 1998 Dec 10 5 Philips Semiconductors Preliminary specification 66–150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver t1 PCK857 t2 | t 1– t 2| v 100pS SW00398 Figure 3. Jitter limit and measurement TEST CIRCUIT 60Ω Vt 25pF Vt + V DDQ 2 SW00399 1998 Dec 10 6 Philips Semiconductors Preliminary specification 66–150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm 1998 Dec 10 7 PCK857 SOT362-1 Philips Semiconductors Preliminary specification 66–150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver PCK857 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 12-98 Document order number: yyyy mmm dd 8 9397-750-04949