PCF8531 34 x 128 pixel matrix driver Rev. 05 — 10 August 2010 Product data sheet 1. General description The PCF8531 is a low-power CMOS1 LCD row and column driver, designed to drive dot matrix graphic displays at multiplex rates of 1:17, 1:26, and 1:34. Furthermore, it can drive up to 128 icons. All necessary functions for the display are provided in a single chip, including on-chip generation of VLCD and the LCD bias voltages, resulting in a minimum of external components and low power consumption. The PCF8531 is compatible with most microcontrollers and communicates via a two-line bidirectional I2C-bus. All inputs are CMOS compatible. Remark: The icon mode is used to reduce current consumption. When only icons are displayed, a much lower operating voltage (VLCD) can be used and the switching frequency of the LCD outputs is reduced. In most applications it is possible to use VDD as VLCD. 2. Features and benefits 1. Single-chip LCD controller and driver 34 row and 128 column outputs Display data RAM 34 × 128 bits 128 icons (last row is used for icons) Fast-mode I2C-bus interface (400 kbit/s) Software selectable multiplex rates: 1:17, 1:26, and 1:34 Icon mode with multiplex rate 1:2: Featuring reduced current consumption while displaying icons only On-chip: Generation of VLCD (external supply also possible) Selectable linear temperature compensation Oscillator requires no external components (external clock also possible) Generation of intermediate LCD bias voltages Power-On Reset (POR) No external components required Software selectable bias configuration Logic supply voltage range VDD1 to VSS1: 1.8 V to 5.5 V Supply voltage range for on-chip voltage generator VDD2 and VDD3 to VSS1 and VSS2: 2.5 V to 4.5 V Display supply voltage range VLCD to VSS: Normal mode: 4 V to 9 V The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19. PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver Icon mode: 3 V to 9 V Low-power consumption, suitable for battery operated systems CMOS compatible inputs Manufactured in silicon gate CMOS process 3. Applications Telecommunication systems Automotive information systems Point-of-sale terminals Instrumentation 4. Ordering information Table 1. Ordering information Type number PCF8531U PCF8531 Product data sheet Package Name Description Version - chip with bumps in tray - All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 2 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 5. Block diagram 34 VSS1 VDD2 VDD3 128 ROW DRIVERS VSS2 VDD1 C0 to C127 R0 to R33 COLUMN DRIVERS POWER-ON RESET ENR INTERNAL RESET RES T1 T2 PCF8531 T3 T4 DATA LATCHES VLCDIN BIAS VOLTAGE GENERATOR OSCILLATOR OSC MATRIX LATCHES TIMING GENERATOR VLCDSENSE VLCDOUT DISPLAY DATA RAM VLCD GENERATOR SCL SDA SDACK INPUT FILTERS MATRIX DATA RAM I2C-BUS CONTROL COMMAND DECODER DISPLAY ADDRESS COUNTER ADDRESS COUNTER mgs465 SA0 Fig 1. PCF8531 Product data sheet Block diagram of PCF8531 All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 3 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 6. Pinning information 6.1 Pinning R0 . .. . .. R32 C0 T2 ... SCL T1 T3 . .. VSS1 . .. VSS2 C31 C32 T4 ENR SA0 SDACK . .. 0, 0 . .. x C63 C64 y SDA VDD1 VDD2 VDD3 RES . .. C95 C96 VLCDIN ... VLCDOUT VLCDSENSE OSC PCF8531 . .. C127 R33 . .. . .. R1 pad1 mgs486 The positioning of the bonding pads is not to scale. Fig 2. PCF8531 Product data sheet Bonding pad location for PCF8531 All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 4 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver Table 2. Pad allocation table Pad Symbol Pad Symbol 15 OSC 55 ENR 16 VLCDSENSE 56 T4 17 to 23 VLCDOUT 57 to 63 VSS2 24 to 30 VLCDIN 64 to 70 VSS1 31 RES 71 T3 32 to 34 VDD3 72 T1 35 to 42 VDD2 73 to 74 SCL 43 to 49 VDD1 78 T2 50 to 51 SDA 87 to 103 R0, R2, R4, R6, R8, R10, R12, R14, R16, R18, R20, R22, R24, R26, R28, R30, R32 52 SDACK 104 to 231 C0 to C127 54 SA0 232 to 248 R33, R31, R29, R27, R25, R23, R21, R19, R17, R15, R13, R11, R9, R7, R5, R3, R1 100 μm 100 μm y center Fig 3. Table 3. PCF8531 Product data sheet 80 μm 100 μm y center 100 μm y center x center x center x center circle C F mgs490 Alignment markers Alignment markers for PCF8531 Alignment marks x (μm) y (μm) C1 −5402.0 823.1 C2 5292.4 950.0 F 5890.3 401.9 circle 1 −5543.0 798.4 circle 2 5637.4 798.4 All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 5 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver L PCF8531 W pitch Y X 001aag908 Fig 4. Chip dimensions Table 4. Bonding pad dimensions Pad Size Unit pad pitch (minimum) 70 μm bump dimensions 50 × 90 × 17.5 (±3) μm wafer thickness (excluding bumps) 381 μm die size L × W 12.14 × 1.86 mm 6.2 Pin description Table 5. Bonding pad description All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 2). PCF8531 Product data sheet Symbol Pad X (μm) Y (μm) Description - 1 5973.6 −821.7 dummy - 2 5969.5 823.4 - 3 5899.5 823.4 - 4 5829.5 823.4 - 5 5479.5 823.4 - 6 5409.5 823.4 - 7 5059.5 823.4 - 8 4989.5 823.4 - 9 4639.5 823.4 - 10 4569.5 823.4 - 11 4219.5 823.4 - 12 4149.5 823.4 - 13 3799.5 823.4 - 14 3729.5 823.4 OSC 15 3449.5 823.4 oscillator input [1] VLCDSENSE 16 3169.5 823.4 voltage multiplier regulation input (VLCD) [2] All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 6 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver Table 5. Bonding pad description …continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 2). PCF8531 Product data sheet Symbol Pad X (μm) Y (μm) Description VLCDOUT 17 3099.5 823.4 voltage multiplier output (VLCD) [3] VLCDOUT 18 3029.5 823.4 VLCDOUT 19 2959.5 823.4 VLCDOUT 20 2889.5 823.4 VLCDOUT 21 2819.5 823.4 VLCDOUT 22 2749.5 823.4 VLCDOUT 23 2679.5 823.4 VLCDIN 24 2539.5 823.4 LCD supply voltage (VLCD) [2] VLCDIN 25 2469.5 823.4 VLCDIN 26 2399.5 823.4 VLCDIN 27 2329.5 823.4 VLCDIN 28 2259.5 823.4 VLCDIN 29 2189.5 823.4 VLCDIN 30 2119.5 823.4 RES 31 1979.5 823.4 external reset input (active LOW) [4] VDD3 32 1699.5 823.4 supply voltage 3 [5] VDD3 33 1629.5 823.4 VDD3 34 1559.5 823.4 VDD2 35 1279.5 823.4 supply voltage 2 [5] VDD2 36 1209.5 823.4 VDD2 37 1139.5 823.4 VDD2 38 1069.5 823.4 VDD2 39 999.5 823.4 VDD2 40 929.5 823.4 VDD2 41 859.5 823.4 VDD2 42 789.5 823.4 VDD1 43 649.5 823.4 supply voltage 1 [5] VDD1 44 579.5 823.4 VDD1 45 509.5 823.4 VDD1 46 439.5 823.4 VDD1 47 369.5 823.4 VDD1 48 299.5 823.4 VDD1 49 229.5 823.4 SDA 50 19.5 823.4 SDA 51 −50.5 823.4 SDACK 52 −400.5 823.4 serial data acknowledge output - 53 −750.5 823.4 dummy SA0 54 −820.5 823.4 I2C-bus slave address input; bit 0 ENR 55 −1100.5 823.4 enable internal Power-On Reset (POR) input serial data line input of the I2C-bus All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 [6] [7] © NXP B.V. 2010. All rights reserved. 7 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver Table 5. Bonding pad description …continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 2). PCF8531 Product data sheet Symbol Pad X (μm) Y (μm) Description T4 56 −1380.5 823.4 test input 4 [8] VSS2 57 −1660.5 823.4 ground 2 [9] VSS2 58 −1730.5 823.4 VSS2 59 −1800.5 823.4 VSS2 60 −1870.5 823.4 VSS2 61 −1940.5 823.4 VSS2 62 −2010.5 823.4 VSS2 63 −2080.5 823.4 VSS1 64 −2220.5 823.4 ground 1 [9] VSS1 65 −2290.5 823.4 VSS1 66 −2360.5 823.4 VSS1 67 −2430.5 823.4 VSS1 68 −2500.5 823.4 VSS1 69 −2570.5 823.4 VSS1 70 −2640.5 823.4 T3 71 −2780.5 823.4 test 3 [8] T1 72 −3060.5 823.4 test 1 [8] SCL 73 −3410.5 823.4 serial clock line input of the I2C-bus SCL 74 −3480.5 823.4 - 75 −3830.5 823.4 - 76 −4180.5 823.4 - 77 −4530.5 823.4 T2 78 −4600.5 823.4 test 2 output - 79 −4880.5 823.4 dummy - 80 −4950.5 823.4 - 81 −5230.5 823.4 - 82 −5300.5 823.4 - 83 −5650.5 823.4 - 84 −5720.5 823.4 - 85 −5930.5 823.4 - 86 −5926.4 −821.7 R0 87 −5786.4 −821.7 R2 88 −5716.4 −821.7 R4 89 −5646.4 −821.7 R6 90 −5576.4 −821.7 R8 91 −5506.4 −821.7 R10 92 −5436.4 −821.7 dummy LCD row driver output All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 [10] © NXP B.V. 2010. All rights reserved. 8 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver Table 5. Bonding pad description …continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 2). PCF8531 Product data sheet Symbol Pad X (μm) Y (μm) Description R12 93 −5366.4 −821.7 LCD row driver output R14 94 −5296.4 −821.7 R16 95 −5226.4 −821.7 R18 96 −5156.4 −821.7 R20 97 −5086.4 −821.7 R22 98 −5016.4 −821.7 R24 99 −4946.4 −821.7 R26 100 −4876.4 −821.7 R28 101 −4806.4 −821.7 R30 102 −4736.4 −821.7 R32 103 −4666.4 −821.7 C0 104 −4526.4 −821.7 C1 105 −4456.4 −821.7 C2 106 −4386.4 −821.7 C3 107 −4316.4 −821.7 C4 108 −4246.4 −821.7 C5 109 −4176.4 −821.7 C6 110 −4106.4 −821.7 C7 111 −4036.4 −821.7 C8 112 −3966.4 −821.7 C9 113 −3896.4 −821.7 C10 114 −3826.4 −821.7 C11 115 −3756.4 −821.7 C12 116 −3688.4 −821.7 C13 117 −3616.4 −821.7 C14 118 −3546.4 −821.7 C15 119 −3476.4 −821.7 C16 120 −3406.4 −821.7 C17 121 −3336.4 −821.7 C18 122 −3266.4 −821.7 C19 123 −3196.4 −821.7 C20 124 −3126.4 −821.7 C21 125 −3056.4 −821.7 C22 126 −2986.4 −821.7 C23 127 −2916.4 −821.7 C24 128 −2846.4 −821.7 C25 129 −2776.4 −821.7 C26 130 −2706.4 −821.7 C27 131 −2636.4 −821.7 LCD column driver output All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 9 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver Table 5. Bonding pad description …continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 2). PCF8531 Product data sheet Symbol Pad X (μm) Y (μm) Description C28 132 −2566.4 −821.7 LCD column driver output C29 133 −2496.4 −821.7 C30 134 −2426.4 −821.7 C31 135 −2356.4 −821.7 C32 136 −2216.4 −821.7 C33 137 −2146.4 −821.7 C34 138 −2076.4 −821.7 C35 139 −2006.4 −821.7 C36 140 −1936.4 −821.7 C37 141 −1866.4 −821.7 C38 142 −1796.4 −821.7 C39 143 −1726.4 −821.7 C40 144 −1656.4 −821.7 C41 145 −1586.4 −821.7 C42 146 −1516.4 −821.7 C43 147 −1446.4 −821.7 C44 148 −1376.4 −821.7 C45 149 −1306.4 −821.7 C46 150 −1236.4 −821.7 C47 151 −1166.4 −821.7 C48 152 −1096.4 −821.7 C49 153 −1026.4 −821.7 C50 154 −956.4 −821.7 C51 155 −886.4 −821.7 C52 156 −816.4 −821.7 C53 157 −746.4 −821.7 C54 158 −676.4 −821.7 C55 159 −606.4 −821.7 C56 160 −534.6 −821.7 C57 161 −466.4 −821.7 C58 162 −396.4 −821.7 C59 163 −326.4 −821.7 C60 164 −256.4 −821.7 C61 165 −186.4 −821.7 C62 166 −116.6 −821.7 C63 167 −46.4 −821.7 C64 168 93.6 −821.7 C65 169 163.6 −821.7 C66 170 233.6 −821.7 All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 10 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver Table 5. Bonding pad description …continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 2). PCF8531 Product data sheet Symbol Pad X (μm) Y (μm) Description C67 171 303.6 −821.7 LCD column driver output C68 172 373.3 −821.7 C69 173 443.6 −821.7 C70 174 513.6 −821.7 C71 175 583.6 −821.7 C72 176 653.6 −821.7 C73 177 723.6 −821.7 C74 178 793.6 −821.7 C75 179 863.6 −821.7 C76 180 933.6 −821.7 C77 181 1003.6 −821.7 C78 182 1073.6 −821.7 C79 183 1143.6 −821.7 C80 184 1213.6 −821.7 C81 185 1283.6 −821.7 C82 186 1353.6 −821.7 C83 187 1423.6 −821.7 C84 188 1493.6 −821.7 C85 189 1563.6 −821.7 C86 190 1633.6 −821.7 C87 191 1703.6 −821.7 C88 192 1773.6 −821.7 C89 193 1843.6 −821.7 C90 194 1913.6 −821.7 C91 195 1983.6 −821.7 C92 196 2053.6 −821.7 C93 197 2123.6 −821.7 C94 198 2193.6 −821.7 C95 199 2263.6 −821.7 C96 200 2403.6 −821.7 C97 201 2473.6 −821.7 C98 202 2543.6 −821.7 C99 203 2613.6 −821.7 C100 204 2683.6 −821.7 C101 205 2753.6 −821.7 C102 206 2823.6 −821.7 C103 207 2893.6 −821.7 C104 208 2963.6 −821.7 C105 209 3033.6 −821.7 All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 11 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver Table 5. Bonding pad description …continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 2). PCF8531 Product data sheet Symbol Pad X (μm) Y (μm) Description C106 210 3103.6 −821.7 LCD column driver output C107 211 3173.6 −821.7 C108 212 3243.6 −821.7 C109 213 3313.6 −821.7 C110 214 3383.6 −821.7 C111 215 3453.6 −821.7 C112 216 3523.6 −821.7 C113 217 3593.6 −821.7 C114 218 3663.6 −821.7 C115 219 3733.6 −821.7 C116 220 3803.6 −821.7 C117 221 3873.6 −821.7 C118 222 3943.6 −821.7 C119 223 4013.6 −821.7 C120 224 4083.6 −821.7 C121 225 4153.6 −821.7 C122 226 4223.6 −821.7 C123 227 4293.6 −821.7 C124 228 4363.6 −821.7 C125 229 4433.6 −821.7 C126 230 4503.6 −821.7 C127 231 4573.6 −821.7 R33 232 4713.6 −821.7 LCD row driver output; icon row R31 233 4783.6 −821.7 LCD row driver output R29 234 4853.6 −821.7 R27 235 4923.6 −821.7 R25 236 4993.6 −821.7 R23 237 5063.6 −821.7 R21 238 5113.6 −821.7 R19 239 5203.6 −821.7 R17 240 5343.6 −821.7 R15 241 5413.6 −821.7 R13 242 5483.6 −821.7 R11 243 5553.6 −821.7 R9 244 5623.6 −821.7 R7 245 5693.6 −821.7 R5 246 5763.6 −821.7 R3 247 5833.6 −821.7 R1 248 5903.6 −821.7 All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 12 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver [1] If the on-chip oscillator is used, this input must be connected to VDD1. [2] If the internal VLCD generation is used, VLCDOUT, VLCDIN, and VLCDSENSE must be connected together. [3] If an external VLCD is used in the application, then pin VLCDOUT must be left open-circuit, otherwise the chip will be damaged. [4] If only the internal Power-On Reset (POR) is used, this input must be connected to VDD1. [5] VDD1 is for the logic supply, VDD2 and VDD3 are for the voltage multiplier. For split power supplies, VDD2 and VDD3 must be connected together. If only one supply voltage is available, VDD1, VDD2, and VDD3 must be connected together. [6] Serial data acknowledge for the I2C-bus. By connecting SDACK to SDA externally, the SDA line becomes fully I2C-bus compatible. Having the acknowledge output separated from the serial data line is advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from the SDACK pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that the PCF8531 will not be able to create a valid logic 0 level during the acknowledge cycle. By splitting the SDA input from the SDACK output, the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid LOW level. [7] If ENR is connected to VSS, Power-On Reset (POR) is disabled; to enable Power-On Reset (POR) ENR must be connected to VDD1. [8] In the application, this input must be connected to VSS. [9] VSS1 and VSS2 must be connected together. [10] In the application, T2 must be left open-circuit. PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 13 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 7. Functional description 7.1 Oscillator The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC input must be connected to VDD. An external clock signal, if used, is connected to this input. 7.2 Power-On Reset (POR) The on-chip Power-On Reset (POR) initializes the chip after power-on or power failure. 7.3 I2C-bus controller The I2C-bus controller receives and executes the commands. The PCF8531 acts as an I2C-bus slave receiver and therefore it cannot control bus communication. 7.4 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 7.5 Display data RAM The PCF8531 contains 34 × 128 bits static RAM for storing the display data, see Figure 7. The RAM is divided into 6 banks of 128 bytes (6 × 8 × 128 bits). Bank 5 is used for icon data. During RAM access, data is transferred to the RAM via the I2C-bus interface. There is a direct correspondence between the X address and column output number. 7.6 Timing generator The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not affected by operations on the data buses. 7.7 Address counter The address counter sets the addresses of the display data RAM for writing. 7.8 Display address counter The display address counter generates the addresses for read out of the display data. 7.9 Command decoder The command decoder identifies command words that arrive on the I2C-bus and determines the destination for the following data bytes. PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 14 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 7.10 Bias voltage generator The bias voltage generator generates four buffered intermediate bias voltages. This block contains the generator for the reference voltages and the four buffers. This block can operate in two voltage ranges: • Normal mode: 4.0 V to 9.0 V • Power save mode: 3.0 V to 9.0 V. 7.11 VLCD generator The VLCD voltage generator contains a configurable 2 to 5 times voltage multiplier; this is programmed by software. 7.12 Reset The PCF8531 has the possibility of two reset modes: internal Power-On Reset (POR) or external reset (RES). The reset mode is selected using the ENR signal. After a reset, the chip has the following state: • All row and column outputs are set to VSS (display off) • RAM data is undefined • Power-down mode 7.13 Power-down During power-down, all static currents are switched off (no internal oscillator, no timing and no LCD segment drive system) and all LCD outputs are internally connected to VSS. The I2C-bus function remains operational. 7.14 Column driver outputs The LCD drive section includes 128 column outputs (C0 to C127) which must be connected directly to the LCD. The column output signals are generated in accordance with the multiplexed row signals and with the data in the display latch. When less than 128 columns are required, the unused column outputs must be left open-circuit. 7.15 Row driver outputs The LCD drive section includes 34 row outputs (R0 to R33), which must be connected directly to the LCD. The row output signals are generated in accordance with the selected LCD drive mode. If less than 34 rows or lower multiplex rates are required, the unused outputs must be left open-circuit. The row signals are interlaced i.e. the selection order is R0, R2, ..., R1, R3, etc. PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 15 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 8. LCD waveforms and DDRAM to data mapping The LCD waveforms and the DDRAM to display data mapping are shown in Figure 5, Figure 6 and Figure 7. frame n + 1 frame n ROW 0 R0(t) ROW 1 R1(t) COL 0 C0(t) COL 1 C1(t) VLCD V2 V3 Vstate1(t) Vstate2(t) V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V3 − VSS Vstate1(t) VLCD − V2 0V V3 − V2 V4 − V5 0V VSS − V5 V4 − VLCD −VLCD VLCD V3 − VSS Vstate2(t) VLCD − V2 0V V3 − V2 V4 − V5 0V VSS − V5 V4 − VLCD −VLCD 0 2 4 6 8... ... 32 1 3 5 7... ... 33 0 2 4 6 8... ... 32 1 3 5 7... ... 33 mgs466 (1) Vstate1(t) = C1(t) − R0(t) (2) Vstate2(t) = C1(t) − R1(t) Fig 5. Typical LCD driver waveforms PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 16 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver frame n frame n + 1 only icons are driven VLCD V2 V3 ROW 0 to 32 V4 V5 VSS VLCD V2 V3 ROW 33 V4 V5 VSS VLCD V2 V3 COL 1 on/off V4 V5 VSS VLCD V2 V3 COL 2 off/on V4 V5 VSS VLCD V2 V3 COL 3 on/on V4 V5 VSS VLCD V2 V3 COL 4 off/off V4 V5 VSS mgs467 Fig 6. LCD waveforms, icon mode, multiplex rate 1:2 PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 17 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver DDRAM bank 0 top of LCD R0 bank 1 R8 bank 2 R16 LCD bank 3 R24 bank 4 R32 R33 (icon row) bank 5 mgs468 Fig 7. DDRAM to display data mapping 8.1 Addressing Data is written in bytes into the RAM matrix of the PCF8531 as shown in Figure 8, Figure 9 and Figure 10. The display RAM has a matrix of 34 × 128 bits. The columns are addressed by the address pointer. The address ranges are X 0 to X 127 (7Fh) and Y 0 to Y 5 (5h). Addresses outside of these ranges are not allowed. In vertical addressing mode (V = 1), the Y address increments after each byte (see Figure 9). After the last Y address (Y = 4), Y wraps around to 0 and X increments to address the next column. In horizontal addressing mode (V = 0), the X address increments after each byte (see Figure 10). After the last X address (X = 127), X wraps around to 0 and Y increments to address the next PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 18 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver row. After the very last address (X = 127 and Y = 4), the address pointers wrap around to address (X = 0 and Y = 0). The Y address 5 is reserved for icon data and is not affected by the addressing mode. Please note that in bank 4 only the LSB (DB0) of the data is written into the RAM and in bank 5 only the 5th data bit (DB4) is written into the RAM. LSB 0 MSB 1 LSB 2 Y address 3 MSB LSB 4 5 icon data 0 X address mgs469 127 MSB Fig 8. RAM format and addressing 0 5 0 1 6 1 2 2 638 3 4 639 4 0 1 5 icon data 0 Fig 9. Y address 3 X address 127 mgs470 Sequence of writing data bytes into RAM with vertical addressing (V = 1) 0 1 2 127 0 128 129 130 255 1 2 256 257 258 383 384 385 386 511 3 512 513 514 639 4 0 1 0 5 icon data X address Y address 127 mgs471 Fig 10. Sequence of writing data bytes into RAM with horizontal addressing (V = 0) PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 19 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 9. Instructions Only two PCF8531 registers, the instruction register and the data register can be directly controlled by the MPU. Before internal operation, control information is stored temporarily in these registers to allow interfacing to various types of MPUs which operate at different speeds or to allow interfacing to peripheral control ICs. The PCF8531 operation is controlled by the instructions given in Table 11. Instructions are of four types: • • • • Those that define PCF8531 functions e.g. display configuration, etc. Those that set internal RAM addresses Those that perform data transfer to/from the internal RAM Others In normal mode instructions which perform data transfer to/from the internal RAM are used most frequently. Automatic incrementing by 1 of internal RAM addresses after each data write reduces the MPU program load. 9.1 Reset After reset or internal Power-On Reset (POR) (depending on the application), the LCD driver is set to the following state: • • • • • • • • Power-down mode (PD = 1) Horizontal addressing (V = 0) Display blank (D = 0; E = 0), no icon mode (IM = 0) Address counter X[6:0] = 0; Y[2:0] = 0 Bias system BS[2:0] = 0 Multiplex rate M[1:0] = 0 (multiplex rate 1:17) Temperature control mode TC[2:0] = 0 HV-gen control, HVE = 0 the high voltage (HV) generator is switched off, PRS = 0 and S[1:0] = 0 • VLCD = 0 V • RAM data is undefined • Command page definition H[1:0] = 0 PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 20 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 9.2 Function set 9.2.1 PD When PD = 1, the power-down mode of the LCD driver is active: • • • • • • All LCD outputs at VSS (display off) Power-On Reset (POR) detection active, oscillator off VLCD can be disconnected I2C-bus is operational, commands can be executed RAM contents not cleared; RAM data can be written Register settings remain unchanged 9.2.2 V When V = 0 the horizontal addressing is selected. The data is written into the DDRAM as shown in Figure 10. When V = 1 the vertical addressing is selected. The data is written into the DDRAM as shown in Figure 9. Icon data is written independently of V when Y address is 5. 9.3 Set Y address Bits Y2, Y1 and Y0 define the Y address vector of the display RAM (see Table 6). Table 6. Y address Y2 Y1 Y0 Bank 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 (icons) 9.4 Set X address The X address points to the columns. The range of X is 0 to 127 (7Fh). 9.5 Set multiplex rate M[1:0] selects the multiplex rate (see Table 7). Table 7. Multiplex rates Multiplex rate M1 M0 1:17 0 0 1:26 1 0 1:34 0 1 9.6 Display control (D, E, and IM) Bits D and E select the display mode (see Table 13). Bit IM (see Table 12) sets the display to icon mode. PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 21 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 9.7 Set bias system The bias voltage levels are set in the ratio of R − R − n × R − R − R (see Figure 11). V1 = VLCD R V2 R V3 n×R V4 R V5 R V6 = VSS 013aaa183 Fig 11. Voltage divider chain Different multiplex rates require different bias settings. Bias settings are programmed by BS[2:0], which sets the binary number n. The optimum value for n is given by: n = muxrate – 3 Supported values of n are given in Table 8. Table 9 shows the intermediate bias voltages. Table 8. BS[2:0] n Bias system Comment 7 1⁄ 11 - 001 6 1⁄ 10 - 010 5 1⁄ 9 - 011 4 1⁄ 8 - 3 1⁄ 7 recommended for 1:34 101 2 1⁄ 6 recommended for 1:26 110 1 1⁄ 5 recommended for 1:17 111 0 1⁄ 4 recommended for icon mode 000 100 PCF8531 Product data sheet Programming the required bias system All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 22 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 9.8 LCD bias voltage Table 9. Intermediate LCD bias voltages Symbol Bias voltage Example for 1⁄7 bias V1 VLCD VLCD V2 n+3 ------------ × V LCD n+4 V3 n+2 ------------ × V LCD n+4 V4 2 ------------ × V LCD n+4 V5 1 ------------ × V LCD n+4 V6 VSS 6⁄ 7 × VLCD 5⁄ 7 × VLCD 2⁄ 7 × VLCD 1⁄ 7 × VLCD VSS 9.9 Set VLCD value VLCD can be set by software. The voltage at intersection temperature [VLCD (T = Tints)] can be calculated as: VLCD (Tints) = a + VLCD × b The generated voltage is dependent on the temperature, programmed Temperature Coefficient (TC) and the programmed voltage at intersection temperature (Tints). VLCD = VLCD (Tints) × [1 + TC × (T − Tints)] The parameter values are given in Table 10. Two overlapping VLCD ranges can be selected via the command HV-gen control (see Table 10 and Figure 12). The maximum voltage which can be generated depends on the VDD2 and VDD3 voltages and the display load current. For multiplex rate 1:34, the optimum VLCD can be calculated as: 1 + 34 V LCD = -------------------------------------- × V th = 5.30 × V th 1 2 × ⎛ 1 – ----------⎞ ⎝ 34⎠ Where Vth is the threshold voltage of the liquid crystal material used. The practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD, the user must ensure, while setting the VOP register and selecting the temperature compensation, that the VLCD limit maximum of 9.0 V is never exceeded under all conditions and including all tolerances. PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 23 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver Table 10. Parameter values for the HV generator programming Symbol Value Unit PRS = 0 PRS = 1 Tints 27 27 °C a 2.94 6.75 V b 0.03 0.03 V programming range 2.94 to 6.75 6.75 to 10.56 V VLCD b a 00 01 02 03 04 05 06 . . . 7D 7E 7F 00 01 02 03 LOW 04 05 06 . . . 5F 6F 7F HIGH mgl935 VOP[6:0] (programmed) [00h to 7Fh] program range LOW to HIGH Fig 12. VLCD programming of PCF8531 9.10 Voltage multiplier control S[1:0] The PCF8531 incorporates a software configurable voltage multiplier. After reset (internal or external), the voltage multiplier is set to 2 × VDD2. The voltage multiplier factors are set by setting bits S[1:0] (see Table 13). 9.11 Temperature compensation Due to the temperature dependency of the viscosity of the liquid crystals, the LCD controlling voltage VLCD should usually be increased at lower temperatures to maintain optimum contrast. Figure 13 shows VLCD for high multiplex rates. PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 24 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver mgs473 VLCD 0 °C T Fig 13. VLCD as a function of liquid crystal temperature Linear temperature compensation is supported in the PCF8531. The temperature coefficient of VLCD can be selected from eight values by setting bits TC[2:0] (see Table 13). Table 11. Instruction set Instruction I2C-bus command[1] I2C-bus command byte RS DB7 R/W DB6 DB5 Description DB4 DB3 DB2 DB1 DB0 H1 and H0 = don’t care (H independent command page) NOP 0 0 0 0 0 0 0 0 0 0 no operation write data 1 0 D7 D6 D5 D4 D3 D2 D1 D0 write data to display RAM set default H[1:0] 0 0 0 0 0 0 0 0 0 1 select H[1:0] = 0 H1 = 0 and H0 = 0 (function and RAM command page) instruction set 0 0 0 0 0 0 1 0 H1 H0 select command page function set 0 0 0 0 1 0 0 PD V 0 power-down control; entry mode set Y address of RAM 0 0 0 1 0 0 0 Y2 Y1 Y0 Set Y address of RAM; 0 ≤ Y ≤ 5 set X address of RAM 0 0 1 X6 X5 X4 X3 X2 X1 X0 Set X address of RAM; 0 ≤ X ≤ 127 H1 = 0 and H0 = 1 (display setting command page) multiplex rate 0 0 0 0 0 0 0 1 M1 M0 set multiplex rate display control 0 0 0 0 0 0 1 D IM E set display configuration bias system 0 0 0 0 0 1 0 BS2 BS1 BS0 set bias system (BSx) H1 = 1 and H0 = 0 (HV-gen command page) HV-gen control 0 0 0 0 0 0 0 1 PRS HVE set VLCD programming range HV-gen configuration 0 0 0 0 0 0 1 0 S1 S0 set voltage multiplication factor PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 25 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver Table 11. Instruction set …continued I2C-bus command[1] I2C-bus command byte RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 temperature control 0 0 0 0 1 0 0 TC2 TC1 TC0 set temperature coefficient test modes 0 0 0 1 X X X X X X do not use (reserved for test) VLCD control 0 0 1 VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0 set VLCD register Instruction [1] Description R/W is set to the slave address byte; Co and RS are set in the control byte. Table 12. Explanation for symbols in Table 11 Bit 0 1 PD chip is active chip is in power-down mode V horizontal addressing vertical addressing normal mode; full display + icons icon mode; only icons are displayed IM H[1:0] [1] see Table 13 D and E see Table 13 HVE voltage multiplier disabled voltage multiplier enabled PRS VLCD programming range LOW VLCD programming range HIGH TC[2:0] see Table 13 S[1:0] see Table 13 [1] The bits H[1:0] identify the command page (use set default H[1:0] command to set H[1:0] = 0). Table 13. Description of bits H, D and E, TC and S Bits Value Description 00 function and RAM command page 01 display setting command page 10 HV-gen command page 00 display blank 10 normal mode 01 all display segments 11 inverse video mode Command page (H) H[1:0] Display modes (D, E) D and E Temperature coefficient (TC) PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 26 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver Table 13. Description of bits H, D and E, TC and S …continued Bits Value Description TC[2:0] 000 temperature coefficient TC0 001 temperature coefficient TC1 010 temperature coefficient TC2 011 temperature coefficient TC3 100 temperature coefficient TC4 101 temperature coefficient TC5 110 temperature coefficient TC6 111 temperature coefficient TC7 00 2 × voltage multiplier 01 3 × voltage multiplier Voltage multiplier factor (S) S[1:0] PCF8531 Product data sheet 10 4 × voltage multiplier 11 5 × voltage multiplier All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 27 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 10. I2C-bus interface 10.1 Characteristics of the I2C-bus The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 10.1.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 14). SDA SCL data line stable; data valid change of data allowed mbc621 Fig 14. Bit transfer 10.1.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are shown in Figure 15. SDA SDA SCL SCL S P START condition STOP condition mbc622 Fig 15. Definition of START and STOP conditions 10.1.3 System configuration The system configuration is shown in Figure 16. • Transmitter: the device that sends the data to the bus • Receiver: the device that receives the data from the bus • Master: the device that initiates a transfer, generates clock signals and terminates a transfer • Slave: the device addressed by a master PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 28 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver • Multi-master: more than one master can attempt to control the bus at the same time without corrupting the message • Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted • Synchronization: procedure to synchronize the clock signals of two or more devices. MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER SDA SCL mga807 Fig 16. System configuration 10.1.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • A slave receiver which is addressed must generate an acknowledge after the reception of each byte. • Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. • The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). • A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is shown in Figure 17. PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 29 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 8 9 S START condition clock pulse for acknowledgement mbc602 Fig 17. Acknowledge on the I2C-bus 10.2 I2C-bus protocol This driver does not support read. The PCF8531 is a slave receiver. Therefore, it only responds when R/W = 0 in the slave address byte. Before any data is transmitted on the I2C-bus, the device that must respond is addressed first. Two 7-bit slave addresses (0111100 and 0111101) are reserved for the PCF8531. The least significant bit of the slave address is set by connecting the input SA0 to either logic 0 (VSS) or logic 1 (VDD). The I2C-bus protocol is shown in Figure 18. The sequence is initiated with a START condition (S) from the I2C-bus master, and is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all others ignore the I2C-bus transfer. After acknowledgement, one or more command words follow, which define the status of the addressed slaves. A command word consists of a control byte, which defines Co and RS, plus a data byte (see Figure 19 and Table 11). The last control byte is tagged with a cleared most significant bit, the continuation bit Co. The control and data bytes are also acknowledged by all addressed slaves on the bus. After the last control byte, depending on the RS bit setting, either a series of display data bytes or command data bytes may follow. If the RS bit was set logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is automatically updated and the data is directed to the intended PCF8531 device. If the RS bit of the last control byte was set logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. The acknowledgement after each byte is made only by the addressed PCF8531. At the end of the transmission, the I2C-bus master issues a STOP condition (P). PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 30 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver slave address S 0 1 1 1 1 control byte 0 SA0 R/W A Co RS X X X X X X mgs474 Fig 18. Slave address and control byte acknowledge from PCF8531 S S 0 1 1 1 1 0 A 0 A 1 RS 0 slave address R/W Co acknowledge from PCF8531 control byte A acknowledge from PCF8531 data byte 2n ≥ 0 bytes A 0 RS Co acknowledge from PCF8531 control byte 1 byte A acknowledge from PCF8531 A P data byte n ≥ 0 bytes MSB . . . . . . . . . . . LSB mgs475 Fig 19. Master transmits to slave receiver; write mode 10.3 Command decoder The command decoder identifies command words that arrive on the I2C-bus. The most significant bit of a control byte is the continuation bit Co. If this bit is logic 1, it indicates that only one data byte (either command or RAM data) will follow. If this bit is logic 0, it indicates that a series of data bytes (either command or RAM data) may follow. The DB6 bit of a control byte is the RAM data/command bit RS. When this bit is logic 1, it indicates that another RAM data byte will be transferred next. If the bit is logic 0, it indicates that another command byte will be transferred next. • Pairs of bytes; information in the second byte, the first byte determines whether information is display or instruction data • Stream of information bytes after Co = 0; display or instruction data, depending on last RS. PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 31 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 11. Internal circuitry PADS 43 to 49 PADS 35 to 42 VDD2 VDD1 VSS1 VSS1 PADS 32 to 34 VDD3 VSS1 VSS2 PADS 64 to 70 PADS 57 to 63 PADS 57 to 63 PADS 16, 24 to 30 VLCDIN (SUPPLY), VSS2 PADS 17 to 23 VLCDOUT VLCDSENSE VSS1 VSS1 VSS1 VLCDIN VDD1 PADS 73, 74, 50, 51, 52 PADS 87 to 248 SCL, SDA, SDACK VSS1 VSS1 VDD1 VDD1 PADS 15, 54, 71, 72, 56, 31, 55 PAD 78 OSC, SA0, T3, T1, T4, RES, ENR VSS1 T2 VSS1 mgs485 For all diagrams the maximum forward current is 5 mA and the maximum reverse voltage is 5 V. Fig 20. Device protection diagrams PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 32 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 12. Limiting values Table 14. Limiting values [1] In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDD1 supply voltage 1 logic supply −0.5 +5.5 V VDD2 supply voltage 2 multiplier supply −0.5 +4.5 V VDD3 supply voltage 3 multiplier supply −0.5 +4.5 V VLCD LCD supply voltage −0.5 +9.0 V VI input voltage −0.5 VDD + 0.5 V VO output voltage −0.5 VDD + 0.5 V IDD(LCD) LCD supply current −50 +50 mA ISS ground supply current −50 +50 mA II input current −10 +10 mA IO output current −10 +10 mA Ptot total power dissipation - 300 mW P/out power dissipation per output VESD PCF8531 Product data sheet electrostatic discharge voltage Ilu latch-up current Tj junction temperature Tstg storage temperature Tamb ambient temperature - 30 mW HBM [2] - ±1500 V MM [3] - ±200 V [4] - 200 mA - +150 °C −65 +150 °C −40 +85 °C [5] operating device [1] Parameters are valid over the whole operating temperature range unless otherwise specified. All voltages are referenced to VSS unless otherwise specified. [2] Pass level; Human Body Model (HBM), according to Ref. 4 “JESD22-A114”. [3] Pass level; Machine Model (MM), according to Ref. 5 “JESD22-A115”. [4] Pass level; latch-up testing according to Ref. 6 “JESD78” at maximum ambient temperature (Tamb(max)). [5] According to the NXP store and transport requirements (see Ref. 8 “NX3-00092”) the devices have to be stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document. All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 33 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 13. Static characteristics Table 15. Static characteristics VDD1 = 1.8 V (1.9 V) to 5.5 V; VDD2 and VDD3 = 2.5 V to 4.5 V; VSS1 = VSS2 = 0 V; VDD1 to VDD3 ≤ VLCD ≤ 9.0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit [1] 4.0 - 9.0 V [1] 3.0 - 9.0 V logic supply 1.9 - 5.5 V Supplies VLCD LCD supply voltage icon mode VDD1 supply voltage 1 Tamb ≥ −25 °C 1.8 - 5.5 V VDD2 supply voltage 2 multiplier supply; LCD voltage internally generated 2.5 - 4.5 V VDD3 supply voltage 3 multiplier supply; LCD voltage internally generated 2.5 - 4.5 V IDD supply current power-down mode; internal VLCD - 2 10 μA [2][3] - 170 350 μA normal mode; external VLCD [2] - 10 50 μA normal mode; external VLCD [2][4] - 25 100 μA icon mode; external VLCD [2][5] - 15 70 μA 0.9 1.2 1.6 V normal mode; internal VLCD IDD(LCD) VPOR LCD supply current [6] power-on reset voltage Logic VIL LOW-level input voltage VSS - 0.3VDD V VIH HIGH-level input voltage 0.7VDD - VDD V IOL(SDA) LOW-level output current on pin SDA VOL = 0.4 V; VDD = 5.0 V 3.0 - - mA ILI input leakage current VI = VDD or VSS −1 - +1 μA - 12 20 kΩ row outputs: R0 to R33 - 12 20 kΩ −100 0 +100 mV - - ±3.9 % Column and row outputs RO output resistance column outputs: C0 to C127 ΔVbias bias voltage variation outputs R0 to R33 and C0 to C127 ΔVLCD LCD voltage variation TC1 to TC7 TC temperature coefficient Tamb = −20 °C to +70 °C Tints [7] [8] TC0; TC[2:0] = 000 - 0 - %/K TC1; TC[2:0] = 001 - −0.026 - %/K TC2; TC[2:0] = 010 - −0.039 - %/K TC3; TC[2:0] = 011 - −0.052 - %/K TC4; TC[2:0] = 100 - −0.078 - %/K TC5; TC[2:0] = 101 - −0.13 - %/K TC6; TC[2:0] = 110 - −0.19 - %/K TC7; TC[2:0] = 111 - −0.26 - %/K - 27 - °C intersection temperature PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 34 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver [1] As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD, the user must ensure, while setting the VOP register and selecting the temperature compensation, that the VLCD maximum limit of 9 V will never be exceeded under all conditions and including all tolerances. [2] LCD outputs are open circuit, inputs at VDD or VSS; bus inactive. [3] VDD1 to VDD3 = 2.85 V; VLCD = 7.0 V; voltage multiplier = 3 × VDD; fosc = 34 kHz. [4] VDD1 to VDD3 = 2.75 V; VLCD = 9.0 V; fosc = 34 kHz. [5] VDD1 to VDD3 = 2.75 V; VLCD = 3.5 V; fosc = 34 kHz. [6] Resets all logic when VDD1 < VPOR. [7] Iload ≤ 50 μA; outputs are tested one at a time. [8] VLCD ≤ 7.7 V. 14. Dynamic characteristics Table 16. Dynamic characteristics VDD1 = 1.8 V (1.9 V) to 5.5 V; VDD2 and VDD3 = 2.5 V to 4.5 V; VSS1 = VSS2 = 0 V; VDD1 to VDD3 ≤ VLCD ≤ 9.0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions ffr(LCD) LCD frame frequency VDD = 3.0 V fosc oscillator frequency fclk(ext) external clock frequency tw(RESL) RES LOW pulse width tsu(RESL) RES LOW set-up time Serial bus interface (see Figure [1] [2] Min Typ Max Unit 40 66 135 Hz 20 34 65 kHz 20 - 65 kHz 300 - - ns - - 30 μs - 400 kHz 22)[3] fSCL SCL clock frequency 0 tLOW LOW period of the SCL clock 1.3 - - μs tHIGH HIGH period of the SCL clock 0.6 - - μs tSU;DAT data set-up time 100 - - ns tHD;DAT data hold time 0 - 0.9 ns 20 + 0.1Cb - 0.3 μs 20 + 0.1Cb - 0.3 μs tr rise time of both SDA and SCL signals [4] tf fall time of both SDA and SCL signals [4] Cb capacitive load for each bus line - - 400 pF tSU;STA set-up time for a repeated START condition 0.6 - - μs tHD;STA hold time (repeated) START condition 0.6 - - μs tSU;STO set-up time for STOP condition 0.6 - - μs tSP pulse width of spikes that must be suppressed by the input filter - - 50 ns tBUF bus free time between a STOP and START condition 1.3 - - μs [1] ffr = fclk(ext)/480 or fosc/480. on bus [2] A reset is generated if tw(RESL) > 3 ns (see Figure 21). [3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH, with an input voltage swing of VSS to VDD. [4] Cb = total capacitance of one bus line in pF. PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 35 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver VDD RES VIL tsu(RESL) tw(RESL) mgs476 Fig 21. Reset timing SDA tBUF tLOW tf SCL tHD;STA tr tHD;DAT tHIGH tSU;DAT SDA tSU;STA tSU;STO mga728 Fig 22. I2C-bus timing PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 36 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver mgs477 400 mgs478 400 IDD IDD (μA) (μA) 2× 5× 300 300 4× 3× 200 200 VLCD = 9 V 7.5 V 4V 100 100 2 3 4 5 VDD2 and VDD3 (V) mgs479 9 VLCD 4 6 8 10 VLCD (V) VDD1 = 2 V; 4 × voltage multiplier; Tamb = 27 °C; TC = 0; BS = 100; no VLCD load. Fig 23. Supply current as a function of supply voltage 2 and supply voltage 3 2 VDD1 = 1.8 V; VDD2 and VDD3 = 2.6 V; Tamb = 27 °C; fosc = 34 kHz; no VLCD load. Fig 24. Supply current as a function of LCD supply voltage; different multiplication factors mgs480 30 I (μA) (V) 8 20 IDD(LCD) TC0 TC1 7 IDD 10 TC6 TC7 6 −50 0 0 50 T (°C) 100 PCF8531 Product data sheet 4 6 8 10 VLCD (V) VLCD = 7.5 V; VDD1 to VDD3 = 2.7 V; Tamb = 27 °C; no VLCD load. Fig 25. LCD supply voltage as a function of temperature 2 VDD1 = 1.8 V; VDD2 and VDD3 = 2.5 V; external VLCD; Tamb = 27 °C; TC = 0; BS = 100; no VLCD load. Fig 26. Supply current as a function of LCD supply voltage All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 37 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver mgs481 30 mgs482 86 I DD I (μA) (μA) 84 I DD(LCD) 20 82 10 I DD 80 78 0 0 20 40 60 f (kHz) 80 VDD1 = 2.5 V; VDD2 and VDD3 = 2.5 V; external VLCD; Tamb = 27 °C; TC = 0; BS = 100; no VLCD load. Fig 27. Supply current as a function of frequency PCF8531 Product data sheet 3 3.2 3.4 3.6 4 3.8 VLCD (V) VDD1 = 1.8 V; VDD2 = 2.5 V; 2 × voltage multiplier; Tamb = 27 °C; TC = 0; BS = 111; no VLCD load. Fig 28. Supply current as a function of LCD supply voltage All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 38 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 15. Application information 15.1 Typical system configuration VLCD VDD1 to VDD3 VDD(I2C) 128 column drivers 34 row drivers RES LCD PANEL ENR SA0 SDACK SCL Rpu PCF8531 SDA Rpu HOST MICROPROCESSOR/ MICROCONTROLLER VSS1, VSS2 VSS RES SCL SDA VSS1, VSS2 mgs483 Fig 29. Typical system configuration The host microprocessor/microcontroller and the PCF8531 are both connected to the I2C-bus. The SDA and SCL lines must be connected to the positive power supply via pull-up resistors. The internal oscillator requires no external components. The appropriate intermediate biasing voltage for the multiplexed LCD waveforms are generated on-chip. The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and suitable capacitors for decoupling VLCD and VDD. 15.2 Power supply connections for internal VLCD generation 1.8 V (1.9 V) to 5.5 V VDD1 VDD1 1 μF 2.5 V to 4.5 V 1 μF GND VDD2 VDD3 VSS1 VSS2 2.5 V to 4.5 V VDD2 VDD3 1 μF GND 013aaa354 VSS1 VSS2 013aaa355 Fig 30. Recommended VDD connections for internal VLCD generation PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 39 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver VLCDIN 1 μF VLCDOUT VSS2 VLCDSENSE 013aaa356 Fig 31. Recommended VLCD connections for internal VLCD generation 15.3 Power supply connections for external VLCD generation 1.8 V (1.9 V) to 5.5 V VLCDIN VDD1 4.0 V to 9.0 V VLCDIN 1 μF 4.0 V to 9.0 V VDD2 VDD3 GND n.c. VLCDOUT or n.c. VLCDOUT 1 μF VSS1 VSS2 VLCDSENSE VLCDSENSE 013aaa358 Remark: When using an external VLCD, the internal VLCD generator must never be switched on otherwise damages will occur. Fig 32. Recommended VDD connections for external VLCD generation 15.4 Information about VLCD connections VLCDIN — This input is used for generating the 5 LCD bias levels. It is the power supply for the bias level buffers. VLCDOUT — This is the VLCD output if VLCD is generated internally. It is the output of the charge pump. In this case pin VLCDOUT must be connected to VLCDIN and to VLCDSENSE (see Figure 31). VLCDOUT must be left open circuit when VLCD is supplied from an external source (see Figure 32). VLCDSENSE — When using the internal VLCD generation, this pin must be connected to VLCDOUT and VLCDIN (see Figure 31). When using an external VLCD supply it must be connected to VLCDIN or to ground (see Figure 32). PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 40 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 15.5 Chip-on-glass application DISPLAY 34 × 128 PIXELS 17 128 17 PCF8531 R I/O Rsupply Cext 3 I/O VDD1 to VDD3 VSS1 VSS2 VLCD mgs484 Fig 33. Chip-on-glass application The required minimum values for the external capacitors in a chip-on-glass application are: • Cext = 100 nF between VLCD and VSS1, VSS2; Cext = 470 nF between VDD1, VDD2, VDD3 and VSS1, VSS2. • Higher capacitor values are recommended for ripple reduction. • For COG applications, the recommended ITO track resistance must be minimized for the I/O and supply connections. Optimized values for these tracks are below 50 Ω for the supply (Rsupply) and below 100 Ω for the I/O connections (RI/O). • To reduce the sensitivity of the reset to ESD/EMC disturbances for a COG application, NXP strongly recommended implementing a series input resistance in the reset line (recommended minimum value 8 kΩ) on the glass (ITO). If the reset input is not used, this input must be connected to VDD1 using a short connection. PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 41 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 15.6 Programming example Table 17. Step Programming example for PCF8531 Serial bus byte Display Operation DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 1 1 1 1 0 SA0 0 start; slave address; R/W = 0 2 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 3 0 0 0 0 0 0 0 1 H[1:0] independent command; select function and RAM command page (H[1:0] = 00) 4 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 5 0 0 1 0 0 0 1 0 function and RAM command page PD = 0 and V = 1 6 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 7 0 0 0 0 1 0 0 1 function and RAM command page select display setting command page H[1:0] = 01 8 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 9 0 0 0 0 1 1 0 0 display setting command page; set normal mode (D = 1; IM = 0 and E = 0) 10 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 11 0 0 0 0 0 1 0 1 select multiplex rate 1:34 12 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 13 0 0 0 0 0 0 0 1 H[2:0] independent command; select function and RAM command page H[1:0] = 00 14 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 15 0 0 0 0 1 0 1 0 function and RAM command page; select HV-gen command page H[1:0] = 10 16 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 17 0 0 0 0 1 0 1 1 HV-gen command page; select voltage multiplication factor 5 S[1:0] = 11 18 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 19 0 0 1 0 0 0 1 0 HV-gen command page; select temperature coefficient 2 TC[2:0] = 010 20 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 21 0 0 0 0 0 1 1 1 HV-gen command page; select high VLCD programming range (PRS = 1); voltage multiplier off (HVE = 1) 22 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 42 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver Table 17. Step Programming example for PCF8531 …continued Serial bus byte Display Operation DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 23 1 0 1 0 0 0 0 0 HV-gen command page; set VLCD = 7.71 V; VOP[6:0] = 0100000 24 0 1 0 0 0 0 0 0 control byte; Co = 0; RS = 1 25 0 0 0 1 1 1 1 1 data write; Y and X are initialized to 0 by default, so they are not set here mgs405 26 0 0 0 0 0 1 0 1 data write mgs406 27 0 0 0 0 0 1 1 1 data write mgs407 28 0 0 0 0 0 0 0 0 data write mgs407 29 0 0 0 1 1 1 1 1 data write mgs409 30 0 0 0 0 0 1 0 0 data write mgs410 31 0 0 0 1 1 1 1 1 data write; last data and stop transmission mgs411 32 0 1 1 1 1 0 SA0 0 repeated start; slave address; R/W = 0 mgs411 PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 43 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver Table 17. Step Programming example for PCF8531 …continued Serial bus byte Display Operation DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 33 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 mgs411 34 0 0 0 0 0 0 0 1 H[1:0] independent command; select function and RAM command page H[1:0] = 00 35 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 36 0 0 0 0 1 0 0 1 function and RAM command page; select display setting command page H[1:0] = 01 mgs411 37 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 38 0 0 0 0 0 0 0 1 H[1:0] independent command; select function and RAM command page H[1:0] = 00 39 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 40 0 0 0 0 1 1 0 1 display control; set inverse video mode (D = 1; E = 1 and IM = 0) mgs412 41 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 mgs412 42 1 0 0 0 0 0 0 0 set X address of RAM; set address to ‘0000000’ mgs412 43 0 1 0 0 0 0 0 0 control byte; Co = 0; RS = 1 mgs412 44 0 0 0 0 0 0 0 0 data write mgs414 PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 44 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 16. Package outline Not applicable. 17. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 18. Packing information Table 18. Tray dimensions (see Figure 34) Symbol Description Value A pocket pitch in x direction 13.72 mm B pocket pitch in y direction 4.17 mm C pocket width in x direction 12.34 mm D pocket width in y direction 2.05 mm E tray width in x direction 50.8 mm F tray width in y direction 50.8 mm x number of pockets, x direction 3 y number of pockets, y direction 10 x A C y D B F E mgs488 Fig 34. Tray details PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 45 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver PCF8531 mgs489 The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram (Figure 2) for the orientating and position of the type name on the die surface. Fig 35. Tray alignment 19. Abbreviations Table 19. PCF8531 Product data sheet Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor COG Chip-On-Glass DDRAM Double Data Random Access Memory EMC ElectroMagnetic Compatibility ESD ElectroStatic Discharge HBM Human Body Model HV High Voltage IC Integrated Circuit ITO Indium Tin Oxide LCD Liquid Crystal Display LSB Least Significant Bit MM Machine Model MPU MicroProcessor Unit POR Power-On Reset RAM Random Access Memory RC Resistance-Capacitance TC Temperature Coefficient SCL Serial Clock Line SDA Serial DAta line All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 46 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 20. References PCF8531 Product data sheet [1] AN10706 — Handling bare die [2] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [4] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [5] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) [6] JESD78 — IC Latch-Up Test [7] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [8] NX3-00092 — NXP store and transport requirements [9] UM10204 — I2C-bus specification and user manual All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 47 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 21. Revision history Table 20. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF8531 v.5 20100810 Product data sheet - PCF8531_4 Modifications: • • • • Added Figure 11, Figure 30 to Figure 32 Added Section 15.2 to Section 15.4 Changes and corrections in Table 4 and Table 11 Deleted old fab information PCF8531_4 20080613 Product data sheet - PCF8531_3 PCF8531_3 20000211 Product data sheet - PCF8531_2 PCF8531_2 19990810 Product data sheet - PCF8531_SDS_1 PCF8531_SDS_1 19990322 Product data sheet - - PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 48 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 22. Legal information 22.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 22.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 22.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 49 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Bare die — All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department. 22.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 23. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCF8531 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 05 — 10 August 2010 © NXP B.V. 2010. All rights reserved. 50 of 51 PCF8531 NXP Semiconductors 34 x 128 pixel matrix driver 24. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 8 8.1 9 9.1 9.2 9.2.1 9.2.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 10 10.1 10.1.1 10.1.2 10.1.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . 14 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power-On Reset (POR) . . . . . . . . . . . . . . . . . 14 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 14 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Display data RAM . . . . . . . . . . . . . . . . . . . . . . 14 Timing generator. . . . . . . . . . . . . . . . . . . . . . . 14 Address counter . . . . . . . . . . . . . . . . . . . . . . . 14 Display address counter . . . . . . . . . . . . . . . . . 14 Command decoder . . . . . . . . . . . . . . . . . . . . . 14 Bias voltage generator . . . . . . . . . . . . . . . . . . 15 VLCD generator . . . . . . . . . . . . . . . . . . . . . . . . 15 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Column driver outputs. . . . . . . . . . . . . . . . . . . 15 Row driver outputs . . . . . . . . . . . . . . . . . . . . . 15 LCD waveforms and DDRAM to data mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Function set . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Set Y address . . . . . . . . . . . . . . . . . . . . . . . . . 21 Set X address . . . . . . . . . . . . . . . . . . . . . . . . . 21 Set multiplex rate . . . . . . . . . . . . . . . . . . . . . . 21 Display control (D, E, and IM). . . . . . . . . . . . . 21 Set bias system . . . . . . . . . . . . . . . . . . . . . . . 22 LCD bias voltage . . . . . . . . . . . . . . . . . . . . . . 23 Set VLCD value . . . . . . . . . . . . . . . . . . . . . . . . 23 Voltage multiplier control S[1:0] . . . . . . . . . . . 24 Temperature compensation . . . . . . . . . . . . . . 24 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 28 Characteristics of the I2C-bus. . . . . . . . . . . . . 28 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 START and STOP conditions . . . . . . . . . . . . . 28 System configuration . . . . . . . . . . . . . . . . . . . 28 10.1.4 10.2 10.3 11 12 13 14 15 15.1 15.2 15.3 15.4 15.5 15.6 16 17 18 19 20 21 22 22.1 22.2 22.3 22.4 23 24 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . Command decoder . . . . . . . . . . . . . . . . . . . . Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics. . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Typical system configuration . . . . . . . . . . . . . Power supply connections for internal VLCD generation . . . . . . . . . . . . . . . . . . . . . . . Power supply connections for external VLCD generation . . . . . . . . . . . . . . . . . . . . . . . Information about VLCD connections . . . . . . . Chip-on-glass application. . . . . . . . . . . . . . . . Programming example. . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Packing information . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 30 31 32 33 34 35 39 39 39 40 40 41 42 45 45 45 46 47 48 49 49 49 49 50 50 51 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 10 August 2010 Document identifier: PCF8531