INTEGRATED CIRCUITS DATA SHEET SAA7335 DSP for CD and DVD-ROM systems Preliminary specification File under Integrated Circuits, IC01 1997 Aug 11 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems FEATURES • Compatibility with CD-I, CD-ROM, MPEG-video DVD-ROM and DVD-video applications • Designed for very high playback speeds • Typical CD-ROM operation up to n = 12, DVD-ROM to n = 1.9, maximum rates (tbf) • Matched filtering, quad-pass error correction (C1-C2-C1-C2), overspeed audio playback function included (up to 3 kbytes buffer) In DVD modes double-pass C1-C2 error correction is used which is capable of correcting up to 5 C1 frame errors and 16 C2 frame errors. • Lock-to-disc playback, Constant Angular Velocity (CAV), pseudo-Constant Linear Velocity (CLV) and CLV motor control loops The SAA7335 contains all the functions required to decode an EFM or EFM+ HF signal directly from the laser pre-amplifier, including analog front-end, PLL data recovery, demodulation and error correction. The spindle motor interface provides both motor control signals from the demodulator and, in addition, contains a tachometer loop that accepts tachometer pulses from the motor unit. • Interface to 32 kbytes SRAM for DVD error correction and de-interleave • Sub-code/ header processing for DVD and CD formats • Programmable HF equalizer The SAA7335 has two independent microcontroller interfaces. The first is a serial I2C-bus and the second is a standard 8-bit multiplexed parallel interface. Both of these interfaces provide access to a total of 32 × 8-bit registers for control and status. • In DVD mode it is still compatible with Philips block decoders • Sub-CPU interface can be parallel or fast I2C-bus • On-chip clock multiplier. This data sheet contains an descriptive overview of the device together with electrical and timing characteristics. For a detailed description of the device refer to the user guide “SAU/UM96018”. GENERAL DESCRIPTION This device is a high-end combined Compact Disc (CD) and Digital Versatile Disc (DVD) compatible decoding device. The device operates with an external 32 kbytes S-RAM memory for de-interleaving operations. The device provides quad-pass error correction for CD-ROM applications (C1-C2-C1-C2) and operates in lock-to-disk, CAV, pseudo CLV and CLV modes. Supply of this CD/DVD IC does not convey an implied license under any patent right to use this IC in any CD or DVD application. QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDDD digital supply voltage 4.5 5.0 5.5 V IDDD digital supply current − 70 300 mA VDDA analog supply voltage 4.5 5.0 5.5 V IDDA analog supply current − 70 300 mA fxtal crystal input frequency 4 25 tbf MHz Tamb operating ambient temperature −20 − +70 °C Tstg storage temperature −55 − +125 °C 1997 Aug 11 2 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION SAA7335GP LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1 BLOCK DIAGRAM handbook, full pagewidth HF input SRAM 32 KBYTES ADC PLL BIT DETECTOR DEMODULATOR EFM/EFM+ DECODER clock input CLOCK GENERATOR SPINDLE MOTOR CONTROL SAA7335 I2S-BUS OUTPUT INTERFACE block decoder output SUB-CPU INTERFACE MGK242 motor control Fig.1 Simplified block diagram. 1997 Aug 11 3 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems PINNING SYMBOL PIN TYPE DESCRIPTION VSSA1 1 supply Iref 2 I analog current reference input for ADC REFLo 3 I analog low reference input for ADC analog ground 1 REFHi 4 I analog high reference input for ADC VREF 5 I analog negative input HFIN 6 I analog positive input VSSA2 7 supply analog ground 2 AGCOUT 8 O VDDA2 9 supply analog supply voltage 2 analog test pin output VDDD1 10 supply digital supply voltage 1 VSSD1 11 supply OTD 12 I off track detect input MOTO1 13 O 3-state motor control output not connected, reserved digital ground 1 n.c. 14 − MOTO2/T3 15 I/O n.c. 16 − not connected, reserved T1 17 I tachometer 1 input T2 18 I tachometer 2 input VDDD2 19 supply digital supply voltage 2 VSSD2 20 supply digital ground 2 TEST1 21 I test input 1 TEST2 22 I test input 2 POR 23 I power-on reset input MUXSWICH 24 I use clock multiplier input n.c. 25 − not connected, reserved CL1 26 O divided clock output BCAIN 27 I BCA input SDA 28 I/O SCL 29 I sub-CPU I2C-bus serial clock input INT 30 O sub-CPU interrupt output (open-drain) VDDD3 31 supply digital supply voltage 3 VSSD3 32 supply digital ground 3 da7 33 I/O sub-CPU data bus bit 7 input/output (parallel) da6 34 I/O sub-CPU data bus bit 6 input/output (parallel) da5 35 I/O sub-CPU data bus bit 5 input/output (parallel) n.c. 36 − da4 37 I/O n.c. 38 − da3 39 I/O sub-CPU data bus bit 3 input/output (parallel) da2 40 I/O sub-CPU data bus bit 2 input/output (parallel) 1997 Aug 11 motor control output/tachometer 3 input sub-CPU I2C-bus serial data input/output not connected, reserved sub-CPU data bus bit 4 input/output (parallel) not connected, reserved 4 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems SYMBOL PIN TYPE DESCRIPTION da1 41 I/O n.c. 42 − da0 43 I/O VDDD4 44 supply digital supply voltage 4 VSSD4 45 supply digital ground 4 WRi 46 I sub-CPU write enable input (active LOW) RDi 47 I sub-CPU read enable input (active LOW) ALE 48 I sub-CPU address latch enable input CSi 49 I sub-CPU chip select input (active HIGH) STOPCLOCK 50 O stop clock output n.c. 51 − not connected, reserved V4 52 O serial subcode output (for CD) EBUOUT 53 O digital audio output SYNC 54 O I2S-bus sector sync output FLAG 55 O I2S-bus correction flag output DATA 56 O I2S-bus serial data output BCLK 57 I/O I2S-bus bit serial clock input/output WCLK 58 I/O I2S-bus word clock input/output VDDD5 59 supply digital supply voltage 5 VSSD5 60 supply digital ground 5 RAMRW 61 O RAM read/write control output n.c. 62 − not connected, reserved RAMDA7 63 I/O RAM data bus bit 7 input/output RAMDA6 64 I/O RAM data bus bit 6 input/output RAMDA5 65 I/O RAM data bus bit 5 input/output RAMDA4 66 I/O RAM data bus bit 4 input/output RAMDA3 67 I/O RAM data bus bit 3 input/output RAMDA2 68 I/O n.c. 69 − RAMDA1 70 I/O sub-CPU data bus bit 1 input/output (parallel) not connected, reserved sub-CPU data bus bit 0 input/output (parallel) RAM data bus bit 2 input/output not connected, reserved RAM data bus bit 1 input/output RAMDA0 71 I/O VDDD6 72 supply digital supply voltage 6 VSSD6 73 supply digital ground 6 RAMAD0 74 O RAM address bit 0 output RAMAD1 75 O RAM address bit 1 output RAMAD2 76 O RAM address bit 2 output RAMAD3 77 O RAM address bit 3 output RAMAD4 78 O RAM address bit 4 output RAMAD5 79 O RAM address bit 5 output RAMAD6 80 O RAM address bit 6 output VDDD7 81 supply 1997 Aug 11 RAM data bus bit 0 input/output digital supply voltage 7 5 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems SYMBOL PIN TYPE VSSD7 82 supply RAMAD7 83 O RAM address bit 7 output RAMAD8 84 O RAM address bit 8 output RAMAD9 85 O RAM address bit 9 output n.c. 86 − not connected, reserved RAMAD10 87 O RAM address bit 10 output RAMAD11 88 O RAM address bit 11 output RAMAD12 89 O RAM address bit 12 output RAMAD13 90 O RAM address bit 13 output RAMAD14 91 O RAM address bit 14 output VDDD8 92 supply digital supply voltage 8 VSSD8 93 supply digital ground 8 CRIN 94 I analog crystal input CROUT 95 O analog crystal output CFLG 96 O correction statistics output MEAS1 97 O front-end telemetry output VDDD9 98 supply digital supply voltage 9 VSSD9 99 supply digital ground 9 VDDA1 100 supply analog supply voltage 1 1997 Aug 11 DESCRIPTION digital ground 7 6 Philips Semiconductors Preliminary specification SAA7335 76 RAMAD2 77 RAMAD3 78 RAMAD4 79 RAMAD5 80 RAMAD6 82 VSSD7 81 VDDD7 83 RAMAD7 84 RAMAD8 85 RAMAD9 86 n.c. 87 RAMAD10 88 RAMAD11 89 RAMAD12 90 RAMAD13 93 VSSD8 92 VDDD8 94 CRIN 95 CROUT 96 CFLG 97 MEAS1 99 VSSD9 98 VDDD9 100 VDDA1 handbook, full pagewidth 91 RAMAD14 DSP for CD and DVD-ROM systems VSSA1 1 75 RAMAD1 Iref 2 74 RAMAD0 REFLo 3 REFHi 4 73 VSSD6 72 VDDD6 VREF 5 71 RAMDA0 HFIN 6 70 RAMDA1 VSSA2 7 69 n.c. AGCOUT 8 68 RAMDA2 VDDA2 9 67 RAMDA3 VDDD1 10 66 RAMDA4 VSSD1 11 65 RAMDA5 OTD 12 64 RAMDA6 SAA7335 MOTO1 13 63 RAMDA7 n.c. 14 62 n.c. MOTO2/T3 15 61 RAMRW T1 17 60 VSSD5 59 VDDD5 n.c. 16 T2 18 58 WCLK VDDD2 19 57 BCLK VSSD2 20 56 DATA TEST1 21 55 FLAG TEST2 22 54 SYNC 53 EBUOUT POR 23 MUXSWICH 24 52 V4 51 n.c. Fig.2 Pin configuration. 1997 Aug 11 7 STOPCLOCK 50 CSi 49 ALE 48 RDi 47 WRi 46 VSSD4 45 VDDD4 44 da0 43 n.c. 42 da1 41 da2 40 da3 39 n.c. 38 da4 37 n.c. 36 da5 35 da6 34 da7 33 VSSD3 32 VDDD3 31 INT 30 SCL 29 SDA 28 BCAIN 27 CL1 26 n.c. 25 MGK241 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems 1. The coincidence counter: this is used to detect the coincidence of successive syncs. It generates a sync coincidence signal if 2 syncs are 588 ±1 EFM clocks apart. FUNCTIONAL DESCRIPTION Analog front-end This block converts the HF input to the digital domain using an 8-bit ADC proceeded by an AGC circuit to obtain the optimum performance from the convertor. This block is clocked by ADCCLK which is set by the external crystal frequency plus a flexible clock multiplier and divider block. 2. The main counter: this is used to partition the EFM signal into 17-bit words. This counter is reset when: a) A sync coincidence is generated b) A sync is found within ±6 EFM clocks of its expected position. PLL and bit detector This subsystem recovers the data from the channel stream. The block corrects asymmetry, performs noise filtering and equalisation and finally recovers the bit clock and data from the channel using a digital PLL. The sync coincidence signal is also used to generate the lock signal which will go active HIGH when 1 sync coincidence is found. It will reset to LOW when, during 61 consecutive frames, no sync coincidence is found. The equalizer and the data slicer are programmable. FRAME SYNC PROTECTION DVD MODE Digital logic This circuit detects the frame synchronization signals. Two synchronization counters are used in the SAA7335: All the digital system logic is clocked from the master ADC clock (ADCCLK) described above. 1. The coincidence counter: this is used to detect the coincidence of successive syncs. It generates a sync coincidence signal if 2 syncs are 1488 ±3 EFM+ clocks apart. Advanced bit detector The advanced bit detector offers improved data recovery for multi-layer discs and contains two extra detection circuits to increase the margins in the bit recovery block: 2. The main counter: this is used to partition the EFM+ signal into 16-bit words. This counter is reset when: 1. Adaptive slicer: adds a second stage slicer with higher bandwidth b) A sync is found within ±10 EFM+ clocks of its expected position. a) A sync coincidence is generated 2. Run length 2 push-back: all T2 run lengths are pushed back to T3, thereby automatically determining the erroneous edge and shifting the transitions on that edge. The sync coincidence signal is also used to generate the lock signal which will go active HIGH when 1 sync coincidence is found. It will reset to LOW when, during 61 consecutive frames, no sync coincidence is found. Demodulator EFM/EFM+ demodulation FRAME SYNC PROTECTION CD MODE The 14-bit EFM (16-bit EFM+) data and subcode words are decoded into 8-bit symbols. This circuit detects the frame synchronization signals. Two synchronization counters are used in the SAA7335: 1997 Aug 11 8 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems The sequence for a write data command (1 data byte) is as follows: Microcontroller interface The SAA7335 has two microcontroller interfaces, one serial I2C-bus and one parallel (8051 microcontroller compatible). • Send START condition • Send address 3EH (write) The two communication modes may be operated at the same time, the modes are described below: • Write command address byte 1. Parallel mode: protocol compatible with 8052 multiplexed bus: • Send STOP condition. • Write data byte a) da0 to da7 = address/data bus The sequence for a read data command (that reads 1 data byte) is as follows: b) ALE = Address Latch Enable, latches the address information on the bus • Send START condition c) WRi = active LOW write signal for write to SAA7335 • Write status address byte • Send address 3EH (write) • Send STOP condition d) RDi = active LOW read signal for read from SAA7335 • Send START condition • Send address 3FH (read) e) CSi = active HIGH Chip Select signal (this signal gates the RDi and WRi signals). • Read data byte 2. I2C-bus mode: I2C-bus protocol where SAA7335 behaves as slave device where: • Send STOP condition. a) SDA = I2C-bus data b) SCL = I2C-bus READING AND WRITING DATA TO THE SAA7335 The SAA7335 has 32 × 8-bit configuration and status registers as shown in Table 1. Not all locations are currently defined and some remain reserved for future upgrades. These can be written to or read from via the microcontroller interface using either the serial or parallel control bus. clock c) I2C-bus slave address (write mode) = 3EH d) I2C-bus slave address (read mode) = 3FH e) Maximum data transfer rate = 400 kbits/s. MICROCONTROLLER INTERFACE (I2C-BUS MODE) Bytes are transferred over the interface in single bytes of which there are two types; write data commands and read data commands. 1997 Aug 11 9 SAA7335 microcontroller register map ADDRESS BIT NAME DEC HEX 0 0 1 1 2 3 4 2 3 4 R/W 7 PLL_LOCK Lock Oride PLL_Freq_R R PLL measured frequency (bits 9 to 2) PLL_SET W SliceBW PLL_ASSYM R PLL asymmetry value (8 bits) PLL_FREQ W PLL frequency (8 MSBs) PLL_Jit R jitter value (bits 9 to 2) PLL_EQU W PLL frequency (2 LSBs) PLL_Lock_In R reserved PLL_F_MEAS W RL3_EN reserved R − W Fmat(3 to 1) 10 5 OUTPUT1 reserved R − 6 6 OUTPUT2 W EBU_Valid reserved R − OUTPUT3 W WCLK_H_ Left reserved R − 7 5 W 5 7 6 8 8 SEMA1 W 9 9 SEMA2 W 4 Pha_Oset 3 2 1 PLL_Force_L Integ_F0 PLLBW_F1 equalizer tap α 1 LP_BW_F3 equaliser tap α 2 Long_Symb F_Lock reserved − − − Descr_On − In_Lock EFM nominal setting (101110) − − WCLK_Op EBU_On 0 − − EBU control bits 28, 29 − Interp_On − − BCLK_Op − Fmat (0) − − − SyncSwap (1 and 0) − − − − − EBU control bits (1 to 4) − CD_ROM_ Flag_Pin Header_On − − Philips Semiconductors Table 1 DSP for CD and DVD-ROM systems 1997 Aug 11 REGISTER MAP − Kill Data On Kill EBU_On − − − CD_ROM_ Scrb_On − general purpose semaphore register R general purpose semaphore register R 10 A SEMA3 W general purpose semaphore register B INTEN Status R Fl_S1 12 C MOTOR1 W frequency set point SLICE1 R slice compensation value MOTOR2 W G(2 to 0) EYE_Open R eye opening value 13 D W hardware pin interrupt enable bits (map to status bits) Fl_S2 Fl_S3 PLL lock Ki DVD rdy Mot Ov Kf Tacho reserved SAA7335 11 Preliminary specification R DEC HEX 14 E R/W 7 MOTOR3 W MTR_F R W 15 F MOTO4 reserved R 16 10 MTR_INTG_L W 6 5 4 3 2 1 0 − − − − − − − − − FIFO set point − PWM_PDM OVF_SW − SW2 − SW1 − motor servo control (3 to 0) − − − motor integrator value (7 to 0) R 17 11 MTR_INTG_H W motor integrator value (15 to 8) R 18 12 19 13 20 11 21 22 23 24 15 16 17 18 19 W CL1Div BCLKG_En Div1 (2 to 0) busy SUB_C_STAT R ready DECMODE W mode CRC_OK SUB_C_DATA R subcode data (7 to 0) Mux 2 err (2 to 0) reserved − − − − reserved W SUB_C_End R no meaning (register read used as a signal) ANASET W AGC_En FIFOFILL_L R number of C1 frames in FIFO VITSET W slice ON AdDet ON FEndAutoS ON BCA_STAT R Buff_ Loaded sync Buff_ORun gain set gain up gain down − AGC_On TACHO1 W tachometer multiplier frequency KTacho (7 to 0) BCA_DATA R BCA data (7 to 0) TACHO2 W tachometer interrupt trip frequency tachometer trip (7 to 0) reserved R TACHO3 W reserved R 1A BCASET W reserved R 27 to 31 1B to 1F reserved − − − servo control source Tacho FRes − − Moto2_T3 − − cor fail reserved read TOC reserved − − − − reserved − Fsam TachoInt_LF reserved − − − − − − − − − − − − − − − − − − − − − − − BCA_Freq (7 to 0) SAA7335 26 Div2 (2 to 0) Preliminary specification 25 14 CLOCKPRE Philips Semiconductors BIT NAME DSP for CD and DVD-ROM systems 1997 Aug 11 ADDRESS Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems READING STATUS INFORMATION FROM THE SAA7335 There are several internal status signals which can be made available on the INT line (see Table 2). Table 2 Internal status signals; note 1 SIGNAL Fl_S1 Fl_S2 Fl_S3 PLLlock DVDrdy MotOv Tacho DESCRIPTION change in semaphore register 1 detected change in semaphore register 2 detected change in semaphore register 3 detected channel data PLL lock (not latched) indicates in-lock condition DVD header or subcode block is available, reset when SUBREADEND register is read motor overflow, (not latched) indicates when a motor overflow is occurring motor speed is higher (or lower depending on TACHO3 bit 2) than motor set point (defined in TACHO2) this signal is not latched Note 1. The status signal to be output is selected by interrupt control register. and with both fundamental and third overtone crystals. External components should be used to suppress the fundamental output of the third overtone crystals as shown in Figs 3 and 4. Typical oscillation frequencies required are 8.462, 16.9344 or 22.57 MHz depending on the internal clock settings used and whether or not the clock multiplier is enabled. Subcode data/DVD header processing Q-CHANNEL PROCESSING The 96-bit Q-channel word is accumulated in an internal buffer. Sixteen bits are used to perform a Cyclic Redundancy Check (CRC). Subcode is available via the V4 output and, in addition, the Q channel code can also be read via the SUBREADDATA register. Error corrector DVD HEADER The data on the V4 pin is clocked on the WCLK edges with a fixed delay and so may be clocked by external circuitry running off the WCLK edges, i.e. at twice the WCLK frequency.The subcode data is also available in the EBU output (DOBM) in a similar format. The error corrector can operate in a number of modes; CD single-pass, CD dual-pass and DVD mode. In the CD single-pass mode the error corrector performs 2 error corrections per frame (C1 and C2). In the CD dual-pass mode up to 4 symbol corrections per frame are possible (C1-C2 then C1-C2 again). For the DVD mode full depth PI and PO error correction is performed allowing 5 corrections per PI row and full depth (2t + e) ≤16 correction to be performed per PO column. The error corrector also contains a flag controller. Flags are assigned to symbols when the error corrector cannot ascertain if the symbols are definitely good. C1 generates output flags which are read (after de-interleaving) by C2, to help in the generation of C2 output flags. The C2 output flags are used by the interpolator for concealment of non-correctable errors. They are also output via the EBU signal (DOBM) and the MISC output via the I2S-bus for CD-ROM applications. Crystal oscillator The flags output pin CFLG provides information on the state of all error correction and concealment flags. The DVD header processor accumulates a selection of bytes from the beginning of the DVD sector. Two header modes are defined, one for reading the normal sector headers and one for filtering the disk physical format information (from the control data block in the lead-in area) This is controlled by the READ_TOC bit in the DECMODE register. OTHER SUBCODE CHANNELS Data of the other subcode channels (Q-to-W) may be read via the V4 pin, this is only valid in CD modes. The crystal oscillator is a conventional 2 pin design. This oscillator is capable of operating with ceramic resonators 1997 Aug 11 12 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems handbook, halfpageSAA7335 OSCILLATOR CROUT CRIN 8.4672 MHz 330 Ω 100 kΩ 22 pF 22 pF MGK243 Fig.3 8.4672 MHz fundamental configuration. handbook, halfpageSAA7335 OSCILLATOR CROUT CRIN 22.57 MHz 330 Ω 3.3 µH 100 kΩ 10 pF 10 pF 1 nF MGK244 Fig.4 22.57 MHz overtone configuration. Interpolation OK Error Hold OK Error Interpolation Error Error OK OK MGA372 Fig.5 Concealment mechanism. 1997 Aug 11 13 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems Table 3 DAC interface formats (notes 1, 2 and 3) Audio functions CONCEALMENT MODE BITS/WORD FORMAT 1 16 Philips I2S-bus 2 16 EIAJ 3 24 Philips I2S-bus 4 24 EIAJ 5 32 Philips I2S-bus 6 32 EIAJ 7 variable Philips I2S-bus A 1-sample linear interpolator becomes active if a single sample is flagged as erroneous but cannot be corrected. The erroneous sample is replaced by a level midway between the preceding and following samples. Left and right channels have independent interpolators. If more than one consecutive non-correctable sample is found the last good sample is held. A 1-sample linear interpolation is then performed before the next good sample (see Fig.5). Notes 1. EIAJ is the abbreviation for Electronic Industries Associated of Japan. DAC Interface The SAA7335 is compatible with a wide range of ROM block decoders and Digital-to-Analog Converters DACs. The seven main formats that are supported are given in Table 3. 2. Number of BCLK periods per half WCLK period (i.e. bits per sample). 3. Clock gating must be DISABLED for format mode 7. handbook, BCLK full pagewidth DATA D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 MISC flag-MSB (1 is unreliable) WCLK flag-LSB left flag-MSB right SYNC MGK245 Fig.6 Philips I2S-bus data format 1 (16-bit word length). 1997 Aug 11 14 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems handbook, full pagewidth BCLK DATA D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 MISC flag-MSB (1 is unreliable) flag-LSB right WCLK flag-MSB left SYNC MGK246 Fig.7 EIAJ (‘S’) data format 2 (16-bit word length). BCLK handbook, full pagewidth DATA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 MISC flag-MSB (1 is unreliable) WCLK flag-LSB flag-MSB left right SYNC MGK247 Fig.8 Philips I2S-bus data format 3 (24-bit word length). BCLK handbook, full pagewidth DATA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 MISC flag-LSB flag-MSB (1 is unreliable) WCLK right flag-MSB left SYNC MGK248 Fig.9 EIAJ (‘S’) data format 4 (24-bit word length). 1997 Aug 11 15 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 MISC flag-MSB (1 is unreliable) WCLK flag-LSB flag-MSB left right SYNC MGK249 Fig.10 Philips I2S-bus data format 5 (32-bit word length). Philips Semiconductors DATA DSP for CD and DVD-ROM systems 1997 Aug 11 BCLK 16 BCLK DATA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 MISC flag-MSB (1 is unreliable) flag-MSB left SYNC MGK250 SAA7335 Fig.11 EIAJ (‘S’) data format 6 (24-bit word length). Preliminary specification WCLK flag-LSB right Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems variable number of clocks handbook, full pagewidth BCLK DATA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 FLAG flag-MSB (1 is unreliable) WCLK flag-LSB left flag-MSB right SYNC MGK251 Fig.12 Philips I2S-bus data format (variable word length). EBU interface AUDIO SAMPLE The biphase-mark digital output signal at pin DOBM is in accordance with the format defined by the “IEC 958” specification. Left and right samples are transmitted alternately. Three different modes can be selected via the EBU output control register (address 1010). Audio samples are flagged (bit 28 = logic 1) if an error has been detected but was non-correctable. This flag remains the same even if data is taken after concealment. VALIDITY FLAG FORMAT USER DATA The digital audio output consists of 32-bit words (subframes) transmitted in biphase-mark code (2 transitions for a logic 1 and one transition for a logic 0). Words are transmitted in blocks of 384 (see Table 4). Subcode bits Q-to-W from the subcode section are transmitted via the user data bit. This data is asynchronous with the block rate. SYNC CHANNEL STATUS The sync word is formed by violation of the biphase rule and therefore does not contain any data. Its length is equivalent to 4 data bits. The three different sync patterns indicate the following situations: The channel status bit is the same for left and right words. Therefore a block of 384 words contains 192 channel status bits. The category code is always CD. The bit assignment is given in Table 5. • Sync B: start of a block (384 words), word contains left sample • Sync M: word contains left sample (no block start) • Sync W: word contains right sample. 1997 Aug 11 17 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems Table 4 EBU word format WORD BITS FUNCTION Sync 0 to 3 − Auxiliary 4 to 7 not used; normally zero Error flags Audio sample 4 8 to 27 CFLG error and interpolation flags when bit 3 of EBU control register is set to logic 1 first 4 bits not used (always zero) Validity flag 28 valid = logic 0 User data 29 used for subcode data (Q-to-W) Channel status 30 control bits and category code Parity bit 31 even parity for bits 4 to 30 Table 5 EBU channel status WORD BITS Consumer/professional 0 Control 1 to 4 FUNCTION always zero copied from bits 3 to 0 of register OUTPUT2, normally should be set to a copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when copy permitted; bit 3 is logic 1 when recording has pre-emphasis Reserved 5 to 7 always zero Category code 8 to 15 CD; bit 8 = logic 1, all other bits = logic 0 Reserved 16 to 27 always zero Clock accuracy 28 to 29 set by OUTPUT2 control register bits 5 and 4; 00 = level II, 01 = level III Remaining 30 to 191 always zero duty cycle corresponds with the motor not actuated, higher duty cycles mean acceleration, lower mean braking. Spindle motor control The spindle motor speed is controlled by a fully integrated digital servo. Address information from the internal ±8 frame FIFO and disc speed information are used to calculate the motor control output signals. In this mode, the MOTO2 signal is the inverse of the MOTO1 signal. Both signals change state only on the edges of a internal clock signal. Possible application diagrams are shown in Fig.13. Several output modes are supported: 1. Pulse density, 1-line, PWM MODE, 2-LINE 2. Pulse density, 2-line (true complement output) (cannot be used with tachometer control) In the PWM mode the motor acceleration signal is put in pulse-width modulation form on the MOTO1 output and the motor braking signal is pulse-width modulated on the MOTO2 output. 3. PWM output, 2-line. The modes are selected via the motor output configuration register. Figure 14 illustrates the PWM mode timing and Fig.15 illustrates a typical PWM mode application diagram. PULSE DENSITY MODE In the pulse density mode the motor output (pin MOTO1) is the pulse density modulated motor output signal. A 50% 1997 Aug 11 18 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems OPERATIONAL MODES The motor servo has a number of operational modes controlled by the motor mode register MOTOR4. POWER LIMIT To start and stop the spindle motor, a fixed positive or negative voltage is applied to the motor. This voltage can be programmed as a percentage of the maximum possible voltage via the motor output configuration register (MOTOR4) to limit current drain during start and stop. The following power limits are possible: • 100% of maximum (no power limit) • 75% of maximum • 50% of maximum • 37% of maximum. LOOP CHARACTERISTICS The gain and crossover frequencies of the motor control loop can be programmed via the motor gain and bandwidth register MOTOR2. 22 kΩ 22 kΩ MOTO1 + – 10 nF VDD MOTO2 + – M VSS 10 nF VSS 22 kΩ 22 kΩ MOTO1 22 kΩ + – 10 nF M VSS 22 kΩ VSS VSS 22 kΩ VDD MGA363 - 1 Fig.13 Motor pulse density application diagrams. 1997 Aug 11 19 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems t rep = 45 µs t dead 240 ns MOTO1 MOTO2 Accelerate Brake MGA366 Fig.14 Motor 2-line PWM mode timing. + M 10 Ω 100 nF MOTO1 MOTO2 VSS MGA365 - 2 Fig.15 Motor 2-line PWM mode application diagram. 1997 Aug 11 20 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems Flags output (CFLG) (open-drain output) A 1-bit flag signal is available at the CFLG pin, this contains 11 bits running off the ADCCLK, each bit period is 7 ADCCLK periods. This signal shows the status of the error corrector and interpolator and is updated every frame. handbook, halfpage pause START bit data bits MGK252 Fig.16 Flags output format. Table 6 Definition of flag bits BIT NUMBER VALUE 0 1 1 to 3 DESCRIPTION START bit 000 C1 first or C1 last; note 1 001 C2 first, CD mode reserved, DVD mode; note 1 010 reserved; note 1 011 C2 last; note 1 100 corrector not active; note 1 all others reserved 4 core fail 5 failure flag set because correction impossible; note 2 flag fail; note 3 9, 6 to 8 root count (3 to 0) 10 0 this indicates the number of errors corrected; note 4 STOP bit Notes 1. For DVD mode read PI for C1 and PO for C2. 2. This flag refers to the previous correction frame. 3. This flag refers to the previous correction frame (is not valid i.e. always logic 0 in DVD mode). 4. Bit order of root count is 9, then 6 to 8 for root count (3 to 0). ABSOLUTE TIME SYNC The sync signal is the absolute time sync signal. In the CD mode it is the FIFO-passed subcode sync and relates the position of the subcode sync to the audio data (DAC output). In the DVD mode it indicates the start of a new sector header. The flag may be used for special purposes such as synchronization of different players. 1997 Aug 11 21 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDDD digital supply voltage −0.3 +6.5 V VDDA analog supply voltage −0.3 +6.5 V Vi(max) maximum input voltage (any input) note 1 −0.3 VDD + 0.5 V Vo(max) maximum output voltage (any output) note 1 − VDD + 0.5 V Io(max) maximum output current (each output) − ±10 mA Tamb operating ambient temperature −20 +70 °C Tstg storage temperature −55 +125 °C VESD electrostatic handling human body model note 2 −2000 +2000 V machine model note 3 −200 +200 V Notes 1. This maximum value has an absolute maximum of 6.5 V independent of the supply voltage. 2. The human body model ESD simulation is equivalent to discharging a 100 pF capacitor via a 1.5 kΩ resistor, which produces a single discharge transient. Reference “Philips Semiconductors Test Method UZW-BO/FQ-A302 (similar to MIL-STD 883C method 3015.7)”. 3. The machine model ESD simulation is equivalent to discharging a 200 pF capacitor via a resistor and series inductor with effective dynamic values of 25 Ω and 2.5 µH, which produces a damped oscillating discharge. Reference “Philips Semiconductors Test Method UZW-BO/FQ-B302 (similar to EIAJ IC-121 Test Method 20 condition C)”. QUALITY This device will meet the requirements of the “Philips Semiconductors General Quality Specification UZW-BO/FQ-0601” in accordance with “Quality Reference Handbook (order number 9397 750 00192)”. This details the acceptance criteria for all Q & R tests applied to the product. 1997 Aug 11 22 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems DC CHARACTERISTICS VDDD = VDDA = 5 to 5.5 V; VSSD = VSSA = 0 V; Tamb = −20 to +70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDD digital supply voltage 4.5 − 5.5 V VDDA analog supply voltage 4.5 − 5.5 V IDD(tot) total supply current − 60 − mA at 25 MHz clock Inputs DIGITAL INPUTS (TTL LEVEL); note 1 VIL LOW-level input voltage − − 0.8 V VIH HIGH-level input voltage 2.0 − − V VOL LOW-level output voltage 0.8 − − V VOH HIGH-level output voltage − − 2.4 V ANALOG INPUTS VI(max)(p-p) maximum input voltage (peak-to-peak value) − − 2 V VI(nom)(p-p) nominal input voltage (peak-to-peak value) − 1 − V DR dynamic range 41 − − dB B −3 dB bandwidth − − − MHz − − − MHz II(AGC) AGC input current − 1 − mA II(ADC) ADC input current − 24 − mA II(buf) output buffer input current − 3 − mA II(tot) total input current − − 28 mA 0 to 12 dB gain 12 to 20 dB gain Note 1. These inputs are analog, VIL and VIH values are quoted as a guide for digital RGB users. AC CHARACTERISTICS VDDD = VDDA = 4.5 to 5.5 V; VSSD = VSSA = 0 V; Tamb = −20 to +70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDD digital supply voltage IDDD digital supply current VDDA analog supply voltage IDDA analog supply current 1997 Aug 11 VDDD = 5 V VDDA = 5 V 23 4.5 5.0 5.5 V − 60 165 mA 4.5 5.0 5.5 V − 60 165 mA Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Analog front-end (VDDA = 4.5 to 5.5 V); HFIN fchan channel frequency − − 50 MHz Digital inputs VIL LOW-level input voltage − − 0.8 V VIH HIGH-level input voltage 2.0 − − V ILI input leakage current −10 − +10 µA Ci input capacitance − − 10 pF Vi = 0 to VDDD Open-drain output; pin INT VOL LOW-level output voltage 0 − 0.4 V IOL LOW-level output current − − 0 mA CL load capacitance − − 50 pF to(f) output fall time CL = 20 pF; note 1 − − 15 ns IOL = 1 mA 3-state outputs VOL LOW-level output voltage IOL = 0 mA 0 − 0.4 V VOH HIGH-level output voltage IOH = −8 mA 2.4 − − V CL load capacitance − − 50 pF to(r) output rise time − − 15 ns to(f) output fall time CL = 20 pF; note 1 − − 15 ns ILI(Z) 3-state leakage current Vi = 0 to VDDD −10 − +10 µA CL = 20 pF; note 1 3-state outputs; pins MOTO1, MOTO2 and DOBM VOL LOW-level output voltage VDDD = 4.5 to 5.5 V; 0 IOL = 10 mA − 0.8 V VOH HIGH-level output voltage VDDD = 4.5 to 5.5 V; −1 IOH = −10 mA − +2.4 V CL load capacitance − − 50 pF to(r) output rise time CL = 20 pF; note 1 − − 10 ns to(f) output fall time CL = 20 pF; note 1 − − 10 ns ILI(Z) 3-state leakage current Vi = 0 to VDDD −10 − +10 µA − − 1.5 V Digital input/outputs (VDDD = 4.5 to 5.5 V) INPUT/OUTPUT: SDA (INPUT/OPEN-DRAIN I2C-BUS OUTPUT) VIL LOW-level input voltage VIH HIGH-level input voltage VOL LOW-level output voltage IOL 3.0 − − V − − 0.4 V LOW-level output current − − − mA CSDA serial data line capacitance − − 10 pF CSCL serial clock line capacitance − − 10 pF NmarL LOW-level noise margin − 0.1VDDD − NmarH HIGH-level noise margin − 0.2VDDD − 1997 Aug 11 IOL = 2 mA; Isink = 3 mA 24 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems SYMBOL PARAMETER Rs series resistance on the SDA and SCL lines Cbus(max) maximum bus capacitance CONDITIONS per wire MIN. TYP. MAX. UNIT − 300 − Ω − 400 − pF −0.3 − 0.3VDDD V INPUT: SCL (CMOS INPUT) VIL LOW-level input voltage VIH HIGH-level input voltage ILI input leakage current Ci input capacitance Vi = 0 − VDDD 0.7VDDD − VDDD + 0.3 V −10 − +10 µA − − 10 pF Crystal oscillator input CRIN (external clock) gm mutual conductance at start-up − 4 − mS Ro output resistance at start-up − 11 − kΩ Ci input capacitance − − 10 pF ILI input leakage current −10 − +10 µA Crystal oscillator output CROUT (see Figs 3 and 4) fxtal crystal frequency 4 25 − MHz Cfb feedback capacitance − − 5 pF Co output capacitance − − 10 pF − 472.4 − ns − − − ns − − − ns − − − ns − − − ns − − − ns − − − ns − tbf − ns I2S-bus timing CLOCK OUTPUT SCLK (see Fig.17) Tcy output clock period tSCLKH clock HIGH time tSCLKL tsu(SCLK) th(SCLK) 1997 Aug 11 set by CLKPRE1 register clock LOW time set-up time hold time 25 − tbf − ns − tbf − ns − tbf − ns − tbf − ns − tbf − ns Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT External RAM timing (see Figs 18 and 20) tAV-DV address valid to data valid − tbf − ns tOE-DV output enable to data valid − tbf − ns tW(W) write pulse width − tbf − ns tsu(A) address set-up before start of write − tbf − ns th(A) address hold after end of write − tbf − ns tsu(D-EW) data set-up to end of write − tbf − ns th(D-EW) data hold after end of write − tbf − ns tOE-DA output enable to data active − tbf − ns tOD-DI output disable to data inactive − tbf − ns − ns Microcontroller interface timing (see Figs 18 and 20) INPUT ALE tsu(A-ALE) address set-up before ALE LOW 25 − th(A-ALE) address hold after ALE LOW 25 − − ns tALEL input LOW time 1 × ADC − CLK + 15 − ns tALEH input HIGH time 1 × ADC − CLK + 15 − ns td(ALEL-WRL) delay time ALE LOW to WR LOW − − − ns tr rise time − − − ns tf fall time − − 240 ns INPUTS RDI AND WRI tIL(R/W) input LOW time 1 × ADC − CLK + 15 − ns tIH(R/W) input HIGH time 1 × ADC − CLK + 15 − ns tr rise time − − − ns tf fall time − − 240 ns td(RLDV) delay time RD LOW to DA0 to DA7 valid 2 × ADC − CLK + 35 − ns td(RHDX) delay time RD HIGH to DA0 to DA7 high-impedance 15 − − ns tsu(QVWX) set-up time WR LOW to DA0 to DA7 − − − ns th(WHQX) hold time WR HIGH to DA0 to DA7 3-state 2 × ADC − CLK + 25 − ns READ MODE WRITE MODE Notes 1. Timing reference voltage levels are 0.8 V and VDDD − 0.8 V. 2. Negative set-up time means that data may change after clock transition. 1997 Aug 11 26 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems Tcy tSCKL tSCLKH V DD – 0.8 V SCLK 0.8 V th(SCLK) tsu(SCLK) V DD – 0.8 V WCLK DATA MISC 0.8 V MGL507 Fig.17 I2S-bus timing. tALEL handbook, full pagewidth tALEH ALE 3 tIH(R/W) RDi th(A-ALE) tsu(A-ALE) DA0 to DA7 9 A0 to A7 td(RLDV) td(RHDX) DATA OUT MGK253 Fig.18 Microcontroller interface timing; parallel read mode. 1997 Aug 11 13 27 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems handbook, full pagewidth ALE tIH(R/W) td(ALEL-WRL) WRi tsu(QVWX) tsu(A-ALE) DA0 to DA7 th(A-ALE) th(WHDX) DATA IN A0 to A7 9 MGK254 Fig.19 Microcontroller interface timing; parallel write mode. tW(W) handbook, full pagewidth WE tOE-DV OE ADDRESS A1 A0 tsu(A) DATA A2 D1 X tsu(D-EW) tAD-DV tsu(D-EW) D2 D1 MBH995 tOD-DI read cycle Fig.20 External RAM timing. 1997 Aug 11 A4 tOE-DA th(A) write cycle A3 28 write cycle Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems APPLICATION INFORMATION The complete data path chipset consists of two ICs, the CD decoder (or DSP) device and the block decoder/host interface manager. In addition to these components a general purpose microcontroller and tracking servo is necessary to produce a complete controller system for a DVD mechanism. The DSP, block decoder and microcontroller are shown highlighted in Fig.21. An ADC application circuit is illustrated in Fig.22. handbook, full pagewidth MECHANISM/SERVO SUBSYSTEM DECODER/DATA PATH SUBSYSTEM RAM BUFFER laser spindle motor PREAMPLIFIER SLED/FOCUS ACTUATORS CD-DSP DEMODULATION C1-C2 ERROR CORRECTOR SERVO CONTROL PD TRACKING (3 BEAM OPTIONAL FOR BACKWARD CD-ROM COMPATIBILITY) AUDIO DAC BLOCK DECODER (FOR CD-ROM COMPATIBILITY) AND HOST INTERFACE RAM BUFFER SYSTEM CONTROLLER MGK255 Fig.21 Basic DVD player block diagram. 1997 Aug 11 29 audio L/R output PC host interface user key switches Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems handbook, full pagewidth VCC TP1 97 98 99 R14 4.7 Ω SAA7335 100 C11 47 µF (50 V) C10 100 nF 1 2 3 R29 AGND1 10 kΩ X6 C16 2.2 nF 5 6 TP6 7 C17 22 nF 8 9 TP5 C19 AGND1 47 µF (50 V) AGND1 HF input 4 C18 22 nF R28 100 kΩ AGND1 C15 47 µF (50 V) VCC R25 4.7 Ω C14 100 nF MGK256 Fig.22 ADC application circuit. 1997 Aug 11 30 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems PACKAGE OUTLINE LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 c y X A 51 75 50 76 ZE e E HE A A2 (A 3) A1 w M θ bp Lp L pin 1 index 100 detail X 26 1 25 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.20 0.05 1.5 1.3 0.25 0.28 0.16 0.18 0.12 14.1 13.9 14.1 13.9 0.5 HD HE 16.25 16.25 15.75 15.75 L Lp v w y 1.0 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) θ 1.15 0.85 7 0o 1.15 0.85 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-12-19 97-08-04 SOT407-1 1997 Aug 11 EUROPEAN PROJECTION 31 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems If wave soldering cannot be avoided, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all LQFP packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1997 Aug 11 32 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF CD/DVD DEVICES Supply of this CD/DVD IC does not convey an implied license under any patent right to use this IC in any CD or DVD application. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Aug 11 33 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems NOTES 1997 Aug 11 34 Philips Semiconductors Preliminary specification SAA7335 DSP for CD and DVD-ROM systems NOTES 1997 Aug 11 35 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1997 SCA55 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 547027/1200/01/pp36 Date of release: 1997 Aug 11 Document order number: 9397 750 01764