74AUP1GU04 Low-power unbuffered inverter Rev. 5 — 29 June 2012 Product data sheet 1. General description The 74AUP1GU04 provides the single unbuffered inverting gate. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption; ICC = 0.9 A (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Multiple package options Specified from 40 C to +85 C and 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1GU04GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 74AUP1GU04GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 1.45 0.5 mm 74AUP1GU04GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 1 0.5 mm 74AUP1GU04GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9 1.0 0.35 mm SOT1115 74AUP1GU04GS 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0 1.0 0.35 mm SOT1202 74AUP1GU04GX 40 C to +125 C X2SON5 X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8 0.8 0.35 mm SOT1226 74AUP1GU04 NXP Semiconductors Low-power unbuffered inverter 4. Marking Table 2. Marking Type number Marking code[1] 74AUP1GU04GW pD 74AUP1GU04GM pD 74AUP1GU04GF pD 74AUP1GU04GN pD 74AUP1GU04GS pD 74AUP1GU04GX pD [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram VCC 540 Ω 50 Ω A 2 A Y 4 2 mna108 Fig 1. 1 Y 4 001aad073 mna109 Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 6. Pinning information 6.1 Pinning 74AUP1GU04 74AUP1GU04 n.c. A GND 1 5 n.c. 1 6 VCC A 2 5 n.c. GND 3 4 Y VCC 2 3 4 Y 001aaf168 Transparent top view 001aaf167 Fig 4. Pin configuration SOT353-1 74AUP1GU04 Product data sheet Fig 5. Pin configuration SOT886 All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 2 of 21 74AUP1GU04 NXP Semiconductors Low-power unbuffered inverter 74AUP1GU04 74AUP1GU04 n.c. n.c. 1 6 VCC A 2 5 n.c. GND 3 4 Y 5 VCC 4 Y 3 GND A 001aaf169 2 aaa-003014 Transparent top view Transparent top view Fig 6. 1 Pin configuration SOT891, SOT1115 and SOT1202 Fig 7. Pin configuration SOT1226 (X2SON5) 6.2 Pin description Table 3. Pin description Symbol Pin Description TSSOP5 and X2SON5 XSON6 n.c. 1 1 not connected A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. - 5 not connected VCC 5 6 supply voltage 7. Functional description Table 4. Function table[1] Input Output A Y L H H L [1] H = HIGH voltage level; L = LOW voltage level. 74AUP1GU04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 3 of 21 74AUP1GU04 NXP Semiconductors Low-power unbuffered inverter 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions VI < 0 V [1] VO < 0 V [1] Min Max Unit 0.5 +4.6 V 50 - mA 0.5 +4.6 V 50 - mA 0.5 VCC + 0.5 V VO output voltage IO output current - 20 mA ICC supply current - +50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C - 250 mW total power dissipation Ptot [1] [2] VO = 0 V to VCC Tamb = 40 C to +125 C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP5 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 and X2SON5 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC Min Max Unit supply voltage 0.8 3.6 V VI input voltage 0 3.6 V VO output voltage 0 VCC V Tamb ambient temperature 40 +125 C t/V input transition rise and fall rate 0 200 ns/V 74AUP1GU04 Product data sheet Conditions VCC = 0.8 V to 3.6 V All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 4 of 21 74AUP1GU04 NXP Semiconductors Low-power unbuffered inverter 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit V Tamb = 25 C VIH HIGH-level input voltage VCC = 0.8 V to 3.6 V 0.75 VCC - - VIL LOW-level input voltage VCC = 0.8 V to 3.6 V - - 0.25 VCC V VOH HIGH-level output voltage IO = 20 A; VCC = 0.8 V to 3.6 V VCC 0.1 - - V IO = 1.1 mA; VCC = 1.1 V 0.75 VCC - - V VOL LOW-level output voltage IO = 1.7 mA; VCC = 1.4 V 1.11 - - V IO = 1.9 mA; VCC = 1.65 V 1.32 - - V IO = 2.3 mA; VCC = 2.3 V 2.05 - - V IO = 3.1 mA; VCC = 2.3 V 1.9 - - V IO = 2.7 mA; VCC = 3.0 V 2.72 - - V IO = 4.0 mA; VCC = 3.0 V 2.6 - - V IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.31 V IO = 1.9 mA; VCC = 1.65 V - - 0.31 V IO = 2.3 mA; VCC = 2.3 V - - 0.31 V IO = 3.1 mA; VCC = 2.3 V - - 0.44 V IO = 2.7 mA; VCC = 3.0 V - - 0.31 V IO = 4.0 mA; VCC = 3.0 V - - 0.44 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.1 A ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.5 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC - 1.5 - pF CO output capacitance VO = GND; VCC = 0 V - 1.8 - pF V Tamb = 40 C to +85 C VIH HIGH-level input voltage VCC = 0.8 V to 3.6 V 0.75 VCC - - VIL LOW-level input voltage VCC = 0.8 V to 3.6 V - - 0.25 VCC V VOH HIGH-level output voltage IO = 20 A; VCC = 0.8 V to 3.6 V VCC 0.1 - - V IO = 1.1 mA; VCC = 1.1 V 0.7 VCC - - V IO = 1.7 mA; VCC = 1.4 V 1.03 - - V IO = 1.9 mA; VCC = 1.65 V 1.30 - - V IO = 2.3 mA; VCC = 2.3 V 1.97 - - V IO = 3.1 mA; VCC = 2.3 V 1.85 - - V IO = 2.7 mA; VCC = 3.0 V 2.67 - - V IO = 4.0 mA; VCC = 3.0 V 2.55 - - V 74AUP1GU04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 5 of 21 74AUP1GU04 NXP Semiconductors Low-power unbuffered inverter Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL LOW-level output voltage Conditions Min Typ Max Unit IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.37 V IO = 1.9 mA; VCC = 1.65 V - - 0.35 V IO = 2.3 mA; VCC = 2.3 V - - 0.33 V IO = 3.1 mA; VCC = 2.3 V - - 0.45 V IO = 2.7 mA; VCC = 3.0 V - - 0.33 V IO = 4.0 mA; VCC = 3.0 V - - 0.45 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.5 A ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.9 A V Tamb = 40 C to +125 C VIH HIGH-level input voltage VCC = 0.8 V to 3.6 V 0.75 VCC - - VIL LOW-level input voltage VCC = 0.8 V to 3.6 V - 0.25 VCC V VOH HIGH-level output voltage VOL LOW-level output voltage - IO = 20 A; VCC = 0.8 V to 3.6 V VCC 0.11 - - V IO = 1.1 mA; VCC = 1.1 V 0.6 VCC - - V IO = 1.7 mA; VCC = 1.4 V 0.93 - - V IO = 1.9 mA; VCC = 1.65 V 1.17 - - V IO = 2.3 mA; VCC = 2.3 V 1.77 - - V IO = 3.1 mA; VCC = 2.3 V 1.67 - - V IO = 2.7 mA; VCC = 3.0 V 2.40 - - V IO = 4.0 mA; VCC = 3.0 V 2.30 - - V V IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.11 IO = 1.1 mA; VCC = 1.1 V - - 0.33 VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.41 V IO = 1.9 mA; VCC = 1.65 V - - 0.39 V IO = 2.3 mA; VCC = 2.3 V - - 0.36 V IO = 3.1 mA; VCC = 2.3 V - - 0.50 V IO = 2.7 mA; VCC = 3.0 V - - 0.36 V IO = 4.0 mA; VCC = 3.0 V - - 0.50 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.75 A ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 1.4 A 74AUP1GU04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 6 of 21 74AUP1GU04 NXP Semiconductors Low-power unbuffered inverter 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9 Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min - 6.2 - - - - ns VCC = 1.1 V to 1.3 V 0.9 2.3 4.4 0.9 4.8 5.3 ns VCC = 1.4 V to 1.6 V 0.7 1.7 3.1 0.6 3.4 3.8 ns VCC = 1.65 V to 1.95 V 0.5 1.4 2.6 0.5 2.9 3.2 ns VCC = 2.3 V to 2.7 V 0.4 1.1 2.0 0.4 2.3 2.6 ns VCC = 3.0 V to 3.6 V 0.3 1.0 1.8 0.3 2.1 2.4 ns - 9.6 - - - - ns VCC = 1.1 V to 1.3 V 1.2 3.1 6.1 1.2 6.8 7.5 ns VCC = 1.4 V to 1.6 V 1.0 2.3 4.0 0.9 4.6 5.1 ns VCC = 1.65 V to 1.95 V 0.8 1.9 3.3 0.7 3.8 4.2 ns VCC = 2.3 V to 2.7 V 0.6 1.5 2.7 0.6 3.1 3.5 ns VCC = 3.0 V to 3.6 V 0.5 1.3 2.4 0.5 2.7 3.0 ns - 13.0 - - - - ns VCC = 1.1 V to 1.3 V 1.6 3.8 7.9 1.4 8.8 9.7 ns VCC = 1.4 V to 1.6 V 1.3 2.8 4.9 1.1 5.7 6.3 ns VCC = 1.65 V to 1.95 V 1.0 2.3 4.0 0.9 4.7 5.2 ns VCC = 2.3 V to 2.7 V 0.8 1.9 3.2 0.8 3.7 4.1 ns VCC = 3.0 V to 3.6 V 0.7 1.6 2.9 0.7 3.3 3.7 ns - 23.2 - - - - Max Max (85 C) (125 C) CL = 5 pF tpd [2] propagation delay A to Y; see Figure 8 VCC = 0.8 V CL = 10 pF tpd [2] propagation delay A to Y; see Figure 8 VCC = 0.8 V CL = 15 pF tpd [2] propagation delay A to Y; see Figure 8 VCC = 0.8 V CL = 30 pF tpd [2] propagation delay A to Y; see Figure 8 VCC = 0.8 V 74AUP1GU04 Product data sheet - VCC = 1.1 V to 1.3 V 2.4 6.0 13.1 2.2 14.8 16.3 ns VCC = 1.4 V to 1.6 V 2.0 4.2 7.6 1.8 9.0 9.9 ns VCC = 1.65 V to 1.95 V 1.7 3.6 6.1 1.5 7.2 8.0 ns VCC = 2.3 V to 2.7 V 1.4 2.9 4.8 1.3 5.7 6.3 ns VCC = 3.0 V to 3.6 V 1.2 2.5 4.3 1.1 5.1 5.7 ns All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 7 of 21 74AUP1GU04 NXP Semiconductors Low-power unbuffered inverter Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9 Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min VCC = 0.8 V - 1.2 - - - - pF VCC = 1.1 V to 1.3 V - 1.1 - - - - pF VCC = 1.4 V to 1.6 V - 1.2 - - - - pF VCC = 1.65 V to 1.95 V - 1.4 - - - - pF VCC = 2.3 V to 2.7 V - 2.8 - - - - pF VCC = 3.0 V to 3.6 V - 4.4 - - - - pF Max Max (85 C) (125 C) CL = 5 pF, 10 pF, 15 pF and 30 pF power dissipation capacitance CPD f = 1 MHz; VI = GND to VCC [1] All typical values are measured at nominal VCC. [2] tpd is the same as tPLH and tPHL [3] [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of the outputs. 12. Waveforms VI VM A input GND t PHL t PLH VOH VM Y output VOL mna640 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 8. Table 9. The data input (A) to output (Y) propagation delays Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 0.8 V to 3.6 V 0.5 VCC 0.5 VCC VCC 3.0 ns 74AUP1GU04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 8 of 21 74AUP1GU04 NXP Semiconductors Low-power unbuffered inverter VCC VEXT 5 kΩ G VI VO DUT CL RT RL 001aac521 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Table 10. Test circuit for measuring switching times Test data Supply voltage Load VEXT [1] VCC CL RL 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 M [1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ open GND 2 VCC For measuring enable and disable times RL = 5 k, for measuring propagation delays, setup and hold times and pulse width RL = 1 M. 74AUP1GU04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 9 of 21 74AUP1GU04 NXP Semiconductors Low-power unbuffered inverter 13. Additional characteristics Rbias = 560 kΩ VCC 0.47 μF input output 100 μF VI (f = 1 kHz) A IO GND mna050 I g fs = --------o V i VO is constant. Fig 10. Test set-up for measuring forward transconductance 001aad074 30 gfs (mA/V) 20 10 0 0 1 2 3 4 VCC (V) Tamb = 25 C. Fig 11. Typical forward transconductance as a function of supply voltage 74AUP1GU04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 10 of 21 74AUP1GU04 NXP Semiconductors Low-power unbuffered inverter 14. Application information Some applications for the 74AUP1GU04 are: • Linear amplifier (see Figure 12) • Crystal oscillator (see Figure 13). Remark: All values given are typical values unless otherwise specified. R2 VCC 1 μF R1 U04 ZL mna052 ZL > 10 k. R1 3 k. R2 1 M. Open loop gain: GOL = 20. G R1 1 + ------- 1 + G OL R2 OL Voltage amplification: A V = – -----------------------------------------. Vo(p-p) = VCC 1.5 V centered at 0.5 VCC. Unity gain bandwidth product is 5 MHz. Fig 12. Linear amplifier application R1 R2 U04 C1 C2 out mna053 C1 = 47 pF. C2 = 22 pF. R1 = 1 M to 10 M. R2 optimum value depends on the frequency and required stability against changes in VCC or average minimum ICC (ICC = 2 mA at VCC = 3.3 V and f = 10 MHz). Fig 13. Crystal oscillator application 74AUP1GU04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 11 of 21 74AUP1GU04 NXP Semiconductors Low-power unbuffered inverter 15. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm E D SOT353-1 A X c y HE v M A Z 5 4 A2 A (A3) A1 θ 1 Lp 3 L e w M bp detail X e1 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e e1 HE L Lp v w y Z(1) θ mm 1.1 0.1 0 1.0 0.8 0.15 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 1.3 2.25 2.0 0.425 0.46 0.21 0.3 0.1 0.1 0.60 0.15 7° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 REFERENCES IEC JEDEC JEITA MO-203 SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Fig 14. Package outline SOT353-1 (TSSOP5) 74AUP1GU04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 12 of 21 74AUP1GU04 NXP Semiconductors Low-power unbuffered inverter SOT886 XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm b 1 2 3 4x (2) L L1 e 6 5 e1 4 e1 6x A (2) A1 D E terminal 1 index area 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit mm max nom min A(1) 0.5 A1 b D E 0.04 0.25 1.50 1.05 0.20 1.45 1.00 0.17 1.40 0.95 e e1 0.6 0.5 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. Outline version SOT886 sot886_po References IEC JEDEC JEITA European projection Issue date 04-07-22 12-01-05 MO-252 Fig 15. Package outline SOT886 (XSON6) 74AUP1GU04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 13 of 21 74AUP1GU04 NXP Semiconductors Low-power unbuffered inverter XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm 1 SOT891 b 3 2 4× (1) L L1 e 6 5 e1 4 e1 6× A (1) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 max b D E e e1 L L1 mm 0.5 0.04 0.20 0.12 1.05 0.95 1.05 0.95 0.55 0.35 0.35 0.27 0.40 0.32 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 SOT891 Fig 16. Package outline SOT891 (XSON6) 74AUP1GU04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 14 of 21 74AUP1GU04 NXP Semiconductors Low-power unbuffered inverter XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1.0 x 0.35 mm 1 SOT1115 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 max 0.35 0.04 0.20 0.95 1.05 nom 0.15 0.90 1.00 0.55 min 0.12 0.85 0.95 0.3 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1115_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-07 SOT1115 Fig 17. Package outline SOT1115 (XSON6) 74AUP1GU04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 15 of 21 74AUP1GU04 NXP Semiconductors Low-power unbuffered inverter XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm 1 SOT1202 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.05 1.05 0.35 0.40 nom 0.15 1.00 1.00 0.55 0.35 0.30 0.35 min 0.12 0.95 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1202_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-06 SOT1202 Fig 18. Package outline SOT1202 (XSON6) 74AUP1GU04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 16 of 21 74AUP1GU04 NXP Semiconductors Low-power unbuffered inverter X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8 x 0.8 x 0.35 mm B A D SOT1226 X A E A1 A3 detail X terminal 1 index area e C v w b 1 2 terminal 1 index area C A B C y1 C y k D h 3 L 5 4 0 1 mm scale Dimensions Unit mm A(1) A1 A3 D Dh E b e k L max 0.35 0.04 0.128 0.85 0.30 0.85 0.27 0.27 nom 0.80 0.25 0.80 0.22 0.48 0.22 min 0.20 0.17 0.040 0.75 0.20 0.75 0.17 v 0.1 w y y1 0.05 0.05 0.05 Note 1. Dimension A is including plating thickness. 2. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version References IEC JEDEC EIAJ sot1226_po European projection Issue date 12-04-10 12-04-25 SOT1226 Fig 19. Package outline SOT1226 (X2SON5) 74AUP1GU04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 17 of 21 74AUP1GU04 NXP Semiconductors Low-power unbuffered inverter 16. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 17. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AUP1GU04 v.5 20120629 Product data sheet - 74AUP1GU04 v.4 Modifications: 74AUP1GU04 v.4 Modifications: • • Added type number 74AUP1GU04GX (SOT1226) Package outline drawing of SOT886 (Figure 15) modified. 20111116 • • Product data sheet - 74AUP1GU04 v.3 Legal pages updated. Package outline drawing SOT363 replaced by SOT353-1. 74AUP1GU04 v.3 20100721 Product data sheet - 74AUP1GU04 v.2 74AUP1GU04 v.2 20060803 Product data sheet - 74AUP1GU04 v.1 74AUP1GU04 v.1 20050810 Product data sheet - - 74AUP1GU04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 18 of 21 74AUP1GU04 NXP Semiconductors Low-power unbuffered inverter 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74AUP1GU04 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 19 of 21 74AUP1GU04 NXP Semiconductors Low-power unbuffered inverter Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74AUP1GU04 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 29 June 2012 © NXP B.V. 2012. All rights reserved. 20 of 21 74AUP1GU04 NXP Semiconductors Low-power unbuffered inverter 20. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Additional characteristics . . . . . . . . . . . . . . . . 10 Application information. . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 29 June 2012 Document identifier: 74AUP1GU04