74HC32; 74HCT32 Quad 2-input OR gate Rev. 5 — 4 September 2012 Product data sheet 1. General description The 74HC32; 74HCT32 is a quad 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V Complies with JEDEC standard JESD7A Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays Input levels: For 74HC32: CMOS level For 74HCT32: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C 74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate 3. Ordering information Table 1. Ordering information Type number 74HC32N Package Temperature range Name Description Version 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm 74HCT32N 74HC32D 74HCT32D 74HC32DB 74HCT32DB 74HC32PW 74HCT32PW 74HC32BQ 74HCT32BQ 4. Functional diagram 1 ≥1 3 ≥1 6 ≥1 8 2 4 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 1Y 3 5 2Y 6 9 10 3Y 8 4Y 11 A 12 Logic symbol 74HC_HCT32 Product data sheet 11 Y 13 mna243 mna242 Fig 1. ≥1 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 5 — 4 September 2012 B Fig 3. mna241 Logic diagram (one gate) © NXP B.V. 2012. All rights reserved. 2 of 17 74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate 5. Pinning information 1A terminal 1 index area 14 VCC 5.1 Pinning 1 14 VCC 1B 2 13 4B 1B 2 13 4B 12 4A 1Y 3 12 4A 2A 4 32 11 4Y 2B 5 GND(1) 10 3B 2Y 6 1 1A 32 11 4Y 10 3B 2B 5 2Y 6 9 3A GND 7 8 3Y 9 8 4 3Y 2A 7 3 GND 1Y 3A 001aad102 Transparent top view 001aad101 (1) The die substrate is attached to this pad using conductive die attach material. It cannot be used as a supply pin or input. Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10,13 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage 6. Functional description Table 3. Function table[1] Input Output nA nB nY L L L L H H H L H H H H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 74HC_HCT32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 4 September 2012 © NXP B.V. 2012. All rights reserved. 3 of 17 74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7 V - 20 mA - 20 mA - 25 mA 50 mA IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] IO output current 0.5 V < VO < VCC + 0.5 V ICC supply current - IGND ground current 50 - mA Tstg storage temperature 65 +150 C DIP14 package - 750 mW SO14, (T)SSOP14 and DHVQFN14 packages - 500 mW total power dissipation Ptot [1] [2] [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C. For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC32 74HCT32 Unit Min Typ Max Min Typ Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 - +125 40 - +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 74HC_HCT32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 4 September 2012 © NXP B.V. 2012. All rights reserved. 4 of 17 74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min Typ VCC = 2.0 V 1.5 VCC = 4.5 V 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max 1.2 - 1.5 - 1.5 - V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V 74HC32 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V VI = VIH or VIL IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V VI = VIH or VIL IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 2.0 - 20 - 40 A CI input capacitance - 3.5 - - - - - pF 74HCT32 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A - 0 0.1 - 0.1 - 0.1 V IO = 5.2 mA - 0.15 0.25 - 0.33 - 0.4 V VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1 - 1 A VOL II input leakage current 74HC_HCT32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 4 September 2012 © NXP B.V. 2012. All rights reserved. 5 of 17 74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min 40 C to +85 C 40 C to +125 C Unit Typ Max Min Max Min Max ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 A ICC additional supply current per input pin; VI = VCC 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V - - 430 - 540 - 590 A CI input capacitance - 3.5 - - - - - pF 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for load circuit see Figure 7. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) 74HC32 tpd propagation delay nA, nB to nY; see Figure 6 [1] VCC = 2.0 V - 22 90 115 135 ns VCC = 4.5 V - 8 18 23 27 ns VCC = 5.0 V; CL = 15 pF - 6 - - - ns - 6 15 20 23 ns VCC = 2.0 V - 19 75 95 110 ns VCC = 4.5 V - 7 15 19 22 ns - 6 13 16 19 ns - 16 - - - pF VCC = 6.0 V tt transition time [2] see Figure 6 VCC = 6.0 V CPD power dissipation capacitance 74HC_HCT32 Product data sheet per package; VI = GND to VCC [3] All information provided in this document is subject to legal disclaimers. Rev. 5 — 4 September 2012 © NXP B.V. 2012. All rights reserved. 6 of 17 74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for load circuit see Figure 7. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) - 11 24 30 36 ns - 9 - - - ns 74HCT32 [1] propagation delay nA, nB to nY; see Figure 6 tpd VCC = 4.5 V VCC = 5.0 V; CL = 15 pF tt transition time VCC = 4.5 V; see Figure 6 [2] CPD power dissipation capacitance per package; VI = GND to VCC 1.5 V [3] [1] - 7 15 19 22 ns - 28 - - - pF tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 11. Waveforms 9, Q$Q%LQSXW 90 *1' W3+/ 92+ 9< Q<RXWSXW 92/ W7+/ W3/+ 90 9; W7/+ DDD Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Table 8. Input to output propagation delays Measurement points Type Input Output VM VM VX VY 74HC32 0.5VCC 0.5VCC 0.1VCC 0.9VCC 74HCT32 1.3 V 1.3 V 0.1VCC 0.9VCC 74HC_HCT32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 4 September 2012 © NXP B.V. 2012. All rights reserved. 7 of 17 74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate VI negative pulse tW 90 % VM VM 10 % GND tr tf tr tf VI 90 % positive pulse GND VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 7. Table 9. Load circuitry for measuring switching times Test data Type Input Load Test VI tr, tf CL 74HC32 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL 74HCT32 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL 74HC_HCT32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 4 September 2012 © NXP B.V. 2012. All rights reserved. 8 of 17 74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. Fig 8. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Package outline SOT27-1 (DIP14) 74HC_HCT32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 4 September 2012 © NXP B.V. 2012. All rights reserved. 9 of 17 74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 9. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT108-1 (SO14) 74HC_HCT32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 4 September 2012 © NXP B.V. 2012. All rights reserved. 10 of 17 74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC JEITA MO-150 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT337-1 (SSOP14) 74HC_HCT32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 4 September 2012 © NXP B.V. 2012. All rights reserved. 11 of 17 74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 11. Package outline SOT402-1 (TSSOP14) 74HC_HCT32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 4 September 2012 © NXP B.V. 2012. All rights reserved. 12 of 17 74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 12. Package outline SOT762-1 (DHVQFN14) 74HC_HCT32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 4 September 2012 © NXP B.V. 2012. All rights reserved. 13 of 17 74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT32 v.5 20120904 Product data sheet - 74HC_HCT32 v.4 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. 74HC_HCT32 v.4 20031212 Product specification - 74HC_HCT32 v.3 74HC_HCT32 v.3 20030829 Product specification - 74HC_HCT32_CNV v.2 74HC_HCT32_CNV v.2 19970827 Product specification - - 74HC_HCT32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 4 September 2012 © NXP B.V. 2012. All rights reserved. 14 of 17 74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 5 — 4 September 2012 © NXP B.V. 2012. All rights reserved. 15 of 17 74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74HC_HCT32 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 4 September 2012 © NXP B.V. 2012. All rights reserved. 16 of 17 74HC32; 74HCT32 NXP Semiconductors Quad 2-input OR gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 4 September 2012 Document identifier: 74HC_HCT32