INTEGRATED CIRCUITS DATA SHEET TZA3014 2.5 Gbits/s postamplifier with level detector Product specification Supersedes data of 2000 Aug 09 File under Integrated Circuits, IC19 2001 Jun 25 Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector TZA3014 FEATURES APPLICATIONS • Single 3.3 V power supply • Postamplifier for SDH/SONET transponder • Wideband operation from 50 kHz to 2.5 GHz (typical value) • SDH/SONET wavelength converter • Fully differential • Fibre channel arbitrated loop • PECL driver • On-chip DC-offset compensation without external capacitor • Signal level detectors • Swing converter CML 200 mV (p-p) to PECL 800 mV (p-p) • Interfacing with supplied positive or negative logic • Positive Emitter Coupled Logic (PECL) or Current-Mode Logic (CML) compatible data outputs adjustable from 200 to 800 mV (p-p) single-ended • 2.5 GHz clock amplification. • Power-down capability for unused output or detector GENERAL DESCRIPTION • Rise and fall times of 80 ps (typical value) The TZA3014 is a low gain postamplifier with a LOS detector and a RSSI designed for use in critical signal path control applications, such as loop-through or Wavelength Division Multiplexing (WDM). The signal path is capable of operating from 50 kHz up to 2.5 GHz. • Inverted output possible • Input level detection circuit for Received Signal Strength Indicator (RSSI) and Loss Of Signal (LOS), programmable from 0.4 to 400 mV (p-p) single-ended, with open-drain comparator output for directly interfacing positive or negative logic The TZA3014 can be delivered in HTQFP32 and HBCC32 packages and as bare die. • Reference voltage for output level and LOS adjustment • HTQFP32 and HBCC32 plastic packages with exposed pad • Mute input. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TZA3014HT HTQFP32 plastic, heatsink thin quad flat package; 32 leads; body 5 × 5 × 1.0 mm SOT547-2 TZA3014VH HBCC32 plastic, heatsink bottom chip carrier; 32 terminals; body 5 × 5 × 0.65 mm SOT560-1 TZA3014U 2001 Jun 25 − DESCRIPTION bare die; 2.22 × 2.22 × 0.28 mm 2 VERSION − Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector TZA3014 BLOCK DIAGRAM handbook, full pagewidth GNDA 32 (40) disable LOS output (31) 25 GNDB comparator LOSTH 10 (12) 5 kΩ RSSI 1× offset compensation LEVEL INV VCCA IN INQ VCCA TEST MUTE (35) 27 (34) 26 offset compensation 12 (15) level 29 (37) (30) 24 1 2 (29) 23 3 (28) 22 cross-over switch 4 15 (19) buffer amplifier BAND GAP REFERENCE TZA3014 31 (39) (27) 21 (17) 14 MGU122 The numbers in parentheses refer to the pad numbers of the bare die version. Fig.1 Block diagram. 2001 Jun 25 LOS RSSI 3 VCCB OUT OUTQ VCCB Vref Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector TZA3014 PINNING SYMBOL PIN PAD TYPE(1) DESCRIPTION VCCA 1 1 S supply voltage for input and LOS detector IN 2 2 I differential input; complimentary to pin INQ; DC bias level is set internally at approximately VCC − 0.33 V INQ 3 3 I differential input; complimentary to pin IN; DC bias level is set internally at approximately VCC − 0.33 V VCCA 4 4 S supply voltage for input and LOS detector n.c. − 5 − not connected n.c. − 6 − not connected n.c. 5 7 − not connected n.c. 6 8 I not connected n.c. 7 9 I not connected n.c. 8 10 S not connected n.c. 9 11 S not connected LOSTH 10 12 I input for setting threshold level of LOS detector; threshold level is set by connecting external resistors between pins VCCA and Vref; when forced to GNDA or not connected, the LOS detector is switched off n.c. 11 13 I not connected n.c. − 14 − not connected LEVEL 12 15 I input for setting AC level of the output circuit; output signal level is set by connecting external resistors between pins VCCA and Vref; when forced to VCCA or not connected, pins OUT and OUTQ will be switched off n.c. 13 16 I not connected Vref 14 17 O reference voltage for programming output level circuit and LOS threshold; typical value is VCC − 1.6 V; no external capacitor allowed n.c. − 18 − not connected TEST 15 19 I for test purposes only; to be left open-circuit in the application n.c. 16 20 S not connected n.c. 17 21 S not connected n.c. 18 22 O not connected n.c. 19 23 O not connected n.c. 20 24 S not connected n.c. − 25 − not connected n.c. − 26 − not connected VCCB 21 27 S supply voltage for output circuit OUTQ 22 28 O PECL or CML compatible differential output; complimentary to pin OUT OUT 23 29 O PECL or CML compatible differential output; complimentary to pin OUTQ VCCB 24 30 S supply voltage for output circuit GNDB 25 31 S ground for output circuit O not connected n.c. − 32 n.c. − 33 2001 Jun 25 O-DRN not connected 4 Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector TZA3014 SYMBOL PIN PAD TYPE(1) RSSI 26 34 O LOS 27 35 n.c. 28 36 TTL not connected INV 29 37 TTL input to invert the signal at pins OUT and OUTQ; supports positive or negative logic n.c. 30 38 TTL not connected MUTE 31 39 TTL input to mute the output signal on pins OUT (‘0’) and OUTQ (‘1’); supports positive or negative logic GNDA 32 40 S ground for input and LOS detector GNDp pad − S ground pad (exposed die pad) DESCRIPTION RSSI output O-DRN output of LOS detector; direct drive to either positive or negative supplied logic via internal 5 kΩ resistor Note 25 GNDB 26 RSSI 27 LOS 28 n.c. 29 INV 30 n.c. handbook, full pagewidth 31 MUTE 32 GNDA 1. Pin type abbreviations: O = output, I = input, S = power supply, TTL = logic input and O-DRN = open-drain output. VCCA 1 24 VCCB IN 2 INQ 3 VCCA 4 n.c. 5 20 n.c. n.c. 6 19 n.c. n.c. 7 n.c. 8 23 OUT exposed pad 22 OUTQ 21 VCCB TZA3014HT 18 n.c. GNDp n.c. 16 TEST 15 Vref 14 n.c. 13 LEVEL 12 n.c. 11 LOSTH 10 n.c. 9 17 n.c. MGU123 Fig.2 Pin configuration HTQFP32 package. 2001 Jun 25 5 Philips Semiconductors Product specification RSSI GNDB INQ LOS 2 n.c. IN INV 1 n.c. VCCA MUTE handbook, full pagewidth TZA3014 GNDA 2.5 Gbits/s postamplifier with level detector 32 31 30 29 28 27 26 25 24 VCCB 3 23 OUT VCCA 4 22 OUTQ n.c. 5 21 VCCB n.c. 6 20 n.c. n.c. 7 19 n.c. n.c. 8 18 n.c. 17 n.c. exposed pad TZA3014VH 10 11 12 13 14 15 16 LOSTH n.c. n.c. Vref TEST n.c. LEVEL 9 n.c. GNDp MGU124 Fig.3 Pin configuration HBCC32 package. 2001 Jun 25 6 Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector TZA3014 FUNCTIONAL DESCRIPTION The TZA3014 is a postamplifier with a RSSI circuit to provide output signals for RSSI and LOS (see Fig.1). The input signal can be amplified to a programmable level. An active level control circuit ensures this level. The control voltage on pin INV inverts the outputs, so avoiding a required complicated Printed Circuit Board (PCB) layout. An offset compensation circuit minimizes the effect of any voltage offset present at the input. handbook, halfpage VCCA 12 pF 420 Ω 50 Ω 50 Ω IN INQ The RSSI and LOS detector are based on a 7-stage ‘successive detection’ circuit which provides a logarithmic output. The LOS detector is followed by a comparator with a programmable threshold. The input signal level detection is implemented to check if the input signal is above the user-programmed level. The user can ensure that data will only be transmitted when the input signal-to-noise ratio is sufficient for low bit error rate system operation. A second offset compensation circuit minimizes the effect of any voltage offset present in the logarithmic amplifier. GNDA MGU125 Fig.4 RF input circuit. RF input circuit RF output level adjustment The input circuit contains internal 50 Ω resistors decoupled to VCCA via an internal common mode 12 pF capacitor (see Fig.4). The output level can be made compatible with CML or PECL by adjusting the voltage on pin LEVEL. The DC voltages on pins OUT and OUTQ relate to the DC voltage on pin LEVEL. Due to the effect of the 50 Ω load resistance at the receiving end, for a given peak-to-peak value on pins OUT and OUTQ, a different voltage is required on pin LEVEL in case the output is AC-coupled and when the output is DC-coupled (see Figs 5 and 6). The inputs IN and INQ are DC-biased at approximately VCCA − 0.33 V by an internal reference generator. The TZA3014 can be DC-coupled, but AC coupling is preferred. When DC-coupled, the drive source must operate within the allowable input range (VCCA − 1.0 V to VCCA + 0.3 V). The DC-offset voltage should stay below a few millivolts since the internal DC-offset compensation circuit has a limited correction range. When AC-coupled, do not use capacitors that cause a 3 dB cut-off point at 50 kHz (postamplifier cut-off point) or at 1 MHz (RSSI cut-off point). When pin LEVEL is not connected or connected to VCCA, the postamplifier is in power-down state (see Fig.5). DC-offset compensation loop A DC-offset compensation loop connected between the amplifier output and the buffer input maintains the toggle point at the buffer input when there is no input signal (see Fig.1). This active control circuit is integrated and does not require an external capacitor. The loop time constant determines the lower cut-off frequency of the amplifier chain, and is internally fixed at approximately 5 kHz. RF output circuit Matching the outputs of the postamplifier (see Fig.5) is not mandatory. In most applications, the receiving end of the transmission line will be properly matched, causing very few reflections. Matching the transmitting end of the transmission line to absorb reflections only, is recommended for very sensitive applications. In such cases, 100 Ω pull-up resistors should be connected to VCCB and pins OUT and OUTQ as close as possible to the IC. However, for most applications these matching resistors are not required. 2001 Jun 25 7 Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector handbook, full pagewidth VCCA 4 TZA3014 (27) 21 VCCB 100 Ω R1 50 Ω 100 Ω Vo (29) 23 OUT 50 Ω (28) 22 OUTQ Transmission lines LEVEL 12 (15) VLEVEL R2 REG VCC VLEVEL Vref 14 (17) Vo(se)(p-p) Vo (V) MGU126 VLEVEL = 0.5 × Vo(se)(p-p). R1 V LEVEL = V ref × ---------------------R1 + R2 VLEVEL = VCC for power-down mode. The numbers in parentheses refer to the pad numbers of the bare die version. a. DC-coupled. handbook, full pagewidth VCCA 4 (27) 21 VCCB 100 Ω R1 50 Ω 100 Ω Vo (29) 23 OUT 50 Ω (28) 22 OUTQ Transmission lines LEVEL 12 (15) VLEVEL VCC R2 REG Vref 14 (17) VLEVEL Vo(se)(p-p) Vo (V) VLEVEL = 1.5 × Vo(se)(p-p). R1 V LEVEL = V ref × ---------------------R1 + R2 VLEVEL = VCC for power-down mode. The numbers in parentheses refer to the pad numbers of the bare die version. b. AC-coupled. Fig.5 RF output configurations. 2001 Jun 25 8 MGU127 Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector TZA3014 MGU128 handbook, full pagewidth 1000 Vo(se)(p-p) (mV) 800 DC-coupled AC-coupled 600 400 200 0 0 20 40 100 80 VLEVEL (% of Vref) 60 Fig.6 Output signal as a function of VLEVEL. TTL logic inputs MUTE and INV Table 1 It should be noted that switch control voltages in positive logic are inverted in case a negative supply voltage is used (see Fig.7). OUT and OUTQ as a function of input MUTE MUTE OUT OUTQ 0 IN INQ 1 ‘0’ ‘1’ Output signal as a function of inputs MUTE and INV Table 2 The default logic level for inputs MUTE and INV is 0 in case these pins are not connected. See Tables 1 and 2. 2001 Jun 25 9 OUT and OUTQ as a function of input INV INV OUT OUTQ 0 IN INQ 1 INQ IN Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector logic level handbook, full pagewidth TZA3014 MGS560 2.0 V 2.0 V 1 (1) T TL 0.8 V 0.8 V 0 1.4 V 1.4 V VCC GND −1 +1 0 +2 +3 +5 +4 +6 VI (V) a. Positive supply voltage (VCC) and positive input voltage (VCC). handbook, full pagewidth logic level MGS559 2.0 V 2.0 V 1 (1) T TL 0.8 V 0.8 V 0 1.4 V 1.4 V VEE −4 VCC GND −3 −2 −1 +1 0 +2 +3 VI (V) b. Negative supply voltage (VEE) and positive input voltage (VCC). handbook, full pagewidth logic level MGS558 2.0 V 2.0 V 1 (1) T TL 0.8 V 0.8 V 0 1.4 V 1.4 V VEE −4 GND −3 −2 −1 0 +1 +2 +3 VI (V) c. Negative supply voltage (VEE) and negative input voltage (VEE). (1) Level not defined. Fig.7 Logic levels on pins MUTE and INV as a function of the supply voltages. 2001 Jun 25 10 Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector TZA3014 RSSI and LOS detection The TZA3014 monitors the level of the input AC signal. This function can prevent the output circuit from reacting to noise in case there is no valid input signal, and can ensure that only data is transmitted when there is sufficient input signal for low bit error rate system operation. handbook, halfpage 103 Vi(se)(p-p) (mV) 102 The RSSI uses seven limiting amplifiers in a ‘successive detection’ topology to closely approximate a logarithmic response over a total range of 70 dB. The AC signal is full-wave rectified by a detector at each amplifier stage. Each detector output has a current driver followed by a low-pass filter providing the first stage in the recovery of the average value of the demodulated input signal. The total current from each detector output is converted to a voltage by an internal load resistor and then buffered. When the RSSI output is used, input pin LOSTH is not to be connected to GND (standby mode). The RSSI output follows the internal 3 dB hysteresis of the LOS comparator. The LOS comparator detects when the input signal level rises above a programmable fixed threshold. Then pin LOS gets a LOW-level. The threshold level is determined by the voltage on pin LOSTH and by the level of the input AC signal (see Fig.8). A filter with a nominal time constant of 1 µs prevents noise spikes from triggering the level detector. (1) (2) LOS HIGH-level 1 10−1 10 VCC −0.16 (3) 20 30 VCC −0.48 40 50 60 70 VLOSTH (% of Vref) VCC −0.8 VCC −1.12 VRSSI (V) (1) PRBS pattern input signal with a frequency <1 GHz. (2) Linearity error typically 0.5 dB. (3) ϕ = 1/12.5 dB/mV. Fig.8 Loss of signal assert level. Its response is independent of the input signal polarity due to the circuit design and to the demodulating action of the detector which transforms the alternating input voltage to a rectified and filtered quasi DC output signal. The logarithmic voltage slope of the TZA3014 is ϕ = 1/12.5 dB/mV and mostly is independent of temperature and supply voltage due to four feedback loops in the reference circuit. The LOS detector output voltage is derived from Vref. Example: a 200 mV (p-p) single-ended 1.2 GB/s PRBS input signal will have a VRSSI voltage of VCC − 1.013 V. If the offset voltage of the first stage increases above a certain level, the high DC gain of the amplifier circuit will cause successive stages to limit prematurely. This is prevented by the LOS detector offset control loop which extends the lower end of the amplifier’s dynamic range. The offset is automatically and continuously compensated by a feedback path from the last stage. An offset at the output of the logarithmic converter is equivalent to a change of amplitude at the input. The sensitivity of the LOS detector is affected by the RMS value of the input signal which, in its turn, depends on the frequency. VLOSTH can be calculated using the following formula: Using DC-coupling, with signal absence, and VIN not equal to VINQ (mute), the LOS detector detects full signal. Only very small signals with an average value equal to zero, can result into a zero output. VLOSTH = VRSSI = (1) where SRSSI in [mV/dB]; VLOSTH, VRSSI and Vi(p-p) in [V]. 2001 Jun 25 LOS LOW-level 10 The LOS comparator has an internal 3 dB hysteresis and drives an open-drain circuit with a 5 kΩ internal resistor allowing it to directly interface positive or negative logic circuits (see Fig.9). V i(p-p) V CC + 0.458 – S RSSI × 20 log -------------------- 26E – 8 MGU129 11 Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector VCC handbook, halfpage TZA3014 VCC handbook, halfpage GND 56 kΩ TZA3014 5.6 kΩ TZA3014 LOS LOS 5 kΩ 5 kΩ GNDA GNDA ILOS ILOS GND MGU132 MGU131 a. Positive supply and positive logic. VEE b. Negative supply and positive logic. GND handbook, halfpage 56 kΩ TZA3014 LOS 5 kΩ GNDA ILOS VEE MGU130 VCC − VEE < 7 V. c. Negative supply and negative logic. Fig.9 Loss of signal output pin LOS. Supply current For the supply current ICCB, see Fig.10. I CCB Using a positive supply voltage (mA) (1) 60 Although the TZA3014 has been designed to use a single +3.3 V supply voltage (see Fig.11), some care should be taken with respect to RF transmission lines. The on-chip signals refer to the various VCC pins. The external transmission lines will most likely be referred to the pins GNDA and GNDB, being the system ground. 50 The RF signals will change from one reference plane to another when interfacing the RF inputs and outputs. A positive supply application is very vulnerable to interference with respect to this point. For a successful +3.3 V application, special care should be taken when designing the PCB layout in order to reduce the influence of interference and to keep the positive supply voltage as clean as possible. 17 40 30 20 10 5 0 0 0.2 0.8 0.5 Vo(se)(p-p) (V) 1 MGU133 (1) Tamb = 25 °C. Fig.10 Supply current as a function of the output voltage. 2001 Jun 25 12 Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector TZA3014 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER MAX. UNIT −0.5 +5.5 pins IN, INQ, LOSTH, LEVEL, Vref, TEST, OUTQ, OUT, GNDp, VCCA and VCCB −0.5 VCC + 0.5 V pins LOS, INV and MUTE −0.5 +7 pins IN and INQ −20 +20 mA pins LOSTH and LEVEL 0 14 µA pins Vref, TEST and LOS −1 +1 mA pins OUT and OUTQ −30 +30 mA VCC supply voltage Vn DC voltage In MIN. V V DC current pins INV and MUTE 0 20 µA Ptot total power dissipation − 0.6 W Tstg storage temperature −65 +150 °C Tj junction temperature − 150 °C Tamb ambient temperature −40 +85 °C THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS VALUE UNIT Rth(j-s) thermal resistance from junction to solder point (exposed die pad) note 1 15 K/W Rth(j-a) thermal resistance from junction to ambient 1s2p multi-layer test board; notes 1 and 2 33 K/W Rth(s-a) thermal resistance from solder point to ambient (exposed die pad) 1s2p multi-layer test board; notes 1 and 2 18 K/W Rth(s-a)(req) required thermal resistance from solder point to ambient LOS detector switched on Vo = 200 mV (p-p) single-ended 130 K/W Vo = 800 mV (p-p) single-ended 75 K/W Notes 1. JEDEC standard. 2. HTQFP32 and HBCC32 packages. 2001 Jun 25 13 Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector TZA3014 CHARACTERISTICS Typical values at Tamb = 25 °C and VCC = 3.3 V; minimum and maximum values are valid over the entire ambient temperature range and supply voltage range; all voltages referenced to ground; note 1; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply (pins VCCA and VCCB) VCC supply voltage ICCA supply current A ICCB supply current B Ptot TC total power dissipation temperature coefficient 3.13 3.3 3.47 V LOS detector power-down 14 24 34 mA LOS detector switched on 24 40 56 mA amplifier power-down 2 6 10 mA Vo = 200 mV (p-p) single-ended 11 17 24 mA Vo = 800 mV (p-p) single-ended 43 60 77 mA power-down 60 100 240 mW Vo = 200 mV (p-p) single-ended 120 190 270 mW Vo = 800 mV (p-p) single-ended 250 330 450 mW LOS detector switched on; ICCA −80 −50 −30 µA/K Vo = 800 mV (p-p) single-ended; ICCB −50 −30 −15 µA/K Tj junction temperature −40 − +125 °C Tamb ambient temperature −40 +25 +85 °C VCC − 0.4 VCC − 0.33 VCC − 0.28 V note 2 VCC − 1.0 − VCC + 0.3 V RF inputs in general (PECL or CML input pins IN and INQ) VI(bias) DC input bias voltage VI DC and AC input window voltage Ri input resistance single-ended 35 50 70 Ω Ci input capacitance single-ended; note 2 0.6 0.8 1.2 pF Cross-over switch and postamplifier PECL OR CML INPUT PINS IN AND INQ Vi(p-p) input voltage swing (peak-to-peak value) single-ended; notes 2 and 3 50 − 500 mV αOS(red) input offset reduction Vo = 200 mV (p-p) single-ended; note 4 3.8 9 13.5 dB Vo = 800 mV (p-p) single-ended; note 4 6 14 22 dB single-ended −10 − +10 mV Vn(i)(eq)(rms) equivalent input noise voltage (RMS value) Vo = 800 mV (p-p) single-ended; note 2 − 75 170 µV Fn note 2 − 5 12 dB Vio(cor) 2001 Jun 25 input offset voltage correction range (peak-to-peak value) noise factor 14 Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector SYMBOL PARAMETER TZA3014 CONDITIONS MIN. TYP. MAX. UNIT BUFFER AND AMPLIFIER Gv small signal voltage gain Vo = 200 mV (p-p) single-ended; note 5 9 15 20 dB Vo = 800 mV (p-p) single-ended; note 5 21 29 34 dB fD signal path data rate notes 6 and 7 − 2.5 − Gbits/s f−3dB(l) low −3 dB cut-off frequency DC compensation note 2 2 5 10 kHz f−3dB(h) high −3 dB cut-off frequency − 2.0 − GHz tPD propagation delay note 2 150 200 250 ps ∆tPD propagation delay difference at the same signal levels; note 2 − 0 5 ps J total jitter 20 bits of the 28.5 kbits pattern; notes 2 and 8 − 8 − ps αct crosstalk note 9 − 110 − dB 200 − 800 mV −1 0 +1 mV/K PECL OR CML OUTPUTS (PINS OUT AND OUTQ) 50 Ω load Vo(se)(p-p) single-ended output voltage (peak-to-peak value) TCVo temperature coefficient output voltage tr rise time 20% to 80%; notes 6 and 8 − 80 − ps tf fall time 80% to 20%; notes 6 and 8 − 80 − ps Ro output resistance single-ended 70 100 130 Ω Co output capacitance single-ended; note 2 0.6 0.8 1.2 pF VCC − Vref − VCC V referenced to VCC 200 350 600 kΩ LEVEL CONTROL INPUT (PIN LEVEL) Vi input voltage Ri input resistance SWITCH CIRCUIT ta assert time multiplexer and inverter − 100 − ns td de-assert time multiplexer and inverter − 80 − ns positive logic; note 10 −0.3 − +0.8 V TTL INPUT PINS MUTE AND INV VIL LOW-level input voltage VIH HIGH-level input voltage positive logic; note 10 2 − VCC + 0.8 V Ri input resistance referenced to GNDA 100 180 400 kΩ Ii input current −40 − +40 µA 2001 Jun 25 15 Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector SYMBOL PARAMETER TZA3014 CONDITIONS MIN. TYP. MAX. UNIT RSSI and LOS detector PECL OR CML INPUT PINS IN AND INQ single-ended 0.4 − Vi(p-p) input voltage swing (peak-to-peak value) 400 mV αOS(red) input offset reduction notes 2 and 4 25 40 50 dB Vio(cor) on-chip DC-offset compensation correction range peak-to-peak value; single-ended −5 − +5 mV 0.5 1 2 MHz 1.5 2 2.5 GHz RSSI CIRCUIT f−3dB(l) low −3 dB cut-off frequency f−3dB(h) high −3 dB cut-off frequency DR dynamic range SRSSI RSSI sensitivity TCsens temperature coefficient sensitivity LE linearity error note 11 57 60 63 dB 50 MHz, square; note 11 10 12.5 15 mV/dB 620 MHz, square; note 11 10 12 14 mV/dB 1.2 GHz, square; note 11 9 11 13.5 mV/dB 100 MB/s PRBS (231 − 1); note 11 9 12.5 15 mV/dB 1.2 GB/s PRBS (231 − 1); note 11 10 12 14.5 mV/dB 2.4 GB/s PRBS (231 − 1); note 11 10 12 14 mV/dB −2 0 +2 µV/dBK see Fig.8; note 2 − 0.5 1 dB input signal waveform dependent 2.0 3.0 4.0 dB LOS DETECTOR hysLOS LOS hysteresis ta assert time note 2 − − 5 µs td de-assert time note 2 − − 5 µs 0 − VCC V 150 350 600 kΩ − − 1 mA 3.5 5 6.5 kΩ INPUT PIN LOSTH Vi input voltage Ri input resistance referenced to GNDA OUTPUT PIN LOS Io(sink) output sink current Ro output resistance 2001 Jun 25 internal output series resistance 16 Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector SYMBOL PARAMETER TZA3014 CONDITIONS MIN. TYP. MAX. UNIT OUTPUT PIN RSSI Vo output voltage VCC − 1.2 − VCC V Io output current −1 − +1 mA Band gap reference circuit OUTPUT PIN Vref Vref reference voltage VCC − 1.85 VCC − 1.6 VCC − 1.45 V Cext allowed external capacitance − − 10 pF Io(sink) output sink current − − 500 µA Notes 1. It is assumed that both CML inputs carry a complementary signal with the specified peak-to-peak value (true differential excitation). 2. Guaranteed by design. 3. Minimum signal with limiting output. G AC 4. αOS(red) = ----------G DC Vo 5. GV = -----Vi 6. Based on −3 dB cut-off frequency and rise/fall time. 7. Low limit can go as low as DC if the input signal overrides the input offset voltage correction range. 8. Vi = 100 mV (p-p) single-ended, Vo = 800 mV (p-p) single-ended. 9. Crosstalk of IC only. 10. When using a negative supply voltage, positive or negative logic can be used. The values will be different, see Fig.7. 11. Sensitivity depends on the waveform and is therefore a function of −3 dB cut-off frequency; see Section “RSSI and LOS detection”, Equation (1). 2001 Jun 25 17 Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector To minimize low frequency switching noise in the vicinity of the TZA3014, the power supply line should be filtered once using a beaded capacitor circuit having a low cut-off frequency. APPLICATION INFORMATION RF input and output connections Striplines, or microstrips, with an odd mode characteristic impedance of Zo = 50 Ω have to be used for the differential RF connections on the PCB. This applies to both signal inputs and signal outputs. Each pair of lines should have the same length. The exposed die pad GNDp connection on the PCB must be a large area of copper to aid the transfer of heat from the IC to the PCB (see Figs 11 and 12). Grounding and power supply decoupling The PCB ground connection has to be a large area of copper connected to a common ground plane with an inductance as low as possible. 2001 Jun 25 TZA3014 18 Philips Semiconductors Product specification handbook, full pagewidth TZA3014 0 1 2 3 4 VCC VCC Boundary of 100 mm2 area 5 mm To central GND decoupling 0603 0603 To central GND decoupling 26 GNDB 25 RSSI 27 28 29 LOS INV 30 GNDA 32 MUTE 31 0603 0603 1 24 VCCB IN 2 23 OUT INQ 3 22 VCCA 21 4 VCCA OUTQ VCCB 20 5 19 6 18 7 17 8 0603 0603 0603 0603 16 15 TEST 14 Vref 13 12 LEVEL 0603 11 10 LOSTH 9 0603 GND signal/GNDp 2.5 Gbits/s postamplifier with level detector HTQFP 0603 cross-section MGU134 In order to enable heat flow out of the package, the following measures have to be taken: (1) Solder the 3 × 3 mm2 exposed die pad to a plane with maximum size. (2) Add a plane with minimum 100 mm2 in an inner layer, surrounded by ground layers. (3) Use maximum amount of vias to connect two planes. (4) Use minimum of openings in heat transport area between hot plane and ground planes. Fig.11 PCB layout for HTQFP package with positive supply voltage. 2001 Jun 25 19 Philips Semiconductors Product specification handbook, full pagewidth TZA3014 0 1 2 3 4 VCC VCC Boundary of 100 mm2 area 5 mm To central GND decoupling 0603 0603 To central GND decoupling RSSI GNDB 27 26 25 28 29 LOS INV 30 32 MUTE 31 GNDA 0603 0603 1 24 VCCB IN 2 23 OUT INQ 3 22 VCCA 21 4 VCCA OUTQ VCCB 20 5 19 6 18 7 17 8 0603 0603 0603 0603 16 15 TEST 14 Vref 13 12 LEVEL 0603 11 10 LOSTH 9 0603 GND signal/GNDp 2.5 Gbits/s postamplifier with level detector HTQFP 0603 cross-section MGU136 In order to enable heat flow out of the package, the following measures have to be taken: (1) Solder the 3 × 3 mm2 exposed die pad to a plane with maximum size. (2) Add a plane with minimum 100 mm2 in an inner layer, surrounded by ground layers. (3) Use maximum amount of vias to connect two planes. (4) Use minimum of openings in heat transport area between hot plane and ground planes. Fig.12 PCB layout for HTQFP package with negative supply voltage. 2001 Jun 25 20 Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector TZA3014 BONDING PAD INFORMATION COORDINATES(1) SYMBOL COORDINATES(1) SYMBOL PAD x PAD y n.c. 25 +928 −81 VCCA 1 −928 +710 n.c. 26 +928 +81 IN 2 −928 +553 VCCB 27 +928 +239 INQ 3 −928 +396 OUTQ 28 +928 +396 VCCA 4 −928 +239 OUT 29 +928 +553 n.c. 5 −928 +81 VCCB 30 +928 +710 n.c. 6 −928 −81 GNDB 31 +707 +928 n.c. 7 −928 −239 n.c. 32 +550 +928 n.c. 8 −928 −396 n.c. 33 +393 +928 n.c. 9 −928 −553 RSSI 34 +236 +928 n.c. 10 −928 −710 LOS 35 +79 +928 n.c. 11 −707 −928 n.c. 36 −79 +928 LOSTH 12 −550 −928 INV 37 −236 +928 n.c. 13 −393 −928 n.c. 38 −393 +928 n.c. 14 −236 −928 MUTE 39 −550 +928 GNDA 40 −707 +928 x y LEVEL 15 −79 −928 n.c. 16 +79 −928 Vref 17 +236 −928 n.c. 18 +393 −928 TEST 19 +550 −928 n.c. 20 +707 −928 n.c. 21 +928 −710 n.c. 22 +928 −553 n.c. 23 +928 −396 n.c. 24 +928 −239 2001 Jun 25 Note 1. All x and y coordinates represent the position of the centre of the pad in µm with respect to the centre of the die (see Fig.13). 21 Philips Semiconductors Product specification GNDB TZA3014 n.c. n.c. RSSI LOS n.c. INV n.c. GNDA handbook, full pagewidth MUTE 2.5 Gbits/s postamplifier with level detector 40 39 38 37 36 35 34 33 32 31 VCCA 1 30 VCCB IN 2 29 OUT INQ 3 28 OUTQ VCCA 4 27 VCCB n.c. 5 26 n.c. n.c. 6 25 n.c. n.c. 7 24 n.c. n.c. 8 23 n.c. n.c. 9 22 n.c. n.c. 10 21 n.c. x 0 0 y TZA3014U n.c. TEST n.c. Vref n.c. LEVEL n.c. n.c. LOSTH n.c. 11 12 13 14 15 16 17 18 19 20 MGU135 Fig.13 Bonding pad locations TZA3014U. 2001 Jun 25 22 Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector TZA3014 PACKAGE OUTLINES HTQFP32: plastic, heatsink thin quad flat package; 32 leads; body 5 x 5 x 1.0 mm SOT547-2 c y heathsink side X Dh 24 17 25 A 16 ZE e E HE Eh (A 3) A A2 A1 w M θ bp Lp pin 1 index 32 L 9 detail X 1 8 ZD w M bp v M A e D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 A2 A3 bp c D(1) Dh E(1) Eh e HD HE L Lp v w y 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 5.1 4.9 3.1 2.7 5.1 4.9 3.1 2.7 0.5 7.1 6.9 7.1 6.9 1.0 0.75 0.45 0.2 0.08 0.08 ZD(1) ZE(1) θ 0.89 0.61 7° 0° 0.89 0.61 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ SOT547-2 2001 Jun 25 EUROPEAN PROJECTION ISSUE DATE 99-06-15 23 Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector TZA3014 HBCC32: plastic, heatsink bottom chip carrier; 32 terminals; body 5 x 5 x 0.65 mm SOT560-1 x B D b1 w M w M ball A1 index area b b3 E w M b2 w M detail X x C A e1 B e y v A C E1 e4 e2 1 32 A1 X D1 A2 e3 A 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 b b1 b2 b3 D D1 E E1 e e1 e2 e3 e4 v w x y mm 0.80 0.10 0.05 0.70 0.60 0.35 0.20 0.50 0.30 0.50 0.35 0.50 0.35 5.1 4.9 3.2 3.0 5.1 4.9 3.2 3.0 0.5 4.2 4.2 4.15 4.15 0.2 0.15 0.15 0.05 OUTLINE VERSION SOT560-1 2001 Jun 25 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 99-09-10 00-02-01 MO-217 24 Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector SOLDERING TZA3014 If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C for small/thin packages. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. 2001 Jun 25 25 Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector TZA3014 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, HBGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(1) suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DATA SHEET STATUS DATA SHEET STATUS(1) PRODUCT STATUS(2) DEFINITIONS Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 2001 Jun 25 26 Philips Semiconductors Product specification 2.5 Gbits/s postamplifier with level detector Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Bare die All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. 2001 Jun 25 TZA3014 27 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 403510/200/02/pp28 Date of release: 2001 Jun 25 Document order number: 9397 750 08203