74AUP1G14 Low-power Schmitt trigger inverter Rev. 6 — 28 June 2012 Product data sheet 1. General description The 74AUP1G14 provides a single inverting Schmitt trigger which accepts standard input signals. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT− is defined as the input hysteresis voltage VH. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Applications Wave and pulse shaper Astable multivibrator Monostable multivibrator 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G14GW −40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 74AUP1G14GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm 74AUP1G14GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm 74AUP1G14GN −40 °C to +125 °C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9 × 1.0 × 0.35 mm SOT1115 74AUP1G14GS −40 °C to +125 °C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0 × 1.0 × 0.35 mm SOT1202 74AUP1G14GX −40 °C to +125 °C X2SON5 X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8 × 0.8 × 0.35 mm SOT1226 5. Marking Table 2. Marking Marking code[1] Type number 74AUP1G14GW pF 74AUP1G14GM pF 74AUP1G14GF pF 74AUP1G14GN pF 74AUP1G14GS pF 74AUP1G14GX pF [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 6. Functional diagram 2 A Y 4 2 mna023 Fig 1. Logic symbol 74AUP1G14 Product data sheet 4 A Y mna025 mna024 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 Fig 3. Logic diagram © NXP B.V. 2012. All rights reserved. 2 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter 7. Pinning information 7.1 Pinning 74AUP1G14 74AUP1G14 n.c. 1 A 2 GND 3 5 n.c. 1 6 VCC A 2 5 n.c. GND 3 4 Y VCC 4 Y 001aaf122 Transparent top view 001aaf121 Fig 4. Pin configuration SOT353-1 Fig 5. Pin configuration SOT886 74AUP1G14 74AUP1G14 n.c. n.c. 1 6 VCC A 2 5 n.c. GND 3 4 Y 5 VCC 4 Y 3 GND A 001aaf123 2 aaa-003002 Transparent top view Transparent top view Fig 6. 1 Pin configuration SOT891, SOT1115 and SOT1202 Fig 7. Pin configuration SOT1226 (X2SON5) 7.2 Pin description Table 3. Symbol Pin description Pin TSSOP5 and X2SON5 Description XSON6 n.c. 1 1 not connected A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. - 5 not connected VCC 5 6 supply voltage 74AUP1G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 3 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter 8. Functional description Table 4. Function table[1] Input Output A Y L H H L [1] H = HIGH voltage level; L = LOW voltage level. 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions VI < 0 V [1] VO < 0 V [1] Min Max Unit −0.5 +4.6 V −50 - mA −0.5 +4.6 V −50 - mA −0.5 +4.6 V - ±20 mA VO output voltage Active mode and Power-down mode IO output current VO = 0 V to VCC ICC supply current - +50 mA IGND ground current −50 - mA Tstg storage temperature −65 +150 °C - 250 mW total power dissipation Ptot [1] [2] Tamb = −40 °C to +125 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP5 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 and X2SON5 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 10. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC Min Max Unit supply voltage 0.8 3.6 V VI input voltage 0 3.6 V VO output voltage Active mode 0 VCC V Power-down mode; VCC = 0 V 0 3.6 V −40 +125 °C Tamb Conditions ambient temperature 74AUP1G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 4 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter 11. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit IO = −20 μA; VCC = 0.8 V to 3.6 V VCC − 0.1 - - V IO = −1.1 mA; VCC = 1.1 V 0.75 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 1.11 - - V Tamb = 25 °C VOH VOL HIGH-level output voltage LOW-level output voltage VI = VT+ or VT− IO = −1.9 mA; VCC = 1.65 V 1.32 - - V IO = −2.3 mA; VCC = 2.3 V 2.05 - - V IO = −3.1 mA; VCC = 2.3 V 1.9 - - V IO = −2.7 mA; VCC = 3.0 V 2.72 - - V IO = −4.0 mA; VCC = 3.0 V 2.6 - - V IO = 20 μA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.31 V IO = 1.9 mA; VCC = 1.65 V - - 0.31 V IO = 2.3 mA; VCC = 2.3 V - - 0.31 V IO = 3.1 mA; VCC = 2.3 V - - 0.44 V IO = 2.7 mA; VCC = 3.0 V - - 0.31 V IO = 4.0 mA; VCC = 3.0 V - - 0.44 V VI = VT+ or VT− II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.1 μA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.2 μA ΔIOFF additional power-off leakage VI or VO = 0 V to 3.6 V; current VCC = 0 V to 0.2 V - - ±0.2 μA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.5 μA ΔICC additional supply current VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V - - 40 μA CI input capacitance VI = GND or VCC; VCC = 0 V to 3.6 V - 1.1 - pF CO output capacitance VO = GND; VCC = 0 V - 1.7 - pF IO = −20 μA; VCC = 0.8 V to 3.6 V VCC − 0.1 - - V IO = −1.1 mA; VCC = 1.1 V 0.7 × VCC - - V Tamb = −40 °C to +85 °C VOH HIGH-level output voltage 74AUP1G14 Product data sheet VI = VT+ or VT− IO = −1.7 mA; VCC = 1.4 V 1.03 - - V IO = −1.9 mA; VCC = 1.65 V 1.30 - - V IO = −2.3 mA; VCC = 2.3 V 1.97 - - V IO = −3.1 mA; VCC = 2.3 V 1.85 - - V IO = −2.7 mA; VCC = 3.0 V 2.67 - - V IO = −4.0 mA; VCC = 3.0 V 2.55 - - V All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 5 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VOL VI = VT+ or VT− LOW-level output voltage Min Typ Max Unit IO = 20 μA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.37 V IO = 1.9 mA; VCC = 1.65 V - - 0.35 V IO = 2.3 mA; VCC = 2.3 V - - 0.33 V IO = 3.1 mA; VCC = 2.3 V - - 0.45 V IO = 2.7 mA; VCC = 3.0 V - - 0.33 V IO = 4.0 mA; VCC = 3.0 V - - 0.45 V - ±0.5 μA II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - VI or VO = 0 V to 3.6 V; VCC = 0 V IOFF power-off leakage current - - ±0.5 μA ΔIOFF additional power-off leakage VI or VO = 0 V to 3.6 V; current VCC = 0 V to 0.2 V - - ±0.6 μA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.9 μA ΔICC additional supply current VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V - - 50 μA Tamb = −40 °C to +125 °C VOH VOL HIGH-level output voltage LOW-level output voltage VI = VT+ or VT− IO = −20 μA; VCC = 0.8 V to 3.6 V VCC − 0.11 - - V IO = −1.1 mA; VCC = 1.1 V 0.6 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 0.93 - - V IO = −1.9 mA; VCC = 1.65 V 1.17 - - V IO = −2.3 mA; VCC = 2.3 V 1.77 - - V IO = −3.1 mA; VCC = 2.3 V 1.67 - - V IO = −2.7 mA; VCC = 3.0 V 2.40 - - V IO = −4.0 mA; VCC = 3.0 V 2.30 - - V IO = 20 μA; VCC = 0.8 V to 3.6 V - - 0.11 V IO = 1.1 mA; VCC = 1.1 V - - 0.33 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.41 V IO = 1.9 mA; VCC = 1.65 V - - 0.39 V IO = 2.3 mA; VCC = 2.3 V - - 0.36 V IO = 3.1 mA; VCC = 2.3 V - - 0.50 V IO = 2.7 mA; VCC = 3.0 V - - 0.36 V IO = 4.0 mA; VCC = 3.0 V - - 0.50 V VI = VT+ or VT− II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.75 μA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.75 μA 74AUP1G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 6 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit ΔIOFF additional power-off leakage VI or VO = 0 V to 3.6 V; current VCC = 0 V to 0.2 V - - ±0.75 μA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 1.4 μA ΔICC additional supply current VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V - - 75 μA 12. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter 25 °C Conditions Min −40 °C to +125 °C Typ[1] Max Min Max (85 °C) Max (125 °C) Unit CL = 5 pF tpd [2] propagation delay A to Y; see Figure 8 VCC = 0.8 V - 19.9 - - - - ns VCC = 1.1 V to 1.3 V 2.7 5.9 11.0 2.4 11.1 11.2 ns VCC = 1.4 V to 1.6 V 2.6 4.3 6.6 2.4 7.1 7.4 ns VCC = 1.65 V to 1.95 V 2.1 3.7 5.4 2.0 6.0 6.2 ns VCC = 2.3 V to 2.7 V 2.0 3.0 4.1 1.7 4.5 4.7 ns VCC = 3.0 V to 3.6 V 1.9 2.8 3.6 1.5 3.9 4.0 ns - 23.4 - - - - ns VCC = 1.1 V to 1.3 V 2.9 6.8 12.7 2.8 12.8 12.9 ns VCC = 1.4 V to 1.6 V 2.8 5.0 7.7 2.6 8.2 8.6 ns VCC = 1.65 V to 1.95 V 2.7 4.2 6.2 2.5 6.7 7.1 ns VCC = 2.3 V to 2.7 V 2.3 3.6 4.8 2.1 5.2 5.5 ns VCC = 3.0 V to 3.6 V 2.1 3.3 4.3 2.0 4.5 4.7 ns - 26.9 - - - - ns VCC = 1.1 V to 1.3 V 3.3 7.6 14.3 3.0 14.5 14.7 ns VCC = 1.4 V to 1.6 V 3.3 5.5 8.6 2.9 9.4 9.8 ns VCC = 1.65 V to 1.95 V 2.8 4.7 7.0 2.8 7.7 8.1 ns VCC = 2.3 V to 2.7 V 2.7 4.0 5.5 2.4 5.9 6.2 ns VCC = 3.0 V to 3.6 V 2.6 3.8 4.8 2.2 5.2 5.4 ns CL = 10 pF tpd [2] propagation delay A to Y; see Figure 8 VCC = 0.8 V CL = 15 pF tpd [2] propagation delay A to Y; see Figure 8 VCC = 0.8 V CL = 30 pF 74AUP1G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 7 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter tpd 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) - 37.3 - - - - ns VCC = 1.1 V to 1.3 V 4.0 9.8 18.7 3.9 19.6 20.0 ns VCC = 1.4 V to 1.6 V 3.7 7.1 11.2 3.8 12.3 12.9 ns VCC = 1.65 V to 1.95 V 3.6 6.0 9.1 3.6 10.0 10.6 ns VCC = 2.3 V to 2.7 V 3.5 5.2 6.9 3.2 7.5 7.9 ns VCC = 3.0 V to 3.6 V 3.3 4.8 6.1 3.1 7.1 7.4 ns VCC = 0.8 V - 2.6 - - - - pF VCC = 1.1 V to 1.3 V - 2.7 - - - - pF VCC = 1.4 V to 1.6 V - 2.9 - - - - pF [2] propagation delay A to Y; see Figure 8 VCC = 0.8 V CL = 5 pF, 10 pF, 15 pF and 30 pF power dissipation capacitance CPD [1] [3] fi = 1 MHz; VI = GND to VCC VCC = 1.65 V to 1.95 V - 3.1 - - - - pF VCC = 2.3 V to 2.7 V - 3.7 - - - - pF VCC = 3.0 V to 3.6 V - 4.3 - - - - pF All typical values are measured at nominal VCC. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 13. Waveforms VI VM A input GND t PHL t PLH VOH VM Y output VOL mna640 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. The data input (A) to output (Y) propagation delays 74AUP1G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 8 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter Table 9. Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 0.8 V to 3.6 V 0.5 × VCC 0.5 × VCC VCC ≤ 3.0 ns VCC VEXT 5 kΩ G VI VO DUT CL RT RL 001aac521 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Table 10. Load circuitry for switching times Test data Supply voltage Load VEXT VCC CL 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ [1] RL [1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ open GND 2 × VCC For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ. 14. Transfer characteristics Table 11. Transfer characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter Conditions Min Typ Max Unit positive-going threshold voltage see Figure 10 and Figure 11 VCC = 0.8 V 0.30 - 0.60 V VCC = 1.1 V 0.53 - 0.90 V VCC = 1.4 V 0.74 - 1.11 V VCC = 1.65 V 0.91 - 1.29 V VCC = 2.3 V 1.37 - 1.77 V VCC = 3.0 V 1.88 - 2.29 V Tamb = 25 °C VT+ 74AUP1G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 9 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter Table 11. Transfer characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter Conditions VT− negative-going threshold voltage see Figure 10 and Figure 11 VH hysteresis voltage Min Typ Max Unit VCC = 0.8 V 0.10 - 0.60 V VCC = 1.1 V 0.26 - 0.65 V VCC = 1.4 V 0.39 - 0.75 V VCC = 1.65 V 0.47 - 0.84 V VCC = 2.3 V 0.69 - 1.04 V VCC = 3.0 V 0.88 - 1.24 V VCC = 0.8 V 0.07 - 0.50 V VCC = 1.1 V 0.08 - 0.46 V VCC = 1.4 V 0.18 - 0.56 V VCC = 1.65 V 0.27 - 0.66 V VCC = 2.3 V 0.53 - 0.92 V VCC = 3.0 V 0.79 - 1.31 V VCC = 0.8 V 0.30 - 0.60 V VCC = 1.1 V 0.53 - 0.90 V VCC = 1.4 V 0.74 - 1.11 V VCC = 1.65 V 0.91 - 1.29 V VCC = 2.3 V 1.37 - 1.77 V VCC = 3.0 V 1.88 - 2.29 V VCC = 0.8 V 0.10 - 0.60 V VCC = 1.1 V 0.26 - 0.65 V VCC = 1.4 V 0.39 - 0.75 V VCC = 1.65 V 0.47 - 0.84 V VCC = 2.3 V 0.69 - 1.04 V VCC = 3.0 V 0.88 - 1.24 V VCC = 0.8 V 0.07 - 0.50 V VCC = 1.1 V 0.08 - 0.46 V VCC = 1.4 V 0.18 - 0.56 V VCC = 1.65 V 0.27 - 0.66 V VCC = 2.3 V 0.53 - 0.92 V VCC = 3.0 V 0.79 - 1.31 V see Figure 10, Figure 11, Figure 12 and Figure 13 Tamb = −40 °C to +85 °C VT+ VT− VH positive-going threshold voltage negative-going threshold voltage hysteresis voltage 74AUP1G14 Product data sheet see Figure 10 and Figure 11 see Figure 10 and Figure 11 see Figure 10, Figure 11, Figure 12 and Figure 13 All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 10 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter Table 11. Transfer characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter Conditions Min Typ Max Unit Tamb = −40 °C to +125 °C VT+ VT− VH positive-going threshold voltage see Figure 10 and Figure 11 negative-going threshold voltage VCC = 0.8 V 0.30 - 0.62 V VCC = 1.1 V 0.53 - 0.92 V VCC = 1.4 V 0.74 - 1.13 V VCC = 1.65 V 0.91 - 1.31 V VCC = 2.3 V 1.37 - 1.80 V VCC = 3.0 V 1.88 - 2.32 V VCC = 0.8 V 0.10 - 0.60 V VCC = 1.1 V 0.26 - 0.65 V VCC = 1.4 V 0.39 - 0.75 V VCC = 1.65 V 0.47 - 0.84 V VCC = 2.3 V 0.69 - 1.04 V VCC = 3.0 V 0.88 - 1.24 V VCC = 0.8 V 0.07 - 0.50 V VCC = 1.1 V 0.08 - 0.46 V VCC = 1.4 V 0.18 - 0.56 V VCC = 1.65 V 0.27 - 0.66 V VCC = 2.3 V 0.53 - 0.92 V VCC = 3.0 V 0.79 - 1.31 V see Figure 10 and Figure 11 hysteresis voltage see Figure 10, Figure 11, Figure 12 and Figure 13 15. Waveforms transfer characteristics VT+ VO VI VH VT− VO VI VH VT− VT+ Fig 10. Transfer characteristic 74AUP1G14 Product data sheet mna207 mna208 VT+ and VT− limits at 70 % and 20 %. Fig 11. Definition of VT+, VT− and VH All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 11 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter 001aad691 240 ICC (μA) 160 80 0 0 0.4 0.8 1.2 1.6 2.0 VI (V) Fig 12. Typical transfer characteristics; VCC = 1.8 V 001aad692 1200 ICC (μA) 800 400 0 0 1.0 2.0 3.0 VI (V) Fig 13. Typical transfer characteristics; VCC = 3.0 V 74AUP1G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 12 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter 16. Application information The slow input rise and fall times cause additional power dissipation, this can be calculated using the following formula: Pad = fi × (tr × ICC(AV) + tf × ICC(AV)) × VCC where: Pad = additional power dissipation (μW); fi = input frequency (MHz); tr = input rise time (ns); 10 % to 90 %; tf = input fall time (ns); 90 % to 10 %; ICC(AV) = average additional supply current (μA). Average ICC differs with positive or negative input transitions, as shown in Figure 14. An example of a relaxation circuit using the 74AUP1G14 is shown in Figure 15. 001aad027 0.3 ΔICC(AV) (mA) (1) 0.2 (2) 0.1 0 0.8 1.8 2.8 3.8 VCC (V) (1) Positive-going edge (2) Negative-going edge. Fig 14. Average ICC as a function of VCC 74AUP1G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 13 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter R C mna035 1 1 f = --- ≈ ----------------T a × RC Average values for variable a are given in Table 12. Fig 15. Relaxation oscillator Table 12. Variable values Supply voltage Variable a 1.1 V 1.28 1.5 V 1.22 1.8 V 1.24 2.8 V 1.34 3.3 V 1.45 74AUP1G14 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 14 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter 17. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm E D SOT353-1 A X c y HE v M A Z 5 4 A2 A (A3) A1 θ 1 Lp 3 L e w M bp detail X e1 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e e1 HE L Lp v w y Z(1) θ mm 1.1 0.1 0 1.0 0.8 0.15 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 1.3 2.25 2.0 0.425 0.46 0.21 0.3 0.1 0.1 0.60 0.15 7° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 REFERENCES IEC JEDEC JEITA MO-203 SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Fig 16. Package outline SOT353-1 (TSSOP5) 74AUP1G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 15 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter SOT886 XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm b 1 2 3 4x (2) L L1 e 6 5 e1 4 e1 6x A (2) A1 D E terminal 1 index area 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit mm max nom min A(1) 0.5 A1 b D E 0.04 0.25 1.50 1.05 0.20 1.45 1.00 0.17 1.40 0.95 e e1 0.6 0.5 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. Outline version SOT886 sot886_po References IEC JEDEC JEITA European projection Issue date 04-07-22 12-01-05 MO-252 Fig 17. Package outline SOT886 (XSON6) 74AUP1G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 16 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm 1 SOT891 b 3 2 4× (1) L L1 e 6 5 e1 4 e1 6× A (1) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 max b D E e e1 L L1 mm 0.5 0.04 0.20 0.12 1.05 0.95 1.05 0.95 0.55 0.35 0.35 0.27 0.40 0.32 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 SOT891 Fig 18. Package outline SOT891 (XSON6) 74AUP1G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 17 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1.0 x 0.35 mm 1 SOT1115 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 max 0.35 0.04 0.20 0.95 1.05 nom 0.15 0.90 1.00 0.55 min 0.12 0.85 0.95 0.3 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1115_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-07 SOT1115 Fig 19. Package outline SOT1115 (XSON6) 74AUP1G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 18 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm 1 SOT1202 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.05 1.05 0.35 0.40 nom 0.15 1.00 1.00 0.55 0.35 0.30 0.35 min 0.12 0.95 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1202_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-06 SOT1202 Fig 20. Package outline SOT1202 (XSON6) 74AUP1G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 19 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8 x 0.8 x 0.35 mm B A D SOT1226 X A E A1 A3 detail X terminal 1 index area e C v w b 1 2 terminal 1 index area C A B C y1 C y k D h 3 L 5 4 0 1 mm scale Dimensions Unit mm A(1) A1 A3 D Dh E b e k L max 0.35 0.04 0.128 0.85 0.30 0.85 0.27 0.27 nom 0.80 0.25 0.80 0.22 0.48 0.22 min 0.20 0.17 0.040 0.75 0.20 0.75 0.17 v 0.1 w y y1 0.05 0.05 0.05 Note 1. Dimension A is including plating thickness. 2. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version References IEC JEDEC EIAJ sot1226_po European projection Issue date 12-04-10 12-04-25 SOT1226 Fig 21. Package outline SOT1226 (X2SON5) 74AUP1G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 20 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter 18. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 19. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AUP1G14 v.6 20120628 Product data sheet - 74AUP1G14 v.5 Modifications: 74AUP1G14 v.5 Modifications: • • Added type number 74AUP1G14GX (SOT1226) Package outline drawing of SOT886 (Figure 17) modified. 20111128 • Product data sheet - 74AUP1G14 v.4 Legal pages updated. 74AUP1G14 v.4 20100713 Product data sheet - 74AUP1G14 v.3 74AUP1G14 v.3 20090708 Product data sheet - 74AUP1G14 v.2 74AUP1G14 v.2 20060828 Product data sheet - 74AUP1G14 v.1 74AUP1G14 v.1 20050718 Product data sheet - - 74AUP1G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 21 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 20.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 20.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74AUP1G14 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 22 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 20.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 21. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74AUP1G14 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 June 2012 © NXP B.V. 2012. All rights reserved. 23 of 24 74AUP1G14 NXP Semiconductors Low-power Schmitt trigger inverter 22. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 12 13 14 15 16 17 18 19 20 20.1 20.2 20.3 20.4 21 22 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Transfer characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms transfer characteristics. . . . . . . . 11 Application information. . . . . . . . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contact information. . . . . . . . . . . . . . . . . . . . . 23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 28 June 2012 Document identifier: 74AUP1G14