INTEGRATED CIRCUITS DATA SHEET UDA1330ATS Low-cost stereo filter DAC Preliminary specification Supersedes data of 1999 Dec 20 File under Integrated Circuits, IC01 2000 Apr 18 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS FEATURES General • Low power consumption • Power supply voltage from 2.7 to 5.5 V • Selectable control via L3 microcontroller interface or via static pin control • System clock frequencies of 256fs, 384fs and 512fs selectable via L3 interface or 256fs and 384fs via static pin control APPLICATIONS • Supports sampling frequencies (fs) from 16 to 55 kHz • PC audio applications • Integrated digital filter plus non inverting Digital-to-Analog Converter (DAC) • Car radio applications. • No analog post filtering required for DAC GENERAL DESCRIPTION • Slave mode only applications The UDA1330ATS is a single-chip stereo DAC employing bitstream conversion techniques. • Easy application • Small package size (SSOP16) The UDA1330ATS supports the I2S-bus data format with word lengths of up to 20 bits, the MSB-justified data format with word lengths of up to 20 bits and the LSB-justified serial data format with word lengths of 16, 18 and 20 bits. • TTL tolerant input pads • Pin and function compatible with the UDA1320ATS. Multiple format input interface The UDA1330ATS can be used in two modes: L3 mode or the static pin mode. • L3 mode: I2S-bus, MSB-justified or LSB-justified 16, 18 and 20 bits format compatible In the L3 mode, all digital sound processing features must be controlled via the L3 interface, including the selection of the system clock setting. • Static pin mode: I2S-bus and LSB-justified 16, 18 and 20 bits format compatible • 1fs input format data rate. In the two static modes, the UDA1330ATS can be operated in the 256fs and 384fs system clock mode. Muting, de-emphasis for 44.1 kHz and four digital input formats (I2S-bus or LSB-justified 16, 18, and 20 bits) can be selected via static pins. The L3 interface cannot be used in this application mode, so volume control is not available in this mode. DAC digital sound processing • Digital logarithmic volume control in L3 mode • Digital de-emphasis for 32, 44.1 and 48 kHz sampling frequencies in L3 mode or 44.1 kHz sampling frequency in static pin mode • Soft mute control both in static pin mode and L3 mode. Advanced audio configuration • Stereo line output (volume control in L3 mode) • High linearity, wide dynamic range and low distortion. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME UDA1330ATS 2000 Apr 18 SSOP16 DESCRIPTION plastic shrink small outline package; 16 leads; body width 4.4 mm 2 VERSION SOT369-1 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA DAC analog supply voltage VDDD digital supply voltage IDDA DAC analog supply current 2.7 5.0 5.5 V 2.7 5.0 5.5 V operating − 9.5 − mA power-down − 400 − µA operating − 7.0 − mA power-down − 250 − µA VDDD = 5.0 V − 5.5 − mA VDDD = 3.3 V − 3.0 − mA −40 − +85 °C VDDA = 5.0 V VDDA = 3.3 V IDDD Tamb digital supply current ambient temperature Digital-to-analog converter (VDDA = VDDD = 5.0 V) Vo(rms) output voltage (RMS value) note 1 − 1.45 − V (THD + N)/S total harmonic distortion-plus-noise to signal ratio at 0 dB − −90 −85 dB at −60 dB; A-weighted − −40 −35 dB S/N signal-to-noise ratio code = 0; A-weighted − +100 −95 dB αcs channel separation − 100 − dB Digital-to-analog converter (VDDA = VDDD = 3.3 V) Vo(rms) output voltage (RMS value) note 1 − 1.0 − V (THD + N)/S total harmonic distortion-plus-noise to signal ratio at 0 dB − −85 − dB at −60 dB; A-weighted − −38 − dB S/N signal-to-noise ratio code = 0; A-weighted − 100 − dB αcs channel separation − 100 − dB VDDA = VDDD = 5.0 V − 75 − mW VDDA = VDDD = 3.3 V − 33 − mW Power dissipation P power dissipation playback mode Note 1. The output voltage scales linearly with the power supply voltage. 2000 Apr 18 3 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS BLOCK DIAGRAM VSSD VDDD handbook, full pagewidth 4 BCK WS DATAI 5 1 2 3 DIGITAL INTERFACE CONTROL INTERFACE 7 11 10 9 8 APPSEL APPL0 APPL1 APPL2 APPL3 UDA1330ATS VOLUME/MUTE/DE-EMPHASIS SYSCLK 6 INTERPOLATION FILTER NOISE SHAPER VOUTL DAC 14 16 DAC 13 15 VDDA VSSA 12 VOUTR MGL401 Vref(DAC) Fig.1 Block diagram. PINNING SYMBOL PIN DESCRIPTION BCK 1 bit clock input WS 2 word select input DATAI 3 data input handbook, halfpage BCK 1 VDDD 4 digital supply voltage VSSD 5 digital ground SYSCLK 6 system clock input: 256fs, 384fs and 512fs VDDD 4 VSSD 5 16 VOUTR WS 2 15 VSSA DATAI 3 14 VOUTL 13 VDDA UDA1330ATS 12 Vref(DAC) APPSEL 7 application mode select input APPL3 8 application input 3 SYSCLK 6 11 APPL0 APPL2 9 application input 2 APPSEL 7 10 APPL1 APPL1 10 application input 1 APPL3 8 APPL0 11 application input 0 Vref(DAC) 12 DAC reference voltage VDDA 13 analog supply voltage for DAC VOUTL 14 left channel output VSSA 15 analog ground VOUTR 16 right channel output 2000 Apr 18 9 APPL2 MGL402 Fig.2 Pin configuration. 4 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS In the L3 mode, pin APPL0 must be set to LOW. It should be noted that when the L3 mode is used, an initialization must be performed when the IC is powered-up. FUNCTIONAL DESCRIPTION System clock The UDA1330ATS operates in slave mode only. Therefore, in all applications the system devices must provide the system clock. The system frequency (fsys) is selectable and depends on the application mode. The options are: 256fs, 384fs and 512fs for the L3 mode and 256fs or 384fs for the static pin mode. The system clock must be locked in frequency to the digital interface input signals. Multiple format input interface DATA FORMATS The digital interface of the UDA1330ATS supports multiple format inputs (see Fig.3). Left and right data-channel words are time multiplexed. The WS signal must have a 50% duty factor for all LSB-justified formats. The UDA1330ATS supports sampling frequencies from 16 to 55 kHz. The BCK clock can be up to 64fs, or in other words the BCK frequency is 64 times the Word Select (WS) frequency or less: fBCK ≤ 64 × fWS. Application modes The application mode can be set with the three-level pin APPSEL (see Table 1): Important: the WS edge MUST fall on the negative edge of the BCK at all times for proper operation of the digital interface. • L3 mode • Static pin mode with fsys = 384fs • Static pin mode with fsys = 256fs. Table 1 The UDA1330ATS also accepts double speed data for double speed data monitoring purposes Selecting application mode and system clock frequency via pin APPSEL VOLTAGE ON PIN APPSEL MODE fsys VSSD L3 mode 256fs, 384fs or 512fs 0.5VDDD VDDD L3 MODE This mode supports the following input formats: • I2S-bus format with data word length of up to 20 bits • MSB-justified format with data word length up to 20 bits 384fs static pin mode • LSB-justified format with data word length of 16, 18 or 20 bits. 256fs STATIC PIN MODE The function of an application input pin (active HIGH) depends on the application mode (see Table 2). Table 2 This mode supports the following input formats: • I2S-bus format with data word length of up to 20 bits Functions of application input pins • LSB-justified format with data word length of 16, 18 or 20 bits. FUNCTION PIN L3 MODE STATIC PIN MODE APPL0 TEST MUTE These four formats are selectable via the static pin codes SF0 and SF1 (see Table 3). APPL1 L3CLOCK DEEM Table 3 APPL2 L3MODE SF0 APPL3 L3DATA SF1 FORMAT For example, in the static pin mode the output signal can be soft muted by setting pin APPL0 to HIGH. De-emphasis can be switched on for 44.1 kHz by setting pin APPL1 to HIGH; setting pin APPL1 to LOW will disable de-emphasis. 2000 Apr 18 Input format selection using SF0 and SF1 5 SF0 SF1 I2S-bus 0 0 LSB-justified 16 bits 0 1 LSB-justified 18 bits 1 0 LSB-justified 20 bits 1 1 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS Interpolation filter (DAC) Filter stream DAC The digital filter interpolates from 1fs to 128fs by cascading a recursive filter and an FIR filter (see Table 4). The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post-filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. Table 4 Interpolation filter characteristics ITEM CONDITION VALUE (dB) Pass-band ripple 0 to 0.45fs ±0.1 >0.55fs −50 0 to 0.45fs 108 Stop band Dynamic range The output voltage of the FSDAC scales linearly with the power supply voltage. Noise shaper The 3rd-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter Stream DAC (FSDAC). 2000 Apr 18 Pin compatibility In the L3 mode the UDA1330ATS can be used on boards that are designed for the UDA1320ATS. Remark: It should be noted that the UDA1330ATS is designed for 5 V operation while the UDA1320ATS is designed for 3 V operation. This means that the UDA1330ATS can be used with the UDA1320ATS supply voltage range, but the UDA1320ATS can not be used with the 5 V supply voltage. 6 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2 >=8 3 2 3 MSB B2 1 >=8 BCK MSB DATA B2 MSB I2 S-BUS FORMAT LEFT WS 1 2 RIGHT >=8 3 1 2 >=8 3 BCK DATA MSB B2 LSB MSB B2 LSB MSB Philips Semiconductors 1 Low-cost stereo filter DAC ook, full pagewidth 2000 Apr 18 RIGHT LEFT WS B2 MSB-JUSTIFIED FORMAT WS LEFT RIGHT 16 15 2 1 16 B15 LSB MSB 15 2 1 BCK 7 DATA MSB B2 B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS WS LEFT RIGHT 18 17 16 15 2 1 18 B17 LSB MSB 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B2 B3 B4 B17 LSB LSB-JUSTIFIED FORMAT 18 BITS WS LEFT 20 RIGHT 19 18 17 16 15 2 1 20 B19 LSB MSB 19 18 17 16 15 2 1 BCK B2 B3 B4 B5 B6 LSB-JUSTIFIED FORMAT 20 BITS Fig.3 Digital interface input format data format. B2 B3 B4 B5 B6 B19 LSB MBL140 Preliminary specification MSB UDA1330ATS DATA Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS L3 INTERFACE The fundamental timing of data transfers (see Fig.5) is essentially the same as the address mode. The maximum input clock frequency and data rate is 64fs. The following system and digital sound processing features can be controlled in the L3 mode of the UDA1330ATS: • De-emphasis for 32, 44.1 and 48 kHz Data transfer can only be in one direction, consisting of input to the UDA1330ATS to program sound processing and other functional features. All data transfers are by 8-bit bytes. Data will be stored in the UDA1330ATS after reception of a complete byte. • Volume A multibyte transfer is illustrated in Fig.6. • System clock frequency • Data input format • Soft mute. Registers The exchange of data and control information between the microcontroller and the UDA1330ATS is accomplished through a serial interface comprising the following signals: The sound processing and other feature values are stored in independent registers. The first selection of the registers is achieved by the choice of data type that is transferred. This is performed in the address mode using bit 1 and bit 0 (see Table 5). • L3DATA • L3MODE • L3CLOCK. Table 5 Information transfer through the microcontroller bus is organized in accordance with the L3 interface format, in which two different modes of operation can be distinguished: address mode and data transfer mode. Selection of data transfer BIT 1 BIT 0 TRANSFER 0 0 data (volume, de-emphasis, mute) 0 1 not used Address mode 1 0 The address mode (see Fig.4) is required to select a device communicating via the L3 interface and to define the destination registers for the data transfer mode. status (system clock frequency, data input format) 1 1 not used The second selection is performed by the 2 MSBs of the data byte (bit 7 and bit 6). The other bits in the data byte (bit 5 to bit 0) represent the value that is placed in the selected registers. Data bits 7 to 2 represent a 6-bit device address where bit 7 is the MSB. The address of the UDA1330ATS is 000101 (bit 7 to bit 2). If the UDA1330ATS receives a different address, it will deselect its microcontroller interface logic. The ‘status’ settings are given in Table 6 and the ‘data’ settings are given in Table 7. Data transfer mode The selected address remains active during subsequent data transfers until the UDA1330ATS receives a new address command. 2000 Apr 18 8 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS handbook, full pagewidth L3MODE tsu(L3)A th(L3)A tCLK(L3)L tsu(L3)A tCLK(L3)H th(L3)A L3CLOCK Tcy(CLK)(L3) tsu(L3)DA th(L3)DA BIT 7 BIT 0 L3DATA MGL723 Fig.4 Timing address mode. handbook, full pagewidth tstp(L3) tstp(L3) L3MODE tCLK(L3)L Tcy(CLK)L3 tCLK(L3)H tsu(L3)D th(L3)D L3CLOCK th(L3)DA tsu(L3)DA L3DATA WRITE BIT 7 BIT 0 MGL882 Fig.5 Timing data transfer mode. 2000 Apr 18 9 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS tstp(L3) handbook, full pagewidth L3MODE L3CLOCK L3DATA address data byte #1 data byte #2 address MGL725 Fig.6 Multibyte data transfer. Programming the features When the data transfer of type ‘status’ is selected, the features for the system clock frequency and the data input format can be controlled. Table 6 Data transfer of type ‘status’ BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 SC1 SC0 IF2 IF1 IF0 0 REGISTER SELECTED SC = system clock frequency (2 bits); see Table 8 IF = data input format (3 bits); see Table 9 1 0 0 0 0 0 0 0 not used When the data transfer of type ‘data’ is selected, the features for volume, de-emphasis and mute can be controlled. Table 7 Data transfer of type ‘data’ BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER SELECTED 0 0 VC5 VC4 VC3 VC2 VC1 VC0 0 1 0 0 0 0 0 0 not used 1 0 0 DE1 DE0 MT 0 0 DE = de-emphasis (2 bits); see Table 10 1 1 0 0 0 0 0 1 VC = volume control (6 bits); see Table 11 MT = mute (1 bit); see Table 12 2000 Apr 18 10 default setting Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS SYSTEM CLOCK FREQUENCY VOLUME CONTROL The system clock frequency is a 2-bit value to select the external clock frequency. The volume control is a 6-bit value to program the volume attenuation from 0 to −60 dB and −∞ dB in steps of 1 dB. Table 8 Table 11 Volume settings SC1 System clock settings SC0 FUNCTION VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB) 0 0 512fs 0 0 0 0 0 0 0 0 1 384fs 0 0 0 0 0 1 0 1 0 256fs 0 0 0 0 1 0 −1 1 1 not used 0 0 0 0 1 1 −2 : : : : : : : DATA FORMAT 1 1 0 0 1 1 The data format is a 3-bit value to select the used data format. 1 1 0 1 0 0 −51 1 1 0 1 0 1 Table 9 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 IF2 Data input format settings IF1 IF0 FORMAT 0 0 0 I2S-bus 0 0 1 LSB-justified 16 bits 0 1 0 LSB-justified 18 bits 0 1 1 LSB-justified 20 bits 1 0 0 MSB-justified 1 0 1 not used 1 1 0 not used 1 1 1 not used MUTE DE-EMPHASIS Mute is a 1-bit value to enable the digital mute. De-emphasis is a 2-bit value to enable the digital de-emphasis filter. Table 12 Mute setting MT Table 10 De-emphasis settings DE1 0 0 1 1 DE0 0 1 0 1 2000 Apr 18 FUNCTION no de-emphasis de-emphasis, 32 kHz de-emphasis, 44.1 kHz de-emphasis, 48 kHz 11 FUNCTION 0 no muting 1 muting −52 −54 −57 −60 −∞ Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDDD digital supply voltage note 1 − 6.0 V VDDA analog supply voltage note 1 − 6.0 V Txtal(max) maximum crystal temperature − 150 °C Tstg storage temperature −65 +125 °C Tamb ambient temperature −40 +85 °C Ves electrostatic handling voltage note 2 −3000 +3000 V note 3 −250 +250 V Isc(DAC) short-circuit current of DAC output short-circuited to VSSA(DAC) − 450 mA output short-circuited to VDDA(DAC) − 300 mA note 4 Notes 1. All supply connections must be made to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor. 3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor. 4. Short-circuit test at Tamb = 0 °C and VDDA = 3 V. DAC operation after short-circuiting cannot be warranted. HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS thermal resistance from junction to ambient in free air QUALITY SPECIFICATION In accordance with “SNW-FQ-611-E”. 2000 Apr 18 12 VALUE UNIT 190 K/W Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS DC CHARACTERISTICS VDDD = VDDA = 5.0 V; Tamb = 25 °C; RL = 5 kΩ; all voltages referenced to ground (pins VSSA and VSSD); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA DAC analog supply voltage note 1 2.7 5.0 5.5 V VDDD digital supply voltage 2.7 5.0 5.5 V IDDA DAC analog supply current VDDA = 5.0 V operating − 9.5 − mA power-down − 400 − µA operating − 7.0 − mA power-down − 250 − µA VDDD = 5.0 V − 5.5 − mA VDDD = 3.3 V − 3.0 − mA VDDA = VDDD = 5.0 V − 75 − mW VDDA = VDDD = 3.3 V − 33 − mW note 1 VDDA = 3.3 V IDDD digital supply current Power dissipation P power dissipation playback mode Digital inputs: pins BCK, WS, DATAI, SYSCLK, APPL0, APPL1, APPL2 and APPL3 (note 2) VIH HIGH-level input voltage VIL LOW-level input voltage 2.2 − − V VDDD = 3.3 V 1.45 − − V VDDD = 5.0 V − − 0.8 V VDDD = 3.3 V − − 0.5 V VDDD = 5.0 V ILI input leakage current − − 1 µA Ci input capacitance − − 10 pF Three-level input: APPSEL VIH HIGH-level input voltage 0.9VDDD − VDDD + 0.5 V VIM MIDDLE-level input voltage 0.4VDDD − 0.6VDDD V VIL LOW-level input voltage −0.5 − +0.1VDDD V 2000 Apr 18 13 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC SYMBOL UDA1330ATS PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DAC Vref(DAC) reference voltage with respect to VSSA 0.45VDDA 0.5VDDA 0.55VDDA V Io(max) maximum output current (THD + N)/S < 0.1%; RL = 5 kΩ − 0.36 − mA Ro output resistance − 0.15 2.0 Ω RL load resistance 3 − − kΩ CL load capacitance − − 50 pF note 3 Notes 1. All supply connections must be made to the same external power supply unit. 2. The digital input pads are TTL compatible at 5 V, but the pads are not 5 V tolerant in the voltage range between 2.7 and 4.5 V. 3. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent oscillations in the output operational amplifier. AC CHARACTERISTICS fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ; all voltages referenced to ground (pins VSSA and VSSD); unless otherwise specified. SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT Digital-to-analog converter (VDDA = VDDD = 5.0 V) Vo(rms) output voltage (RMS value) 1.45 − V ∆Vo unbalance between channels 0.1 − dB (THD + N)/S total harmonic distortion-plus-noise to signal ratio at 0 dB −90 −85 dB at −60 dB; A-weighted −40 −35 dB S/N signal-to-noise ratio code = 0; A-weighted +100 −95 dB αcs channel separation 100 − dB 1.0 − V Digital-to-analog converter (VDDA = VDDD = 3.3 V) Vo(rms) output voltage (RMS value) ∆Vo unbalance between channels 0.1 − dB (THD + N)/S total harmonic distortion-plus-noise to signal ratio at 0 dB −85 − dB at −60 dB; A-weighted −38 − dB S/N signal-to-noise ratio code = 0; A-weighted αcs channel separation PSRR power supply ripple rejection 2000 Apr 18 fripple = 1 kHz; Vripple = 100 mV (p-p) 14 100 − dB 100 − dB 60 − dB Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS TIMING VDDD = VDDA = 4.5 to 5.5 V; Tamb = −40 to +85 °C; RL = 5 kΩ; all voltages referenced to ground (pins VSSA and VSSD); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT System clock (see Fig.7) Tsys system clock cycle time tCWL LOW-level system clock pulse width tCWH HIGH-level system clock pulse width fsys = 256fs 78 88 244 ns fsys = 384fs 52 59 162 ns fsys = 512fs 39 44 122 ns fsys < 19.2 MHz 0.3Tsys − 0.7Tsys ns fsys ≥ 19.2 MHz 0.4Tsys − 0.6Tsys ns fsys < 19.2 MHz 0.3Tsys − 0.7Tsys ns fsys ≥ 19.2 MHz 0.4Tsys − 0.6Tsys ns Digital interface (see Fig.8) Tcy(BCK) bit clock cycle time 300 − − ns tBCKH bit clock HIGH time 100 − − ns tBCKL bit clock LOW time 100 − − ns tr rise time − − 20 ns tf fall time − − 20 ns tsu(DATAI) data input set-up time 20 − − ns th(DATAI) data input hold time 0 − − ns tsu(WS) word select set-up time 20 − − ns th(WS) word select hold time 10 − − ns 500 − − ns Control interface L3 mode (see Figs 4 and 5) Tcy(CLK)L3 L3CLOCK cycle time tCLK(L3)H L3CLOCK HIGH time 250 − − ns tCLK(L3)L L3CLOCK LOW time 250 − − ns tsu(L3)A L3MODE set-up time for address mode 190 − − ns th(L3)A L3MODE hold time for address mode 190 − − ns tsu(L3)D L3MODE set-up time for data transfer mode 190 − − ns th(L3)D L3MODE hold time for data transfer mode 190 − − ns tsu(L3)DA L3DATA set-up time for data transfer and address mode 190 − − ns th(L3)DA L3DATA hold time for data transfer and address mode 30 − − ns tstp(L3) L3MODE stop time for data transfer mode 190 − − ns 2000 Apr 18 15 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS t CWH handbook, full pagewidth MGR984 t CWL Tsys Fig.7 System clock timing. handbook, full pagewidth WS th(WS) tBCKH tr tsu(WS) tf BCK tsu(DATAI) tBCKL Tcy(BCK) th(DATAI) DATAI MGL880 Fig.8 Serial interface timing. 2000 Apr 18 16 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS APPLICATION INFORMATION analog supply voltage handbook, full pagewidth digital supply voltage R2 1Ω C1 R3 1Ω 100 µF (16 V) system clock R1 SYSCLK 47 Ω C5 C6 100 nF (63 V) VSSA 100 nF (63 V) 15 VDDA 13 VSSD 5 VDDD 4 6 14 BCK WS DATAI APPSEL 47 µF (16 V) 1 2 APPL1 APPL2 APPL3 R4 100 Ω left output R5 10 kΩ 3 7 UDA1330ATS APPL0 VOUTL C2 16 VOUTR C3 47 µF (16 V) R6 100 Ω right output R7 10 kΩ 11 10 9 12 8 Vref(DAC) C7 100 nF (63 V) C4 47 µF (16 V) MGL403 Fig.9 Application diagram. 2000 Apr 18 17 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS PACKAGE OUTLINE SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm D SOT369-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 1.5 0.15 0.00 1.4 1.2 0.25 0.32 0.20 0.25 0.13 5.30 5.10 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.45 0.65 0.45 0.2 0.13 0.1 0.48 0.18 10 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT369-1 2000 Apr 18 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 MO-152 18 o Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS SOLDERING If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 2000 Apr 18 19 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(1) suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2000 Apr 18 20 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS DATA SHEET STATUS DATA SHEET STATUS PRODUCT STATUS DEFINITIONS (1) Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2000 Apr 18 21 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS NOTES 2000 Apr 18 22 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1330ATS NOTES 2000 Apr 18 23 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753503/25/04/pp24 Date of release: 2000 Apr 18 Document order number: 9397 750 06964