INTEGRATED CIRCUITS 74F225 16X5 asynchronous FIFO (3-State) Product specification IC15 Data Handbook 1992 Jun 15 Philips Semiconductors Product specification 16 × 5 asynchronous FIFO (3-State) 74F225 Ready (IR), Unload Clock Output (UNCPOUT) and Output Ready (OR). The data outputs are non–inverting with respect to the data inputs and are disabled when the OE input is High. When OE is Low, the data outputs are enabled to function as totem–pole outputs. FEATURES • Independent synchronous inputs and outputs • Organized as 16 words of 5 bits • DC to 25MHz data rate • 3–State outputs • Cascadable in word–width and depth direction DESCRIPTION TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT ( TOTAL) 74F225 25MHz 65mA ORDERING INFORMATION This 80–bit active element First–In–First–Out (FIFO) is a monolithic Schottky–clamped transistor–transistor logic (STTL) array organized as 16–words of 5–bits each. A memory system using the ’F225 can be easily expanded in multiples of 16–words of 5–bits as shown in Figure 1. The 3–State outputs controlled by a single enable input (OE) make bus connection and multiplexing simple. The ’F225 processes data in a parallel format at any desired clock rate from DC to 25MHz. Status of the ’F225 is provided by three outputs, Input ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C PKG DWG # 20–pin plastic DIP N74F225N SOT146-1 20–pin plastic SOL N74F225D SOT163-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Load clock A and load clock B inputs 1.0/0.033 20µA/20µA Data inputs 1.0/0.033 20µA/20µA Output enable input (active–Low) 1.0/0.033 20µA/20µA Unload clock input 1.0/0.033 20µA/20µA MR Master reset input (active–Low) 1.0/0.033 20µA/20µA IR Input ready output 50/33 1.0mA/20mA Unload clock output (active–Low) 50/33 1.0mA/20mA Data outputs 150/40 3.0mA/24mA 50/33 1.0mA/20mA CPA, CPB D0 – D4 OE UNCPIN UNCPOUT Q0 – Q4 DESCRIPTION OR Output ready output NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. RESET MODE READ MODE A High–to–Low transition on the Master Reset (MR) input invalidates all data stored in the FIFO by clearing the control logic and setting OR Low. This High–to–Low transition on the MR input does not effect the data outputs but since OR is driven Low, it signifies invalid data on the outputs. The Output Ready (OR) output is High when valid data is present on the data outputs. Data in the array is shifted on the Low–to–High transition of the Unload Clock Input (UNCPIN). In order for Output Ready (OR) to go High, Unload Clock Input (UNCPIN) must also be High. WRITE MODE Data may be written into the array on the Low–to–High transition of either load clock (CPA or CPB) input. When writing data into the FIFO, one of the load clock inputs must be held High while the other strobes data into the FIFO. This arrangement allows either load clock to function as an inhibit for the other. Input Ready (IR) monitors the status of the last word location and signifies when the FIFO is full. This output is High whenever the FIFO is available to accept new data. The unload clock output (UNCPOUT) also monitors the last word location. This output generates a Low–logic–level pulse (synchronized to the internal clock pulse) when the last word location is vacant June 15, 1992 2 853-1652 06992 Philips Semiconductors Product specification 16 × 5 asynchronous FIFO (3-State) 74F225 PIN CONFIGURATION CPA IR IEC/IEEE SYMBOL 1 20 VCC 2 19 CPB UNCPOUT 3 18 MR 9 18 EN5 CT<16 4 17 OR D1 5 16 UNCPIN 3 + 1 & – G1 G2/Z3 2CT<16 2 17 D2 6 15 Q0 16 D3 7 14 Q1 4 D4 8 13 Q2 5 14 OE 9 12 Q3 6 13 11 Q4 7 12 8 11 GND 10 SF00334 5 6 7 8 D0 D1 D2 D3 D4 1 CPA 19 CPB 16 UNCPIN 9 OE 18 MR UNCPOUT 5 15 SF00336 LOGIC SYMBOL 4 4 Z4 1D 3 Q0 Q1 Q2 Q3 Q4 IR OR June 15, 1992 & 1 19 D0 3 CT=0 CT>0 VCC = Pin 20 GND = Pin 10 FIFO 16 X 5 CTR 15 14 13 12 11 2 17 SF00335 3 Philips Semiconductors Product specification 16 × 5 asynchronous FIFO (3-State) 74F225 LOGIC DIAGRAM Word 16 (last word) Word 15 Word 3–14 same as 2 or 16 Word 2 Word 1 (first word) Detail A 4 15 D0 QO 5 14 D1 Detail A 6 13 Detail A D2 7 D3 12 Detail A 8 11 D4 Detail A Q1 Q2 Q3 Q4 9 OE CPA CPB 1 19 Q 17 CP OR D CLR 16 3 UNCPIN UNCPOUT IR MR 2 VCC = pin 20 GND = pin 10 18 SF00337 June 15, 1992 4 Philips Semiconductors Product specification 16 × 5 asynchronous FIFO (3-State) 74F225 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) PARAMETER SYMBOL RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA –0.5 to VCC V VOUT Voltage applied to output in High output state IOUT Current applied to output in Low output state IR, OR, UNCPOUT 40 mA Current applied to output in Low output state Data outputs 48 mA 0 to +70 °C –65 to +150 °C Tamb Operating free air temperature range Tstg Storage temperature range RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNIT MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 VIN High–level input voltage 2.0 VIL Low–level input voltage 0.8 V IIk Input clamp current –18 mA IOH High–level output current IR, OR, UNCPOUT –1 mA Data outputs –3 mA IOL Low–level output current IR, OR, UNCPOUT 20 mA Data outputs 24 mA +70 °C Tamb Operating free air temperature range June 15, 1992 0 5 V V Philips Semiconductors Product specification 16 × 5 asynchronous FIFO (3-State) 74F225 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) TEST CONDITIONS1 PARAMETER SYMBOL LIMITS MIN VOH High-level output voltage IR, OR, VCC = MIN, VIL = MAX UNCPOUT VIH = MIN, IOH = MAX Data VCC = MIN, VIL = MAX outputs VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX ±10%VCC ±5%VCC ±10%VCC ±5%VCC ±10%VCC ±5%VCC TYP2 UNIT MAX 2.5 V 2.7 V 2.4 V 2.7 V VOL Low-level output voltage VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage VCC = MAX, VI = 7.0V IIH High–level input current VCC = MAX, VI = 2.7V IIL Low–level input current VCC = MAX, VI = 0.5V IOZH Offset–output current, High–level voltage applied VCC = MAX, VI = 2.7V 50 µA IOZL Offset–output current, Low–level voltage applied VCC = MAX, VI = 0.5V –50 µA -150 mA 95 mA VIH = MIN, IOL = MAX current3 IOS Short-circuit output ICC Supply current (total) VCC = MAX VCC = MAX 0.35 0.50 V 0.35 0.50 V -0.73 -1.2 V 100 20 µA µA –20 µA -60 65 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of High-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. June 15, 1992 6 Philips Semiconductors Product specification 16 × 5 asynchronous FIFO (3-State) 74F225 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5.0V TEST CONDITION CL = 50pF, RL = 500Ω MIN fMAX Maximum clock frequency, Cascade mode tPLH tPHL Tamb = 0°C to +70°C TYP VCC = +5.0V ± 10% UNIT CL = 50pF, RL = 500Ω MAX MIN MAX Waveform 2 and 3 25 25 MHz Propagation delay UNCPIN to Qn Waveform 2 10.0 9.5 13.0 12.0 19.5 16.0 9.0 8.5 22.0 19.0 ns tPLH tPHL Propagation delay UNCPIN to OR Waveform 2 16.0 6.0 20.0 8.5 25.0 11.0 14.0 5.0 29.0 12.0 ns tSK Output skew Qn to OR ↑ Waveform 4 2.0 12.0 0.0 15.0 ns tPLH Propagation delay UNCPIN to IR Waveform 2 50 60 70 50 85 ns tPLH Propagation delay CPA or CPB to OR Waveform 4 55 65 75 50 90 ns tPLH tPHL Propagation delay CPA or CPB to UNCPOUT Waveform 4 20.0 8.5 23.0 11.5 27.0 15.0 17.0 7.5 29.0 16.0 ns tw(L) Pulse width, Low UNCPOUT Waveform 4 tPHL Propagation delay CPA or CPB to IR Waveform 3 11.0 13.5 17.0 9.0 19.0 ns tPHL Propagation delay MR to OR Waveform 3 5.5 8.5 11.5 5.0 13.0 ns tPHL Propagation delay MR to IR Waveform 3 2.0 4.0 7.0 1.5 7.5 ns tPZH tPZL Output enable time to High or Low level Waveform 5 Waveform 6 1.5 2.5 3.5 4.5 6.5 7.5 1.0 2.0 7.0 9.0 ns tPHZ tPLZ Output disable time from High or Low level Waveform 5 Waveform 6 1.5 2.0 3.5 4.0 7.0 7.0 1.0 1.5 7.5 7.5 ns 12.0 ns AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5.0V TEST CONDITION CL = 50pF, RL = 500Ω MIN TYP MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% UNIT CL = 50pF, RL = 500Ω MIN MAX ts(H) ts(L) Setup time, High or Low Dn to CPA or CPB Waveform 1 0.0 0.0 0.0 0.0 ns th(H) th(L) Hold time, High or Low Dn to CPA or CPB Waveform 1 14.0 12.5 16.5 14.0 ns Recovery time MR to CPA or CPB Waveform 1 0.0 0.0 ns tw(H) tw(L) CPA or CPB pulse width, High or Low Waveform 1 6.5 3.0 8.5 3.5 ns tw(L) UNCPIN pulse width, High or Low Waveform 2 24.0 3.5 28.0 4.0 ns tw(L) MR pulse width, Low Waveform 1 3.5 4.5 ns trec June 15, 1992 7 Philips Semiconductors Product specification 16 × 5 asynchronous FIFO (3-State) 74F225 TYPICAL TIMING DIAGRAM MR CPA CPB Dn Word 1 Word 2 Word 3 is Low Word 16 UNCPIN IR UNCPOUT OR Qn Word 1 Word 1 Clear Word 2 Load words 3–15 Load word 1 Load word 2 Word 16 Word 3 Unload words 4–15 Load word 16 Unload word 2 Unload word 3 Unload word 16 SF00338 NOTE: Shaded areas Indicates irrelevant input conditions. June 15, 1992 8 Philips Semiconductors Product specification 16 × 5 asynchronous FIFO (3-State) 74F225 AC WAVEFORMS 1/fMAX tw(L) CP VM VM VM VM CPA or CPB tw(H) th VM tPHL tsu Dn VM VM VM tw(L) VM VM tPLH tsu MR tPLH VM VM UNCPOUT VM tw(L) VM OR VM tSK SF00339 Waveform 1. MR and Clock Pulse Widths, Data Setup and Hold Times and MR to Clock Setup Time Qn VM SF00342 1/fMAX tw(L) VM VM tw(H) VM UNCPIN VM tPHL tPLH Qn Waveform 4. CPA or CPB to UNCPOUT and OR Delay, UNCPOUT Pulse Width and Qn to OR Skew VM VM OE tPHL OR tPLH VM tPZH VM VM VM Qn tPHZ VOH -0.3V VM 0V tPLH IR SF00343 VM Waveform 5. 3-State Output Enable Time to High Level and Output Disable Time from High Level SF00340 Waveform 2. UNCPIN to Output Delays OE 1/fMAX CPA or CPB VM VM tPZL VM Qn tPHL Waveform 6. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level VM tPHL OR VM SF00341 Waveform 3. CPA or CPB to IR Delay and MR to IR and OR Delay NOTES: 1. For all waveforms, VM = 1.5V. 2. The shaded areas indicate when the input is permitted to change for predictable output performance. June 15, 1992 VM SF00344 tPLH VM IR tPLZ VOL +0.3V VM MR VM 9 Philips Semiconductors Product specification 16 × 5 asynchronous FIFO (3-State) 74F225 APPLICATION Load clock CPA CPA OR UNCPOUT NC NC OR Output ready UNCPIN Unload clock CPB UNCPOUT UNCPIN IR 5–bit data input CPA OR CPB CPB UNCPOUT UNCPIN NC IR IR D0 Q0 D0 Q0 D0 Q0 D1 Q1 D1 Q1 D1 Q1 D2 Q2 D2 Q2 D2 Q2 D3 Q3 D3 Q3 D3 Q3 Q4 D4 Q4 D4 D4 MR OE MR OE 5–bit data output Q4 MR OE Output enable Master reset Input ready MR OE CPA MR OR CPB NC UNCPOUT MR UNCPIN OR CPB UNCPOUT NC OE CPA OR CPB IR 5–bit data input OE CPA UNCPOUT UNCPIN UNCPIN IR NC IR D0 Q0 D0 Q0 D0 Q0 D1 Q1 D1 Q1 D1 Q1 D2 Q2 D2 Q2 D2 Q2 D3 Q3 D3 Q3 D3 Q3 D4 Q4 D4 Q4 D4 Q4 5–bit data output SF00345 Figure 1. Expanding the 74F225 FIFO (48 words of 10 bits) TEST CIRCUIT AND WAVEFORM VCC 7.0V VIN RL VOUT PULSE GENERATOR tw 90% NEGATIVE PULSE VM CL AMP (V) VM 10% D.U.T. RT 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V RL AMP (V) 90% 90% Test Circuit for Open Collector Outputs POSITIVE PULSE VM VM 10% TEST tPLZ tPZL All other SWITCH closed closed open DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 10% tw SWITCH POSITION 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00128 June 15, 1992 10 Philips Semiconductors Product specification 16X5 asynchronous FIFO (3-State) 74F225 DIP20: plastic dual in-line package; 20 leads (300 mil) 1992 Jun 15 11 SOT146-1 Philips Semiconductors Product specification 16X5 asynchronous FIFO (3-State) 74F225 SO20: plastic small outline package; 20 leads; body width 7.5 mm 1992 Jun 15 12 SOT163-1 Philips Semiconductors Product specification 16X5 asynchronous FIFO (3-State) 74F225 NOTES 1992 Jun 15 13 Philips Semiconductors Product specification 16X5 asynchronous FIFO (3-State) 74F225 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 14 Date of release: 10-98 9397-750-05099