74LVT125 3.3 V quad buffer; 3-state Rev. 05 — 10 February 2005 Product data sheet 1. General description The LVT125 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device combines low static and dynamic power dissipation with high speed and high output drive. The 74LVT125 device is a quad buffer that is ideal for driving bus lines. The device features four output enable inputs (1OE, 2OE, 3OE and 4OE), each controlling one of the 3-state outputs. 2. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Quad bus interface 3-state buffers Output capability: +64 mA and −32 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted No bus current loading when output is tied to 5 V bus Power-up 3-state Latch-up protection: ◆ JESD78: exceeds 500 mA ESD protection: ◆ MIL STD 883 method 3015: exceeds 2000 V ◆ Machine model: exceeds 200 V 3. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit tPLH propagation delay nA to nY CL = 50 pF; VCC = 3.3 V - 2.7 - ns tPHL propagation delay nA to nY CL = 50 pF; VCC = 3.3 V - 2.9 - ns CI input capacitance VI = 0 V or 3.0 V - 4 - pF CO output capacitance outputs disabled; VO = 0 V or 3.0 V - 8 - pF ICC quiescent supply current outputs disabled; VCC = 3.6 V - 0.13 - mA 74LVT125 Philips Semiconductors 3.3 V quad buffer; 3-state 4. Ordering information Table 2: Ordering information Type number Package Temperature range Name Description Version 74LVT125D −40 °C to +85 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74LVT125DB −40 °C to +85 °C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74LVT125PW −40 °C to +85 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74LVT125BQ −40 °C to +85 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin SOT762-1 quad flat package; no leads; 14 leads terminals; body 2.5 × 3 × 0.85 mm 5. Functional diagram 2 1A 1 1OE 5 2A 4 2OE 9 3A 1Y 3 2 1 2Y 6 1 3 EN1 5 6 4 3Y 8 9 8 10 10 3OE 12 4A 12 4Y 11 11 13 13 4OE mna229 mna228 Fig 1. Logic symbol Fig 2. IEC logic symbol nA nY nOE mna227 Fig 3. Logic diagram 9397 750 14703 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 05 — 10 February 2005 2 of 15 74LVT125 Philips Semiconductors 3.3 V quad buffer; 3-state 6. Pinning information 1 terminal 1 index area 2 13 4OE 2 1Y 3 2OE 4 125 2A 5 GND(1) 2Y 6 12 4A 1Y 3 2OE 4 2A 5 2Y 6 9 3A GND 7 8 3Y 125 11 4Y 13 4OE 12 4A 11 4Y 10 3OE 9 8 1A 1A 3Y 14 VCC 7 1 GND 1OE 14 VCC 1OE 6.1 Pinning 3A 10 3OE 001aac477 Transparent top view (1) The die substrate is attached to the exposed die pad using conductive die attach material. It can not be used as a supply pin or input. 001aac476 Fig 4. Pin configuration SO14, SSOP14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 6.2 Pin description Table 3: Pin description Symbol Pin Description 1OE 1 1 output enable input (active LOW) 1A 2 1 data input 1Y 3 1 data output 2OE 4 2 output enable input (active LOW) 2A 5 2 data input 2Y 6 2 data output GND 7 ground (0 V) 3Y 8 3 data output 3A 9 3 data input 3OE 10 3 output enable input (active LOW) 4Y 11 4 data output 4A 12 4 data input 4OE 13 4 output enable input (active LOW) VCC 14 supply voltage 9397 750 14703 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 05 — 10 February 2005 3 of 15 74LVT125 Philips Semiconductors 3.3 V quad buffer; 3-state 7. Functional description 7.1 Function table Table 4: Function table [1] Input Output nOE nA nY L L L L H H H X Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC Conditions Max Unit −0.5 +4.6 V [1] −0.5 +7.0 V [1] −0.5 +7.0 V supply voltage VI input voltage VO output voltage output in OFF-state or HIGH-state IIK input diode current VI < 0 V - −50 mA IOK output diode current VO < 0 V - −50 mA IO output current output in LOW-state - 128 mA output in HIGH-state - −64 mA −65 +150 °C - 150 °C Tstg Tj storage temperature junction temperature [2] [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. 9397 750 14703 Product data sheet Min © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 05 — 10 February 2005 4 of 15 74LVT125 Philips Semiconductors 3.3 V quad buffer; 3-state 9. Recommended operating conditions Table 6: Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage 2.7 - 3.6 V VI input voltage 0 - 5.5 V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V IOH HIGH-level output current - - −32 mA IOL LOW-level output current none - - 32 mA current duty cycle ≤ 50 %; f ≥ 1 kHz - - 64 mA 0 - 10 ns/V −40 - +85 °C ∆t/∆V input transition rise or fall rate Tamb ambient temperature in free air 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 Conditions Min Typ Max −0.9 −1.2 Unit °C [1] VIK input diode voltage IIK = −18 mA; VCC = 2.7 V - VOH HIGH-level output voltage IOH = −100 µA; VCC = 2.7 V to 3.6 V; VCC − 0.2 VCC − 0.1 - V IOH = −8 mA; VCC = 2.7 V 2.4 2.5 - V IOH = −32 mA; VCC = 3.0 V 2.0 2.2 - V IOL = 100 µA - 0.1 0.2 V IOL = 24 mA - 0.3 0.5 V IOL = 16 mA - 0.25 0.4 V IOL = 32 mA - 0.3 0.5 V IOL = 64 mA - 0.4 0.55 V - 1 10 µA - ±0.1 ±1 µA - 0.1 1 µA VOL LOW-level output voltage V VCC = 2.7 V VCC = 3.0 V ILI input leakage current all input pins VCC = 0 V or 3.6 V; VI = 5.5 V control pins VCC = 3.6 V; VCC or GND data pins VCC = 3.6 V; VI = VCC [2] VCC = 3.6 V; VI = 0 V [2] - −1 −5 µA - 1 ±100 µA 75 150 - µA VCC = 3 V; VI = 2.0 V −75 −150 - µA VCC = 0 V to 3.6 V; VI = 3.6 V ±500 - - µA IOFF power-down output current VCC = 0 V; VI or VO = 0 V to 4.5 V IHOLD bus hold current nA input VCC = 3 V; VI = 0.8 V 9397 750 14703 Product data sheet [3] © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 05 — 10 February 2005 5 of 15 74LVT125 Philips Semiconductors 3.3 V quad buffer; 3-state Table 7: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit IEX external current into output output in HIGH-state when VO > VCC; VO = 5.5 V and VCC = 3.0 V - 60 125 µA IPU, IPD power-up or power-down 3-state output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; nOE = don’t care - ±1 ±100 µA IOZ 3-state output current VCC = 3.6 V; VI = VIH or VIL output HIGH: VO = 3.0 V - 1 5 µA output LOW: VO = 0.5 V - −1 −5 µA - 0.13 0.19 mA quiescent supply current ICC [4] VCC = 3.6 V; VI = GND or VCC; IO = 0 A outputs HIGH outputs LOW outputs disabled - 2 7 mA [5] - 0.13 0.19 mA [6] - 0.1 0.2 mA ∆ICC additional supply current per input pin VCC = 3 V to 3.6 V; one input at VCC − 0.6 V and other inputs at VCC or GND; CI input capacitance VI = 0 V or 3.0 V - 4 - pF CO output capacitance outputs disabled; VO = 0 V or 3.0 V - 8 - pF [1] Typical values are measured at VCC = 3.3 V and Tamb = 25 °C. [2] Unused pins at VCC or GND. [3] This is the bus hold overdrive current required to force the input to the opposite logic state. [4] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only. [5] ICC is measured with outputs pulled to VCC or GND. [6] This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 11. Dynamic characteristics Table 8: Dynamic characteristics GND = 0 V; tr = tf = 2.5 ns; CL = 50 pF; RL = 500 Ω; for test circuit see Figure 8. Symbol Parameter Tamb = −40 °C to +85 tPLH tPHL tPZH tPZL Conditions Min Typ Max Unit °C [1] propagation delay nA to nY propagation delay nA to nY output enable time nOE to nY output enable time nOE to nY VCC = 2.7 V - - 4.5 ns VCC = 3.3 V ± 0.3 V 1.0 2.7 4.0 ns VCC = 2.7 V - - 4.9 ns VCC = 3.3 V ± 0.3 V 1.0 2.9 3.9 ns VCC = 2.7 V - - 6.0 ns VCC = 3.3 V ± 0.3 V 1.0 3.4 4.7 ns VCC = 2.7 V - - 6.5 ns VCC = 3.3 V ± 0.3 V 1.1 3.4 4.7 ns 9397 750 14703 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 05 — 10 February 2005 6 of 15 74LVT125 Philips Semiconductors 3.3 V quad buffer; 3-state Table 8: Dynamic characteristics …continued GND = 0 V; tr = tf = 2.5 ns; CL = 50 pF; RL = 500 Ω; for test circuit see Figure 8. Symbol Parameter Conditions Min Typ Max Unit tPHZ VCC = 2.7 V - - 5.7 ns VCC = 3.3 V ± 0.3 V 1.8 3.7 5.1 ns VCC = 2.7 V - - 4.0 ns VCC = 3.3 V ± 0.3 V 1.3 2.6 4.5 ns output disable time nOE to nY output disable time nOE to nY tPLZ [1] Typical values are at VCC = 3.3 V and Tamb = 25 °C. 12. Waveforms VI nA input VM VM GND tPLH tPHL VOH VM nY output VM VOL mnb072 VM = 1.5 V. VOL and VOH are typical voltage output drop that occur with the output load. Fig 6. Propagation delay input (nA) to output (nY) VI nOE input VM GND tPZL tPLZ VCC VM nY output VOL + 0.3 V VOL t PZH t PHZ VOH nY output VM VOH − 0.3 V 0V 001aac475 VM = 1.5 V. VOL and VOH are typical voltage output drop that occur with the output load. Fig 7. Enable and disable times of 3-state outputs 9397 750 14703 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 05 — 10 February 2005 7 of 15 74LVT125 Philips Semiconductors 3.3 V quad buffer; 3-state VI tW 90 % negative pulse 90 % VM 0V VI tTHL(tf) tTLH(tr) tTLH(tr) tTHL(tf) 90 % positive pulse 0V VM 10 % VM VM 10 % 10 % tW 001aac221 VM = 1.5 V. a. Input pulse definition VEXT VCC PULSE GENERATOR VI RL VO D.U.T. CL RT RL mna616 Test data is given in Table 9. Definitions test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. b. Test circuit Fig 8. Load circuitry for switching times Table 9: Test data Input Load VI fi tW 2.7 V ≤ 10 MHz 500 ns tr, tf CL RL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL ≤ 2.5 ns 50 pF 500 Ω GND 9397 750 14703 Product data sheet VEXT 6V open © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 05 — 10 February 2005 8 of 15 74LVT125 Philips Semiconductors 3.3 V quad buffer; 3-state 13. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. Package outline SO14 (SOT108-1) 9397 750 14703 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 05 — 10 February 2005 9 of 15 74LVT125 Philips Semiconductors 3.3 V quad buffer; 3-state SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC JEITA MO-150 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SSOP14 (SOT337-1) 9397 750 14703 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 05 — 10 February 2005 10 of 15 74LVT125 Philips Semiconductors 3.3 V quad buffer; 3-state TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 11. Package outline TSSOP14 (SOT402-1) 9397 750 14703 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 05 — 10 February 2005 11 of 15 74LVT125 Philips Semiconductors 3.3 V quad buffer; 3-state DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 12. Package outline DHVQFN14 (SOT762-1) 9397 750 14703 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 05 — 10 February 2005 12 of 15 74LVT125 Philips Semiconductors 3.3 V quad buffer; 3-state 14. Revision history Table 10: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes 74LVT125_5 20050210 Product data sheet - 9397 750 14703 74LVT125_4 • Modifications: Table 2: Corrected type number 74LVT125_4 20050207 Product data sheet - 9397 750 14552 74LVT125_3 74LVT125_3 20040624 Product data sheet - 9397 750 13535 74LVT125_2 74LVT125_2 19980219 Product specification - 9397 750 03514 74LVT125_1 74LVT125_1 - - - - - 9397 750 14703 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 05 — 10 February 2005 13 of 15 74LVT125 Philips Semiconductors 3.3 V quad buffer; 3-state 15. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. Definitions 17. Disclaimers Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 18. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 9397 750 14703 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 05 — 10 February 2005 14 of 15 74LVT125 Philips Semiconductors 3.3 V quad buffer; 3-state 19. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information . . . . . . . . . . . . . . . . . . . . 14 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 10 February 2005 Document number: 9397 750 14703 Published in The Netherlands