PHILIPS SAA2510

INTEGRATED CIRCUITS
DATA SHEET
SAA2510
Video CD (VCD) decoder
Preliminary specification
File under Integrated Circuits, IC02
1996 May 21
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
FEATURES
(With standard microcode loaded)
• Decoding and display of MPEG1 video streams
(constrained parameters)
• Decoding of MPEG audio streams (layer II)
• Decoding, storage (compressed) and display of
high-resolution still pictures of 704 × 576 pixels
• EBU audio output, fully transparent from input to output
in CD-DA mode and generated in MPEG mode
• Requires only 4 Mbits of external 70 ns DRAM
• Downloadable microcode for internal controllers
• Audio transparency mode for CD-DA discs
• Internal video timing generator
• On-screen display capability
• Requires 40 MHz crystal for system clock generation
• Play options:
• Requires 27 MHz crystal or external 27 MHz source for
video timing generation
– Play
– Stop
– Pause/continue
• Requires 16.9344 MHz (384 × 44.1 kHz) clock locked to
CD drive
– Slow-motion forward
• Internal generation of 90 kHz MPEG clock
– Scan forward
• Capability of sharing external DRAM by 3-stating all
DRAM pins.
– Scan backward.
• Supports auto-pause feature
• Disc interface: Philips I2S, EIAJ, MEC formats and
IEC 958 (EBU) interface
APPLICATION
• Dedicated video CD players.
• Separate error flag input (EFIN) and data valid input
(NDAV)
GENERAL DESCRIPTION
• Performs basic block decoder functions:
MPEG1 audio and video CD (VCD) decoder, intended for
use in low-cost dedicated video CD players. When used
with a 4 Mbit DRAM and a digital video encoder, the
decoder adds the required functionality to a CD decoder to
implement a low-cost video CD player capable of playing
discs coded to version 2.0 of the video CD specification.
The SAA2510 is an I2C-bus controlled chip and features
serial data input in four common bus formats. It provides
digital video output in CCIR601 and 656 formats.
– serial-to-parallel conversion
– sync detection
– descrambling
– EDC calculation
– error-correction for mode 2 form 1 sectors
– header and sub-header interpretation.
• I2C-bus interface
• Video output YUV 4 : 2 : 2 format. DMSD bus
compatible
A bit-mapped on-screen display is provided and output
video timing can be 525 lines/30 frames per second or
625 lines/25 frames per second. The chip is microcode
programmable for feature enhancement.
• Also supports CCIR656 video interface, including line
and field timing codes
• Audio output: 44.1 kHz. 16, 18 or 20 bits per audio
sample in Philips I2S, Sony or MEC formats
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA2510
1996 May 21
QFP100
DESCRIPTION
plastic quad flat package; 100 leads (lead length 1.95 mm);
body 14 × 20 × 2.7 mm; high stand-off height
2
VERSION
SOT317-1
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VDD3
supply voltage
3.0
3.3
3.6
V
VDD5
supply voltage
4.5
5.0
5.5
V
IDD
supply current
−
tbf
−
mA
fxtal s
system clock crystal frequency
−
40.0
−
MHz
fxtal v
video clock crystal frequency
−
27.0
−
MHz
fi
audio clock input frequency
−
16.9344
−
MHz
Tamb
operating ambient temperature
−20
−
+70
°C
1996 May 21
3
Sys_osc_0
76
74
RESET
CAS
RAS A0 to A8
VIDEO
BUFFER
1
VIDEO
BUFFER
0
W
VIDEO
BUFFER
2
CDIR
DR0 to DR15
27
79
84
MEMORY MANAGEMENT UNIT
SYSTEM CLOCK
86
82
VIDEO
CLOCK
80
EBUIN
AUDIOCLK
WSIN
CLIN
BLOCK
DECODER
VIDEO DECODER
4
EFIN
DAIN
SYSTEM
CONTROLLER
NDAV
SDA
SCL
INT
DATA
SORTER
IDCT
HOST
I2C
INTERFACE
FRAME
RECONSTRUCTOR
VIDEO
GENERATOR
8
7 to 1
100
8
95 to 88
99
97
11
9
Vid_osc_0
Vid_osc_1
Philips Semiconductors
Sys_osc_1
VIDEO
FIFO
Video CD (VCD) decoder
3k
AUDIO
FIFO
BLOCK DIAGRAM
andbook, full pagewidth
1996 May 21
PLAY
CONTROL
BUFFER
7k
OSD
BUFFER
EXTERNAL
4 Mbit DRAM
CLK27
CREF
UV0 to UV7
Y0 to Y7
VSYNC
HREF
TLSAND
CSYNC
ASEL
12
SAA2510
13
AUDIO DECODER
14
TEST CONTROL
78
DAOUT
CLOUT
WSOUT
28
MGE325
TP1
TP2
DRAMON
SAA2510
Fig.1 Block diagram.
Preliminary specification
77
16
EBUOUT
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
PINNING
SYMBOL
UV6
PIN
1
DESCRIPTION
video UV bus output bit 6;
16-bit video output mode: the UV bus outputs alternating U and V chroma samples
at 13.5 Mbytes/s
CCIR656 mode: this bus is not used (inactive)
UV5
2
video UV bus bit 5
UV4
3
video UV bus bit 4
UV3
4
video UV bus bit 3
UV2
5
video UV bus bit 2
UV1
6
video UV bus bit 1
UV0
7
video UV bus bit 0
VDD5
8
5 V external pad power supply
CSYNC
9
composite sync output; 525 lines/60 Hz or 625 lines/50 Hz
VSS5
10
0 V external pad power supply
TLSAND
11
two-level Sandcastle (composite blanking) output; requires external resistor network
to define horizontal/vertical blanking level
EBUOUT
12
IEC 958 digital audio output
DAOUT
13
I2S data; digital audio output
WSOUT
14
I2S word select digital audio output
VDD3
15
+3 V internal power supply
CLOUT
16
I2S bit clock output
VSS
17
0 V internal power supply
AUDIOCLK
18
16.9 MHz audio clock input
VDD5
19
5 V internal power supply
EBUIN
20
EBU (IEC 958) input
CLIN
21
I2S bit clock input
WSIN
22
I2S word select input
DAIN
23
I2S digital data input
VDD3
24
+3 V internal power supply
EFIN
25
error flag input from I2S source
VSS
26
0 V internal power supply
RESET
27
active low reset input
DRAMON
28
DRAM pin 3-state control input; also 3-states video outputs and some timing signals
INT
29
active low open drain interrupt request to host microcontroller
NDAV
30
data not valid input (data on I2S or EBU input not valid)
ASEL
31
I2C-bus address select pin
SDA
32
I2C-bus data pin
VDD5
33
5 V external pad power supply
SCL
34
I2C-bus clock input
VSS5
35
0 V external pad power supply
DR15
36
DRAM data input/output bit 5
1996 May 21
5
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SYMBOL
SAA2510
PIN
DESCRIPTION
DR14
37
DRAM data input/output bit 14
DR13
38
DRAM data input/output bit 13
DR12
39
DRAM data input/output bit 12
DR11
40
DRAM data input/output bit 11
DR10
41
DRAM data input/output bit 10
DR9
42
DRAM data input/output bit 9
VDD5
43
5 V external pad power supply
DR8
44
DRAM data input/output bit 8
VSS5
45
0 V external pad power supply
DR7
46
DRAM data input/output bit 7
DR6
47
DRAM data input/output bit 6
DR5
48
DRAM data input/output bit 5
DR4
49
DRAM data input/output bit 4
DR3
50
DRAM data input/output bit 3
DR2
51
DRAM data input/output bit 2
DR1
52
DRAM data input/output bit 1
DR0
53
DRAM data input/output bit 0
VSS5
54
0 V external pad power supply
CAS
55
DRAM column address strobe
VDD5
56
5 V external pad power supply
A8
57
DRAM row/column address pin A8
A7
58
DRAM row/column address pin A7
A6
59
DRAM row/column address pin A6
A5
60
DRAM row/column address pin A5
A4
61
DRAM row/column address pin A4
VDD3
62
+3 V internal power supply
W
63
active low DRAM write strobe
VSS
64
0 V internal power supply
RAS
65
DRAM row address strobe
VDD5
66
5 V internal power supply
A3
67
DRAM row/column address pin A3
VSS5
68
0 V external pad power supply
A2
69
DRAM row/column address pin A2
VDD5
70
5 V external pad power supply
A1
71
DRAM row/column address pin A1
A0
72
DRAM row/column address pin A0
VDDO3
73
3 V internal power supply for oscillator
Sys_osc_0
74
oscillator input pin; 40 MHz oscillator
VSS
75
0 V internal power supply
Sys_osc_1
76
oscillator output pin; 40 MHz oscillator
TP1
77
factory test pin; connect to ground
1996 May 21
6
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SYMBOL
SAA2510
PIN
DESCRIPTION
TP2
78
factory test pin; connect to ground
CDIR
79
clock direction control pin; when high, CLK27 is an output
CREF
80
clock qualifier output; 13.5 MHz timing signal used in 16-bit video output mode; can
also be used as 13.5 MHz video sample clock
VSS5
81
0 V external pad power supply
CLK27
82
27 MHz clock input or output; direction controlled by CDIR pin
VDD5
83
5 V external pad power supply
Vid_osc_0
84
oscillator pin; 27 MHz; input pin
VSS
85
0 V internal power supply
Vid_osc_1
86
oscillator pin; 27 MHz; output pin
VDDO3
87
3 V internal power supply for oscillator
Y7
88
video Y bus output bit 7
DMSD mode: the Y bus outputs luminance samples at 13.5 Mbytes/s
CCIR656 mode: this pin supplies multiplexed chrominance and luminance
(27 Mbytes/s)
Y6
89
video Y bus bit 6
Y5
90
video Y bus bit 5
Y4
91
video Y bus bit 4
Y3
92
video Y bus bit 3
Y2
93
video Y bus bit 2
Y1
94
video Y bus bit 1
Y0
95
video Y bus bit 0
VSS5
96
0 V external pad power supply
HREF
97
horizontal (line) timing reference signal; high during active video part of line, low
during line blanking
VDD5
98
5 V external pad power supply
VSYNC
99
vertical (field/frame) timing reference signal; high during vertical blanking interval of
field
UV7
100
video UV bus output bit 7
DMSD mode: the UV bus outputs alternating U and V chroma samples at
13.5 Mbytes/s
CCIR656 mode: this bus is not used (inactive)
1996 May 21
7
Philips Semiconductors
Preliminary specification
81 VSS5
UV6
1
80
CREF
UV5
2
79
CDIR
UV4
3
78
TP2
UV3
4
77
TP1
UV2
5
76
Sys_osc_1
UV1
6
75
VSS
UV0
7
74
Sys_osc_0
VDD5
CSYNC
8
73
VDDO3
9
72
A0
VSS5 10
71
A1
TLSAND 11
70
VDD5
EBUOUT 12
69
A2
DAOUT 13
68
VSS5
WSOUT 14
67
A3
66
VDD5
VDD3 15
SAA2510
CLOUT 16
65
RAS
VSS 17
64
VSS
AUDIOCLK 18
63
W
VDD5 19
EBUIN 20
62
VDD3
61
A4
CLIN
21
60
A5
WSIN
22
59
A6
51
DR2
8
DR3 50
30
DR4 49
DR1
NDAV
DR5 48
DR0
52
DR6 47
53
29
DR7 46
28
INT
VSS5 45
DRAMON
DR8 44
VSS5
VDD5 43
54
DR9 42
27
DR10 41
CAS
RESET
DR11 40
55
DR12 39
26
DR13 38
VDD5
VSS
DR14 37
56
DR15 36
25
VSS5 35
A8
EFIN
SCL 34
A7
57
VDD5 33
58
24
SDA 32
23
ASEL 31
DAIN
VDD3
Fig.2 Pin configuration.
1996 May 21
83 VDD5
82 CLK27
87 VDDO3
88 Y7
89 Y6
90 Y5
91 Y4
92 Y3
93 Y2
94 Y1
95 Y0
96 VSS5
97 HREF
98 VDD5
99 VSYNC
100 UV7
handbook, full pagewidth
85 VSS
84 Vid_osc_0
SAA2510
86 Vid_osc_1
Video CD (VCD) decoder
MGE324
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
The OSD is implemented as 48 vertical ‘slices’ of 8 pixels
(horizontally) and 32 (vertically). Each pixel is stored as
2 bits. This gives three programmable logical colours, plus
a transparent option. Each slice is identified by a slice code
(slice number).
FUNCTIONAL DESCRIPTION
Block decoder
The VCD chip receives MPEG A/V or CD digital audio data
from a CD decoder chipset using any one of four common
interface formats (Philips I2S, EIAJ, MEC or IEC 958). The
Philips I2S, EIAJ and Matsushita input modes use the bit
clock (CLIN), word select (WSIN), data (DAIN) and error
flag (EFIN) inputs. If IEC 958 (EBU) input mode is
selected, only the EBUIN pin needs to be connected. The
chip also requires a 16.9 MHz clock input (CLIN) which is
synchronous with the data input from the CD decoder
providing the serial data input.
The horizontal position of a slice is defined by its position
in a slice code sequence written to the VCD chip. This
arrangement reduces the need to completely update the
OSD bit map in many situations. It may be possible to
simply reorder the slices, e.g. if a track time display is
being updated and slices are prepared to represent digits.
At any time, up to 44 of the 48 slices can be displayed.
Video decoder
The VCD chip contains a block decoder and descrambler
which performs error correction on the Video CD data track
(form 1) sectors and error detection on real-time audio and
video tracks where an error correction code is present.
Video output data can be presented in one of two modes:
1. 16-bit wide data is output in YUV 4 : 2 : 2 format as
8 bits of luminance and 8 bits of alternating U and
V chrominance. The video output data rate in this
mode is 13.5 Mwords/s.
In most events, audio output can be in any of the three
(I2S, EIAJ or MEC) formats, independent of input type.
When playing CD digital audio discs, the input is copied to
the outputs.
2. 8-bit wide, CCIR656-like, data is output providing
4 : 2 : 2 format video as an 8-bit UYVY multiplex at
27 Mbytes/s.
The block decoder supports some special functions which
enable recovery of play control lists. The desired sectors
can be acquired by programming a sector address via the
I2C-bus microcontroller interface. The microcontroller then
instructs the CD servo/decoder subsystem to execute a
servo jump to the required disc location and then waits for
an interrupt indicating that the desired sector information
has been received and error-corrected.
In either case, the VCD chip can be programmed to output
525 line or 625 line format timing to match the type of
display (TV) connected to its output. Additional
programmability is provided to cope with the Video CD disc
source picture coding type (525/625 lines).
The VCD chip performs vertical and horizontal
interpolation to convert the MPEG SIF (352 pixels per line)
normal resolution pictures to CCIR601 resolution.
Vertically interpolated pixels are output on the odd fields
during display of normal resolution pictures.
System controller
Overall control of the chip and a number of its less
time-critical functions is carried out by a dedicated
RISC processor. The microcode for this processor is
executed from an on-chip RAM. This microcode must be
loaded into RAM after power-up by the host
microcontroller, using the I2C-bus interface. This enables
the functionality of the chip to be customized for specific
applications.
The Video CD disc being played may have been coded
with 525 lines/60 Hz or 625 lines/50 Hz pictures. When the
Video CD player is connected to a display with a different
timebase to the coded disc material, some adjustments
must be made to allow for the different number of lines on
the display and the reconstructed picture. Two examples
are shown in Figs. 3 and 4.
On-screen display
The VCD chip can be programmed to position the
reconstructed picture with respect to horizontal and
vertical syncs anywhere on the display screen with a
programmable ‘viewport’ position. Figure 3 shows an
MPEG SIF resolution picture (352 pixels by 288 lines)
being displayed on an NTSC display having only
240 active display lines per field. In this event, the top and
bottom 24 lines are not displayed.
The VCD chip provides a bit-mapped On-Screen-Display
(OSD), containing 32 display lines of 352 pixels per line.
There is a double-height mode which repeats OSD lines so
that the maximum height of OSD objects becomes
64 lines. This character-set-independent OSD permits
display of ideographic characters and simple graphic
displays anywhere on the screen.
1996 May 21
9
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
The second example, illustrated in Fig.4, is where a
240 active lines per field NTSC picture needs to be
displayed on a 288 line PAL format display. The ‘missing’
lines can be filled with a programmable border colour.
In this event, the horizontal and vertical resolution of the
reconstructed picture is double that of normal resolution
(moving) pictures. In order to fit the picture in the available
frame buffer DRAM, a data compression scheme is
applied to the stored picture.
High-resolution still pictures can be present on a Video CD
disc.
handbook, halfpage
24
reconstructed picture
352
not displayed
reconstructed picture
window
24
handbook, halfpage
border = blank
viewport
240 288
not displayed
MGE333
One field of a 625-line picture on a 525-line
display.
1996 May 21
240 288
border = blank
MGE332
Fig.3
display window
352
Fig.4 525-line picture on a 625-line display.
10
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
to read data stored in three play-control sector buffers,
which normally will be used to store Video CD data track
information. This interface features a two or three byte
sub-addressing scheme allowing access to any DRAM
location. However, in normal use, only two byte
sub-addressing is needed.
‘Trickmode’ implementation
Compared with CD digital audio players, it is likely that
Video CD players will need to offer additional functionality
similar to VCRs. These features are commonly called
‘trickmodes’. Typically, the player will offer features such
as still picture (freeze frame), scan forwards and
backwards as well as slow motion replay.
An interrupt pin is available to signal a number of events
so that the controlling processor does not need to poll VCD
status registers.
These features require a combination of CD servo control
and Video CD decoder functions for effective
implementation. The VCD chip provides high level
command features to support these modes in order to
minimize microcontroller time-critical software.
Input pin NDAV is used to signal that data on the block
decoder input is not valid, e.g. during CD servo jumps.
A complete memory map and list of registers will be
included in a later version of this data sheet.
STILL PICTURE DISPLAY
I2C-bus slave address selection
This is implemented directly using a Pause command,
causing the VCD chip to hold the displayed picture at the
next frame update.
A6
0
A5
A4
0
SCAN FORWARD AND SCAN BACKWARDS
Note
There is no difference as far as the VCD chip is concerned.
The controlling microcomputer must command the CD
servo to execute a servo jump and re-synchronize. The
VCD chip is then commanded to display the next I
(Intra-coded) picture following re-acquisition of sector
sync.
1. ASEL.
1
A3
1
A2
0
A1
A0
1
A0(1)
R/W
The data transfer protocol is as follows:
Two and three byte sub-addressing: first the device
sub-address is transmitted, preceded by a START
condition and the slave address:
SLOW-MOTION REPLAY
Two and three byte sub-addressing
A command is provided by the VCD chip, allowing a
slow-motion ‘factor’ in the range 2 to 8 to be selected. This
is the factor by which replay will be slowed down. Because
the rate of decoding of video sectors has been reduced,
the video FIFO fills up. The block decoder is designed to
automatically disable acquisition when the video FIFO fills
in this way and an interrupt is generated. At this point, the
next wanted sector (address) has been loaded into a
register in the VCD chip. The controlling microcomputer
then commands a CD servo jump to position on the disc
just before the next desired sector, making allowance for
re-synchronization by the servo and VCD chip.
S
W
SUB_A
S = START
SLA = Slave address
W = Write
SUB_A = Sub-address
The sub-address can be either 2 or 3 bytes. The 3-byte
sub-address is used for DRAM random access. This is not
used for normal operation. It exists only as a test mode.
Since the Video CD IC is internally fully word (16 bits)
oriented, the sub-address must always be an even
address. If an odd-numbered address is given, the Video
CD IC will not acknowledge this byte. For the sub-address,
the least significant byte is sent first. The second
sub-address byte contains 2 control bits.
I2C-bus interface
The VCD chip is programmed via the I2C-bus interface.
The chip is a slave transceiver capable of operating at the
maximum specified bus clock frequency of 400 kHz. It
does not support the general call feature. One of two slave
addresses can be used. The address is selected by the
ASEL input pin.
This bus provides access to the internal registers of the
device. The bus is also used to write OSD slice data and
1996 May 21
SLA
11
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
Sub-address byte format
MSB
A7
A6
A5
A4
A3
A2
A1
LSB
MSB
A0
C1
When A0 is a ‘1’, the address byte is not acknowledged
(odd address).
A11
A10
A9
A8
P: STOP condition generated by bus master
A: Acknowledge bit generated by master or slave
according to transaction type and stage
N: Negative acknowledge; acknowledge bit is not set by
bus master during last byte of a read
3-byte sub-address - most significant byte format
MSB
LSB
A18
A12
S: START condition generated by bus master
C0 = 1; 3-byte sub-address. The next byte transmitted is
also an address byte:
0
A13
The following notation is used to describe bus
transactions:
C0 = 0; 2-byte sub-address.
0
C0
I2C-bus transaction summary
Explanation of control bits
0
LSB
A17
A16
A15
SLA: 7-bit slave address generated by bus master
A14
W: R/W bit after slave address is set to write
R: R/W bit after slave address is set to read
C1 = 0; sub-address post increment enabled. After each
transfer of 2 bytes, the address is automatically
incremented by 2.
SUB_N: Sub-address byte N (N = 0, 1 or 2); least
significant address byte is SUB_0
D(M): A data byte transmitted by master or slave on the
bus; D(0) is the first byte sent; as all transfers must be
an even number of bytes, it follows that M must be odd.
C1 = 1; sub-address post increment disabled.
The master will terminate a read action by NOT
acknowledging the last read byte followed by a STOP
condition.
Set 2-byte sub-address and write (M + 1) bytes
S
SLA
W
A
SUB_0
A
SUB_1
A
D(0)
A
D(1)
A to D(M) A
P
Set 2-byte sub-address and read (M + 1) bytes
S
SLA
W
A
SUB_0 A
SUB_1 A
S
SLA
R
D(0)
A
D(1)
A to D(M)
N
P
Set 3-byte sub-address and write (M + 1) bytes
S
SLA
W
A
SUB_0 A
SUB_1 A
SUB_2
A
D(0) A
D(1)
A to D(M)
A
P
Set 3-byte sub-address and read (M + 1) bytes
S SLA
W A
SUB_0 A
SUB_1 A
SUB_2
A
S
SLA
R
A D(0)
A
D(1) A to D(M)
N
P
This addressing mode is valid only if sub-address auto incrementing is disabled. It is intended for fast polling of a status
register.
1996 May 21
12
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
Byte-order within words
LSB
MSB
Word
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
I2C-bus
B7
B6
B5
B4
B3
B2
B1
B0
B15
B14
B13
B12
B11
B10
B9
B8
For each transmitted word (read or written) the least significant byte is transmitted first.
CHARACTERISTICS
Tamb = −20 to +70 °C; VDD5 = 4.5 to 5.5 V; VDD3 = 3.0 to 3.6 V; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD5
supply voltage (5 V) range
4.5
5
5.5
V
IDD5
VDD5 supply current
−
tbf
tbf
mA
VDD3
supply voltage (3 V) range
3
3.3
3.6
V
IDD3
VDD3 supply current
−
tbf
tbf
mA
IDD(tot)
total supply current
−
tbf
tbf
mA
V
Digital inputs
ALL INPUTS (EXCEPT RESET AND OSCILLATOR INPUTS)
VIL
LOW level input voltage
−0.3
−
+0.8
VIH
HIGH level input voltage
2
−
VDD + 0.5 V
ILI
input leakage current
−10
−
+10
µA
Ci
input capacitance
−
−
10
pF
V
Vi = 0 to VDD
RESET INPUT: (SCHMITT INPUT)
VIL
LOW level input voltage
−0.3
+2
VIH
HIGH level input voltage
3.5
VDD + 0.5 V
ILI
input leakage current
−10
+10
µA
Vhys
hysteresis voltage
(VIH − VIL)
Vi = 0 to VDD
1
−
−
V
V
Inputs/outputs
SDA AND SCL (I2C-BUS DATA AND CLOCK)
VIL
LOW level input voltage
−0.5
−
+1.5
VIH
HIGH level input voltage
3
−
VDD + 0.5 V
ILI
input leakage current
−10
−
+10
µA
Vi = 0 to VDD
Ci
input capacitance
−
−
10
pF
CL
load capacitance
−
−
400
pF
VOL
LOW level output voltage
(IOL = 3.0 mA)
0
−
0.4
V
VOL
LOW level output voltage
(IOL = 6.0 mA)
0
−
0.6
V
V
CLK27
VIL
LOW level input voltage
−0.3
−
+0.8
VIH
HIGH level input voltage
2.4
−
VDD + 0.5 V
1996 May 21
13
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SYMBOL
PARAMETER
ILI
input leakage current
SAA2510
CONDITIONS
Vi = 0 to VDD
MIN.
−10
TYP.
MAX.
UNIT
−
+10
µA
Ci
input capacitance
−
−
10
pF
VOL
LOW level output voltage
(IOL = 1.6 mA)
0
−
0.4
V
VOH
HIGH level output voltage
(IOH = −0.2 mA)
2.6
−
VDD
V
tr
input rise time
0.6 to 2.6 V
−
−
4
ns
tf
input fall time
0.6 to 2.6 V
−
−
4
ns
V
DR15 TO DR0 (DRAM DATA I/O)
VIL
LOW level input voltage
−0.3
−
+0.8
VIH
HIGH level input voltage
2
−
VDD + 0.5 V
ILI
input leakage current
−10
−
+10
µA
Vi = 0 to VDD
Ci
input capacitance
−
−
10
pF
CL
load capacitance
−
−
30
pF
VOL
LOW level output voltage
(IOL = 1.6 mA)
0
−
0.4
V
VOH
HIGH level output voltage
(IOH = −0.2 mA)
2.4
−
VDD
V
tr
output rise time
0.6 to 2.6 V; load = CL
3
−
10
ns
tf
output fall time
0.6 to 2.6 V; load = CL
3
−
10
ns
−
0.4
V
Outputs
RAS, CAS, W, A0 TO A8 (DRAM CONTROL AND ADDRESS LINES)
VOL
LOW level output voltage
(IOL = 1.6 mA)
0
VOH
HIGH level output voltage
(IOH = −0.2 mA)
2.4
CL
load capacitance
tr
output rise time
0.6 to 2.2 V; load = CL
tf
output fall time
−
VDD
V
−
30
pF
3
−
10
ns
0.6 to 2.2 V; load = CL
3
−
10
ns
0
−
0.4
V
Y0 TO Y7 (VIDEO OUTPUT Y BUS)
VOL
LOW level output voltage
(IOL = 1.6 mA)
VOH
HIGH level output voltage
(IOH = −0.2 mA)
CL
load capacitance
tr
output rise time
tf
output fall time
2.4
−
VDD
V
−
−
30
pF
0.6 to 2.6 V; load = CL
−
−
4
ns
0.6 to 2.6 V; load = CL
−
−
4
ns
UV0 TO UV7 (VIDEO OUTPUT UV BUS)
VOL
LOW level output voltage
(IOL = 1.6 mA)
0
−
0.4
V
VOH
HIGH level output voltage
(IOH = -0.2 mA)
2.4
−
VDD
V
CL
load capacitance
−
−
30
pF
tr
output rise time
0.6 to 2.2 V; load = CL
−
−
10
ns
tf
output fall time
0.6 to 2.2 V; load = CL
3
−
10
ns
INT (OPEN DRAIN; INTERRUPT)
VOL
LOW level output voltage
CL
load capacitance
tr
output rise time
1996 May 21
(IOL = 1.6 mA)
0.6 to 2.2 V; load = CL
14
0
−
0.4
V
−
−
30
pF
−
−
10
ns
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SYMBOL
tf
PARAMETER
output fall time
SAA2510
CONDITIONS
MIN.
TYP.
MAX.
UNIT
0.6 to 2.2 V; load = CL
−
−
10
ns
EBUOUT (IEC 958 OUT)
VOL
LOW level output voltage
(IOL = 10 mA)
0
−
1
V
VOH
HIGH level output voltage
(IOH = −10 mA)
VDD5−1
−
VDD
V
CL
load capacitance
−
−
50
pF
tr
output rise time
0.8 V to (VDD5 − 0.8 V);
load = CL
−
−
10
ns
tr
output fall time
0.8 V to (VDD5 − 0.8 V);
load = CL
−
−
10
ns
VOL
LOW level output voltage
(IOL = 1.6 mA)
0
−
0.4
V
VOH
HIGH level output voltage
(IOH = −0.2 mA)
CL
load capacitance
tr
output rise time
tf
output fall time
ALL OTHER INPUTS
2.4
−
VDD
V
−
−
50
pF
0.6 to 2.6 V; load = CL
−
−
30
ns
0.6 to 2.6 V; load = CL
−
−
30
ns
I2S input/output timing; (Fig.5)
INPUT TIMING
fclk
input clock frequency
−
2.118
−
MHz
tclkH
input clock HIGH period
166
−
−
ns
tclkL
input clock LOW period
166
−
−
ns
tsu
set-up time (DAIN, EFIN,
WSIN)
95
−
−
ns
th1
hold time DAIN, EFIN,
WSIN)
0
−
−
ns
fclk
output clock frequency
−
2.118
−
MHz
tclkH
output clock HIGH period
166
−
−
ns
th2
hold time (DAOUT,
WSOUT)
195
−
−
ns
td
output delay time (DAOUT,
WSOUT)
−
−
147
ns
OUTPUT TIMING
I2C-bus input/output timing (Fig.6)
100 kHz CLOCK FREQUENCY
fclk
clock frequency
0
−
100
kHz
tLOW
clock LOW period
4.7
−
−
µs
tHIGH
period
4
−
−
µs
tSU;DAT
data set-up time
250
−
−
ns
tHD;DAT
data hold time
0
−
−
ns
tSU;STO
set-up time clock HIGH to
STOP
4.7
−
−
µs
1996 May 21
15
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SYMBOL
PARAMETER
SAA2510
CONDITIONS
MIN.
TYP.
MAX.
UNIT
tBUF
set-up time STOP to
START
4.7
−
−
µs
tHD;STA
START hold time
4
−
−
µs
tSU;STA
set-up time clock rising
edge to START
4.7
−
−
µs
tr
rise time (SDA and SCL)
VILmin to VIHmax
50
−
1000
ns
tf
fall time (SDA and SCL)
VILmin to VIHmax
50
−
300
ns
400 kHz CLOCK FREQUENCY
fclk
clock frequency
0
−
400
kHz
tLOW
clock LOW period
1.3
−
−
µs
tHIGH
period
0.6
−
−
µs
tSU;DAT
data set-up time
100
−
−
ns
tHD;DAT
data hold time
0
−
−
ns
tSU;STO
set-up time clock HIGH to
STOP
0.6
−
−
µs
tBUF
set-up time STOP to
START
1.3
−
−
µs
tHD;STA
START hold time
0.6
−
−
µs
tSU;STA
set-up time clock rising
edge to START
0.6
−
−
µs
tr
rise time (SDA and SCL)
VILmin to VIHmax
50
−
300
ns
tf
fall time (SDA and SCL)
VILmin to VIHmax
50
−
300
ns
Video Output Timing (Figs. 7 and 8)
16-BIT VIDEO OUTPUT MODE
tsu
set-up time (CREF, HREF,
UV and Y valid to CLK27)
10
−
−
ns
th2
hold time (CLK27 to CREF,
HREF, UV and Y invalid)
3
−
−
ns
tsu
set-up time (UV and Y
valid to CREF rising edge)
6
−
−
ns
th1
hold time (CREF rising
edge to UV and Y invalid)
10
−
−
ns
8-BIT VIDEO OUTPUT MODE
tsu
set-up time (HREF and Y
valid to CLK27)
7
−
−
ns
th2
hold time (CLK27 to HREF
and Y invalid)
5
−
−
ns
DRAM Timing (Fig.9)
tCYC
cycle time
130
−
−
ns
tRP
RAS pre-charge time
50
−
−
ns
tCSH
CAS hold time
70
−
−
ns
tRCD
RAS to CAS delay time
20
−
−
ns
1996 May 21
16
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SYMBOL
PARAMETER
SAA2510
CONDITIONS
MIN.
TYP.
MAX.
UNIT
20
−
−
ns
page mode cycle time
50
−
−
ns
CAS pre-charge time
10
−
−
ns
tRSH
RAS hold time after CAS
20
−
−
ns
tCRP
CAS to RAS pre-charge
time
15
−
−
ns
tASR
row address set-up time
0
−
−
ns
tRAH
row address hold time
10
−
−
ns
tASC
column address set-up
time
0
−
−
ns
tCAH
column address hold time
15
−
−
ns
tRCS
read command set-up time
0
−
−
ns
tRCH
read command hold time
(CAS)
0
−
−
ns
tRRH
read command hold time
(RAN)
0
−
−
ns
tWCS
write command set-up
time
0
−
−
ns
tCAS
CAS pulse width LOW
tPC
tCP
tWCH
write command hold time
15
−
−
ns
tDS
data-in set-up time
0
−
−
ns
tDH
data-in hold time
15
−
−
ns
tCAC
read access time (CAS)
−
−
20
ns
tRAC
read access time (RAS)
−
−
70
ns
V
Crystal oscillators
40 MHz SYSTEM CLOCK OSCILLATOR
Vosc(p-p)
oscillation amplitude
(peak-to-peak)
−
tbf
−
Gv
small signal voltage gain
−
tbf
−
Gm
mutual conductance
tbf
−
−
mA/V
Ci
input capacitance
−
−
tbf
pF
Cfb
feedback capacitance
−
tbf
−
pF
fOSC
oscillation frequency
−
40
−
MHz
∆f
frequency tolerance
−
−
−
ppm
V
27 MHz SYSTEM CLOCK OSCILLATOR
Vosc(p-p)
oscillation amplitude
(peak-to-peak)
−
tbf
−
GV
small signal voltage gain
−
tbf
−
Gm
mutual conductance
tbf
−
−
mA/V
Ci
input capacitance
−
−
tbf
pF
1996 May 21
17
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SYMBOL
PARAMETER
SAA2510
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Cfb
feedback capacitance
−
tbf
−
pF
fosc
oscillation frequency
−
27
−
MHz
∆f
frequency tolerance
−
−
−
ppm
tclkH
handbook, full pagewidth
I2S bit clock
CLKIN
or
CLKOUT
tclkL
td
th
I2S data
and
word select outputs
DAOUT, WSOUT
tsu
th
I2S data,
word select
and
error flags inputs
DAIN, WSIN, EFIN
MGE327
Fig.5 I2S input/output timing.
tr
handbook, full pagewidth
tHIGH
tf
tLOW
SCL
tSU; STA
tSU; DAT
tHD; DAT
tSU;STO
tHD; STA
SDA
MGE328
tBUF
Fig.6 I2C-bus timing.
1996 May 21
18
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
handbook, full
27pagewidth
MHz clock
(CLK27)
th1
tsu
CREF
tsu1
HREF
th1
th2
tsu2
th2
U0 (Cb0)
V0 (Cr0)
V718
Y0
Y1
Y719
pixel #0
pixel #719
CSYNC
MGE329
(1)
Timing applies to CLK27 when programmed as an input or an output of the SAA2510.
(1) CSYNC (HIGH-to-LOW) to first sample and HREF (LOW-to-HIGH) = 264.5/244.5 CLK27 periods (625 lines/525 lines mode).
Fig.7 16-bit video output mode timing.
27pagewidth
MHz clock
handbook, full
(CLK27)
tsu
HREF
th1
Y bus
output
Cb
th2
Cr
Y
pixel #0
pixel #719
Fig.8 8-bit video CCIR656 output mode timing.
1996 May 21
Y719
19
MGE330
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
handbook, full pagewidth
SAA2510
tCYC
tRP
tRSH
RAS
tCRP
tCSH
tPC
CAS
tCAS
tRCD
tCP
tASC
tASR
tRAH
tCAH
ADDRESS
tRRH
tRCS
tRCH
W
tCAC
READ
CYCLE
DRAM
data out
tRAC
tWCH
tWCS
W
tDS
tDH
WRITE
CYCLE
VCD
data to
DRAM
MGE331
Fig.9 DRAM timing.
1996 May 21
20
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
APPLICATION INFORMATION
handbook, full pagewidth
40 MHz
crystal
Sys_osc_0
0V
EBU
INTERFACE
Sys_osc_1
EBU input
EBUOUT
EBUIN
AUDIOCLK
CLIN
CLOUT
DAIN
DAOUT
WSIN
WSOUT
Audio L, R
AUDIO DAC
ESIN
COMPACT DISC
MECHANISM
AND
DECODER
16
9
4 Mbit
DRAM
DR0 to DR15
CVBS
HREF
A0 to A8
DIGITAL
VIDEO
ENCODER
VSYNC
CASN
RASN
SAA2510
UV0 to 7
Y0 to 7
W
8
8
VP0 to 7
CREF
CREF
ASEL
LLC
CLK27
+5 V
I2C-bus
Y, C
e.g.: SAA7185
CDIR
SDA
SCL
Vid_osc_0
RESET
MICROCONTROLLER
AND
USER INTERFACE
27 MHz
crystal
NDAV
Vid_osc_1
INTN
DRAMON
TEST1, 2
MGE326
2
0V
VCD power supply pins not shown.
Fig.10 Application diagram; 16-bit video output mode.
1996 May 21
21
0V
I2C-bus
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
PACKAGE OUTLINE
QFP100: plastic quad flat package;
100 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height
SOT317-1
c
y
X
80
A
51
81
50
ZE
e
E HE
A
A2
(A 3)
A1
θ
wM
pin 1 index
Lp
bp
L
31
100
detail X
30
1
wM
bp
e
ZD
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
3.3
0.36
0.10
2.87
2.57
0.25
0.40
0.25
0.25
0.13
20.1
19.9
14.1
13.9
0.65
24.2
23.6
18.2
17.6
1.95
1.0
0.6
0.2
0.15
0.1
Z D (1) Z E (1)
0.8
0.4
1.0
0.6
θ
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
95-02-04
97-08-01
SOT317-1
1996 May 21
EUROPEAN
PROJECTION
22
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
SOLDERING
Wave soldering
Introduction
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Reflow soldering
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).
Reflow soldering techniques are suitable for all QFP
packages.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1996 May 21
23
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1996 May 21
24
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
NOTES
1996 May 21
25
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
NOTES
1996 May 21
26
Philips Semiconductors
Preliminary specification
Video CD (VCD) decoder
SAA2510
NOTES
1996 May 21
27
Philips Semiconductors – a worldwide company
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Tel. (01) 4099 6161, Fax. (01) 4099 6427
Germany: P.O. Box 10 51 40, 20035 HAMBURG,
Tel. (040) 23 53 60, Fax. (040) 23 53 63 00
Greece: No. 15, 25th March Street, GR 17778 TAVROS,
Tel. (01) 4894 339/4894 911, Fax. (01) 4814 240
Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block,
Dr. Annie Besant Rd. Worli, BOMBAY 400 018
Tel. (022) 4938 541, Fax. (022) 4938 722
Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. (01) 7640 000, Fax. (01) 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,
Tel. (03) 645 04 44, Fax. (03) 648 10 07
Italy: PHILIPS SEMICONDUCTORS,
Piazza IV Novembre 3, 20124 MILANO,
Tel. (0039) 2 6752 2531, Fax. (0039) 2 6752 2557
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108, Tel. (03) 3740 5130, Fax. (03) 3740 5077
Korea: Philips House, 260-199 Itaewon-dong,
Yongsan-ku, SEOUL, Tel. (02) 709-1412, Fax. (02) 709-1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,
SELANGOR, Tel. (03) 750 5214, Fax. (03) 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO,
TEXAS 79905, Tel. 9-5(800) 234-7831, Fax. (708) 296-8556
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. (040) 2783749, Fax. (040) 2788399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. (09) 849-4160, Fax. (09) 849-7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. (022) 74 8000, Fax. (022) 74 8341
Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC,
MAKATI, Metro MANILA,
Tel. (63) 2 816 6380, Fax. (63) 2 817 3474
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. (022) 612 2831, Fax. (022) 612 2327
Portugal: see Spain
Romania: see Italy
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. (65) 350 2000, Fax. (65) 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd.,
195-215 Main Road Martindale, 2092 JOHANNESBURG,
P.O. Box 7430 Johannesburg 2000,
Tel. (011) 470-5911, Fax. (011) 470-5494
South America: Rua do Rocio 220 - 5th floor, Suite 51,
CEP: 04552-903-SÃO PAULO-SP, Brazil,
P.O. Box 7383 (01064-970),
Tel. (011) 821-2333, Fax. (011) 829-1849
Spain: Balmes 22, 08007 BARCELONA,
Tel. (03) 301 6312, Fax. (03) 301 4107
Sweden: Kottbygatan 7, Akalla. S-16485 STOCKHOLM,
Tel. (0) 8-632 2000, Fax. (0) 8-632 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. (01) 488 2211, Fax. (01) 481 77 30
Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,
Chung Hsiao West Road, Sec. 1, P.O. Box 22978,
TAIPEI 100, Tel. (886) 2 382 4443, Fax. (886) 2 382 4444
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. (66) 2 745-4090, Fax. (66) 2 398-0793
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. (0212) 279 2770, Fax. (0212) 282 6707
Ukraine: PHILIPS UKRAINE,
2A Akademika Koroleva str., Office 165, 252148 KIEV,
Tel. 380-44-4760297, Fax. 380-44-4766991
United Kingdom: Philips Semiconductors LTD.,
276 Bath Road, Hayes, MIDDLESEX UB3 5BX,
Tel. (0181) 730-5000, Fax. (0181) 754-8421
United States: 811 East Arques Avenue, SUNNYVALE,
CA 94088-3409, Tel. (800) 234-7381, Fax. (708) 296-8556
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. (381) 11 825 344, Fax. (359) 211 635 777
Internet: http://www.semiconductors.philips.com/ps/
For all other countries apply to: Philips Semiconductors,
Marketing & Sales Communications, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Fax. +31-40-2724825
SCDS48
© Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
Printed in The Netherlands
537021/1200/01/pp28
Document order number:
Date of release: 1996 May 21
9397 750 00851