INTEGRATED CIRCUITS DATA SHEET SAA2503 MPEG2 audio decoder Objective specification File under Integrated Circuits, IC01 1997 Jul 02 Philips Semiconductors Objective specification MPEG2 audio decoder SAA2503 FEATURES • Single-chip MPEG2 multichannel audio decoder • Decodes MPEG high quality audio: – MPEG1 layer 2 (44.1 kHz) – MPEG2 multichannel layer 2 (48 kHz) – Supports pause frames • Outputs 2 channels – Quasi surround down-mixing for Left and Right Dolby surround channel (Lt and Rt) – Stereo down-mixing for stereo reproduction APPLICATIONS – Stereo signal selection This IC is mainly intended for use in Digital Versatile Disc (DVD) players. However it may also be used in any application that is able to accept an MPEG2 audio bitstreams such as: – Single channel down-mixing • Karaoke modes • Linear PCM modes: • Set top boxes – Down-sampling from 96 to 48 kHz • Multimedia PCs – Pass 48 kHz signals • Digital television • Bitstream input interface I2S-bus (IEC 1937 formatted) • Next generation audio equipment. • IEC 958 output interface (IEC 1937 formatted) • IEC 958 output simultaneously available while decoding MPEG2 GENERAL DESCRIPTION The SAA2503 incorporates all necessary functions, such as MPEG2 multichannel audio decoding plus down-mixing, MPEG1 layer 2 decoding, Linear PCM (LPCM) processing all producing high quality audio. Together with the serial audio interfaces and the IEC 958 transmitter this allows for the complete audio function of a DVD player in a single chip. • I2C-bus control • Output flags for direct control • Stand-alone operation possible (self-booting) • No external DRAM or SRAM required • On-chip PLL for internal clock generation • 13.5 or 27 MHz master clock • 100 pins plastic LQFP package • 5 V power supply. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION SAA2503HT LQFP100 plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 1997 Jul 02 2 Philips Semiconductors Objective specification MPEG2 audio decoder SAA2503 FUNCTIONAL I/O DIAGRAM handbook, full pagewidth H0 to H7 HA2 HA0 to HA2 HR/W HEN I2C-BUS SERIAL HOST INTERFACE PARALLEL HOST INTERFACE HA0 SDA SLK HOREQ HREQ HACK/PB14 SDB SCKR WSR SAA2503 SCKT GPIO0 to GPIO3 I2CEN BUSY WST SERIAL AUDIO INTERFACE SDI0 SDI1 FLAGS MUTE SDO0 SDO1 ADO ACI SDO2 IEC 958 TRANSMITTER DSCK/OS1 OnCE resrved (19) DSI/OS0 DSO DR MODC reset interrupt MODB PLL MODA PLOCK PCAP PINIT RESET EXTAL MGK396 Fig.1 Functional I/O diagram. 1997 Jul 02 3 Philips Semiconductors Objective specification MPEG2 audio decoder SAA2503 PINNING SYMBOL PIN I/O DESCRIPTION n.c. 1 − not connected n.c. 2 − not connected GNDA1 3 GND n.c. 4 − not connected n.c. 5 − not connected H7/PB7 6 I/O not used H6/PB6 7 I/O not used GNDH1 8 GND HOA2/PB10 9 I/O VCCH1 10 supply ground 1 for some sections of internal logic isolated ground 1 for the HI I/O drivers not used isolated power supply 1 for some sections of the internal chip logic HOA1/PB9 11 I/O not used HR/W/PB11 12 I/O not used HEN/PB12 13 I/O not used VCCQ1 14 supply GNDQ1 15 GND HACK/PB14 16 I/O GNDH2 17 GND HOA0/PB8 18 I/O not used H5/PB5 19 I/O not used VCCH2 20 supply H4/PB4 21 I/O not used H3/PB3 22 I/O not used GNDH3 23 GND H2/PB2 24 I/O not used H1/PB1 25 I/O not used H0/PB0 26 I/O not used HOREQ/PB13 27 I/O GNDH4 28 GND VCCH3 29 supply ADO 30 O digital audio data output ACI 31 I audio clock input n.c. 32 − not connected n.c. 33 − not connected n.c. 34 − not connected PLOCK 35 O HIGH when PLL is phase locked VCCQ2 36 supply GNDQ2 37 GND PINIT 38 I GNDP 39 GND PCAP 40 I 1997 Jul 02 isolated power supply 1 for the HI I/O drivers isolated ground 1 for the internal logic not used isolated ground 2 for the HI I/O drivers isolated power supply 2 for the HI I/O drivers isolated ground 3 for the HI I/O drivers not used isolated ground 4 for the HI I/O drivers isolated power supply 3 for the HI I/O drivers isolated power supply 2 for some sections of the internal chip logic isolated ground 2 for the internal logic PLL enable/disable control ground dedicated for the PLL PLL capacitor input 4 Philips Semiconductors Objective specification MPEG2 audio decoder SYMBOL SAA2503 PIN I/O DESCRIPTION VCCP 41 supply EXTAL 42 I external clock/crystal Input SCL 43 I I2C-bus serial clock GNDS1 44 GND SDA 45 I/O RESET 46 I hardware reset for the microcontroller MODA 47 I mode select A MODB 48 I mode select B MODC 49 I mode select C VCCS1 50 supply HA0 51 I/O I2C-bus slave address 0 HA2 52 I I2C-bus slave address 2 HREQ 53 I host request GNDS2 54 GND SDO2 55 O not used SDO1 56 O not used SDO0 57 O serial data output 0 VCCS2 58 supply SCKT 59 O transmit serial clock WST 60 O transmit word select SCKR 61 I receive serial clock GNDQ3 62 GND VCCQ3 63 supply GNDS3 64 GND WSR 65 I receive word select SDI1 66 I serial data input 1 SDI0 67 I not used DSO 68 O not used DSI/OS0 69 O not used DSCK/OS1 70 O not used n.c. 71 − not connected n.c. 72 − not connected n.c. 73 − not connected supply voltage for the Phase Locked Loop (PLL) isolated ground 1 for the SHI I/O drivers I2C-bus data and acknowledge isolated power supply 1 for the SHI I/O drivers isolated ground 2 for the SHI I/O drivers isolated power supply 2 for the SHI I/O drivers ground 3 dedicated for the PLL isolated power supply 3 for some sections of the internal chip logic isolated ground 3 for the SHI I/O drivers n.c. 74 − not connected DR 75 I not used SDB 76 I/O general purpose I/O MUTE 77 I/O general purpose I/O GNDD1 78 GND BUSY 79 I/O general purpose I/O I2CEN 80 I/O general purpose I/O VCCD1 81 supply 1997 Jul 02 ground 1 for some sections of internal logic isolated power supply 1 for some sections of the internal chip logic 5 Philips Semiconductors Objective specification MPEG2 audio decoder SYMBOL SAA2503 PIN I/O DESCRIPTION GPIO3 82 I/O not used GPIO2 83 I/O not used GNDD2 84 GND GPIO1 85 I/O not used GPIO0 86 I/O not used GNDQ4 87 GND VCCQ4 88 supply n.c. 89 − not connected n.c. 90 − not connected GNDA2 91 GND n.c. 92 − ground 2 for some sections of internal logic ground 4 for some sections of internal logic isolated power supply 4 for some sections of the internal chip logic ground 2 for some sections of internal logic not connected VCCA1 93 supply n.c. 94 − not connected n.c. 95 − not connected GNDA3 96 GND n.c. 97 − not connected n.c. 98 − not connected not connected n.c. 99 − VCCA2 100 supply 1997 Jul 02 isolated power supply 1 for some sections of the internal chip logic ground 3 for some sections of internal logic isolated power supply 2 for some sections of the internal chip logic 6 Philips Semiconductors Objective specification GNDD1 MUTE SDB 77 76 BUSY 79 78 I2CEN 80 81 VCCD1 82 GPIO3 83 GPIO2 84 GNDD2 85 GPIO1 86 GPIO0 87 GNDQ4 88 VCCQ4 89 n.c 90 n.c 91 GNDA2 93 VCCA1 92 n.c 94 n.c SAA2503 95 n.c 96 GNDA3 97 n.c 98 n.c handbook, full pagewidth 99 n.c 100 VCCA2 MPEG2 audio decoder n.c. 1 75 DR n.c. 2 74 n.c GNDA1 3 73 n.c n.c 4 72 n.c n.c 5 71 n.c H7/PB7 6 70 DSCK/OS1 H6/PB6 7 69 DSI/OS0 GNDH1 8 68 DSO HOA2/PB10 9 67 SDI0 VCCH1 10 66 SDI1 HOA1/PB9 11 65 WSR HR/W/PB11 12 64 GNDS3 63 VCCQ3 VCCQ1 14 62 GNDQ3 GNDQ1 15 61 SCKR HACK/PB14 16 60 WST GNDH2 17 59 SCKT HOA0/PB8 18 58 VCCS2 H5/PB5 19 57 SDO0 VCCH2 20 56 SDO1 H4/PB4 21 55 SDO2 SAA2503 HEN/PB12 13 Fig.2 Pin configuration. 1997 Jul 02 7 VCCS1 50 MODC 49 MODB 48 MODA 47 RESET 46 SDA 45 GNDS1 44 SCL 43 EXTAL 42 VCCP 41 PCAP 40 GNDP 39 PINIT 38 GNDQ2 37 ADO PLOCK 35 HA0 VCCQ2 36 51 n.c 34 25 n.c 33 HA2 H1/PB1 n.c. 32 52 ACI 31 24 30 HREQ H2/PB2 VCCH3 29 GNDS2 53 GNDH4 28 54 23 H0/PB0 26 22 HOREQ/PB13 27 H3/PB3 GNDH3 MGK395 Philips Semiconductors Objective specification MPEG2 audio decoder SAA2503 • LPCM down-sampling DVD (96 kHz: 4 channel input; 48 kHz 2 channel output) FUNCTIONAL DESCRIPTION Operating modes • LPCM DVD (48 kHz: 8 channel input; 2 channel output). The SAA2503 can operate in 2 modes. Stand-alone (mode 4) System clock In this mode (modC = 1, modB = 0 and modA = 0) the SAA2503 boots itself from the internal program ROM after power-up and can start decoding when a decoding mode has been selected via the I2C-bus. The preferred system clock to be applied to the EXTAL pin of the SAA2503 is 27 MHz if booted in mode 4 (stand-alone operation). Booting via the I2C-bus The internal PLL multiplies this clock by a factor of 3 to obtain an 81 MHz internal clock. (mode 7) In this mode (modC = 1, modB = 1 and modA = 1) the SAA2503 starts executing an internal boot program that will receive 1536 bytes via the I2C-bus and then write those to an on-chip program RAM. If using another external clock frequency it is advisable to ensure that: This mode allows the standard behaviour (I/O interfaces, additional processing) to be modified as specified in the stand-alone mode. • That 10 MHz < (fclk(ext) × 3) < 81 MHz. Decoding modes Serial audio interface The SAA2503 has the following decoding modes: The serial audio interface can be configured as an I2S-bus interface and when required, as Quad I2S interface. The signal received via the I2S-bus is an encoded audio bitstream in accordance with IEC 1937, or LPCM. • The internal PLL is disabled during booting when fclk(ext) > 27 MHz INTERFACING TO THE A/V SPLITTER • MPEG decoding (48 kHz DVD; 44.1 kHz VCD) IEC 958 LPCM • MPEG decoding (48 kHz DVD; 44.1 kHz VCD) IEC 958 BITSTR • LPCM CD-DA (44.1 kHz) Table 1 Pinning of the I2S-bus interface PINS DESCRIPTION PIN NUMBER DIRECTION SDI0 high impedance 67 not used SDI1 serial data 66 input/output SDO0 serial data 57 output SDO1 serial data 56 not used SDO2 serial data 55 not used SCKR I2S-bus clock; notes 1 and 2 61 input WSR word select receive 65 input SDB serial data begin 76 input SCKT I2S-bus clock; notes 1 and 2 59 input WST word select transmit 60 input Notes 1. SCKT is equal to SCKR when the I2S-bus format is the format of the input signal. When Quad I2S-bus is used SCKT = 1⁄4SCKR. 2. The maximum allowed clock frequency for SCK is 1⁄3fclk (fclk is the internal clock generated by the PLL of the SAA2503). 1997 Jul 02 8 Philips Semiconductors Objective specification MPEG2 audio decoder SAA2503 MPEG2 bitstreams QUAD I2S-BUS The MPEG2 audio bitstream is received via the I2S-bus in the same format as specified in IEC 1937. The MPEG2 audio bitstream consists of data bursts of 1 frame. The data is formatted in 16-bit chunks. The time period until the next frame is filled with logic 0. The serial data is received by the SAA2503 via the SDI1 pin (pin 66). Quad I2S-bus is the interface providing audio samples in LPCM with 4 times the sampling frequency. The interface is an extension of the I2S-bus where the Serial Data Begin (SDB) indicates the first 2 channels out of 8 channels. The audio samples are transferred with MSB first, where each sample occupies 32 bits, filled with logic 0. For more information on transporting MPEG2 bitstreams via IEC 958 see IEC 1937. Linear PCM (LPCM) I2S-BUS Linear PCM samples are received in an I2S-bus format. Serial audio data is received via SDI1 (pin 66). The I2S-bus clock is received via SCKR (pin 61) and the I2S-bus word select is received via WSR (pin 65); the I2S-bus clock operates at 64fs. handbook, full pagewidth SD Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 WS ,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,, SDB SCK 12S-bus clock/Quad 12S-bus clock 1 sampling period MGK398 Fig.3 Quad I2S-bus frame format. The SDB remains HIGH when only 2 channels LPCM or encode bitstreams (in accordance with IEC 1937) are transferred (Quad I2S-bus is equal to I2S-bus). 1997 Jul 02 9 Philips Semiconductors Objective specification MPEG2 audio decoder Table 2 SAA2503 Allocation of LPCM channels on Quad I2S-bus, fs = 48 or 96 kHz INPUT NUMBER OF LPCM CHANNELS fs (kHz) 1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 48 Q0 mute mute mute mute mute mute mute 2 48 Q0 Q1 mute mute mute mute mute mute 3 48 Q0 Q1 Q2 mute mute mute mute mute 4 48 Q0 Q1 Q2 Q3 mute mute mute mute 5 48 Q0 Q1 Q2 Q3 Q4 mute mute mute 6 48 Q0 Q1 Q2 Q3 Q4 Q5 mute mute 7 48 Q0 Q1 Q2 Q3 Q4 Q5 Q6 mute 8 48 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 1 96 Q0 mute mute mute Q0 mute mute mute 2 96 Q0 Q1 mute mute Q0 Q1 mute mute 3 96 Q0 Q1 Q2 mute Q0 Q1 Q2 mute 4 96 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 handbook, full pagewidth channel n + 1 SD WS channel n SDB SCK 0 31 0 31 channel 0, 2, 4 or 6 channel 1, 3, 5 or 7 Fig.4 Quad I2S-bus channel format. 1997 Jul 02 10 MGK397 Philips Semiconductors Objective specification MPEG2 audio decoder SAA2503 The burst_preamble provides a sync_word, information on the burst_payload and the bitstream number. AUDIO OUTPUTS INTERFACING Also see Chapter “Interfacing to the A/V splitter”. The interface may convey one or more bitstreams. Each type of bitstream may impose a particular requirement for the repetition time for the data bursts that make up the bitstream. Stereo output for DAC The output stereo down-mixing signal is in I2S-bus format and can be directly connected to a DAC. The SDO0 (pin 57) provides the output for the serial audio data. Furthermore, SCKT (pin 59) provides the I2S-bus clock and WST (pin 60), the I2S-bus word select. The 16-bit data words of a data burst are placed in time slots 12 to 27 of an IEC 958 sub frame. In the consumer application, both odd and even IEC 958-sub frames (CH1 and CH2) are simultaneously used to carry 32-bit data words (32-bit mode). This allows the consumer IEC 958 to convey either 2-channel LPCM audio, or a set of alternating data words, but not both simultaneously. For more information see IEC 1937. IEC 958 transmitter The format of the IEC 958 interface consists of a sequence of IEC 958 sub frames. Each IEC 958 sub frame is normally used to carry one LPCM sample. The IEC 958 sub frame may also be used to convey data words. The non-PCM encoded audio bitstreams to be transferred are formed into data bursts. These bitstreams consist of a sequence of data words. The IEC 958 interface is of the digital audio interface. This conveys LPCM or encoded audio bitstreams according to IEC 1937 (IEC 1937), using the ‘network layer’ of IEC 958 (IEC 958). The audio data will be accompanied by a validity bit, channel status and user data (sub code). Each data burst contains a 64-bit burst_preamble, followed by the burst_payload. Table 3 Pinning of IEC 958 interface PINS DESCRIPTION PIN NUMBER DIRECTION ADO Audio Data Output 30 output ACI Audio Clock Input; note 1 31 input Note 1. The ACI clock is 256fs (or 512 or 384fs). 3. MPEG decoding active and synchronised (pin 77); MUTE: when the SAA2503 operates in the MPEG decoding mode, this flag indicates the state of the SAA2503 (synchronized or not). When this pin is at logic 1 the SAA2503 is out of sync, when set to logic 0 the SAA2503 is synchronized. It will not change state when the SAA2503 remains synchronized. When the SAA2503 is operating in one of the LPCM modes, the MUTE pin is set at logic 1 during initialization and logic 0 during processing. INTERFACING WITH THE MICROCONTROLLER Flags The SAA2503 has 3 flags which, after a hardware reset, are all initialized to logic 1. 1. I2C-bus communication disabled (pin 80); I2CEN: this flag is set to logic 0 when the SAA2503 is ready to accept messages via the I2C-bus. 2. Life test (pin 79); BUSY: when the SAA2503 operates in the MPEG decoding mode, this flag toggles whenever the SAA2503 has detected a synchronization pattern. The flag will then produce a 20.833 Hz (fas = 48 kHz) and a 19.140 Hz (fas = 44.1 kHz) signal. It can be used to monitor the MPEG decoding process. When this flag no longer toggles there is an error. When the SAA2503 operates in one of the LPCM modes however, the flag produces either a 23.437 Hz (fas = 48 kHz) or a 21.533 Hz (fas = 44.1 kHz) signal. 1997 Jul 02 I2C-bus interface The I2C-bus interface supports data rates of up to 400 kbits/s. For a description of the I2C-bus see “The I2C-bus and how to use it”, ordering number 9398 393 40011. For a description of the I2C-bus commands controlling the SAA2503 see Table 1. 11 Philips Semiconductors Objective specification MPEG2 audio decoder SAA2503 APPLICATION SCHEMATIC RESET handbook, full pagewidth L14 POWER VSS C73 100 nF GND 24 22 21 19 7 6 18 11 9 12 R134 13 10 kΩ 27 R135 16 VCCS2 WSR SCKR H2/PB2 SDI0 H3/PB3 SDI1 H4/PB4 WST H5/PB5 SCKT H6/PB6 SDO0 H7/PB7 SDO1 HOA0/PB8 SDO2 HOA1/PB9 HOA2/PB10 ADO HR/W/PB11 ACI SAA2503 HEN/PB12 HOREQ/PB13 DSCK/OS1 HACK/PB14 DSI/OS0 10 kΩ DSO 39 3 91 96 78 84 51 52 45 43 53 47 48 49 46 8 65 WS-IN 61 SCK-IN 67 SD-IN A B C 66 60 59 57 D E F 56 55 IEC 958 30 OUT (EBU) 31 G 70 69 68 75 17 23 28 15 37 62 87 44 4 35 40 38 42 H I J GNDS2 n.c. GNDS1 GNDQ4 GNDQ3 GNDQ2 GNDQ1 GNDH4 GNDH3 GNDH2 SDB GNDH1 MUTE RESET EXTAL MODC JP41 76 BUSY MODB SDB PINIT MODA JP40 jumper I2CEN HREQ MUTE 77 PCAP SCL BUSY 79 GPIO3 SDA JP39 jumper PLOCK HA2 I2CEN 80 GPIO2 HA0 82 GNDD2 JP38 C76 100 nF GPIO1 GNDD1 83 GNDA3 jumper GNDA2 85 GNDA1 JP37 DR GPIO0 GNDP 86 jumper C75 100 nF 50 58 VCCS1 VCCQ4 VCCQ3 36 63 88 VCCQ2 14 VCCQ1 VCCH3 20 29 VCCH2 10 VCCH1 81 VCCD1 H1/PB1 VCCA1 VCCP 25 H0/PB0 VCCA2 93 100 41 26 C74 100 nF 54 jumper RESET MODE SETTINGS JP42 jumper R136 JP43 jumper R137 10 kΩ JP44 jumper 10 kΩ R138 JP45 jumper R139 JP46 jumper 10 kΩ R140 10 kΩ I2C-BUS ADDRESS SETTINGS K 10 kΩ JP U11B 3 4 SCL MUTE SDA 74HC04 1 2 HEADER 3 Fig.5 Application diagram (continued in Fig.6). 1997 Jul 02 I2C-BUS CONTROL 3 12 MGK399 Philips Semiconductors Objective specification MPEG2 audio decoder serial audio data handbook, full pagewidth from A/V splitter SAA2503 JP HEADER 4 1 2 3 D/A-CLK 4 A B SDB C D 12 5 SCK 4 DATA-L-R EMP1 R142 470 Ω U11A 1 18 EMP2 21 VCC 2 19 MUTE 20 VCC 74HC04 H 6 17 13 I 3 J JP50 jumper R141 11 C78 1.2 nF 10 kΩ CLKS2 WS FILTCL VOR DATA DEEM2 TDA1305 FILTCR Vref 26 MUSB DSMB VDDO n.c. TEST2 9 1 2 VSSO C 100 nF VCC BLM21A10 8 VCC 5 U54 27 MHz OSC OUT 100E C32 100 nF GND 4 Fig.6 Application diagram (continued from Fig.5). 1997 Jul 02 10 µF 28 C 100 nF 47 kΩ VCC 47 µF 27 C 47 µF MGK400 74HC04 decoupling C79 100 nF L7 K C C 1 nF TEST1 VCC DR R110 24 via OP-AMP to analog output ATSB C 100 nF R143 4.7 kΩ C 10 µF 1 nF 25 DEEM1 10 VCC 22 23 R 47 kΩ C BCK VSSA D8 LED SWS VOL VDDA VCC 8 VSSD G 7 SYSCLK1 VDDD J2 BNC 15 VSSD SYSCLK0 F CLKS1 14 n.c. 16 E 13 C 100 nF Philips Semiconductors Objective specification MPEG2 audio decoder SAA2503 PACKAGE OUTLINE LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 c y X A 51 75 50 76 ZE e Q E HE A A2 (A 3) A1 w M θ bp Lp L pin 1 index 100 detail X 26 1 25 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.20 0.05 1.5 1.3 0.25 0.28 0.16 0.18 0.12 14.1 13.9 14.1 13.9 0.5 HD HE 16.25 16.25 15.75 15.75 L Lp Q v w y 1.0 0.75 0.45 0.70 0.57 0.2 0.12 0.1 Z D (1) Z E (1) θ 1.15 0.85 7 0o 1.15 0.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-12-19 SOT407-1 1997 Jul 02 EUROPEAN PROJECTION 14 o Philips Semiconductors Objective specification MPEG2 audio decoder SAA2503 If wave soldering cannot be avoided, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all LQFP packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1997 Jul 02 15 Philips Semiconductors Objective specification MPEG2 audio decoder SAA2503 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Jul 02 16 Philips Semiconductors Objective specification MPEG2 audio decoder SAA2503 NOTES 1997 Jul 02 17 Philips Semiconductors Objective specification MPEG2 audio decoder SAA2503 NOTES 1997 Jul 02 18 Philips Semiconductors Objective specification MPEG2 audio decoder SAA2503 NOTES 1997 Jul 02 19 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1997 SCA54 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 547027/1200/01/pp20 Date of release: 1997 Jul 02 Document order number: 9397 750 01802