PHILIPS TDA8961

INTEGRATED CIRCUITS
DATA SHEET
TDA8961
ATSC Digital Terrestrial TV
demodulator/decoder
Objective specification
File under Integrated Circuits, IC02
2000 May 19
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
FEATURES
General features
• One-chip ATSC-compliant demodulator and
concatenated trellis (Viterbi)/Reed Solomon decoder
with de-interleaver and de-randomizer
• 0.35 µm process
On-chip forward error correction
• Trellis (Viterbi) decoder
• 3.3 V device
• QFP80 package
• Rate 2⁄3 (Rate 1⁄2 Ungerboeck code based)
• Boundary Scan Test (BST)
• (207, 187, T = 10) Reed Solomon code
• 12 MHz external clock
• Internal convolutional de-interleaving (I = 52; using
internal memory)
• 36 MHz output for external D/A converter
8-Vestigial Side Band (VSB) demodulator
• External indication of uncorrectable error;
transport_error_indicator bit in MPEG packet header is
also set
• Accepts 10-bit IF data sampled at 36 MHz
• De-randomizer based on ATSC standard
• 6 MHz wide IF signal, centered at 4 MHz
• Segment error rate readable through I2C.
• Parallel or serial MPEG-2 transport stream output.
• On-chip digital circuitry for tuner AGC
I2C interface
• Square-root raised-cosine filter with 11.5% roll-off factor
I2C-bus interface to initialize and monitor the demodulator
and Forward Error Correction (FEC) decoder. An
operation without I2C-bus is possible (default).
• Fully internal carrier recovery loop
• No need for external voltage controlled crystal oscillator
due to internal sample rate converter
• Fully internal symbol timing recovery with
programmable loop filters
System interfaces
• 8-bit wide or serial MPEG-2 transport stream interface
• Technology to handle dynamic multipath conditions.
• ITU656 bypass mode
• MPEG-2 serial transport stream input to reduce external
components when the IC is combined in a system with a
Quadrature Amplitude Modulation (QAM), Quadrature
Phase Shift Keying (QPSK) or Orthogonal Frequency
Division Multiplexing (OFDM) channel decoder.
Adaptive equalizer
• Including feed forward and feedback sections with
Decision Feedback Equalizer (DFE) structure
• Range of −2.3 to +22.5 µs by default (in conjunction with
external software, −2.3 to +80 µs)
• Adaptation based on ATSC field sync (trained) and/or
8-VSB data (blind).
APPLICATIONS
NTSC co-channel interference filter
• Personal computers with digital television capabilities
• Digital ATSC compliant TV receiver
• Set top-boxes.
Patented NTSC co-channel interference technology with
low noise penalty.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
TDA8961
2000 May 19
QFP80
DESCRIPTION
plastic quad flat package; 80 leads (lead length 1.95 mm);
body14 × 20 × 2.8 mm
2
VERSION
SOT318-2
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
• Down converts the incoming 6 MHz wide 8-VSB IF
signal to a low-IF signal centered at 4 MHz: The low-IF
signal is then digitized, using an on-chip 10-bit A/D
converter, and fed to the TDA8961 for further
processing. In this application, AGC is also managed by
the TDA8980 so that no other external components,
such as an operational amplifier loop integrator, are
required.
GENERAL DESCRIPTION
The TDA8961 is an Advanced Television Systems
Committee (ATSC)-compliant demodulator and FEC
decoder for reception of 8-VSB modulated signals for
terrestrial and cable applications:
• Terrestrial: reception of 8-VSB modulated signals via
standard 6 MHz VHF/UHF terrestrial TV channels (TV
channels 2 to 69 in the United States).
Although the TDA8980 has an internal 2-D comb filter,
external filters such as a 3-D comb filter and other picture
improvement devices can easily be connected. Sound can
be decoded using an external device such as the
TDA9851 I2C-bus controlled economic BTSC stereo
decoder. This IC has an internal switch allowing it to
process either analog NTSC IF or digital 8-VSB IF signals.
• Cable: reception of 8-VSB modulated signals via
standard 6 MHz VHF/UHF cable TV channels.
An application using the TDA8961 and the TDA8980
NTSC/ATSC TV input processor for TV and Multi-Media is
shown in Fig.1. A tuner converts the incoming RF signal to
a fixed IF centered at 44 MHz. The output signal from the
tuner is filtered and fed to the TDA8980 which performs the
following functions:
A 12 MHz clock signal is generated using a 12 MHz crystal
connected to the TDA8980. The TDA8961 also uses this
clock signal which is fed from the TDA8980 to pin XTALI of
the TDA8961.
• Decodes the analog NTSC signals: The audio signals
are digitized, using on-chip audio stereo A/D converters,
into an I2S-bus stream; the video information is digitized,
using on-chip video A/D converters, into an ITU656
stream.
handbook, full pagewidth
TUNER
I2C
NTSC
SAW
FILTER
FLAT
SAW
FILTER
TDA8980
TDA8961
PDOVAL
TVIFIN
ADCLK
VCLK
VSBIFIN
PDOERR
D9 to D0
ADIN9 to ADIN0
REF12M
XTALI
PDO7 to PDO0
PDOSYNC
AGCOUT
VIFAGC
MPEG-2
transport
stream
PDOCLK
TUNERAGC
I2C X12MOUT X12MIN
12 MHz
I2C PDI0 PDISYNC PDIVAL PDICLK PDIERR
serial MPEG-2 transport
stream input
I2C
master
Fig.1 Front-end design for a hybrid TV system using the TDA8980 and TDA8961.
2000 May 19
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MGU085
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
correct up to 10 bytes. The decoded stream is then
de-randomized using a pseudo-random binary sequence
(PRBS) and the data passed to a FIFO which prevents the
appearance of irregular gaps in the output data.
The incoming data has a sample rate of 36 MHz. This is
internally converted to a sample rate of 21.52 MHz which
is twice the 8-VSB symbol rate. This patented Philips
Semiconductors’ technology eliminates the need for
external symbol timing recovery loop components. When
the TDA8980 is decoding analog NTSC, the TDA8961 can
be set to a ITU656 bypass mode which allows the 8-bit
ITU656 data output from the TDA8980 to appear at the
TDA8961 Moving Pictures Expert Group (MPEG-2)
transport stream output, from where it can be fed to the
main graphics display device in the system.
The output of the TDA8961 is a clock signal and an
ATSC-compliant MPEG-2 packetized data stream. Signal
flag outputs are provided to indicate the occurrence of
sync bytes, valid data bytes and uncorrected Reed
Solomon blocks. The packetized data stream is available
in either an 8-bit parallel, or a 1-bit serial format for
connection to an MPEG-2 transport stream demultiplexer.
The recovery of the carrier is performed entirely within the
TDA8961. This function consists of a digital frequency and
Frequency Phase-Locked Loop (FPLL).
An application using the TDA8961 and a stand-alone
TDA9829 Downconverter for DVB (Digital Video
Broadcast) with an A/D converter is shown in Fig.2. A tuner
converts the incoming RF signal to a fixed IF centered at
44 MHz. The output signal from the tuner is filtered using
two Surface Acoustical Wave (SAW) filters and then down
converted to an IF of 4 MHz by the TDA9829. The signal
is then digitized by an A/D converter at a sample rate of
36 MHz using the clock signal output from the TDA8961.
Data shaping is performed by a square-root raised-cosine
(half Nyquist) filter having a roll-off factor of 11.5%.
After the TDA8961 has performed carrier recovery,
Nyquist filtering and symbol timing recovery, it then
performs adaptive equalization. The adaptive equalizer
uses a DFE structure with equalization based on the ATSC
field sync (trained equalization) and/or the 8-VSB data
itself (blind equalization).
The full input range of the A/D converter is utilized by
placing it within what is effectively a fine-AGC loop
integrator circuit which has a variable gain stage at the
output of the IF downmixer section. However, it is also
possible to apply the AGC control output of the TDA8961
to the tuner via the integrator. The peak level of the input
signals to the TDA8961 is determined by the AGC output
detector which is located just after the A/D.
The equalizer is followed by a patented NTSC co-channel
interference filter which removes any unwanted NTSC
signal interference from the 8-VSB terrestrial DTV signal.
After trellis decoding, the stream is de-interleaved to a
depth of 52 by a convolutional de-interleaver whose
memory is provided on-chip. The Reed Solomon decoder
is ATSC-compliant, with a length of 207, and able to
integrator
handbook, full pagewidth
AGC
Vref
RF
SAW
FILTER
TUNER RF
SAW
FILTER
AGCOUT
VAGC
44 MHz
VoDVB
ViIF
TDA9829
ADIN9 to
ADIN0
A
D
TDA8961
IF DOWNMIXER
MPEG-2
transport
stream
ADCLK
CLK36 XTALI
VCO
96 MHz
OSCILLATOR
PDO7 to
PDO0
MGU086
12 MHz
÷8
Fig.2 Front-end design for the TDA8961 using a stand-alone IF down converter (TDA9829) and A/D converter.
2000 May 19
4
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VDD
supply voltage
IDD
supply current
fclk
CONDITIONS
MIN.
TYP.
MAX.
UNIT
2.7
3.3
3.6
V
−
390
−
mA
clock frequency
−
12
−
MHz
fsym
symbol frequency
−
10.76
−
Msymbols/s
fs
sample frequency
−
36
−
MHz
fc(IF2)
second IF centre frequency
−
4
−
MHz
IL
implementation loss
−
−
−
dB
αro
half Nyquist filter roll-off factor
−
11.5
−
%
tacq
acquisition time
−
−
290
ms
Tamb
ambient temperature
−20
−
+70
°C
Ptot
total power dissipation
−
1.3
−
W
VDD = 3.3 V
note 1
Note
1. Corresponds to 12 training sequences.
2000 May 19
5
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
BLOCK DIAGRAM
ADIN9 TO ADIN0
handbook, full pagewidth
ADCLK
10, 9, 8, 7, 6,
5, 4, 3, 2, 1
TMS
TDO
TDI
TRST
TCK
LOCKINDIC
EQLOCKINDIC
RST_AN
A0
A1
SCL
SDA
XTALI
XTALO
CLK36
PDISYNC
PDICLK
PDIERR
PDIVAL
PDI0
20
23
19
22
21
DIGITAL FRONT-END:
BOUNDARY
SCAN TEST
CONTROLLER
78
79
* SAMPLE RATE CONVERTER
* FINE AGC
66
* CARRIER RECOVERY
HALF
NYQUIST
FILTERING
*
* SYNC RECOVERY AND PILOT REMOVAL
* SYMBOL TIMING RECOVERY
* ADAPTIVE EQUALIZATION
AGCOUT
CONTROL
77
NTSC CO-CHANNEL INTERFACE FILTER
13
TRELLIS DECODER
14
I2C-BUS
INTERFACE
15
16
DE-INTERLEAVER
69
REED SOLOMON DECODER
CLOCK
GENERATION
70
75
DE-RANDOMIZER
26
30
32
28
27
OUTPUT FORMATTER
TDA8961
34
35
67
FSYNC
FSHNDSHK
SSYNC
39
40
43, 44, 45,
47, 48, 49,
51, 52
37
41
PDOCLK
PDOSYNC
PDO7 TO PDO0
PDOVAL
PDOERR
Fig.3 Block diagram.
2000 May 19
80
6
MGU087
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
PINNING
SYMBOL
PIN
I/O
DESCRIPTION
ADIN0
1
I
data input bit 0 (LSB)
ADIN1
2
I
data input bit 1
ADIN2
3
I
data input bit 2
ADIN3
4
I
data input bit 3
ADIN4
5
I
data input bit 4
ADIN5
6
I
data input bit 5
ADIN6
7
I
data input bit 6
ADIN7
8
I
data input bit 7
ADIN8
9
I
data input bit 8
ADIN9
10
I
data input bit 9 (MSB)
VDDD1
11
−
digital core supply voltage 1 (3.3 V)
VSSD1
12
−
digital core ground 1
A0
13
I
I2C-bus slave address bit 0
A1
14
I
I2C-bus slave address bit 1
SCL
15
I
I2C-bus clock
SDA
16
I/O
I2C-bus serial data
VDDD2
17
−
I/O supply (3.3 V)
VSSD2
18
−
digital core ground 2
TDI
19
I
TAP controller data input; note 1
TMS
20
I
TAP controller test mode select; note 1
TCK
21
I
TAP controller test clock; note 1
TRST
22
I
TAP controller asynchronous reset (active LOW); notes 1 and 2
TDO
23
O
TAP controller test data (3-state); note 1
VDDD3
24
−
digital core supply voltage 3 (3.3 V)
VSSD3
25
−
digital core ground 3
PDISYNC
26
I
transport stream interface packet sync indicator
PDI0
27
I
transport stream interface packet data bit 0
PDIVAL
28
I
transport stream interface packet data valid signal
VDDD4
29
−
digital core supply voltage 4 (3.3 V)
PDICLK
30
I
transport stream interface packet data clock signal
VSSD4
31
−
digital core ground 4
PDIERR
32
I
transport stream interface packet error signal
VDDD5
33
−
digital core supply voltage 5 (3.3 V)
FSYNC
34
I
field sync strobe (for debug modes)
SSYNC
35
I
segment sync strobe (for debug modes)
VSSD5
36
−
digital core ground 5
PDOERR
37
O
transport stream interface packet error signal (3-state)
VDDQ1
38
−
I/O supply voltage 1 (3.3 V)
PDOSYNC
39
O
transport stream interface packet sync indicator signal (3-state)
PDOVAL
40
O
transport stream interface packet data valid indicator signal (3-state)
2000 May 19
7
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
SYMBOL
TDA8961
PIN
I/O
DESCRIPTION
PDOCLK
41
O
transport stream interface packet data clock signal (3-state)
VSSQ1
42
−
I/O ground 1
PDO7
43
O
transport stream interface packet data bit 7 (3-state)
PDO6
44
O
transport stream interface packet data bit 6 (3-state)
PDO5
45
O
transport stream interface packet data bit 5 (3-state)
VDDQ2
46
−
I/O supply voltage 2 (3.3 V)
PDO4
47
O
transport stream interface packet data bit 4 (3-state)
PDO3
48
O
transport stream interface packet data bit 3 (3-state)
PDO2
49
O
transport stream interface packet data bit 2 (3-state)
VSSQ2
50
−
I/O ground 2
PDO1
51
O
transport stream interface packet data bit 1(3-state)
PDO0
52
O
transport stream interface packet data bit 0 (3-state)
VDDQ3
53
−
I/O supply 3 (3.3 V)
n.c.
54
not connected
n.c.
55
VSSQ3
56
n.c.
57
not connected
n.c.
58
not connected
n.c.
59
not connected
VDDQ4
60
n.c.
61
not connected
n.c.
62
not connected
n.c.
63
not connected
VSSQ4
64
n.c.
65
AGCOUT
66
O
AGC control (3-state)
FSHNDSHK
67
O
field sync strobe or symbol capture memory handshake signal
VDDA1
68
−
analog supply voltage (3.3 V)
XTALI
69
I
external crystal
XTALO
70
O
external crystal
VSSA1
71
−
analog ground 1
VDDA2
72
−
analog supply 2 (3.3 V)
n.c.
73
VDDQ5
74
−
I/O supply 5 (3.3 V)
CLK36
75
O
36 MHz clock signal
VSSQ5
76
−
I/O ground 5
RST_AN
77
I
asynchronous reset (active LOW)
LOCKINDIC
78
O
front-end lock indicator
EQLOCKINDIC
79
O
equalizer lock indicator
ADCLK
80
I
incoming data sampling clock signal (36 MHz)
2000 May 19
not connected
−
−
−
I/O ground 3
I/O supply 4 (3.3 V)
I/O ground 4
not connected
not connected
8
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
Notes
1. Input pins TCK, TDI, TMS and TRST have an internal pull-up transistor and must be connected to ground when not
used; pin TDO is a 3-state output in accordance with IEEE 1149.1.
2. Pin TRST is active LOW. It can be used to immediately force the Test Access Port (TAP) controller to the test logic
reset state (normal operation) in accordance with IEEE 1149.1.
2000 May 19
9
Philips Semiconductors
Objective specification
65 n.c.
66 AGCOUT
67 FSHNDSHK
68 VDDA1
69 XTALI
70 XTALO
71 VSSA1
72 VDDA2
73 n.c.
74 VDDQ5
75 CLK36
TDA8961
76 VSSQ5
77 RST_AN
78 LOCKINDIC
handbook, full pagewidth
79 EQLOCKINDIC
80 ADCLK
ATSC Digital Terrestrial TV
demodulator/decoder
ADIN0
1
64 VSSQ4
ADIN1
2
63 n.c.
ADIN2
3
62 n.c.
ADIN3
4
61 n.c.
ADIN4
5
60 VDDQ4
ADIN5
6
59 n.c.
ADIN6
7
58 n.c.
ADIN7
8
57 n.c.
ADIN8
9
56 VSSQ3
ADIN9 10
55 n.c.
VDDD1 11
54 n.c.
VSSD1 12
53 VDDQ3
TDA8961
A0 13
52 PDO0
A1 14
51 PDO1
SCL 15
50 VSSQ2
SDA 16
49 PDO2
VDDD2 17
48 PDO3
VSSD2 18
47 PDO4
46 VDDQ2
TDI 19
TMS 20
45 PDO5
TCK 21
44 PDO6
TRST 22
43 PDO7
TDO 23
42 VSSQ1
Fig.4 Pin configuration.
2000 May 19
10
PDOVAL 40
PDOSYNC 39
VDDQ1 38
PDOERR 37
VSSD5 36
SSYNC 35
FSYNC 34
VDDD5 33
PDIERR 32
VSSD4 31
PDICLK 30
VDDD4 29
PDIVAL 28
PDI0 27
PDISYNC 26
41 PDOCLK
VSSD3 25
VDDD3 24
MGU088
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
FUNCTIONAL DESCRIPTION
Fine AGC
The internal architecture of the TDA8961 basically
comprises two parts:
The fine AGC section controls the gain of analog signals
over a range of ±20 dB.
• The front-end: containing the AGC, carrier recovery,
half Nyquist filter, symbol timing recovery, sync recovery
and adaptive equalization sections.
The level of the signal at pins ADIN9 to ADIN0 is
monitored and an average level from several samples is
acquired. The default number of samples is 64, but this
value can be set to 256 by setting I2C-bus
bit AGC_SAMPLES (see Table 10). A comparator
compares the level of the filtered signal with a threshold
level represented by a signed four-bit value set by I2C-bus
bits AGC_TR_LOW. The comparator output determines
the level at pin AGCOUT which is used to either charge or
discharge an off-chip ideal integrator, which in turn,
controls the gain of the tuner front-end module.
• The back-end: containing the NTSC co-channel
rejection filter, trellis decoder, de-interleaver, the Reed
Solomon decoder and de-randomizer sections.
Sample rate converter
INTRODUCTION
The sample rate converter section changes the incoming
data frequency of 36 MHz to an internal sampling
frequency of twice the symbol rate.
To make the level at pin AGCOUT compatible with the
AGC circuits in other devices, the comparator output can
be inverted by setting I2C-bus bit AGC_DIR (see
Table 10). The default value of bit AGC_DIR is 0 making
the output at pin AGCOUT compatible with the AGC circuit
in the TDA8980. The levels at pin AGCOUT with respect
to the value of bit AGC_DIR are shown in Table 2.
The 10-bit wide data from either the TDA8980 or a
stand-alone A/D converter (TDA8763A is recommended)
arrives at the sample rate converter input of the TDA8961
via inputs ADIN9 to ADIN0. The format of the incoming
samples can be programmed by the status of I2C-bus
bit AD_FMT (see Table 9). The format can be either two’s
complement or binary. The default setting is binary to
comply with the TDA8980.
The AGC section can be reset by setting I2C-bus
bit AGC_RESET (see Table 8).
PINNING
The functions of the input interface pins are given in
Table 1. If a stand-alone A/D converter is used, pin CLK36
is connected externally to pin ADCLK.
Table 1
Input interface
NAME
ADIN9 to ADIN0
FUNCTION
10-bit data input (from external A/D converter)
ADCLK
36 MHz clock signal input
CLK36
clock signal output for sampling incoming data (to external A/D converter)
Table 2
AGC
COMPARATOR OUTPUT
I2C-bus
bit AGC_DIR
Pin AGCOUT
Above threshold
1
0
1
Below threshold
0
0
0
Above threshold
1
1
0
Below threshold
0
1
1
Equal to threshold
Z
0
Z
FILTER OUTPUT LEVEL
2000 May 19
11
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
Carrier recovery
CONTROL
The carrier recovery circuit recovers the frequency and
phase of the pilot carrier signal. If, as in some cases, the
pilot signal is present at the higher edge of the VSB
spectrum, the I2C-bus bit CR_INV can be set to ensure
that when the frequency is shifted, the pilot signal is DC.
An integrated sophisticated finite state machine controls
the sequence of operations that must be performed to
correctly decode a valid VSB data signal into an MPEG-2
packetized transport stream.
After a reset has been applied, the finite state machine is
in state 0. When a valid VSB data signal is detected, the
finite state machine ensures that the following three states
occur.
Half Nyquist filtering
The half Nyquist filtering section is a square-root
raised-cosine filter with 11.5% roll-off.
State 1: channel acquisition
Sync recovery
The sync recovery section performs several functions
including the recovery of segment sync and field sync.
When this section detects the data segment sync signal,
pin LOCKINDIC goes HIGH. The status of
pin LOCKINDIC can also be read via the I2C-bus
bit LOCK_INDICATOR (see Table 16).
In this state there is either no channel signal present or a
channel signal is in the process of being acquired. Before
the channel signal can be acquired, the AGC, timing
recovery and carrier recovery loops must first lock onto it.
If segment sync lock is lost, either pin LOCKINDIC goes
LOW, or a hardware reset is applied to the TDA8961 and
the finite state machine returns to state 0.
Timing recovery
State 2: equalizer training
The timing recovery section takes signals from the half
Nyquist filter and forms part of a closed loop in order to
acquire and maintain a constant sampling rate and clock
frequency for the complete system.
The finite state machine remains in state 1 until the MSE
of the equalized training sequence falls between two
specific threshold values. It should be noted that in state 1,
the back-end section of the TDA8961 is continuously reset
to make sure that after its demodulator has locked onto a
signal, the trellis decoder and the following sections begin
processing at the start of the next complete data field.
The value of I2C-bus bit MSE can be used for applications
such as antenna pointing.
Adaptive equalizer
The adaptive equalizer comprises a forward filter and a
feedback filter section. At every symbol period, it receives
demodulated symbols from the sync recovery section.
The equalizer filters these symbols in an attempt to
eliminate the effects of multipath conditions on the symbol
stream during transmission. The coefficients of the filters
are updated every symbol period using the training
sequence and/or using blind equalization if required.
State 3: normal operation
Normally the finite state machine remains in state 2 unless
a synchronization error occurs. If the MSE of the equalized
training sequence exceeds 100 ms, the equalizer is reset
for one symbol period and the adaptation process restarts.
The equalizer is designed to correct a maximum pre-echo
of 2.32 µs and a maximum post-echo of 22.5 µs.
The equalizer has an optimized typical acquisition time of
12 training sequences, which corresponds to about
290 ms. It is defined that acquisition occurs when the
output signal-to-noise ratio reaches the Threshold Of
Visibility (TOV). For 8-VSB, the ATSC defines a TOV of
14.9 dB.
If the demodulator synchronization and equalization are
both locked, pin EQLOCKINDIC goes HIGH and I2C-bus
bit LOCK_INDICATOR is set to 11 (see Table 16).
The filtered output signal is then routed to the NTSC
co-channel interference filter.
NTSC co-channel interference filter
A Mean Square Error (MSE) signal is generated based on
the training signal and on the output of the equalizer.
The error signal represents a 16-bit value which is read via
the I2C-bus bit MSE (see Table 18) and used to monitor
the channel adaptation process.
The NTSC co-channel interference filter uses patented
Philips’ technology making its performance considerably
better than the ATSC specified comb filter. The filter can
be bypassed by setting I2C-bus bit FLT_BYPASS (see
Table 13).
It is possible to use software control to extend the range of
the feedback filter to a maximum of 80 µs.
2000 May 19
12
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
when used with DVB devices, the parity bytes are
transferred; when used with non-DVB devices, zeroed
parity bytes and field sync data are transferred.
Transport stream interface
INTRODUCTION
The transport stream interface performs the following
functions:
The period when the PDOVAL signal is LOW can vary, but
will be a minimum of ten PDOCLK cycles. Due to the
averaging operation of the FIFO, the number of parity
bytes transferred can vary slightly. The PDOCLK signal
runs continuously and is not affected by a reset. In parallel
output format, it has a frequency of 3 MHz.
• Buffers the data from the Reed Solomon decoder and
de-randomizer section
• Inserts the MPEG sync byte at the start of every packet
• Indicates error conditions using a
transport_error_indicator bit in the packet header and
the error signal output PDOERR.
• Outputs either a serial or a parallel output format.
When the TDA8961 is trying to acquire a channel, the
PDOERR signal goes HIGH (I2C-bus bit FPBP = 1). If this
occurs, the PDOVAL signal stays LOW.
PINNING
SERIAL OUTPUT FORMAT
The functions of the transport stream interface outputs are
summarized in Table 3. It should be noted that different
source decoder devices may have different uses for the
PDOERR output; its polarity is programmable using
I2C-bus bit FPBP (see Table 14).
Figure 6 shows the timing diagram for the serial output
format. The LSB of the 8-bit PDO data bus is used to
output the MPEG-2 transport stream packets.
The PDOSYNC signal indicates the occurrence of the
sync byte in the packet and is only HIGH during
8 PDOCLK cycles. The polarity of the PDOVAL and
PDOERR signals is programmable via I2C-bus bits FDVP
and FPBP respectively; Fig.6 shows their default
polarities.
PARALLEL OUTPUT FORMAT
Figure 5 shows the timing diagram for the parallel output
format. The PDOSYNC signal indicates the occurrence of
the sync byte in the packet and is only HIGH for one clock
period. The polarity of the PDOVAL and PDOERR signals
is programmable via I2C-bus bits FDVP and FPBP
respectively; Fig.5 shows their default polarities.
The PDOVAL signal is active for the duration of the
188 bytes of the transport stream packet. When the
188 bytes have been transferred, the PDOVAL signal
goes LOW for a period corresponding to the duration of the
parity and field sync information. Figure 6 shows the
PDOERR signal is HIGH for the whole packet length
indicating that the packet contains errors. The PDOCLK
signal has a frequency of 27 MHz.
The PDOVAL signal is active for the duration of the
188 bytes of the transport stream packet. When the
188 bytes have been transferred, the PDOVAL signal
goes LOW for at least ten PDOCLK cycles during which,
Table 3 Transport stream interface outputs
All pins are 3-state outputs.
SYMBOL
FUNCTION
PDOCLK
clock signal for MPEG-2 packet data bytes (parallel and serial)
PDOVAL
indicates a valid data signal
PDO7 to PDO0
packet data bits 7 to 0 (8-bit wide output bus)(1)
PDOSYNC
indicates the start of a packet; goes HIGH at the start of a packet and stays HIGH during the first
byte, otherwise known as the sync byte
PDOERR
indicates packet error; goes HIGH (I2C-bus bit FPBP = 1) for every packet (188 bytes) in which the
Reed Solomon decoder found more errors than it could correct
Note
1. In serial output format, only pin PDO0 (LSB) is used to output the data.
2000 May 19
13
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
handbook, PDOCLK
full pagewidth
PDO7 to
PDO0
(1)
20
1
2
186
(2)
187
(2)
(2)
(2)
(1)
1
PDOSYNC
PDOVAL
(3)
PDOERR
(3)
MGU090
(1) Sync byte.
(2) Parity byte; contents set to 00H.
(3) The polarity of these signals is programmable.
Fig.5 Parallel output format.
handbook,
full pagewidth
PDOCLK
PDO0
MSB
6
5
PDOSYNC
(1)
PDOVAL
(2)
PDOERR
(2)
LSB
7
6
0
0
7
7
6
0
7
0
MGU091
sync byte (47H)
byte 1
byte 187
(1) Sync byte.
(2) The polarity of these signals is programmable.
Fig.6 Serial output format.
2000 May 19
14
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
SYNC BYTE AND TRANSPORT STREAM ERROR INDICATOR
SERIAL TRANSPORT STREAM INPUT
Figure 7 shows the structure of the so-called transport
stream packet header of which only the first two bytes are
significant to the TDA8961. The first byte in each header is
the sync byte which must have the same value for all
packets in accordance with the MPEG-2 standard
specification. The TDA8961 sets the sync byte for each
outgoing transport stream packet to 47H. The MSB of the
second byte in the header is the
transport_error_indicator bit. It is asserted when the Reed
Solomon decoder is unable to correct all errors in the
transport stream packet and indicates that the packet
contains invalid data.
The TDA8961 can be used with another channel decoder
without requiring the transport stream outputs from either
decoder to be selected by an external switch. This
configuration requires the serial transport stream output
from the other channel decoder to be connected to the
serial transport stream input of the TDA8961. When the
system requires the transport stream from the other
channel decoder, the TDA8961 internally connects
PDIERR to PDOERR, PDIVAL to PDOVAL, PDICLK to
PDOCLK, PDISYNC to PDOSYNC and PDI0 to PDO0
allowing the transport stream from the other channel
decoder to pass through the TDA8961. This pass-through
mode is enabled by setting the value of I2C-bus TSMODE
bits to 11 (see Table 14).
To perform bit error rate (BER) measurements, the
external channel decoder generates a pseudo-random bit
sequence (PRBS) in the last 187 bytes of each transport
stream packet.The same PRBS signal is generated within
the BER tester which compares it with the PRBS in each
transport packet and records any mismatch as an error.
It should be noted that during BER measurements, the
TDA8961 must not be allowed to set the
transport_error_indicator bit. This option is possible using
I2C-bus bit FTEI (see Table 14). If bit FTEI is not set, the
transport error interface bit is not allowed to indicate an
error. If bit FTEI is set, the Reed Solomon decoder is
allowed to set the transport_error_indicator bit according
to the result of the error correction process. This is the
default setting.
ITU656 BYPASS MODE
Figure 1 shows the tuner output connected to the
TDA8980 which processes the IF and then outputs an 8-bit
wide MPEG-2 transport stream to the TDA8961 where it is
further processed before it is output to the video processor.
This arrangement allows one system to receive both
analog and digital broadcasts. When analog signals are
received, the TDA8980 supplies an ITU656 format video
stream to the TDA8961 input interface comprising
pins ADIN9 to ADIN0 and ADCLK. The ITU656 format
uses 8-bit data and a 27 MHz clock signal.
188 bytes
handbook, full pagewidth
adaptation field
(if present)
payload
(if present)
transport packet header
0
1
0
0
0
1
1
1
1st byte
sync byte
4th byte
MSB
LSB
transport_error_indicator
MGR605
Fig.7 Transport packet header structure.
2000 May 19
15
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
EXTERNAL INTERFACE
Pins PDO0 to PDO7 and PDOCLK are normally part of the
transport stream output interface. The signals to these
pins are normally routed via an internal multiplexer.
However, in the ITU656 bypass mode, these pins connect
directly to the lower 8 bits of ADIN9 to ADIN0 and ADCLK.
In this mode, PDOSYNC and PDOVAL are kept LOW and
the polarity of PDOERR depends on the setting of I2C-bus
bit FPBP. If required, these transport stream interface
outputs can be forced to 3-state mode by making I2C-bus
bit TSO = 0 (see Table 14).
The TAP external interface has five pins whose functions
are described in Table 4.
Table 4
TAP external interface
SIGNAL
ITU656 bypass mode is enabled by setting the
I2C-bus TSMODE bits to 10.
DESCRIPTION
TMS
Test mode select input
TCK
Test clock signal input
TDI
Test data input
TDO
Test data output
TRST
Test asynchronous reset input
SEGMENT ERROR COUNTER
I2C-bus interface
The TDA8961 transport stream output interface is able to
calculate the Segment Error, or packet error, Rate (SER)
over a certain time period. The time period can be set to
either 1, 4, 8 or 16 seconds by the I2C-bus bits SERTM
(see Table 14). The IC counts any packet errors occurring
in the set time period. At the end of the time period, the
16-bit value representing the counted number of packet
errors can be read via I2C-bus bit SER (see Table 19).
The I2C-bus interface writes control information to, and
reads low-speed diagnostic information from the
TDA8961. The key features of the I2C-bus interface are:
• I2C-bus data rate of up to 400 kbits/s
• Support for only 7-bit addressing and the ability to
externally modify the slave address.
A typical system using the I2C-bus interface is shown in
Fig.8. The TDA8961 is acting as a slave and is connected
to a master via the I2C-bus lines SCL and SDA. It should
be noted that the SCL and SDA lines are connected to
separate pull-up resistors.
After a reset, the register value is set to 12935 (3287H)
which is equivalent to an infinite SER. The TDA8961 is
able to automatically reset itself when the SER exceeds a
preset threshold value. The SER threshold is a 14-bit value
programmable in the range 3 to 13000 represented by
I2C-bus bits SER_THRES (see Table 14).
It should be noted that the time period set by the
SERTM bits should be long enough to allow this threshold
to be reached. This reset function is enabled by setting
I2C-bus bit SER_RST (see Table 14). The reset function is
disabled by default.
VDD
handbook, halfpage
I2C-BUS
MASTER
TDA8961
Rpu
Rpu
Boundary scan interface
SCL
The TDA8961 TAP conforms to the IEEE 1149.1 (JTAG)
standard. It is used for board-level testing and for internally
testing integrated circuits. The JTAG standard defines the
on-chip test logic which comprises an instruction register,
a group of test data registers including a bypass register
and a boundary scan register, four dedicated pins
comprising the TAP, and a TAP controller.
2000 May 19
SDA
MGU089
Fig.8 Typical I2C system implementation.
16
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
A write operation is shown in Fig.9. The master transmitter
sends a START condition followed by the 7-bit slave
address which is followed by bit R/W set to 0. The slave
receiver (TDA8961) responds by sending an
acknowledge. The master then sends write data starting at
address zero. If the master sends more than one byte of
write data, the TDA8961 automatically increments to the
next address. The TDA8961 sends an acknowledge after
it receives each byte. If the TDA8961 does not
acknowledge the data transfer and/or the master sends a
STOP condition, the data transfer stops. It should be noted
that the TDA8961 does not support I2C-bus
sub-addressing. Therefore, each I2C-bus transfer starting
with the transmission of the slave address and bit R/W,
starts at address zero.
EXTERNAL INTERFACE
I2C-bus
The
external interface has three pins whose
functions are described in Table 5.
Table 5
I2C-bus external interface
SIGNAL
DESCRIPTION
SDA
I2C-bus
serial data input/output
SCL
I2C-bus
clock input
A0
I2C-bus slave address input bit 0
A1
I2C-bus slave address input bit 1
The TDA8961 I/O and I2C-bus signals range between
ground and 3.3 V. Systems that have devices which
operate at different supply voltages may require special
circuitry to allow these devices to communicate and to be
controlled. Circuit requirements are described in
“Application Report AN97055” (issued Aug. 04, 1997)
available from Philips Semiconductors.
A read operation is shown in Fig.10. The master
transmitter sends a START condition followed by the 7-bit
slave address which is followed by bit R/W set to 1.
The slave receiver (TDA8961) responds by sending an
acknowledge and the value at address zero. The master
responds by sending an acknowledge. If the master
follows the acknowledge with a STOP condition, the data
transfer stops, otherwise the slave is allowed to transfer
more bytes. The slave TDA8961 automatically increments
to the next address of read data to be sent to the master.
ADDRESSING THE DEVICE
The TDA8961 must be addressed by its 7-bit (A6-A0)
slave address sent via the system I2C-bus in accordance
with the correct protocols, and with bit R/W set to either 1
(write data) or 0 (read data).
The slave address of the TDA8961 is given in Table 6.
Bits A6 to A2 are preset, but bits A1 and A0 can be set via
their corresponding external pins.
Table 6
TDA8961 slave address
A6
A5
A4
A3
A2
A1
A0
R/W
0
0
0
1
1
A1
A0
0 = write
1 = read
2000 May 19
17
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
handbook, full pagewidth
TDA8961
(1)(2)
S
(1)
SLAVE ADDRESS
(1)(3)
R/W
(4)(5)
A
(1)
DATA
(4)(5)
A
(1) (4)(5)(6)
DATA
A/A
(8)
(1)
(2)
(3)
(4)
From master to slave
S = START condition
Logic 0 (write)
From slave to master
(5)
(6)
(7)
(8)
(1)(7)
P
MGR607
A = acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
P = STOP condition
Data transferred (n bytes + acknowledge).
Fig.9 Master transmitter addressing a slave receiver with a 7-bit address (write mode).
handbook, full pagewidth
(1)(2)
S
(1)
SLAVE ADDRESS
(1)(3)
R/W
(4)(5)
(4)
A
DATA
(1)(5)
A
(4)
DATA
(8)
(1)
(2)
(3)
(4)
(5)
From master to slave.
S = START condition.
Logic 1 (read).
From slave to master.
A = acknowledge (SDA LOW).
(1)(6)
(1)(7)
A
P
MGR608
(6) A = not acknowledge (SDA HIGH).
(7) P = STOP condition.
(8) Data transferred (n bytes + acknowledge).
Fig.10 Master transmitter addressing a slave receiver with a 7-bit address (read mode).
2000 May 19
18
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I2C-bus write register overview
FUNCTION
General
settings
ADDRESS
(HEX)
D7
00
01
D6
D5
D4
D3
D2
D1
D0
EQ_RST_
DISABLE
EQ_FREEZE
EQ_RESET
BE_RESET
GNRL_RESET
INITIAL_
RESET
AGC_RESET
CR_RESET
TR_RESET
SR_RESET
02
03
04
SRC
05
AGC/
Carrier
recovery
06
AGC_
SAMPLES
AD_FMT
07
AGC_DIR
AGC_TR_LOW
Philips Semiconductors
Table 7
ATSC Digital Terrestrial TV
demodulator/decoder
2000 May 19
I2C-BUS REGISTER MAP
CR_INV
08
09
19
0A
0B
0C
0D
0E
0F
10
Equalizer
11
MSE_THR_1[15 to 8]
12
MSE_THR_1[7 to 0]
13
MSE_THR_2[15 to 8]
14
MSE_THR_2[7 to 0]
16
18
19
1A
TDA8961
17
Objective specification
15
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D7
D6
D5
D4
D3
D2
D1
D0
1B
1C
1D
1E
1F
20
21
22
23
24
Philips Semiconductors
ADDRESS
(HEX)
ATSC Digital Terrestrial TV
demodulator/decoder
2000 May 19
FUNCTION
25
26
27
28
20
29
2A
2B
2C
NTSC
co-channel
interference
filter
2D
FLT_BYPASS
2E
2F
30
31
32
33
34
FPBP
FDVP
TSO
SER_RST
PMSM
TSMODE
SERTM
SER_THRES[13 to 8]
SER_THRES[7 to 0]
TDA8961
32
FTEI
Objective specification
Transport
stream
interface
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
Table 8
TDA8961
General settings (write)
BIT NAME
BIT VALUE
INITIAL_RESET
GNRL_RESET
BE_RESET
EQ_RESET
EQ_FREEZE
EQ_RST_DISABLE
FE_RST_DISABLE
SR_RESET
AGC_RESET
TR_RESET
CR_RESET
DESCRIPTION
0
normal operation (default)
1
initial reset; note 1
0
normal operation (default)
1
general reset; note 2
0
normal operation (default)
1
backend reset
0
normal operation (default)
1
equalizer reset
0
normal operation (default)
1
equalizer adaptation freeze
0
normal operation (default)
1
equalizer reset disable
0
normal operation (default)
1
front-end reset disable
0
normal operation (default)
1
reset sync recovery section
0
normal operation (default)
1
reset input AGC
0
normal operation (default)
1
reset the timing recovery
0
normal operation (default)
1
carrier recovery reset enable
Notes
1. Operating modes and control parameters of all sections in the TDA8961 are not affected.
2. Operating modes and control parameters of all sections in the TDA8961 are reset to their initial values.
Table 9
Sample rate converter settings (write)
BIT NAME
BIT VALUE
AD_FMT
DESCRIPTION
0
two’s complement
1
binary (default)
Table 10 AGC settings (write)
BIT NAME
AGC_SAMPLES
AGC_DIR
AGC_TR_LOW
2000 May 19
BIT VALUE
DESCRIPTION
0
average over 64 samples (default)
1
average over 256 samples
0
AGC operation compatible with TDA8980 (default)
1
AGC operation compatible with TDA9819/9829
−
AGC threshold value
21
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
Table 11 Carrier recovery settings (write)
BIT NAME
CR_INV
BIT VALUE
DESCRIPTION
0
selects non-inverted spectrum; carrier at lower band-edge
1
selects inverted spectrum; carrier at higher band-edge (default)
Table 12 Equalizer settings (write)
BIT NAME
BIT VALUE
DESCRIPTION
MSE_THR_1
−
MSE loss-of-convergence threshold value 1
MSE_THR_2
−
MSE loss-of-convergence threshold value 2
Table 13 NTSC co-channel interference filter settings (write)
BIT NAME
FLT_BYPASS
BIT VALUE
DESCRIPTION
0
normal operation (default)
1
bypass NTSC co-channel interference filter
Table 14 Transport stream interface settings (write)
BIT NAME
PMSM
TSO
FDVP
FPBP
FTEI
TSMODE
SERTM
BIT VALUE
0
parallel format (default)
1
serial format
0
transport stream outputs in 3-state mode
1
transport stream outputs active (default)
0
polarity of PDOVAL is LOW during the packet length of 188 data bytes
1
polarity of PDOVAL is HIGH during the packet length of 188 data bytes
(default)
0
polarity of PDOERR goes LOW if block cannot be corrected
1
polarity of PDOERR goes HIGH if block cannot be corrected (default)
0
transport_error_indicator bit is not allowed to indicate any errors detected in
the transport stream
1
transport_error_indicator bit is allowed to indicate errors in the transport
stream which could not be corrected by the Reed Solomon decoder (default)
00
normal operation (default)
01
reserved
10
ITU656 bypass mode
11
serialized transport input (pass-through mode)
00
SER is calculated over a 1 second period (default)
01
SER is calculated over a 4 second period
10
SER is calculated over a 8 second period
11
SER is calculated over a 16 second period
SER_THRES
SER_RST
2000 May 19
DESCRIPTION
SER threshold value (used if SER_RST is set to 1)
0
normal operation (default)
1
TDA8961 is reset when the SER exceeds 2.5
22
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
Table 15 I2C-bus read registers overview
FUNCTION
ADDRESS
(HEX)
Basic
operation
00
Carrier
recovery
01
D7
D6
D5
D4
D3
D2
D1
LOCK_I
NDICAT
OR
D0
STATE
CR_OFFSET[7 to 0]
02
03
Equalizer
04
MSE[15 to 8]
05
MSE[7 to 0]
06
07
08
09
0A
Transport
stream
interface
0B
SER[15 to 8]
0C
SER[7 to 0]
IC version(1)
0D
TYPE[3 to 0]
VERSION[3 to 0]
Note
1. This register allows the type and version of the TDA8961 to be read by the controlling host. The TYPE[3 to 0] field
contains 1H corresponding to the TDA8961. The VERSION[3 to 0] field contains EH corresponding to the TDA8961
version N1E. Philips Semiconductors reserves the right to change the values in this register for future versions of the
TDA8961.
Table 16 General (read)
BIT NAME
BIT VALUE
STATE
LOCK_INDICATOR
DESCRIPTION
01
state 1 (channel acquisition)
10
state 2 (equalizer training)
11
state 3 (normal operation)
01
channel acquisition: no synchronization; equalization locked
10
equalizer training: synchronization locked; no equalization
11
normal operation: synchronization locked; equalization locked
Table 17 Carrier recovery (read)
BIT NAME
CR_OFFSET
BIT VALUE
−
DESCRIPTION
Carrier recovery offset value
Table 18 Equalizer (read)
BIT NAME
MSE
2000 May 19
BIT VALUE
−
DESCRIPTION
Equalizer mean square error value
23
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
Table 19 Transport stream interface (read)
BIT NAME
BIT VALUE
−
SER
DESCRIPTION
segment error rate value
Table 20 TDA8961 version (read)
BIT NAME
BIT VALUE
DESCRIPTION
TYPE
0001
1H = TDA8961
VERSION
1110
EH = TDA8961 version N1E
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDD
supply voltage
3.0
3.6
V
VI
input voltage on any pin with
respect to ground (VSS)
−0.5
VDD + 0.5
V
II
DC current into any input
−
tbf
mA
IO
DC current out of any output
−
tbf
mA
Tj
junction temperature
0
125
°C
Tstg
storage temperature
−
−
°C
Tamb
ambient temperature
−20
+70
°C
Ptot
total power dissipation
−
−
W
Ves
electrostatic handling
note 1
±2000
±4000
V
note 2
±200
±400
V
Notes
1. Human body model: 2000 V (typical); C = 100 pF; R = 1.5 kΩ; 3 zaps positive and 3 zaps negative.
2. Machine model: 200 V (typical); C = 200 pF; L = 0.5 µH; R = 10 Ω; 3 zaps positive and 3 zaps negative.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
in free air
QUALITY SPECIFICATION
In accordance with quality specification: “SNW-FQ-611W”.
2000 May 19
24
VALUE
UNIT
43
K/W
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
DC CHARACTERISTICS
VDD = 3.3 V; VSS = 0 V; Tamb = 25 °C; unless otherwise specified; note 1.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
supply voltage
2.7
3.3
3.6
V
IDD
supply current
−
390
−
mA
VIL
LOW-level input voltage
−
−
0.2VDD
V
Inputs
VIH
HIGH-level input voltage
2.0
−
−
V
ILI
input leakage current
−
−
1
µA
Ci
input capacitance
−
−
25
pF
VOL
LOW-level output voltage
−
−
0.4VDD
V
VOH
HIGH-level input voltage
0.85VDD
−
−
V
IOL
LOW-level output current
−
−
4
mA
Outputs
3-state outputs (pins AGCOUT, PDO7 to 0, PDOCLK, PDOSYNC, PDOVAL and PDOERR)
IO(Z)
high-impedance output current
−
−
1
µA
CO(Z)
high-impedance output
capacitance
−
−
25
pF
−0.5
−
+0.3VDD
V
I2C-bus (pins SDA and SCL)
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
0.7VDD
−
VDD + 0.5
V
VOL
LOW-level output voltage
0
−
0.4
V
VOH
HIGH-level output voltage
−
−
VDD
V
note 2
IOL
LOW-level output current
VOL = 0.4 V
3
−
−
mA
IL
leakage current
VI = VSS or VDD
−
−
±10
µA
Ci
input capacitance
VI = VSS
−
−
8
pF
Notes
1. All supply connections must be made to the same external power supply unit.
2. Open drain output, determined by VDD via an external pull-up resistor.
2000 May 19
25
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
AC CHARACTERISTICS
VDD = 3.3 V; VSS = 0 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System clock (pin XTALI)
fclk(sys)
system clock frequency
note 1
−
12
−
MHz
δclk(sys)
system clock duty factor
note 1
−
50
−
%
5
−
−
ns
A/D interface (pins ADIN[9 to 0] and ADCLK); see Fig.11
tsu(A/D)
A/D interface set-up time
th(A/D)
A/D interface hold time
5
−
−
ns
Tcy(ADCLK)
ADCLK cycle time
27.8
−
−
ns
Transport stream interface (pins PDOCLK, PDO[7 to 0], PDOSYNC, PDOERR and PDOVAL)
tPDOCLKL(par)
transport stream interface
notes 2 and 3
PDOCLK LOW time; parallel format
166.7
−
−
ns
tPDOCLKH(par)
transport stream interface
PDOCLK HIGH time;
parallel format
notes 2 and 3
166.7
−
−
ns
Tcy(PDOCLK)(par) transport stream interface
notes 2 and 3
PDOCLK cycle time; parallel format
333.3
−
−
ns
tPDOVALH(par)
transport stream interface PDOVAL notes 3 and 4
HIGH time; parallel format
62666.7
−
−
ns
tPDOVALL(par)
transport stream interface PDOVAL note 3
LOW time; parallel format
−
−
−
ns
td(o)(par)
delay between transport stream
interface outputs PDO to PDOVAL,
PDOERR and PDOSYNC;
parallel format
note 3
0
−
−
ns
tPDOCLKL(ser)
transport stream interface
PDOCLK LOW time; serial format
notes 5 and 6
18.5
−
−
ns
tPDOCLKH(ser)
transport stream interface
PDOCLK HIGH time; serial format
notes 5 and 6
18.5
−
−
ns
Tcy(PDOCLK)(ser) transport stream interface
PDOCLK cycle time; serial format
notes 5 and 6
37.0
−
−
ns
tPDOSYNCH(ser)
transport stream interface
PDOSYNC HIGH time;
serial format
note 5
296.3
−
−
ns
tPDOVALH(ser)
transport stream interface PDOVAL notes 5 and 7
HIGH; serial format
55703.7
−
−
ns
tPDOVALL(ser)
transport stream interface PDOVAL note 5
LOW; serial format
−
−
−
ns
td(o)(ser)
delay between transport stream
interface outputs PDO to PDOVAL,
PDOERR and PDOSYNC;
serial format
0
−
−
ns
2000 May 19
note 5
26
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
SYMBOL
PARAMETER
TDA8961
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I2C-bus (pins SDA and SCL); see Fig.15
fSCL
SCL clock frequency
0
−
400
kHz
tBUF
bus free time between a STOP and
START condition
1.3
−
−
ms
tHD;STA
hold time for a repeated START
condition; after this period the first
clock pulse is generated
0.6
−
−
ms
tLOW
LOW period of the SCL clock
1.3
−
−
ms
tHIGH
HIGH period of the SCL clock
0.6
−
−
ms
tSU;STA
set-up time for a repeated START
condition
0.6
−
−
ms
tSU;STO
set-up time for STOP condition
0.6
−
−
ms
tHD;DAT
data hold time
0
−
0.9
ms
tSU;DAT
data set-up time
100
−
−
ns
tSP
pulse width of spikes which must
be suppressed by the input filter
tbf
−
tbf
ns
tr
rise time of both SDA and SCL
signals
20 + 0.1Cb
−
300
ns
tf
fall time of both SDA and SCL
signals
20 + 0.1Cb
−
300
ns
Cb
capacitive load for each bus line
−
−
400
pF
note 8
JTAG interface (pins TDO, TDI, TCK, TMS and TRST); see Fig.14
td(TCK-TDO)
pin TCK to TDO valid delay
2
−
10
ns
tsu(i)(TCK)
input set-up time to TCK
10
−
−
ns
th(i)(TCK)
input hold time from TCK
2
−
−
ns
23
−
−
ns
Reset (pin RST_AN)
tsu(PO)L
power-on set-up time LOW
Notes
1. The system clock signal is supplied by either an external 12 MHz crystal or another device such as the TDA8980
generating a stable 12 MHz clock signal.
2. When used for parallel format, the frequency of PDOCLK is 3 MHz.
3. See the timing measurement conditions in Fig.12.
4. This is calculated by multiplying 188 bytes (the length of a packet) by the PDOCLK clock cycle period.
5. See the timing measurement conditions in Fig.13.
6. When used for serial format, the frequency of PDOCLK is 27 MHz.
7. This is calculated by multiplying 188 bytes (the length of a packet) by the PDOCLK clock cycle period, multiplied by 8.
8. Cb = total capacitance of one bus line in pF.
2000 May 19
27
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
Tcy(ADCLK)
handbook, full pagewidth
ADCLK
t su(A/D)
t h(A/D)
valid
ADIN9 to ADIN0
MGU092
Fig.11 A/D interface timing.
handbook, full pagewidth
Tcy(PDOCLK)(par)
PDOCLK
t PDOCLKL(par)
t PDOCLKH(par)
PDOSYNC
| t d(o)(par)|
PDOVAL
t PDOVALH(par)
t PDOVALL(par)
PDOERR
PDO7 to
PDO0
47H
MGU093
Fig.12 Transport stream interface timing (parallel output format).
2000 May 19
28
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
Tcy(PDOCLK)(ser)
handbook, full pagewidth
PDOCLK
t PDOCLKL(ser)
t PDOCLKH(ser)
PDOSYNC
| t d(o)(ser)|
t PDOSYNCH(ser)
PDOVAL
t PDOVALH(ser)
t PDOVALL(ser)
PDOERR
PDO0
0
1
0
0
1
1
1
1
MGU094
Fig.13 Transport stream interface timing (serial output format).
handbook, full pagewidth
TCK
t d(TCK-TDO)
t su(i)(TCK)
t h(i)(TCK)
valid
TDO
MGU095
Fig.14 JTAG I/O timing.
2000 May 19
29
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Philips Semiconductors
ATSC Digital Terrestrial TV
demodulator/decoder
2000 May 19
SDA
t LOW
t BUF
tr
tf
t HD;STA
t SP
30
SCL
S
t SU;DAT
t HIGH
t SU;STA
MBC611
P
Objective specification
Fig.15 I2C-bus timing diagram.
t SU;STO
Sr
TDA8961
P = STOP condition.
S = START condition.
Sr = repeated START condition.
t HD;DAT
handbook, full pagewidth
t HD;STA
P
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
PACKAGE OUTLINE
QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT318-2
c
y
X
64
A
41
40
65
ZE
e
E HE
A
A2
(A 3)
A1
θ
wM
pin 1 index
Lp
bp
80
L
25
detail X
24
1
wM
bp
e
ZD
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
3.2
0.25
0.05
2.90
2.65
0.25
0.45
0.30
0.25
0.14
20.1
19.9
14.1
13.9
0.8
24.2
23.6
18.2
17.6
1.95
1.0
0.6
0.2
0.2
0.1
Z D (1) Z E (1)
1.0
0.6
1.2
0.8
θ
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT318-2
2000 May 19
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
97-08-01
99-12-27
MO-112
31
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
2000 May 19
32
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
BGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(1)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2000 May 19
33
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
DATA SHEET STATUS
DATA SHEET STATUS
PRODUCT
STATUS
DEFINITIONS (1)
Objective specification
Development
This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification
Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
DEFINITIONS
DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2000 May 19
34
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV
demodulator/decoder
TDA8961
NOTES
2000 May 19
35
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Internet: http://www.semiconductors.philips.com
SCA 69
© Philips Electronics N.V. 2000
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Printed in The Netherlands
753504/01/pp36
Date of release: 2000
May 19
Document order number:
9397 750 06769