INTEGRATED CIRCUITS DATA SHEET UDA1328T Multi-channel filter DAC Preliminary specification Supersedes data of 1999 Oct 12 File under Integrated Circuits, IC01 2000 Jan 04 Philips Semiconductors Preliminary specification Multi-channel filter DAC UDA1328T CONTENTS 10 LIMITING VALUES 11 HANDLING 12 THERMAL CHARACTERISTICS 13 QUALITY SPECIFICATION 14 DC CHARACTERISTICS 15 AC CHARACTERISTICS (ANALOG) 1 FEATURES 1.1 1.2 1.3 1.4 General Multiple format input interface Multi-channel DAC Advanced audio configuration 2 APPLICATIONS 16 AC CHARACTERISTICS (DIGITAL) 3 GENERAL DESCRIPTION 17 APPLICATION INFORMATION 4 ORDERING INFORMATION 18 PACKAGE OUTLINE 5 QUICK REFERENCE DATA 19 SOLDERING 6 BLOCK DIAGRAM 19.1 7 PINNING 8 FUNCTIONAL DESCRIPTION 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.7.1 8.7.2 8.7.3 8.8 8.8.1 8.8.2 System clock Application modes Interpolation filter (DAC) Digital silence detection Noise shaper Filter Stream DAC Static Mode System clock setting De-emphasis control Digital interface formats L3 mode Digital interface formats L3 address Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 9 L3 INTERFACE DESCRIPTION 9.1 9.2 9.2.1 Address mode Data transfer mode Programming the sound processing and other features Reset bit System clock frequency Data input format Quick mute Power control Feature settings Volume control Sub volume control Mute Digital silence mode De-emphasis Output polarity control 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 2000 Jan 04 19.2 19.3 19.4 19.5 2 20 DEFINITIONS 21 LIFE SUPPORT APPLICATIONS Philips Semiconductors Preliminary specification Multi-channel filter DAC 1 1.1 UDA1328T FEATURES General • 2.7 to 3.6 V power supply • 5 V tolerant TTL compatible inputs • Selectable control via L3 microcontroller interface or via static pin control • Multi-channel integrated digital filter plus non-inverting Digital-to-Analog Converter (DAC) • Supports sample frequencies between 5 and 100 kHz 2 • Digital silence detection (output) This multi-channel DAC is eminently suitable for DVD like applications in which 5.1 channel encoded signals are used. • Slave mode only applications APPLICATIONS • No analog post filtering required for DAC • Easy application. 1.2 3 The UDA1328 is a single-chip 6-channel DAC employing bitstream conversion techniques, which can be used either in L3 microcontroller mode or in static pin mode. Multiple format input interface • I2S-bus, MSB-justified and LSB-justified format compatible (in L3 mode) The UDA1328 supports the I2S-bus data format with word lengths of up to 24 bits, the MSB-justified data format with word lengths of up to 24 bits and the LSB-justified serial data format with word lengths of 16, 18, 20 and 24 bits. • I2S-bus and LSB-justified format compatible • 1fs input format data rate. 1.3 Multi-channel DAC All digital sound processing features can be controlled with the L3 interface e.g. volume control, selecting digital silence type, output polarity control and mute. Also system features such as power control, digital silence detection mode and output polarity control. • 6-channel DAC with power on/off control • Digital logarithmic volume control via L3; volume can be set for each of the channels individually • Digital de-emphasis for 32, 44.1, 48 and 96 kHz fs via L3 and, for 32, 44.1 and 48 kHz in static mode Under static pin control, via static pins, the system clock can be set to either 256fs or 384fs support, digital de-emphasis can be set, there is digital mute and the digital input formats can also be set. • Soft or quick mute via L3 • Output signal polarity control via L3 microcontroller interface. 1.4 GENERAL DESCRIPTION Advanced audio configuration • 6-channel line output (under L3 volume control) • A stereo differential output (channel 1 and channel 2) for improved performance • High linearity, wide dynamic range, low distortion. 4 ORDERING INFORMATION TYPE NUMBER UDA1328T 2000 Jan 04 PACKAGE NAME SO32 DESCRIPTION plastic small outline package; 32 leads; body width 7.5 mm 3 VERSION SOT287-1 Philips Semiconductors Preliminary specification Multi-channel filter DAC 5 UDA1328T QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA analog supply voltage VDDD digital supply voltage IDDA analog supply current IDDD Tamb 2.7 3.3 3.6 V 2.7 3.3 3.6 V − 28 − mA digital supply current − 11 − mA ambient temperature −40 − +85 °C − 2 − V fs = 48 kHz − −95 −88 dB fs = 96 kHz − −90 − dB fs = 48 kHz − −46 − dB fs = 96 kHz − −44 − dB fs = 48 kHz − 106 − dB fs = 96 kHz − 104 − dB − 1 − V fs = 48 kHz − −90 −83 dB fs = 96 kHz − −85 − dB fs = 48 kHz − −43 − dB fs = 96 kHz − −41 − dB fs = 48 kHz − 103 − dB fs = 96 kHz − 101 − dB − 100 − dB 6 channels active DAC: channels 1 and 2 differential Vo(rms) output voltage (RMS value) notes 1 and 2 (THD + N)/S total harmonic distortion plus noise-to-signal ratio at 0 dB at −60 dB; A-weighted S/N signal-to-noise ratio code = 0; A-weighted DAC: channels 3 to 6 (channels 1 and 2 non-differential) Vo(rms) output voltage (RMS value) note 1 (THD + N)/S total harmonic distortion plus noise-to-signal ratio at 0 dB at −60 dB; A-weighted S/N αcs signal-to-noise ratio code = 0; A-weighted channel separation Notes 1. The output voltage scales proportionally with the power supply voltage. 2. In this case the two outputs per channel (for channels 1 and 2) are combined. 2000 Jan 04 4 Philips Semiconductors Preliminary specification Multi-channel filter DAC 6 UDA1328T BLOCK DIAGRAM handbook, full pagewidth VDDD VSSD 21 20 9 UDA1328T 23 BCK WS DATAI12 DATAI34 DATAI56 10 24 11 12 CONTROL INTERFACE DIGITAL INTERFACE 13 25 18 19 17 14 26 VOLUME/MUTE/DE-EMPHASIS STATIC MUTE DEEM1 DEEM0 L3CLOCK L3DATA L3MODE DS INTERPOLATION FILTER TEST1 SYSCLK VOUT1P VOUT1N 27 8 16 DAC 28 DAC 31 1 2 5 7, 15 3 30 MGR979 VDDA n.c. VSSA Fig.1 Block diagram. 2000 Jan 04 TEST2 VOUT2P VOUT2N VOUT4 DAC 4 6 TEST3 DAC DAC VOUT5 32 29 DAC VOUT3 22 6-CHANNEL NOISE SHAPER 5 Vref VOUT6 Philips Semiconductors Preliminary specification Multi-channel filter DAC 7 UDA1328T PINNING SYMBOL PIN DESCRIPTION VOUT3 1 channel 3 analog output VOUT4 2 channel 4 analog output VSSA 3 analog ground VOUT5 4 channel 5 analog output VOUT6 5 channel 6 analog output VDDA 6 analog supply voltage n.c. 7 not connected (reserved) TEST3 8 test output 3 VOUT3 1 32 VOUT2P STATIC 9 static mode/L3 mode switch input VOUT4 2 31 VOUT2N BCK 10 bit clock input WS 11 word select input DATAI12 12 data input channel 1 and 2 DATAI34 13 data input channel 3 and 4 DATAI56 14 data input channel 5 and 6 n.c. 15 not connected (reserved) SYSCLK 16 system clock: 256fs, 384fs, 512fs and 768fs handbook, halfpage L3MODE 17 L3 mode selection input L3CLOCK 18 L3 clock input L3DATA 19 L3 data input VSSD 20 VDDD VSSA 3 30 Vref VOUT5 4 29 VOUT1N VOUT6 5 28 VOUT1P VDDA 6 27 TEST1 n.c. 7 26 DS TEST3 8 25 DEEM0 UDA1328T STATIC 9 24 DEEM1 BCK 10 23 MUTE WS 11 22 TEST2 digital ground DATAI12 12 21 VDDD 21 digital supply voltage DATAI34 13 20 VSSD TEST2 22 test output 2 DATAI56 14 19 L3DATA MUTE 23 static mute control input DEEM1 24 DEEM control 1 input (static mode) DEEM0 25 L3 address select (L3 mode)/DEEM control 0 input (static mode) DS 26 digital silence detect output TEST1 27 test input 1 VOUT1P 28 channel 1 analog output P VOUT1N 29 channel 1 analog output N Vref 30 DAC reference voltage VOUT2N 31 channel 2 analog output N VOUT2P 32 channel 2 analog output P 2000 Jan 04 n.c. 15 18 L3CLOCK SYSCLK 16 17 L3MODE MGR980 Fig.2 Pin configuration. 6 Philips Semiconductors Preliminary specification Multi-channel filter DAC 8 UDA1328T 8.4 FUNCTIONAL DESCRIPTION 8.1 The UDA1328 can detect digital silence conditions in channels 1 to 6, and report this via the output pin DS. This function is implemented to allow for external manipulation of the audio signal in the absence of program material, such as muting or recorder control. System clock The UDA1328 operates in slave mode only, this means that in all applications the system must provide the system clock. The system frequency is selectable. The options are 256fs, 384fs, 512fs and 768fs for the L3 mode and 256fs or 384fs for the static mode. The system clock must be frequency-locked to the digital interface signals. An active LOW output is produced at the DS pin if the channels selected via L3 or for all channels in static mode, carries all zeroes for at least 9600 consecutive audio samples (equals 200 ms for fs = 48 kHz). The DS pin is also active LOW when the output is digitally muted either via the L3 interface or via the STATIC pin. It should be noted that the UDA1328 can operate from 5 to 100 kHz sampling frequency (fs). However in 768fs mode the sampling frequency must be limited to 55 kHz. 8.2 Application modes In static mode all channels participate in the digital silence detection. In L3 mode control each channel can be set, either to participate in the digital silence detection or not. Operating mode can be set with the STATIC pin, either to L3 mode (STATIC = LOW) or to the static mode (STATIC = HIGH). See Table 1 for pin functions in the static mode. Table 1 8.5 L3 MODE STATIC MODE L3CLOCK L3CLOCK clock select L3MODE L3MODE SF1(1) L3DATA SF0(1) MUTE X(2) MUTE DEEM1 X(2) DEEM1 DEEM0 L3ADR DEEM0 L3DATA 8.6 1. SF1 and SF0 are the Serial Format inputs (2-bit). 2. X means that the pin has no function in this mode and can best be connected to ground. Interpolation filter (DAC) The output voltage of the FSDAC scales proportionally with the power supply voltage. The digital filter interpolates from 1 to 128fs by cascading a half-band filter and a FIR filter, see Table 2. The overall filter characteristic of the digital filters is illustrated in Fig.3, and the pass-band ripple is illustrated in Fig.4. Both figures are with a 44.1 kHz sampling frequency. Table 2 8.7 CONDITION VALUE (dB) Pass-band ripple 0 to 0.45fs ±0.02 >0.55fs −55 0 to 0.45fs >114 − −3.5 Stop band Dynamic range DC gain 2000 Jan 04 Static mode The UDA1328 is set to static mode by setting the STATIC pin HIGH. The function of 6 pins of the device now get another function as can be seen in Table 1. Interpolation filter characteristics ITEM Filter stream DAC The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. No post-filter is needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. Notes 8.3 Noise shaper The 3rd-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter Stream DAC (FSDAC). Mode selection in the static mode PIN Digital silence detection 8.7.1 SYSTEM CLOCK SETTING In static mode pin 18 (L3CLOCK) is used to select the system clock setting. When pin 18 is LOW, the device is in 256fs mode, when pin 18 is HIGH the device is in 384fs mode. 7 Philips Semiconductors Preliminary specification Multi-channel filter DAC 8.7.2 UDA1328T DE-EMPHASIS CONTROL 8.8 In static pin mode the pins DEEM0 and DEEM1 control the de-emphasis mode; see Table 3. Table 3 The device is set to L3 mode by setting the STATIC pin to LOW. The device can then be controlled via the L3 microcontroller interface (see Chapter 9). De-emphasis control DEEM MODE DEEM1 DEEM0 No de-emphasis 0 0 32 kHz de-emphasis 0 1 44.1 kHz de-emphasis 1 0 48 kHz de-emphasis 1 1 8.7.3 8.8.1 • I2S-bus with data word length of up to 24 bits • MSB-justified with data word length of up to 24 bits • LSB-justified format with data word length of 16, 18, 20 or 24 bits. In static pin mode the digital audio interface formats can be selected via pin 17 (SF1) and 19 (SF0). The following interface formats can be selected (see also Table 4): 8.8.2 • LSB-justified format with data word length of 16, 20 or 24 bits. The address can be selected using pin 25 (DEEM0) in L3 mode. When pin 25 is set LOW, the address is 000100. When pin 25 is set HIGH the address is 000101. Input format selection in the static mode SF1 SF0 I2S-bus 0 0 LSB-justified 16 bits 0 1 LSB-justified 20 bits 1 0 LSB-justified 24 bits 1 1 It should be noted that the digital audio interface holds that the BCK frequency can be 64 times the WS maximum frequency, or fBCK ≤ 64 × fWS 2000 Jan 04 L3 ADDRESS The UDA1328 can be addressed via the L3 microcontroller interface using one of two addresses. This is done in order to individually control the UDA1328 and other Philips DACs or CODECs via the same L3 bus. • I2S-bus with data word length of up to 24 bits INPUT FORMAT DIGITAL INTERFACE FORMATS The following interface formats can be selected in the L3 mode: DIGITAL INTERFACE FORMATS Table 4 L3 mode 8 Philips Semiconductors Preliminary specification Multi-channel filter DAC UDA1328T MGR981 0 handbook, halfpage volume (dB) −20 −40 −60 −80 −100 40 0 80 120 160 200 f (kHz) fs = 6.14400 MHz Fig.3 Overall frequency characteristics. MGR982 −3.45 handbook, halfpage Vo (dB) −3.47 −3.49 −3.51 −3.53 0 10 20 f (kHz) fs = 6.14400 MHz Fig.4 Pass-band ripple of all filters. 2000 Jan 04 9 30 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... >=8 3 2 3 MSB B2 1 BCK DATA MSB B2 >=8 MSB INPUT FORMAT I2S WS LEFT RIGHT 16 15 1 16 B15 LSB MSB 2 15 2 1 BCK DATA MSB B2 B2 Philips Semiconductors 2 Multi-channel filter DAC 1 andbook, full pagewidth 2000 Jan 04 RIGHT LEFT WS B15 LSB LSB JUSTIFIED FORMAT 16 BITS WS LEFT RIGHT 18 17 16 15 1 18 B17 LSB MSB 2 17 16 15 2 1 BCK 10 DATA MSB B2 B3 B4 B2 B3 B4 B17 LSB LSB JUSTIFIED FORMAT 18 BITS WS LEFT 20 RIGHT 19 18 17 16 15 1 20 B19 LSB MSB 2 19 18 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B5 B6 B2 B3 B4 B5 B6 B19 LSB LSB JUSTIFIED FORMAT 20 BITS WS LEFT 23 22 21 20 RIGHT 19 18 17 16 15 2 1 24 B23 LSB MSB 23 22 21 20 19 18 17 16 15 2 1 BCK MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB MGR751 LSB JUSTIFIED FORMAT 24 BITS Fig.5 Serial interface; input formats. UDA1328T DATA Preliminary specification 24 Philips Semiconductors Preliminary specification Multi-channel filter DAC 9 UDA1328T L3 INTERFACE DESCRIPTION Table 5 The following system and digital sound processing features can be controlled in the microcontroller mode of the UDA1328: Selection of data transfer BIT 1 BIT 0 0 0 data (volume, de-emphasis, mute, digital silence mode, polarity control) 0 1 not used 1 0 status (system clock frequency, data input format, mute mode, power control) 1 1 not used • Data input format • De-emphasis for 32, 44.1, 48 and 96 kHz • Volume control: master and for individual channels • Soft or quick mute: master and for individual channels • Output polarity control: master and for individual channels • Digital silence control: master and for individual channels TRANSFER Data bits 7 to 2 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the UDA1328 is 000100 (bit 7 to bit 2) when L3ADR (DEEM0) = LOW or 000101 when L3ADR = HIGH. In the event that the UDA1328 receives a different address, it will deselect its microcontroller interface logic. • Power-down mode. The exchange of data and control information between the microcontroller and the UDA1328 is accomplished via a serial hardware interface comprising the following pins: L3DATA: microcontroller interface data line 9.2 L3MODE: microcontroller interface mode line The selection preformed in the address mode remains active during subsequent data transfers, until the UDA1328 receives a new address command. The fundamental timing of data transfers is essentially the same as in the address mode, shown in Fig.6. The maximum input clock and data rate is 64fs. All transfers are byte wise, i.e. they are based on groups of 8 bits. Data will be stored in the UDA1328 after the eighth bit of a byte has been received. A multibyte transfer is illustrated in Fig.8. L3CLOCK: microcontroller interface clock line. Information transfer via the microcontroller bus is organized LSB first and is in accordance with the so called ‘L3’ format, in which two different modes of operation can be distinguished. The address mode and data transfer mode are illustrated in Figs 6 and 7. The address mode is required to select a device communicating via the L3-bus and to define the destination registers for the data transfer mode. Data transfer for the UDA1328 can only be in one direction; input to the UDA1328 to program its sound processing and other functional features. 9.1 9.2.1 PROGRAMMING THE SOUND PROCESSING AND OTHER FEATURES The sound processing and other feature values are stored in independent registers. The first selection of the registers is achieved by the choice of data type that is transferred. This is performed in the address mode, bit 1 and bit 0 (see Table 5). The second selection is performed by the 2 MSBs of the data byte (bit 7 and bit 6). The other bits in the data byte (bit 5 to bit 0) is the value that is placed in the selected registers. Address mode The address mode is used to select a device for subsequent data transfer and to define the destination registers. The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 data bits. The fundamental timing is shown in Fig.6. Data bits 0 and 1 indicate the type of subsequent data transfer as given in Table 5. 2000 Jan 04 Data transfer mode When the data transfer of type ‘data’ is selected, the features volume, sub volume, de-emphasis, mute, digital silence settings, output polarity control and channel selection can be controlled. When the data transfer of type ‘status’ is selected, the features system clock frequency, data input format, mute mode and power control can be controlled. 11 Philips Semiconductors Preliminary specification Multi-channel filter DAC UDA1328T handbook, full pagewidth L3MODE tsu(L3)A th(L3)A tsu(L3)A tCLK(L3)L tCLK(L3)H th(L3)A L3CLOCK Tcy(CLK)(L3) tsu(L3)DA th(L3)DA BIT 7 BIT 0 L3DATA MGL723 Fig.6 Timing address mode. handbook, full pagewidth tstp(L3) tstp(L3) L3MODE tCLK(L3)L Tcy(CLK)L3 tCLK(L3)H tsu(L3)D th(L3)D L3CLOCK th(L3)DA tsu(L3)DA L3DATA WRITE BIT 7 BIT 0 MGL882 Fig.7 Timing for data transfer mode. 2000 Jan 04 12 Philips Semiconductors Preliminary specification Multi-channel filter DAC UDA1328T tstp(L3) handbook, full pagewidth L3MODE L3CLOCK L3DATA address data byte #1 data byte #2 address MGL725 Fig.8 Multibyte transfer. Table 6 Data transfer of type ‘status’ BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 RST SC1 SC0 IF2 IF1 IF0 0 REGISTER SELECTED ReSeT System Clock frequency (1 and 0) data Input Format (2 to 0) 1 0 0 0 0 0 QM PC Quick/soft Mute Power Control Table 7 Data transfer of type ‘data’ BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER SELECTED 0 0 VC5 VC4 VC3 VC2 VC1 VC0 Volume Control (5 to 0) 0 1 0 0 0 0 VQ1 VQ0 0.25 dB step sub volume (1 and 0) 1 0 DE2 DE1 DE0 MT DSM PLC DE-emphasis (2 to 0) MuTe Digital Silence Mode PoLarity Control 1 1 0 0 ACH CH2 CH1 CH0 All CHannels select CHannel select (2 to 0) 2000 Jan 04 13 Philips Semiconductors Preliminary specification Multi-channel filter DAC 9.2.2 UDA1328T RESET BIT 9.2.5 A 1-bit value to initialize the L3 registers with the default settings (except the system clock setting and the data input format setting) by writing a logic 1 to RST (see Table 6). QUICK MUTE A 1-bit value to set the mute mode to either soft mute (via cosine roll-off), quick or hard mute. Table 10 Quick mute The default settings after reset are as follows: QM FUNCTION • Mute mode: soft mute 0 soft mute mode • Power: on 1 quick mute mode • Volume: 0 dB • Sub volume: 0 dB 9.2.6 • De-emphasis: off A 1-bit value to disable the ADC and/or DAC to reduce power consumption. • Mute: off • Silence detect mode: detect POWER CONTROL Table 11 Power control settings • Polarity: non-inverting. 9.2.3 SYSTEM CLOCK FREQUENCY A 2-bit value (SC1 and SC0) to select the used external clock frequency (see Table 8). Table 8 System clock frequency settings SC1 SC0 FUNCTION 0 0 512fs 0 1 384fs 1 0 256fs 1 1 768fs 9.2.4 9.3 IF2 1 all channels on Feature settings • Mute • Output polarity control • Digital silence detect. When a ‘per-channel’ setting is required for these features, the ACH bit (see Table 7) must be set to logic 0 before writing a new value to one of the features. Once this has been performed a channel is selected via the CH2 to CH0 bits. The features for this channel can be controlled without sending the same channel address again (low microcontroller mode). FUNCTION 0 0 0 I2S-bus 0 0 1 LSB-justified; 16 bits 0 1 0 LSB-justified; 18 bits 0 1 1 LSB-justified; 20 bits 1 0 0 MSB-justified 1 0 1 LSB-justified; 24 bits 1 1 0 reserved 1 1 1 reserved 2000 Jan 04 all channels off • Sub volume control Data input format settings IF0 0 • Volume control DATA INPUT FORMAT IF1 FUNCTION In the UDA1328 there are features that can be controlled either per-channel or all at the same time. These features are: A 3-bit value (IF2 to IF0) to select the used data format (see Table 9). Table 9 PC When the ACH bit is set to logic 1, which means ‘all channels select’, all channels will be set to the same value of the feature sent afterwards. For the digital silence detector it holds that the DS pin is either active on the selected channel when bit ACH is set to logic 0 before writing the DSM bit, or the DS pin is active on all channels when the ACH bit is set to logic 1. 14 Philips Semiconductors Preliminary specification Multi-channel filter DAC 9.3.1 UDA1328T CHANNEL SELECTION MODE 9.3.3 A 1-bit value to set the selection mode (either individually or per-channel) for the volume, mute, polarity control and silence detect is given in Table 12. The 3-bit value is given in Table 13. SUB VOLUME CONTROL A 2-bit value to program the channel volume attenuation with a 0.25 dB step (VQ1 and VQ0). To validate the sub volume settings in these registers, the volume control registers of corresponding channels must be updated one after the other. Table 12 1-bit selection ACH(1) Table 15 Sub volume settings FUNCTION 0 individual channel select; use CH(2 : 0) 1 all channels selected Note 1. For setting the de-emphasis mode, the ACH bit must be set to logic 1 before setting the de-emphasis. 9.3.4 Table 13 3-bit selection VQ1 VQ0 VOLUME (dB) 0 0 0.00 0 1 −0.25 1 0 −0.50 1 1 −0.75 MUTE A 1-bit value to enable the digital mute (the type of mute is set via the QM bit in the status register). CH2 CH1 CH0 0 0 0 channel 1 selected 0 0 1 channel 2 selected 0 1 0 channel 3 selected MT FUNCTION 0 1 1 channel 4 selected 0 no muting 1 0 0 channel 5 selected 1 muting 1 0 1 channel 6 selected 1 1 0 not used 9.3.5 1 1 1 not used A 1-bit value to set the digital silence mode. This bit is set together with the channel address CH2 to CH0 and the ACH bit. 9.3.2 FUNCTION Table 16 Mute VOLUME CONTROL DIGITAL SILENCE MODE A 6-bit value to program the channel volume attenuation (VC5 to VC0). The range is 0 dB to −∞ dB in steps of 1 dB (see Table 14). When the ACH bit is set to logic 0, each channel can be selected for digital silence detection. When the ACH bit is set to logic 1 all channels are selected. Table 14 Volume settings Table 17 Digital silence mode VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB) DSM FUNCTION 0 0 0 0 0 0 0 0 no participation 0 0 0 0 0 1 0 1 participates 0 0 0 0 1 0 −1 0 0 0 0 1 1 −2 : : : : : : : 1 1 1 0 1 1 −58 1 1 1 1 0 0 −59 1 1 1 1 0 1 −60 1 1 1 1 1 0 −∞ 1 1 1 1 1 1 −∞ 2000 Jan 04 15 Philips Semiconductors Preliminary specification Multi-channel filter DAC 9.3.6 UDA1328T 9.3.7 DE-EMPHASIS A 2-bit value to enable the digital de-emphasis filter. A 1-bit value to program the output polarity of the output signal. This bit must be used together with the CH2 to CH0 bits and the ACH bit to either select the polarity for all channels or to set for each channel individually. Table 18 De-emphasis settings DE2 DE1 DE0 0 0 0 no de-emphasis 0 0 1 de-emphasis; 32 kHz 0 1 0 de-emphasis; 44.1 kHz 0 1 1 de-emphasis; 48 kHz 1 0 0 de-emphasis; 96 kHz OUTPUT POLARITY CONTROL FUNCTION Table 19 Output polarity control PLC FUNCTION 0 non-inverting 1 inverting 10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDDD digital supply voltage note 1 − 5.0 VDDA analog supply voltage note 1 − 5.0 V Txtal(max) maximum crystal temperature − 150 °C Tstg storage temperature −65 +125 °C Tamb ambient temperature −40 +85 °C Ves electrostatic handling V note 2 −3000 +3000 V note 3 −250 +250 V Notes 1. All supply connections must be made to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor, expect pin 19 (L3DATA) which can withstand ESD pulses of −2500 to +2500 V. 3. Equivalent to discharging a 200 pF capacitor via a 0.75 µH series inductor. 11 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. 12 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS thermal resistance from junction to ambient in free air VALUE UNIT 58 K/W 13 QUALITY SPECIFICATION In accordance with “SNW-FQ-611-E”. The number of the quality specification can be found in the “Quality Reference Handbook”. 2000 Jan 04 16 Philips Semiconductors Preliminary specification Multi-channel filter DAC UDA1328T 14 DC CHARACTERISTICS VDDD = VDDA = 3.3 V; Tamb = 25 °C; RL = 5 kΩ. All voltages referenced to ground (pins 3 and 20); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA analog supply voltage note 1 VDDD digital supply voltage note 1 2.7 3.3 3.6 V IDDA analog supply current all channels active; operating mode − 28 − mA IDDD digital supply current operating mode − 11 − mA 2.7 3.3 3.6 V Digital input pins: 5 V tolerant TTL compatible VIH HIGH-level input voltage 2.0 − − V VIL LOW-level input voltage − − 0.8 V VIL(th) LOW-level threshold input voltage; falling edge 0.9 − 1.45 V VIH(th) HIGH-level threshold input voltage; rising edge 1.4 − 1.9 V Vhyst Schmitt trigger hysteresis voltage 0.4 − 0.7 V ILI input leakage current − − 1 µA Ci input capacitance − − 10 pF Digital output pin VOH HIGH-level output voltage IOH = −2 mA 0.85VDDD − − V VOL LOW-level output voltage IOL = 2 mA − − 0.4 V Vref reference voltage referenced to VSSA 0.45VDDA 0.5VDDA 0.55VDDA V Io(max) maximum output current (THD + N)/S < 0.1% − 0.22 − mA RL load resistance 3 − − kΩ CL load capacitance − − 50 pF DAC note 2 Notes 1. All supply connections must be made to the same external power supply unit. 2. When the DAC drives a capacitive load above 50 pF, a series resistor of 100 Ω must be used to prevent oscillations in the output operational amplifier. 2000 Jan 04 17 Philips Semiconductors Preliminary specification Multi-channel filter DAC UDA1328T 15 AC CHARACTERISTICS (ANALOG) VDDD = VDDA = 3.3 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ. All voltages referenced to ground (pins 3 and 20); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DAC: channels 1 and 2 in differential mode Vo(rms) output voltage (RMS value) ∆Vo unbalance between channels (THD + N)/S total harmonic distortion plus noise-to-signal ratio − signal-to-noise ratio − V − 0.1 − dB − −95 −88 dB fs = 48 kHz; at −60 dB; A-weighted − −46 − dB fs = 48 kHz; at 0 dB − −90 − dB fs = 96 kHz; at −60 dB; A-weighted − −44 − dB fs = 48 kHz; code = 0; A-weighted − 106 − dB fs = 96 kHz; code = 0; A-weighted − 104 − dB fs = 96 kHz; at 0 dB S/N 2 DAC: channels 3 to 6 Vo(rms) output voltage (RMS value) − 1 − V ∆Vo unbalance between channels − 0.1 − dB (THD + N)/S total harmonic distortion plus noise-to-signal ratio − −90 −83 dB fs = 48 kHz; at −60 dB; A-weighted − −43 − dB − −85 − dB fs = 96 kHz; at −60 dB; A-weighted − −41 − dB fs = 48 kHz; code = 0; A-weighted − 103 − dB fs = 96 kHz; code = 0; A-weighted − 101 − dB fripple = 1 kHz; Vripple(p-p) = 100 mV − 50 − dB fs = 48 kHz; at 0 dB fs = 96 kHz; at 0 dB S/N PSRR 2000 Jan 04 signal-to-noise ratio power supply rejection ratio 18 Philips Semiconductors Preliminary specification Multi-channel filter DAC UDA1328T 16 AC CHARACTERISTICS (DIGITAL) VDDD = VDDA = 2.7 to 3.6 V; Tamb = −20 to +85 °C; RL = 5 kΩ. All voltages referenced to ground (pins 3 and 20); unless otherwise specified. The typical timing is specified at 44.1 kHz sampling frequency. SYMBOL Tsys tCWL tCWH PARAMETER system clock cycle CONDITIONS MIN. TYP. MAX. UNIT fsys = 256fs 35 88 780 ns fsys = 384fs 23 59 520 ns fsys = 512fs 20 44 390 ns fsys = 768fs; note 1 20 30 260 ns LOW-level system clock pulse width fsys < 19.2 MHz 30 − 70 %Tsys fsys ≥ 19.2 MHz 40 − 60 %Tsys HIGH-level system clock pulse width fsys < 19.2 MHz 30 − 70 %Tsys fsys ≥ 19.2 MHz 40 − 60 %Tsys tr rise time − − 20 ns tf fall time − − 20 ns Serial input data timing (see Fig.9) Tcy(CLK)(bit) bit clock period 140 − − ns tCLKH(bit) bit clock HIGH time 60 − − ns tCLKL(bit) bit clock LOW time 60 − − ns tr rise time − − 20 ns tf fall time − − 20 ns tsu(i)(D) data input set-up time 20 − − ns th(i)(D) data input hold time 0 − − ns tsu(WS) word selection set-up time 20 − − ns th(WS) word selection hold time 10 − − ns Microcontroller interface timing (see Figs 6, 7 and 8) Tcy(CLK)(L3) L3CLOCK time 500 − − ns tCLK(L3)H L3CLOCK HIGH time 250 − − ns tCLK(L3)L L3CLOCK LOW time 250 − − ns tsu(L3)A L3MODE set-up time addressing mode 190 − − ns th(L3)A L3MODE hold time addressing mode 190 − − ns tsu(L3)D L3MODE set-up time data transfer mode 190 − − ns th(L3)D L3MODE hold time data transfer mode 190 − − ns tsu(L3)DA L3DATA set-up time data transfer and addressing mode 190 − − ns th(L3)DA L3DATA hold time data transfer and addressing mode 30 − − ns tstp(L3) L3MODE halt time − − ns 190 Note 1. In the 768fs clock mode, the sampling frequency must be limited to 55 kHz. 2000 Jan 04 19 Philips Semiconductors Preliminary specification Multi-channel filter DAC UDA1328T handbook, full pagewidth WS th(WS) tCLKH(bit) tr tsu(WS) tf BCK tCLKL(bit) tsu(i)(D) Tcy(CLK)(bit) th(i)(D) DATAI MGL721 Fig.9 Serial interface timing. handbook, full pagewidth t CWH MGR984 t CWL Tsys Fig.10 System clock timing. 2000 Jan 04 20 Philips Semiconductors Preliminary specification Multi-channel filter DAC UDA1328T 17 APPLICATION INFORMATION AGND handbook, full pagewidth R13 100 Ω C7 47 µF (16 V) VOUT3 R14 10 kΩ AGND R15 100 Ω C8 47 µF (16 V) VOUT4 VOUT3 10 kΩ 32 1 10 kΩ VOUT2P 5 6 VOUT4 31 2 VOUT2N VSSA AGND C9 47 µF (16 V) VOUT5 R18 10 kΩ R19 100 Ω C10 47 µF (16 V) VOUT6 10 kΩ 3 30 Vref 10 kΩ C13 47 µF (16 V) C14 100 nF VOUT5 4 29 100 µF (16 V) AGND 10 kΩ 100 pF AGND VOUT1N 10 kΩ 2 47 µF 1 VOUT6 28 5 VOUT1P 1Ω 6 27 VOUT1 1/2 (16 V) NE5532 10 kΩ 100 nF VDDA 7 26 10 kΩ TEST1 AGND AGND n.c. 100 Ω 3 10 kΩ R20 10 kΩ AGND VDDA VOUT2 100 pF AGND AGND 100 Ω (16 V) 10 kΩ R16 10 kΩ R17 100 Ω 1/2 NE5532 47 µF 7 DS VDDA 3.3 V TEST3 8 25 DEEM0 BZN32A07 DEEM1 100 µF (16 V) VDDD UDA1328T STATIC/L3 STATIC 9 24 100 µF (16 V) AGND DGND BCK 10 23 MUTE ground WS DATAI12 DATAI34 DATAI56 n.c. 47 Ω SYSCLK SYSCLK 11 22 12 21 13 20 14 19 15 18 16 17 TEST2 AGND DGND 1Ω VDDD VSSD 100 nF L3DATA DGND L3CLOCK L3MODE MGR983 Fig.11 Application diagram. 2000 Jan 04 21 100 µF (16 V) VDDD Philips Semiconductors Preliminary specification Multi-channel filter DAC UDA1328T 18 PACKAGE OUTLINE SO32: plastic small outline package; 32 leads; body width 7.5 mm SOT287-1 D E A X c y HE v M A Z 17 32 Q A2 A (A 3) A1 pin 1 index θ Lp L 16 1 0 detail X w M bp e 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.27 0.18 20.7 20.3 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.2 1.0 0.25 0.25 0.1 0.95 0.55 inches 0.10 0.012 0.096 0.004 0.086 0.01 0.02 0.01 0.011 0.007 0.81 0.80 0.30 0.29 0.050 0.419 0.394 0.055 0.043 0.016 0.047 0.039 0.01 0.01 0.004 0.037 0.022 θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT287-1 2000 Jan 04 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-22 99-12-27 MO-119 22 Philips Semiconductors Preliminary specification Multi-channel filter DAC UDA1328T If wave soldering is used the following conditions must be observed for optimal results: 19 SOLDERING 19.1 Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 19.2 – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 19.3 19.4 Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. 2000 Jan 04 Manual soldering When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 23 Philips Semiconductors Preliminary specification Multi-channel filter DAC 19.5 UDA1328T Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 20 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 21 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 2000 Jan 04 24 Philips Semiconductors Preliminary specification Multi-channel filter DAC UDA1328T NOTES 2000 Jan 04 25 Philips Semiconductors Preliminary specification Multi-channel filter DAC UDA1328T NOTES 2000 Jan 04 26 Philips Semiconductors Preliminary specification Multi-channel filter DAC UDA1328T NOTES 2000 Jan 04 27 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545002/25/02/pp28 Date of release: 2000 Jan 04 Document order number: 9397 750 06677