PCA21125 SPI-bus Real-Time Clock and calendar Rev. 01 — 16 November 2009 Product data sheet 1. General description The PCA21125 is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low-power consumption and an operating temperature up to 125 °C. Data is transferred via a Serial Peripheral Interface (SPI-bus) with a maximum data rate of 6.0 Mbit/s. Alarm and timer functions are also available with the possibility to generate a wake-up signal on the interrupt pin. AEC Q100 compliant for automotive applications. 2. Features Provides year, month, day, weekday, hours, minutes, and seconds based on 32.768 kHz quartz crystal Resolution: seconds to years Clock operating voltage: 1.3 V to 5.5 V Low backup current: typical 0.55 μA at VDD = 3.0 V and Tamb = 25 °C 3-line SPI-bus with separate, but combinable data input and output Serial interface at VDD = 1.6 V to 5.5 V 1 second or 1 minute interrupt output Freely programmable timer with interrupt capability Freely programmable alarm function with interrupt capability Integrated oscillator capacitors Internal Power-On Reset (POR) Open-drain interrupt pin 3. Applications Automotive time keeping Metering 1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 17. PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 4. Ordering information Table 1. Ordering information Type number Package PCA21125T/Q900/1 Name Description Version TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 5. Marking Table 2. Marking codes Type number Marking code PCA21125T/Q900/1 PC21125 6. Block diagram OSCI OSCILLATOR 32.768 kHz DIVIDER CLKOUT CLOCK OUT OSCO COSCO CONTROL MONITOR 00h Control_1 01h Control_2 0Dh CLKOUT_control POWER-ON RESET TIME 02h Seconds VDD 03h Minutes VSS 04h Hours WATCHDOG 05h Days 06h Weekdays 07h Months 08h Years ALARM FUNCTION SDO SPI INTERFACE SDI SCL 09h Minute_alarm 0Ah Hour_alarm 0Bh Day_alarm 0Ch Weekday_alarm INT INTERRUPT CE TIMER FUNCTION Rpd PCA21125 0Eh Timer_control 0Fh Countdown_timer 013aaa217 Fig 1. Block diagram of PCA21125 PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 2 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 7. Pinning information 7.1 Pinning OSCI 1 14 VDD OSCO 2 13 CLKOUT n.c. 3 n.c. 4 INT 5 10 SCL CE 6 9 SDI VSS 7 8 SDO 12 n.c. PCA21125 11 n.c. 013aaa074 Fig 2. Pin configuration for TSSOP14 7.2 Pin description Table 3. Pin description Symbol Pin Description OSCI 1 oscillator input OSCO 2 oscillator output n.c. 3, 4 not connected; do not connect and do not use as feed through; connect to VDD if floating pins are not allowed INT 5 interrupt output (open-drain; active LOW) CE 6 chip enable input (active HIGH) with 200 kΩ pull-down resistor VSS 7 ground supply voltage SDO 8 serial data output, push-pull SDI 9 serial data input; might float when CE inactive SCL 10 serial clock input; might float when CE inactive n.c. 11, 12 not connected; do not connect and do not use as feed through; connect to VDD if floating pins are not allowed CLKOUT 13 clock output (open-drain) VDD 14 supply voltage PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 3 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 8. Functional description The PCA21125 contains 16 8-bit registers with an auto-incrementing address register, an on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency divider which provides the source clock for the RTC, a programmable clock output, and a 6 MHz SPI-bus. All 16 registers are designed as addressable 8-bit parallel registers although not all bits are implemented: • The first two registers at addresses 00h and 01h (Control_1 and Control_2) are used as control and status registers. • Registers at addresses 02h to 08h (Seconds, Minutes, Hours, Days, Weekdays, Months, Years) are used as counters for the clock function. Seconds, minutes, hours, days, months, and years are all coded in Binary Coded Decimal (BCD) format. When one of the RTC registers is read the contents of all counters are frozen. Therefore, faulty reading of time and date during a carry condition is prevented. • Registers at addresses 09h to 0Ch (Minute_alarm, Hour_alarm, Day_alarm, and Weekday_alarm) define the alarm condition. • The register at address 0Dh (CLKOUT_control) defines the clock output mode. • Registers at addresses 0Eh and 0Fh (Timer_control and Countdown_timer) are used for the countdown timer function. The countdown timer has four selectable source clocks allowing for countdown periods in the range from less than 1 ms to more than 4 hours (see Table 29). There are also two pre-defined timers which can be used to generate an interrupt once per second or once per minute. These are defined in register Control_2 (01h). PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 4 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 8.1 Register overview The time, date, and alarm registers are encoded in BCD to simplify application use. Other registers are either bit-wise or standard binary. Table 4. Register overview Bits labeled - are not implemented and will return logic 0 when read. Bit positions labeled N should always be written with logic 0. After reset, all registers are set according to Table 37. Address Register name Bit 7 6 5 4 3 2 1 0 Control and status registers 00h Control_1 EXT_TEST N STOP N POR_OVRD 12_24 N N 01h Control_2 MI SI MSF TI_TP AF AIE TIE TF Time and date registers 02h Seconds RF SECONDS (0 to 59) 03h Minutes - MINUTES (0 to 59) 04h Hours - - AMPM - - HOURS (0 to 23) in 24 hour mode HOURS (1 to 12) in 12 hour mode 05h Days - - DAYS (1 to 31) 06h Weekdays - - - - 07h Months - - - MONTHS (1 to 12) 08h Years YEARS (0 to 99) - WEEKDAYS (0 to 6) Alarm registers 09h Minute_alarm AE_M MINUTE_ALARM (0 to 59) 0Ah Hour_alarm AE_H - AMPM - HOUR_ALARM (0 to 23) in 24 hour mode HOUR_ALARM (1 to 12) in 12 hour mode 0Bh Day_alarm AE_D - DAY_ALARM (1 to 31) 0Ch Weekday_alarm AE_W - - - - WEEKDAY_ALARM (0 to 6) - - - - - COF - - - - - CLKOUT control register 0Dh CLKOUT_control Timer registers 0Eh Timer_control TE 0Fh Countdown_timer COUNTDOWN_TIMER PCA21125_1 Product data sheet CTD © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 5 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 8.2 Control and status registers 8.2.1 Register Control_1 Table 5. Bit Control_1 - control and status register 1 (address 00h) bit description Symbol Value Description Reference 7 EXT_TEST 0[1] normal mode Section 8.8 1 external clock test mode 6 N 0 unused 5 STOP 0[1] RTC source clock runs - 1 RTC clock is Section 8.9 stopped[2] 4 N 0 unused - 3 POR_OVRD 0 POR override facility is disabled; Section 8.10.1 Remark: set logic 0 for normal operation 2 12_24 1 to 0 N 1[1] POR override enabled 0[1] 24 hour mode selected 1 12 hour mode selected 0 unused Table 10 and Table 18 - [1] Default value. [2] CLKOUT at 32.768 kHz, 16.384 kHz or 8.192 kHz is still available; divider chain flip-flops are asynchronously set logic 0. 8.2.2 Register Control_2 Table 6. Bit Control_2 - control and status register 2 (address 01h) bit description Symbol Value Description Reference 7 MI 0[1] minute interrupt disabled Section 8.6.1 1 minute interrupt enabled 6 SI 0[1] second interrupt disabled 1 second interrupt enabled 0[1] no minute or second interrupt generated 1 flag set when minute or second interrupt generated 0[1] interrupt pin follows TF and MSF (see Figure 9) 1 interrupt pin generates a pulse Section 8.6 et seqq. and Section 8.7 et seqq. 0[1] no alarm interrupt generated Section 8.4.5 1 flag set when alarm triggered; 5 MSF 4 TI_TP 3 AF Section 8.6.1 Section 8.6.1 Remark: flag must be cleared to clear interrupt 2 TF 1 AIE 0 [1] TIE 0[1] no countdown timer interrupt generated 1 flag set when countdown timer interrupt generated Section 8.6 et seqq. and Section 8.7 et seqq. 0[1] no interrupt generated from alarm flag Section 8.7.3 1 interrupt generated when alarm flag set 0[1] no interrupt generated from countdown timer flag 1 interrupt generated when countdown timer flag set Section 8.7 Default value. PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 6 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 8.3 Time and date registers The majority of these registers are coded in the Binary Coded Decimal (BCD) format. BCD is used to simplify application use. An example is shown for register Seconds in Table 8. Loading these registers with values outside of the given range will result in unpredictable time and date generation (see Figure 3 “Data flow of the time function”). 8.3.1 Register Seconds Table 7. Seconds - seconds and clock integrity status register (address 02h) bit description Bit Symbol Value Description 7 RF 0 clock integrity is guaranteed 1[1] clock integrity is not guaranteed; chip reset has occurred since flag was last cleared 6 to 4 SECONDS 3 to 0 [1] 0 to 5 ten’s place 0 to 9 unit place Start-up value. Table 8. Seconds coded in BCD format Seconds value in decimal Upper-digit (ten’s place) Digit (unit place) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 0 0 0 0 0 0 0 01 0 0 0 0 0 0 1 02 0 0 0 0 0 1 0 : : : : : : : : 09 0 0 0 1 0 0 1 10 0 0 1 0 0 0 0 : : : : : : : : 58 1 0 1 1 0 0 0 59 1 0 1 1 0 0 1 8.3.2 Register Minutes Table 9. Minutes - minutes register (address 03h) bit description Bit Symbol Value Description 7 - 0 unused 6 to 4 MINUTES 0 to 5 ten’s place 0 to 9 unit place 3 to 0 PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 7 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 8.3.3 Register Hours Table 10. Hours - hours register (address 04h) bit description Bit Symbol Value Description 7 to 6 - 0 unused 0 indicates AM 1 indicates PM 0 to 1 ten’s place 0 to 9 unit place 0 to 2 ten’s place 0 to 9 unit place 12 hour mode[1] 5 AMPM 4 to 0 HOURS 3 to 0 24 hour mode[1] 5 to 4 HOURS 3 to 0 [1] Hour mode is set by bit 12_24 in register Control_1 (see Table 5). 8.3.4 Register Days Table 11. Bit Days - days register (address 05h) bit description Value Place value Description 7 to 6 - - - unused 5 to 4 DAYS[1] 0 to 3 ten’s place actual day coded in BCD format 3 to 0 0 to 9 unit place [1] Symbol The PCA21125 compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly divisible by 4, including the year 00. 8.3.5 Register Weekdays Table 12. Bit Weekdays - weekdays register (address 06h) bit description Symbol Value Description 7 to 3 - - unused 2 to 0 WEEKDAYS 0 to 6 actual weekday, values see Table 13 Table 13. Weekday assignments Day[1] Bit 2 1 0 Sunday 0 0 0 Monday 0 0 1 Tuesday 0 1 0 Wednesday 0 1 1 Thursday 1 0 0 Friday 1 0 1 Saturday 1 1 0 [1] Definition may be re-assigned by the user. PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 8 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 8.3.6 Register Months Table 14. Months - months register (address 07h) bit description Bit Symbol Value Description 7 to 5 - 0 unused 4 MONTHS 0 to 1 ten’s place 0 to 9 unit place 3 to 0 Table 15. Month assignments in BCD format Month Upper-digit (ten’s place) Digit (unit place) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 January 0 0 0 0 1 February 0 0 0 1 0 March 0 0 0 1 1 April 0 0 1 0 0 May 0 0 1 0 1 June 0 0 1 1 0 July 0 0 1 1 1 August 0 1 0 0 0 September 0 1 0 0 1 October 1 0 0 0 0 November 1 0 0 0 1 December 1 0 0 1 0 8.3.7 Register Years Table 16. Bit Years - years register (08h) bit description Symbol Value Place value Description 7 to 4 YEARS 0 to 9 ten’s place 3 to 0 0 to 9 unit place PCA21125_1 Product data sheet actual year coded in BCD format © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 9 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 8.3.8 Setting and reading the time Figure 3 shows the data flow and data dependencies starting from the 1 Hz clock tick. 1 Hz tick SECONDS MINUTES 12_24 hour mode HOURS LEAP YEAR CALCULATION DAYS WEEKDAY MONTHS YEARS Fig 3. 001aaf901 Data flow of the time function During read/write operations, the time counting circuits (memory locations 02h through 08h) are blocked. This prevents • Faulty reading of the clock and calendar during a carry condition • Incrementing the time registers during the read cycle After this read/write access is completed, the time circuit is released again and any pending request to increment the time counters that occurred during the read/write access is serviced. A maximum of 1 request can be stored; therefore, all accesses must be completed within 1 second (see Figure 4). t<1s data bus COMMAND DATA DATA DATA chip enable 013aaa222 Fig 4. Access time for read/write operations As a consequence of this method, it is very important to make a read or write access in one go, that is, setting or reading seconds through to years should be made in one single access. Failing to comply with this method could result in the time becoming corrupted. PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 10 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar As an example, if the time (seconds through to hours) is set in one access and then in a second access the date is set, it is possible that the time may increment between the two accesses. A similar problem exists when reading. A roll over may occur between reads thus giving the minutes from one moment and the hours from the next. Therefore it is advised to read all time and date registers in one access. 8.4 Alarm registers When one or several alarm registers are loaded with a valid minute, hour, day, or weekday value and its corresponding alarm enable bit (AE_x) is logic 0, then that information is compared with the current minute, hour, day, and weekday value. 8.4.1 Register Minute_alarm Table 17. Minute_alarm - minute alarm register (address 09h) bit description Bit Symbol Value Place value Description 7 AE_M 0 - minute alarm is enabled 1[1] - minute alarm is disabled 6 to 4 MINUTE_ALARM 0 to 5 ten’s place 3 to 0 0 to 9 unit place minute alarm information coded in BCD format [1] Default value. 8.4.2 Register Hour_alarm Table 18. Hour_alarm - hour alarm register (address 0Ah) bit description Bit Symbol Value Description 7 AE_H 0 hour alarm is enabled 1[1] hour alarm is disabled 0 unused 0 indicates AM 1 indicates PM 0 to 1 ten’s place 0 to 9 unit place 0 to 2 ten’s place 0 to 9 unit place 6 - 12 hour mode[2] 5 AMPM 4 to 0 HOUR_ALARM 3 to 0 24 hour mode[2] 5 to 4 HOURS 3 to 0 [1] Default value. [2] Hour mode is set by bit 12_24 in register Control_1 (see Table 5). PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 11 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 8.4.3 Register Day_alarm Table 19. Day_alarm - day alarm register (address 0Bh) bit description Bit Symbol Value Place value Description 7 AE_D 0 - day alarm is enabled 1[1] - day alarm is disabled - - unused 5 to 4 DAY_ALARM 0 to 3 ten’s place 3 to 0 0 to 9 unit place day alarm information coded in BCD format 6 [1] - Default value. 8.4.4 Register Weekday_alarm Table 20. Weekday_alarm - weekday alarm register (address 0Ch) bit description Bit Symbol Value Description 7 AE_W 0 weekday alarm is enabled 1[1] weekday alarm is disabled - unused 6 to 3 - 2 to 0 WEEKDAY_ALARM 0 to 6 [1] weekday alarm information coded in BCD format Default value. 8.4.5 Alarm flag By clearing the MSB, AE_x (Alarm Enable), of one or more of the alarm registers the corresponding alarm condition(s) are active. When an alarm occurs, AF (register Control_2, see Table 6) is set logic 1. The asserted AF can be used to generate an interrupt (INT). The AF is cleared using the interface. check now signal example AE_M AE_M = 1 MINUTE ALARM = 1 0 MINUTE TIME AE_H HOUR ALARM = HOUR TIME set alarm flag AF (1) AE_D DAY ALARM = DAY TIME AE_W WEEKDAY ALARM = 013aaa088 WEEKDAY TIME Fig 5. Alarm function block diagram PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 12 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar The registers at addresses 09h through 0Ch contain alarm information. When one or more of these registers is loaded with minute, hour, day, or weekday, and its corresponding Alarm Enable bit (AE_x) is logic 0, then that information is compared with the current minute, hour, day, and weekday. When all enabled comparisons first match, the Alarm Flag (AF) is set logic 1. The generation of interrupts from the alarm function is controlled via bit AIE (register Control_2, see Table 6). If bit AIE is enabled, the INT pin follows the condition of bit AF. AF will remain set until cleared by the interface. Once AF has been cleared, it will only be set again when the time increments to match the alarm condition once more. Alarm registers which have their AE_x bit logic 1 are ignored. Generation of interrupts from the alarm function is described in Section 8.7.3. Figure 6, Table 21 and Table 22 show an example for clearing bit AF, but leaving bit MSF and bit TF unaffected. The flags are cleared by a write command, therefore bits 7, 6, 4, 1 and 0 must be written with their previous values. Repeatedly re-writing these bits has no influence on the functional behavior. minutes counter 44 minute alarm 45 46 45 AF INT when AIE = 1 001aaf903 Example where only the minute alarm is used and no other interrupts are enabled. Fig 6. Alarm flag timing To prevent the timer flags being overwritten while clearing bit AF, logic AND is performed during a write access. A flag is cleared by writing logic 0 whilst a flag is not cleared by writing logic 1. Writing logic 1 will result in the flag value remaining unchanged. Table 21. Flag location in register Control_2 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control_2 - - MSF - AF TF - - Table 22 shows what instruction must be sent to clear bit AF. In this example, bit MSF and bit TF are unaffected. Table 22. Example to clear only AF (bit 3) in register Control_2 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control_2 - - 1 - 0 1 - - PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 13 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 8.5 Register CLKOUT_control and clock output A programmable square wave is available at pin CLKOUT. Operation is controlled by control bits COF[2:0] in register CLKOUT_control (0Dh); see Table 23. Frequencies of 32.768 kHz (default) down to 1 Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. Table 23. Bit CLKOUT_control - CLKOUT control register (address 0Dh) bit description Symbol Value Description 7 to 3 - - unused 2 to 0 COF[2:0] see Table 24 frequency output at pin CLKOUT Pin CLKOUT is an open-drain output and enabled at power-on. When disabled the output is LOW. The duty cycle of the selected clock is not controlled, but due to the nature of the clock generation, all clock frequencies, except 32.768 kHz, have a duty cycle of 50 : 50. The stop function can also affect the CLKOUT signal, depending on the selected frequency. When STOP is active, the CLKOUT pin will generate a continuous LOW for those frequencies that can be stopped. For more details, see Section 8.9. Table 24. CLKOUT frequency selection Bits COF[2:0] CLKOUT frequency (Hz) Typical duty cycle[1] (%) Effect of STOP 000[2] 32 768 60 : 40 to 40 : 60 no effect 001 16 384 50 : 50 no effect 010 8 192 50 : 50 no effect 011 4 096 50 : 50 CLKOUT = LOW 100 2 048 50 : 50 CLKOUT = LOW 101 1 024 50 : 50 CLKOUT = LOW 110 1 50 : 50 CLKOUT = LOW 111 CLKOUT = LOW [1] Duty cycle definition: HIGH-level time (%) : LOW-level time (%). [2] Default value. 8.6 Timer registers The countdown timer has four selectable source clocks allowing for countdown periods in the range from less than 1 ms to more than 4 hours (see Table 29). There are also two pre-defined timers which can be used to generate an interrupt once per second or once per minute. Registers Control_2 (01h), Timer_control (0Eh), and Countdown_timer (0Fh) are used to control the timer function and output. PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 14 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar Table 25. Bit 7 Symbol Value Description Reference TE 0[1] countdown timer is disabled Section 8.6.2 1 countdown timer is enabled 6 to 2 - 0 unused 1 to 0 CTD[1:0] 00 4.096 kHz countdown timer source clock 01 64 Hz countdown timer source clock 10 1 Hz countdown timer source clock 11[1] 1⁄ [1] Table 26. Timer_control - timer control register (address 0Eh) bit description 60 Hz countdown timer source clock Default value. Countdown_timer - countdown timer register (address 0Fh) bit description Bit Symbol Value Description Reference 7 to 0 COUNTDOWN_TIMER[7:0] 00h to FFh countdown period in seconds: Section 8.6.2 n CountdownPeriod = -------------------------------------------------------------SourceClockFrequency where n is the countdown value 8.6.1 Second and minute interrupt The second and minute interrupts (bits SI and MI) are pre-defined timers for generating periodic interrupts. The timers can be enabled independently of one another, however a minute interrupt enabled on top of a second interrupt will not be distinguishable since it will occur at the same time; see Figure 7. The minute and second flag (MSF) is set logic 1 when either the seconds or the minutes counter increments according to the currently enabled interrupt. The flag can be read and cleared by the interface. The status of bit MSF does not affect the INT pulse generation. If the MSF flag is not cleared prior to the next coming interrupt period, an INT pulse will still be generated. Table 27. Effect of bits MI and SI on INT generation Minute interrupt (bit MI) Second interrupt (bit SI) Result 0 0 no interrupt generated 1 0 an interrupt once per minute 0 1 an interrupt once per second 1 1 an interrupt once per second Table 28. Effect of bits MI and SI on bit MSF Minute interrupt (bit MI) Second interrupt (bit SI) Result 0 0 MSF never set 1 0 MSF set when minutes counter increments[1] 0 1 MSF set when seconds counter increments 1 1 MSF set when seconds counter increments [1] In the case of bit MI = 1 and bit SI = 0 bit MSF will be cleared automatically after 1 second. PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 15 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar seconds counter 58 59 minutes counter 59 00 11 12 00 01 INT MSF 001aai520 a. INT and MSF when SI enabled (MSF flag not cleared after an interrupt) seconds counter 58 59 minutes counter 59 00 11 12 00 01 INT MSF 001aai521 b. INT and MSF when only MI enabled Bit TI_TP is set logic 1 resulting in 1⁄64 Hz wide interrupt pulse. Fig 7. INT example for bits SI and MI The purpose of the flag is to allow the controlling system to interrogate the PCA21125 and identify the source of the interrupt such as the minute/second or countdown timer. 8.6.2 Countdown timer function The 8-bit countdown timer at address 0Fh is controlled by the timer control register at address 0Eh. The timer control register determines one of 4 source clock frequencies for the timer (4.096 kHz, 64 Hz, 1 Hz, or 1⁄60 Hz) and enables or disables the timer. Table 29. CTD[1:0] CTD[1:0] for timer frequency selection and countdown timer durations Timer source clock frequency Delay 00 4.096 kHz 244 μs 62.256 ms 01 64 Hz 15.625 ms 3.984 s 10 1 Hz 1s 255 s 11 1⁄ 60 s[1] 4 h 15 min [1] 60 Hz Minimum timer duration Maximum timer duration n=1 n = 255 When not in use, CTD[1:0] must be set to 1⁄60 Hz for power saving. Remark: Note that all timings which are generated from the 32.768 kHz oscillator are based on the assumption that there is 0 ppm deviation. Deviation in oscillator frequency will result in a corresponding deviation in timings. This is not applicable to interface timing. PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 16 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar The timer counts down from a software-loaded 8-bit binary value n. Loading the counter with 0 effectively stops the timer. Values from 1 to 255 are valid. When the counter reaches 1, the countdown timer flag (bit TF in register Control_2, see Table 6) will be set and the counter automatically re-loads and starts the next timer period. Reading the timer will return the current value of the countdown counter; see Figure 8. countdown value, n xx 03 xx 03 timer source clock countdown counter 02 01 03 02 01 03 02 01 03 TE TF INT n n duration of first timer period after enable may range from n − 1 to n + 1 001aaf906 In the example it is assumed that the timer flag is cleared before the next countdown period expires and that the INT is set to pulsed mode. Fig 8. General countdown timer behavior If a new value of n is written before the end of the current timer period, then this value will take immediate effect. It is not recommended to change n without first disabling the counter (by setting bit TE = 0). The update of n is asynchronous with the timer clock, therefore changing it without setting bit TE = 0 will result in a corrupted value loaded into the countdown counter which results in an undetermined countdown period for the first period. The countdown value n will however be correctly stored and correctly loaded on subsequent timer periods. When the countdown timer flag is set, an interrupt signal on INT will be generated, provided that this mode is enabled. See Section 8.7.2 for details on how the interrupt can be controlled. When starting the timer for the first time, the first period will have an uncertainty which is a result of the enable instruction being generated from the interface clock which is asynchronous with the timer source clock. Subsequent timer periods will have no such delay. The amount of delay for the first timer period will depend on the chosen source clock; see Table 30. Table 30. First period delay for timer counter value n Timer source clock Minimum timer period Maximum timer period 4.096 kHz n n+1 64 Hz n n+1 1 Hz (n − 1) + 1⁄64 Hz 1⁄ 60 Hz (n − 1) + 1⁄ 64 Hz PCA21125_1 Product data sheet n + 1⁄64 Hz n + 1⁄64 Hz © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 17 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar At the end of every countdown, the timer sets the countdown timer flag (bit TF). Bit TF can only be cleared by using the interface. The asserted bit TF can be used to generate an interrupt (INT). The interrupt can be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of bit TF. Bit TI_TP is used to control this mode selection and the interrupt output can be disabled with bit TIE. For accurate read back of the count down value, it is recommended to read the register twice and check for consistent results, since it is not possible to freeze the countdown timer counter during read back. 8.6.3 Timer flags When a minute or second interrupt occurs, bit MSF (register Control_2, see Table 6) is set logic 1. Similarly, at the end of a timer countdown, bit TF is set logic 1. These bits maintain their value until overwritten by using the interface. If both countdown timer and minute/second interrupts are required in the application, the source of the interrupt can be determined by reading these bits. To prevent one flag being overwritten while clearing another, a logic AND is performed during a write access. A flag is cleared by writing logic 0 whilst a flag is not cleared by writing logic 1. Writing logic 1 will result in the flag value remaining unchanged. Three examples are given for clearing the flags. Flags MSF and TF are cleared by a write command, therefore bits 7, 6, 4, 1, and 0 must be written with their previous values. Repeatedly re-writing these bits has no influence on the functional behavior. Table 31. Flag location in register Control_2 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control_2 - - MSF - AF TF - - Table 32, Table 33, and Table 34 show what instruction must be sent to clear the appropriate flag. Table 32. Example to clear only TF (bit 2) in register Control_2 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control_2 - - 1 - 1 0 - - Table 33. Example to clear only MSF (bit 5) in register Control_2 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control_2 - - 0 - 1 1 - - Table 34. Example to clear both TF and MSF (bits 2 and 5) in register Control_2 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control_2 - - 0 - 1 0 - - Clearing the alarm flag (bit AF) operates in exactly the same way; see Section 8.4.5. 8.7 Interrupt output An active LOW interrupt signal is available at pin INT. Operation is controlled via the bits of register Control_2. Interrupts can be sourced from three places: second/minute timer, countdown timer, and alarm function. PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 18 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar Bit TI_TP configures the timer generated interrupts to be either a pulse or to follow the status of the interrupt flags (bits TF and MSF). SI MSF: MINUTE SECOND FLAG SET SECONDS COUNTER MINUTES COUNTER CLEAR MI to interface: read MSF SI MI 0 PULSE GENERATOR 1 TRIGGER 1 CLEAR from interface: clear MSF TE TF: TIMER COUNTDOWN COUNTER INT TI_TP to interface: read TF TIE 0 SET CLEAR PULSE GENERATOR 2 TRIGGER 1 CLEAR from interface: clear TF set alarm flag, AF AF: ALARM FLAG SET to interface: read AF CLEAR AIE 001aaf907 from interface: clear AF When bits SI, MI, TIE and AIE are all disabled, pin INT will remain high-impedance. Fig 9. Interrupt scheme Remark: Note that the interrupts from the three groups are wired-OR, meaning they will mask one another; see Figure 9. 8.7.1 Minute and second interrupts The pulse generator for the minute/second interrupt operates from an internal 64 Hz clock and consequently generates a pulse of 1⁄64 second duration. If the MSF flag is clear before the end of the INT pulse, then the INT pulse is shortened. This allows the source of a system interrupt to be cleared immediately it is serviced, i.e., the system does not have to wait for the completion of the pulse before continuing; see Figure 10. Instructions for clearing MSF are given in Section 8.6.3. PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 19 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar seconds counter 58 59 MSF INT (1) SCL 8th clock CLEAR INSTRUCTION instruction 001aaf908 (1) Indicates normal duration of INT pulse (bit TI_TP = 1). Fig 10. Example of shortening the INT pulse by clearing the MSF flag The timing shown for clearing bit MSF in Figure 10 is also valid for the non-pulsed interrupt mode, i.e., when bit TI_TP = 0, where the pulse can be shortened by setting both bits MI and SI logic 0. 8.7.2 Countdown timer interrupts Generation of interrupts from the countdown timer is controlled via bit TIE (register Control_2, see Table 6). The pulse generator for the countdown timer interrupt also uses an internal clock which is dependent on the selected source clock for the countdown timer and on the countdown value n. As a consequence, the width of the interrupt pulse varies; see Table 35. Table 35. INT operation (bit TI_TP = 1) Source clock (Hz) INT period (s) n = 1[1] n>1 4 096 1⁄ 8 192 1⁄ 4 096 64 1⁄ 128 1⁄ 64 1 1⁄ 64 1⁄ 64 1⁄ 1⁄ 64 1⁄ 64 60 [1] n = loaded countdown value. Timer stopped when n = 0. If the TF flag is cleared before the end of the INT pulse, then the INT pulse is shortened. This allows the source of a system interrupt to be cleared immediately it is serviced, i.e., the system does not have to wait for the completion of the pulse before continuing; see Figure 11. Instructions for clearing TF are given in Section 8.6.3. PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 20 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar countdown counter 01 n CDTF INT (1) SCL 8th clock CLEAR INSTRUCTION instruction 001aaf909 (1) Indicates normal duration of INT pulse (bit TI_TP = 1). Fig 11. Example of shortening the INT pulse by clearing the TF flag The timing shown for clearing bit TF in Figure 11 is also valid for the non-pulsed interrupt mode, i.e., when bit TI_TP = 0, where the pulse can be shortened by setting bit TIE = 0. 8.7.3 Alarm interrupts Generation of interrupts from the alarm function is controlled via bit AIE (register Control_2, see Table 6). If bit AIE is enabled, the INT pin follows the status of bit AF. Clearing bit AF will immediately clear INT. No pulse generation is possible for alarm interrupts; see Figure 12. minute counter 44 minute alarm 45 45 AF INT SCL 8th clock instruction CLEAR INSTRUCTION 001aaf910 Example where only the minute alarm is used and no other interrupts are enabled. Fig 12. AF timing 8.8 External clock test mode A test mode is available which allows for on-board testing. In this mode it is possible to set up test conditions and control the operation of the RTC. The test mode is entered by setting the EXT_TEST bit in register Control_1 (see Table 5). The CLKOUT pin then becomes an input. The test mode replaces the internal signal with the signal applied to pin CLKOUT. PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 21 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a maximum period of 1 000 ns. The internal clock, now sourced from pin CLKOUT, is divided down to 1 Hz by a 26 divide chain called a prescaler; see Section 8.9. The prescaler can be set into a known state by using the STOP bit. When the STOP bit is set, the prescaler is reset to 0. (STOP must be cleared before the prescaler can operate again.) From a stop condition, the first 1 second increment will take place after 32 positive edges on pin CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment. Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When entering the test mode, no assumption as to the state of the prescaler can be made. Operation example: 1. Set EXT_TEST test mode (register Control_1, bit EXT_TEST = 1). 2. Set STOP (register Control_1, bit STOP = 1). 3. Clear STOP (register Control_1, bit STOP = 0). 4. Set time registers to desired value. 5. Apply 32 clock pulses to pin CLKOUT. 6. Read time registers to see the first change. 7. Apply 64 clock pulses to pin CLKOUT. 8. Read time registers to see the second change. Repeat steps 7 and 8 for additional increments. 8.9 STOP bit function The STOP bit function (register Control_1, see Table 5) allows the accurate starting of the time circuits. The STOP bit function will cause the upper part of the prescaler (F2 to F14) to be held at reset, thus no 1 Hz ticks will be generated. The time circuits can then be set and will not increment until STOP is released; see Figure 13. F13 RES RES 2 Hz F2 reset 4096 Hz F1 8192 Hz F0 16384 Hz OSC 32768 Hz OSC STOP DETECTOR F14 1 Hz tick RES stop 1 Hz 1024 Hz CLKOUT source 8192 Hz 16384 Hz 001aaf911 Fig 13. Stop bit functional diagram PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 22 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar STOP will not affect the output of 32.768 kHz, 16.384 kHz, or 8.192 kHz; see Section 8.5. The lower two stages of the prescaler (F0 and F1) are not reset and because the SPI-bus is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be between 0 and one 8.192 kHz cycle; see Figure 14. The first increment of the time circuits is between 0.499 888 s and 0.500 000 s after stop is released. The uncertainty is caused by prescaler bits F0 and F1 not being reset; see Table 36. 8192 Hz stop released 0 μs to 122 μs 001aaf912 Fig 14. STOP bit release timing Table 36. Example: first increment of time circuits after stop release Bit STOP Prescaler bits 1 Hz tick F0F1-F2 to F14[1] Time Comment hh:mm:ss Clock is running normally 0 01-0 0001 1101 0100 12:45:12 prescaler counting normally Stop is activated by user. F0F1 are not reset and values can not be predicted externally 1 XX-0 0000 0000 0000 12:45:12 prescaler is reset; time circuits are frozen 08:00:00 prescaler is reset; time circuits are frozen 08:00:00 prescaler is now running 08:00:00 - 08:00:00 - 08:00:00 - : : 08:00:00 - 00-0 0000 0000 0001 08:00:01 0 to 1 transition of F14 increments the time circuits 10-0 0000 0000 0001 08:00:01 - : : : 11-1 1111 1111 1111 08:00:01 - 00-0 0000 0000 0000 08:00:01 - 10-0 0000 0000 0000 08:00:01 - : : : 11-1 1111 1111 1110 08:00:01 - 08:00:02 0 to 1 transition of F14 increments the time circuits New time is set by user 1 XX-0 0000 0000 0000 XX-0 0000 0000 0000 XX-1 0000 0000 0000 XX-0 1000 0000 0000 XX-1 1000 0000 0000 : 11-1 1111 1111 1110 1s 0 0.499888 - 0.500000 s Stop is released by user 00-0 0000 0000 0001 001aaf913 [1] F0 is clocked at 32.768 kHz. PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 23 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 8.10 Reset The PCA21125 includes an internal reset circuit which is active whenever the oscillator is stopped; see Figure 15. The oscillator can be stopped, for example, by connecting one of the oscillator pins OSCI or OSCO to ground. OSCILLATOR SDI CE osc stopped 0 = stopped, 1 = running POR OVERRIDE reset 0 = override inactive 1 = override active CLEAR Bit POR_OVRD 0 = clear override mode 1 = override possible 001aaf898 Fig 15. Reset system The oscillator is considered to be stopped during the time between power-on and stable crystal resonance; see Figure 16. This time can be in the range of 200 ms to 2 s depending on crystal type, temperature and supply voltage. Whenever an internal reset occurs, the reset flag RF (register Seconds, see Table 7) is set. chip in reset chip not in reset VDD oscillation internal reset t 001aaf897 Fig 16. Power-On Reset (POR) PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 24 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar Table 37. Register reset values Bits labeled - are not implemented and will return logic 0 when read. Bits labeled X are undefined at power-on and unchanged by subsequent resets. Address Register name Bit 7 6 5 4 3 2 1 0 00h Control_1 0 0 0 - 1 0 - - 01h Control_2 0 0 0 0 0 0 0 0 02h Seconds 1 X X X X X X X 03h Minutes - X X X X X X X 04h Hours - - X X X X X X 05h Days - - X X X X X X 06h Weekdays - - - - - X X X 07h Months - - - X X X X X 08h Years X X X X X X X X 09h Minute_alarm 1 X X X X X X X 0Ah Hour_alarm 1 - X X X X X X 0Bh Day_alarm 1 - X X X X X X 0Ch Weekday_alarm 1 - - - - X X X 0Dh CLKOUT_control - - - - - 0 0 0 0Eh Timer_control 0 - - - - - 1 1 0Fh Countdown_timer X X X X X X X X After reset, the following mode is entered: • 32.768 kHz on pin CLKOUT active • POR override available to be set • 24 hour mode is selected The SPI-bus is initialized whenever the chip enable pin CE is inactive (LOW). 8.10.1 POR override The Power-On Reset (POR) duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and hence speed up the on-board test of the device. minimum 500 ns SDI CE reset override minimum 500 ns minimum 2000 ns POR override set at this time 001aaf900 Fig 17. POR override sequence PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 25 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar The setting of this mode requires that bit POR_OVRD (register Control_1, see Table 5) be set logic 1 and that the signals at the SPI-bus pins SDI and CE are toggled as illustrated in Figure 17. All timings are required minimums. Once the override mode has been entered, the device immediately stops being reset and set-up operation can commence, i.e., entry into the external clock test mode via the SPI-bus access. The override mode can be cleared by writing logic 0 to bit POR_OVRD. Bit POR_OVRD must be set logic 1 before a re-entry into the override mode is possible. Setting bit POR_OVRD logic 0 during normal operation has no effect except to prevent accidental entry into the POR override mode. This is the recommended setting. 8.11 3-line SPI-bus Data transfer to and from the device is made via a 3-line SPI-bus; see Table 38. Table 38. Serial interface Pin Function Description CE chip enable input when HIGH, data transfer is active when LOW, data transfer is inactive; the interface is reset; pull-down resistor included; active input can be higher than VDD, but must not be wired HIGH permanently SCL serial clock input when pin CE = LOW, this input might float; input can be higher than VDD SDI serial data input when pin CE = LOW, this input might float; input can be higher than VDD; input data is sampled on the rising edge of SCL SDO serial data output push-pull output; drives from VSS to VDD; output data is changed on the falling edge of SCL The data lines for input and output are split. The data input and output lines can be connected together to facilitate a bidirectional data bus (see Figure 18). SDI SDI SDO SDO two wire mode single wire mode 001aai560 Fig 18. SDI, SDO configurations The chip enable signal is used to identify the transmitted data. Each data transfer is a byte, with the Most Significant Bit (MSB) sent first; see Figure 19. data bus COMMAND DATA DATA DATA chip enable 001aaf914 Fig 19. Data transfer overview PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 26 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar The transmission is initiated by an active HIGH chip enable signal CE and terminated by an inactive LOW signal. The first byte transmitted is the command byte (see Table 39 and Figure 20). Subsequent bytes will be either data to be written or data to be read. Data is captured on the rising edge of the clock and transferred internally on the falling edge. The command byte defines the address of the first register to be accessed and the read/write mode. The address counter will auto increment after every access and will reset to zero after the last valid register is accessed. The read/write bit (R/W) defines if the following bytes will be read or write information. Table 39. Command byte definition Bit Symbol 7 R/W Value Description data read or data write selection 0 write data 1 read data subaddress; other codes will cause the device to ignore data transfer 6 to 4 SA 001 3 to 0 RA 00h to 0Fh register address b7 b6 b5 b4 b3 SA R/W b1 b2 b0 RA 013aaa219 Fig 20. Command byte In Figure 21 the register Seconds is set to 45 seconds and the register Minutes to 10 minutes. R/W b7 0 seconds data 45BCD addr 02HEX b6 0 b5 0 b4 1 b3 0 b2 0 b1 1 b0 0 b7 0 b6 1 b5 0 b4 0 b3 0 b2 1 minutes data 10BCD b1 0 b0 1 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 b1 0 b0 0 SCL SDI CE address counter 02 xx 03 04 001aaf915 Fig 21. Serial bus write example In Figure 22 the Months and Years registers are read. In this example, pins SDI and SDO are not connected together. PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 27 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar R/W b7 1 months data 11BCD addr 07HEX b6 0 b5 0 b4 1 b3 0 b2 1 b1 1 b0 1 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 years data 06BCD b1 0 b0 1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 1 b1 1 b0 0 SCL SDI SDO CE address counter 07 xx 08 09 001aaf916 Fig 22. Serial bus read example 8.11.1 Interface watchdog timer During read/write operations, the time counting circuits are frozen. To prevent a situation where the accessing device becomes locked and does not clear the interface by setting pin CE LOW, the PCA21125 has a built in watchdog timer. Should the interface be active for more than 1 s from the time a valid subaddress is transmitted, then the PCA21125 will automatically clear the interface and allow the time counting circuits to continue counting. CE must return LOW once more before a new data transfer can be executed. tw(CE) < 1 s CE data valid sub-address data data WD timer running WD timer time counters data running time counters frozen running 001aai563 a. Correct data transfer: read or write 1 s < tw(CE) < 2 s CE data valid sub-address data data data transfer fail WD timer running WD timer time counters data running time counters frozen WD trips running 001aai564 b. Incorrect data transfer: read or write Fig 23. Interface watchdog timer PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 28 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar The watchdog is implemented to prevent the excessive loss of time due to interface access failure, e.g., if main power is removed from a battery backed-up system during an interface access. Each time the watchdog period is exceeded, 1 s will be lost from the time counters. The watchdog will trigger between 1 s and 2 s after receiving a valid subaddress. 9. Internal circuitry VDD OSCI CLKOUT OSCO SCL INT SDI CE SDO VSS PCA21125 013aaa218 Fig 24. Device diode protection diagram PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 29 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 10. Limiting values Table 40. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Max Unit VDD supply voltage −0.5 +6.5 V IDD supply current −50 +50 mA VI input voltage −0.5 +6.5 V VO output voltage −0.5 +6.5 V II input current −10 +10 mA IO output current −10 +10 mA Ptot total power dissipation - 300 mW Tamb ambient temperature VESD Ilu Tstg [1] −40 +125 °C HBM [1] - ±3 500 V MM [2] - ±200 V CDM [3] - ±1 500 V latch-up current [4] - 100 mA storage temperature [5] −65 +150 °C electrostatic discharge voltage Pass level; Human Body Model (HBM) according to Ref. 5 “JESD22-A114”. [2] Pass level; Machine Model (MM), according to Ref. 6 “JESD22-A115”. [3] Pass level; Charged-Device Model (CDM), according to Ref. 7 “JESD22-C101”. [4] Pass level; latch-up testing, according to Ref. 8 “JESD78” at maximum ambient temperature (Tamb(max) = +125 °C). [5] According to the NXP store and transport requirements (see Ref. 10 “NX3-00092”) the devices have to be stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document. PCA21125_1 Product data sheet Min © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 30 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 11. Static characteristics Table 41. Static characteristics VDD = 1.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +125 °C; fosc = 32.768 kHz; quartz Rs = 60 kΩ; CL = 12.5 pF; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 1.3 - 5.5 V 1.6 - 5.5 V - - 500 μA - - 100 μA Tamb = 25 °C - 820 - nA Tamb = −40 °C to +125 °C - 1140 3 300 nA VDD = 5.0 V - 1 220 - nA VDD = 3.0 V - 940 - nA VDD = 2.0 V - 810 - nA VDD = 5.0 V - - 4 000 nA VDD = 3.0 V - - 2 400 nA VDD = 2.0 V - - 1 900 nA pin OSCI −0.5 - VDD + 0.5 V pins CE, SDI, SCL −0.5 - +5.5 V Supply: pin VDD VDD supply voltage IDD supply current SPI-bus inactive; for clock data integrity [1] SPI-bus active SPI-bus active fSCL = 6.0 MHz fSCL = 1.0 MHz SPI-bus inactive; CLKOUT disabled; VDD = 2.0 V to 5.0 V [2] SPI-bus inactive (fSCL = 0 Hz); CLKOUT enabled at 32 kHz Tamb = 25 °C Tamb = −40 °C to +125 °C Inputs VI input voltage VIL LOW-level input voltage VSS - 0.3VDD V VIH HIGH-level input voltage 0.7VDD - VDD V IL leakage current −1 0 +1 μA CI input capacitance - - 7 pF Rpd pull-down resistance pin CE - 240 550 kΩ output voltage pins OSCO and SDO - - VDD + 0.5 V pins CLKOUT and INT; refers to external pull-up voltage - - 5.5 V VI = VDD or VSS; on pins SDI, SCL and CLKOUT [3] Outputs VO VOH HIGH-level output voltage pin SDO 0.8VDD - VDD V VOL LOW-level output voltage pin SDO VSS - 0.2VDD V pins CLKOUT and INT; VDD = 5 V; IOL = −1.5 mA VSS - 0.4 V PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 31 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar Table 41. Static characteristics …continued VDD = 1.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +125 °C; fosc = 32.768 kHz; quartz Rs = 60 kΩ; CL = 12.5 pF; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit IOH HIGH-level output current output source current; pin SDO; VOH = 4.6 V; VDD = 5 V 1.5 - - mA IOL LOW-level output current output sink current; pins INT, SDO and CLKOUT; VOL = 0.4 V; VDD = 5 V 1.5 - - mA ILO output leakage current VO = VDD or VSS −1 0 +1 μA Cext external capacitance - 25 - pF [4] [1] For reliable oscillator start at power-up: VDD = VDD(min) + 0.3 V. [2] Timer source clock = 1⁄60 Hz; voltage on pins CE, SDI and SCL at VDD or VSS. [3] Implicit by design. [4] CL is a calculation of Cext and COSCO in series: C L = --------------------------------------- . ( C ext + C OSCO ) ( C ext ⋅ C OSCO ) PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 32 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 12. Dynamic characteristics Table 42. Dynamic characteristics VDD = 1.6 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +125 °C; all timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage swing of VSS to VDD. Symbol Parameter Conditions VDD = 1.6 V VDD = 2.7 V VDD = 4.5 V VDD = 5.5 V Unit Min Max Min Max Min Max Min - 1.5 - 4.0 - 5.00 - Max Pin SCL fclk(SCL) SCL clock frequency 6.25 MHz tSCL SCL time 660 - 250 - 200 - 160 - ns tclk(H) clock HIGH time 320 - 120 - 100 - 70 - ns tclk(L) clock LOW time 320 - 130 - 100 - 90 - ns tr rise time - 100 - 100 - 100 - 100 ns tf fall time - 100 - 100 - 100 - 100 ns Pin CE tsu(CE) CE set-up time 30 - 30 - 30 - 30 - ns th(CE) CE hold time 100 - 60 - 40 - 30 - ns trec(CE) CE recovery time 100 - 100 - 100 - 100 - ns tw(CE) CE pulse width - 0.99 - 0.99 - 0.99 - 0.99 s Pin SDI tsu set-up time 25 - 15 - 15 - 10 - ns th hold time 100 - 60 - 40 - 30 - ns - 320 - 130 - 100 - 90 ns - 50 - 30 - 30 - 25 ns 0 - 0 - 0 - 0 - ns Pin SDO td(R)SDO tdis(SDO) SDO read delay time bus load = 85 pF SDO disable time tt(SDI-SDO) transition time from SDI to SDO [1] [1] no load value to avoid bus conflict Bus will be held up by bus capacitance; use RC time constant with application values. PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 33 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar tw(CE) CE tsu(CE) trec(CE) tr th(CE) tf 80% SCL 20% tclk(L) tclk(H) WRITE tsu th SDI SDO R/W SA2 RA0 b6 b0 b7 b6 b0 Hi Z READ SDI b7 tt(SDI-SDO) tdis(SDO) td(R)SDO SDO Hi Z b7 b6 b0 001aag900 Fig 25. SPI interface timing PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 34 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 13. Application information 13.1 Application diagram 1F supercapacitor 100 nF Cext OSCI OSCO VDD CLKOUT PCA21125 CE SCL SDI SDO INT VSS 013aaa179 The 1 farad capacitor is used as a standby and back-up supply. With the RTC in its minimum power configuration, i.e., timer off and CLKOUT off, the RTC can operate for several weeks. Fig 26. Application diagram 13.2 Quartz frequency adjustment 1. Method 1: fixed OSCI capacitor A fixed capacitor can be used whose value can be determined by evaluating the average capacitance necessary for the application layout; see Figure 26. The frequency is best measured via the 32.768 kHz signal at pin CLKOUT available after power-on. The frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average ±5 × 10−6). An average deviation of ±5 minutes per year can easily be achieved. 2. Method 2: OSCI trimmer Fast setting of a trimmer is possible using the 32.768 kHz signal at pin CLKOUT available after power-on. 3. Method 3: OSCO output Direct measurement of OSCO output (accounting for test probe capacitance). PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 35 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 14. Package outline TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 27. Package outline SOT402-1 (TSSOP14) PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 36 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 15. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 37 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 16.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 28) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 43 and 44 Table 43. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 44. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2 000 > 2 000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 28. PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 38 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 17. Abbreviations Table 45. Abbreviations Acronym Description AEC Automotive Electronics Council AM Ante Meridiem BCD Binary Coded Decimal CDM Charged-Device Model CMOS Complementary Metal Oxide Semiconductor HBM Human Body Model IC Integrated Circuit MM Machine Model MOS Metal Oxide Semiconductor MSB Most Significant Bit MSL Moisture Sensitivity Level PCB Printed-Circuit Board PM Post Meridiem POR Power-On Reset RC Resistance-Capacitance RTC Real-Time Clock SMD Surface Mount Device SPI Serial Peripheral Interface PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 39 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 18. References [1] AN10365 — Surface mount reflow soldering description [2] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [4] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [5] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [6] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) [7] JESD22-C101 — Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components [8] JESD78 — IC Latch-Up Test [9] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [10] NX3-00092 — NXP store and transport requirements [11] SNV-FA-01-02 — Marking Formats Integrated Circuits 19. Revision history Table 46. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA21125_1 20091116 Product data sheet - - PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 40 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 20.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 20.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 20.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 21. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCA21125_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 16 November 2009 41 of 42 PCA21125 NXP Semiconductors SPI-bus Real-Time Clock and calendar 22. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.2.1 8.2.2 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.5 8.6 8.6.1 8.6.2 8.6.3 8.7 8.7.1 8.7.2 8.7.3 8.8 8.9 8.10 8.10.1 8.11 8.11.1 9 10 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Register overview . . . . . . . . . . . . . . . . . . . . . . . 5 Control and status registers . . . . . . . . . . . . . . . 6 Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 6 Register Control_2 . . . . . . . . . . . . . . . . . . . . . . 6 Time and date registers . . . . . . . . . . . . . . . . . . 7 Register Seconds . . . . . . . . . . . . . . . . . . . . . . . 7 Register Minutes. . . . . . . . . . . . . . . . . . . . . . . . 7 Register Hours . . . . . . . . . . . . . . . . . . . . . . . . . 8 Register Days . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Register Weekdays. . . . . . . . . . . . . . . . . . . . . . 8 Register Months . . . . . . . . . . . . . . . . . . . . . . . . 9 Register Years . . . . . . . . . . . . . . . . . . . . . . . . . 9 Setting and reading the time. . . . . . . . . . . . . . 10 Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . 11 Register Minute_alarm . . . . . . . . . . . . . . . . . . 11 Register Hour_alarm . . . . . . . . . . . . . . . . . . . 11 Register Day_alarm . . . . . . . . . . . . . . . . . . . . 12 Register Weekday_alarm . . . . . . . . . . . . . . . . 12 Alarm flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Register CLKOUT_control and clock output. . 14 Timer registers . . . . . . . . . . . . . . . . . . . . . . . . 14 Second and minute interrupt . . . . . . . . . . . . . 15 Countdown timer function . . . . . . . . . . . . . . . . 16 Timer flags . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 18 Minute and second interrupts . . . . . . . . . . . . . 19 Countdown timer interrupts. . . . . . . . . . . . . . . 20 Alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . 21 External clock test mode . . . . . . . . . . . . . . . . 21 STOP bit function . . . . . . . . . . . . . . . . . . . . . . 22 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 POR override . . . . . . . . . . . . . . . . . . . . . . . . . 25 3-line SPI-bus . . . . . . . . . . . . . . . . . . . . . . . . . 26 Interface watchdog timer . . . . . . . . . . . . . . . . 28 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 29 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 30 11 12 13 13.1 13.2 14 15 16 16.1 16.2 16.3 16.4 17 18 19 20 20.1 20.2 20.3 20.4 21 22 Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics. . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Application diagram . . . . . . . . . . . . . . . . . . . . Quartz frequency adjustment. . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 33 35 35 35 36 37 37 37 37 38 38 39 40 40 41 41 41 41 41 41 42 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 16 November 2009 Document identifier: PCA21125_1