SN74LS373 SN74LS374 Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output http://onsemi.com The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all ON Semiconductor TTL families. • • • • • • • LOW POWER SCHOTTKY 20 Eight Latches in a Single Package 3-State Outputs for Bus Interfacing Hysteresis on Latch Enable Edge-Triggered D-Type Inputs Buffered Positive Edge-Triggered Clock Hysteresis on Clock Input to Improve Noise Margin Input Clamp Diodes Limit High Speed Termination Effects 1 PLASTIC N SUFFIX CASE 738 GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage 20 Min Typ Max Unit 4.75 5.0 5.25 V 0 25 70 °C TA Operating Ambient Temperature Range IOH Output Current – High – 2.6 mA IOL Output Current – Low 24 mA 1 SOIC DW SUFFIX CASE 751D ORDERING INFORMATION Device SN74LS373N SN74LS373DW SN74LS374N SN74LS374DW Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 6 1 Package Shipping 16 Pin DIP 1440 Units/Box 16 Pin 2500/Tape & Reel 16 Pin DIP 1440 Units/Box 16 Pin 2500/Tape & Reel Publication Order Number: SN74LS373/D SN74LS373 SN74LS374 CONNECTION DIAGRAM DIP (TOP VIEW) SN74LS374 SN74LS373 VCC O7 D7 D6 O6 O5 D5 D4 O4 LE VCC O7 D7 D6 O6 O5 D5 D4 O4 CP 20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11 1 OE 2 O0 3 D0 4 D1 5 O1 6 O2 7 D2 8 D3 9 O3 10 GND 1 OE 2 O0 3 D0 4 D1 5 O1 6 O2 7 D2 8 D3 9 O3 10 GND NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. LOADING (Note a) PIN NAMES D0 – D7 LE CP OE O0 – O7 Data Inputs Latch Enable (Active HIGH) Input Clock (Active HIGH Going Edge) Input Output Enable (Active LOW) Input Outputs HIGH LOW 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. TRUTH TABLE LS373 LS374 Dn LE OE On Dn H H L H H L H L L L X L L Q0 X X X H Z* H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance * Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE). http://onsemi.com 2 LE X OE On L H L L H Z* SN74LS373 SN74LS374 LOGIC DIAGRAMS SN74LS373 3 4 D0 D1 D D2 D Q G LATCH ENABLE LE 11 8 7 13 D3 D Q G 14 D4 D Q G 17 D5 D Q G 18 D6 D Q G VCC = PIN 20 GND = PIN 10 = PIN NUMBERS D7 D Q G D Q G Q G OE 1 O1 O0 O2 5 2 O3 9 6 O4 O5 12 O6 16 15 O7 19 SN74LS374 3 4 D0 11 7 D1 8 D2 13 D3 14 D4 17 18 D5 D6 D7 CP CP D Q Q CP D Q Q CP D Q Q CP D Q Q CP D Q Q CP D Q Q CP D Q Q CP D Q Q OE 1 O0 2 O1 5 O2 O3 6 O4 9 O5 12 15 O6 O7 16 19 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL O Output LOW Voltage Min Typ Max 2.0 0.8 – 0.65 2.4 – 1.5 3.1 Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table 0.25 0.4 V IOL = 12 mA 0.35 0.5 V IOL = 24 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table IOZH Output Off Current HIGH 20 µA VCC = MAX, VOUT = 2.7 V IOZL Output Off Current LOW – 20 µA VCC = MAX, VOUT = 0.4 V IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current – 30 0.1 mA VCC = MAX, VIN = 7.0 V – 0.4 mA VCC = MAX, VIN = 0.4 V – 130 mA VCC = MAX 40 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. http://onsemi.com 3 SN74LS373 SN74LS374 AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits LS373 Symbol Parameter Min Typ LS374 Max Min Typ 35 50 Unit Max fMAX Maximum Clock Frequency tPLH tPHL Propagation Delay, Data to Output 12 12 18 18 tPLH tPHL Clock or Enable to Output 20 18 30 30 15 19 28 28 ns tPZH tPZL Output Enable Time 15 25 28 36 20 21 28 28 ns tPHZ tPLZ Output Disable Time 12 15 20 25 12 15 20 25 ns Test Conditions MHz ns pF CL = 45 pF, RL = 667 Ω CL = 5.0 pF AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits LS373 Symbol Parameter Min LS374 Max Min Max Unit tW Clock Pulse Width 15 15 ns ts Setup Time 5.0 20 ns th Hold Time 20 0 ns DEFINITION OF TERMS HOLD TIME (th) — is defined as the minimum time following the LE transition from HIGH-to-LOW that the logic level must be maintained at the input in order to ensure continued recognition. SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to LE transition from HIGH-to-LOW in order to be recognized and transferred to the outputs. http://onsemi.com 4 SN74LS373 SN74LS374 SN74LS373 AC WAVEFORMS tW tW 1.3 V LE ts th Dn tPLH tPHL OUTPUT Figure 1. OE 1.3 V tPZL VOUT OE 1.3 V tPLZ 1.3 V tPHZ tPZH 1.3 V 1.3 V 1.3 V VOUT 1.3 V VOL VOH 1.3 V 0.5 V 0.5 V Figure 2. Figure 3. AC LOAD CIRCUIT VCC SWITCH POSITIONS RL SYMBOL SW1 TO OUTPUT UNDER TEST 5.0 kΩ CL* SW2 * Includes Jig and Probe Capacitance. Figure 4. http://onsemi.com 5 SW1 SW2 tPZH Open Closed tPZL Closed Open tPLZ Closed Closed tPHZ Closed Closed SN74LS373 SN74LS374 SN74LS374 AC WAVEFORMS tWH CP tWL 1.3 V 1.3 V OE 1.3 V th ts Dn 1.3 V tPZL tPLZ VOUT 1.3 V tPLH 1.3 V ≈ 1.3 V 1.3 V VOL tPHL OUTPUT 0.5 V 1.3 V Figure 6. 1.3 V Figure 5. OE 1.3 V 1.3 V tPZH VOUT tPHZ ≥ VOH ≈ 1.3 V 1.3 V 0.5 V Figure 7. AC LOAD CIRCUIT VCC SWITCH POSITIONS RL SW1 TO OUTPUT UNDER TEST 5.0 kΩ CL* SW2 * Includes Jig and Probe Capacitance. Figure 8. http://onsemi.com 6 SYMBOL SW1 SW2 tPZH Open Closed tPZL Closed Open tPLZ Closed Closed tPHZ Closed Closed SN74LS373 SN74LS374 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 738–03 ISSUE E –A– 20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B L C –T– DIM A B C D E F G J K L M N K SEATING PLANE M N E G F J D 20 PL 0.25 (0.010) 20 PL 0.25 (0.010) T A M M T B M M INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 D SUFFIX PLASTIC SOIC PACKAGE CASE 751D–05 ISSUE F q A 20 X 45 _ h 1 10 20X B B 0.25 M T A S B S A L H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 18X e A1 SEATING PLANE DIM A A1 B C D E e H h L q C T http://onsemi.com 7 MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ SN74LS373 SN74LS374 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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