PCA9544A 4-channel I2C-bus multiplexer with interrupt logic Rev. 04 — 15 June 2009 Product data sheet 1. General description The PCA9544A is a 1-of-4 bidirectional translating multiplexer, controlled via the I2C-bus. The SCL/SDA upstream pair fans out to four SCx/SDx downstream pairs, or channels. Only one SCx/SDx channel is selected at a time, determined by the contents of the programmable control register. Four interrupt inputs, INT0 to INT3, one for each of the SCx/SDx downstream pairs, are provided. One interrupt output, INT, which acts as an AND of the four interrupt inputs, is provided. A power-on reset function puts the registers in their default state and initializes the I2C-bus state machine with no channels selected. The pass gates of the multiplexer are constructed such that the VDD pin can be used to limit the maximum high voltage which will be passed by the PCA9544A. This allows the use of different bus voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V or 3.3 V parts can communicate with 5 V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant. 2. Features n n n n n n n n n n n n n n n n 1-of-4 bidirectional translating multiplexer I2C-bus interface logic; compatible with SMBus 4 active LOW interrupt inputs Active LOW interrupt output 3 address pins allowing up to 8 devices on the I2C-bus Channel selection via I2C-bus Power-up with all multiplexer channels deselected Low Ron switches Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses No glitch on power-up Supports hot insertion Low standby current Operating power supply voltage range of 2.3 V to 5.5 V 5 V tolerant Inputs 0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA n Three packages offered: SO20, TSSOP20 and HVQFN20 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic 3. Ordering information Table 1. Ordering information Type number Package Name Description Version PCA9544AD SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 PCA9544APW TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 PCA9544ABS HVQFN20 plastic thermal enhanced very thin quad flat package; SOT662-1 no leads; 20 terminals; body 5 × 5 × 0.85 mm 3.1 Ordering options Table 2. Ordering options Type number Topside mark Temperature range PCA9544AD PCA9544AD −40 °C to +85 °C PCA9544APW PA9544A −40 °C to +85 °C PCA9544ABS 9544A −40 °C to +85 °C PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 2 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic 4. Block diagram PCA9544A SC0 SC1 SC2 SC3 SD0 SD1 SD2 SD3 VSS VDD SCL SDA SWITCH CONTROL LOGIC POWER-ON RESET INPUT FILTER A0 I2C-BUS CONTROL A1 A2 INT[3:0] INT INTERRUPT LOGIC 002aae296 Fig 1. Block diagram PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 3 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic 5. Pinning information 5.1 Pinning A0 1 A1 2 20 VDD 19 SDA A0 1 A1 2 20 VDD 19 SDA A2 3 18 SCL A2 3 18 SCL INT0 4 17 INT INT0 4 17 INT SD0 5 16 SC3 SD0 5 SC0 6 15 SD3 SC0 6 INT1 7 14 INT3 INT1 7 14 INT3 SD1 8 13 SC2 SD1 8 13 SC2 SC1 9 12 SD2 SC1 9 12 SD2 VSS 10 11 INT2 VSS 10 11 INT2 PCA9544AD PCA9544APW 002aae293 15 SD3 002aae294 Pin configuration for TSSOP20 16 SCL 17 SDA 18 VDD 20 A1 terminal 1 index area Fig 3. 19 A0 Pin configuration for SO20 A2 1 15 INT INT0 2 14 SC3 SD0 3 SC0 4 12 INT3 INT1 5 11 SC2 7 8 9 SC1 VSS INT2 SD2 10 6 PCA9544ABS SD1 Fig 2. 16 SC3 13 SD3 002aae295 Transparent top view Fig 4. Pin configuration for HVQFN20 PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 4 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic 5.2 Pin description Table 3. Symbol Pin description Pin Description SO20, TSSOP20 HVQFN20 A0 1 19 A1 2 20 address input 1 A2 3 1 address input 2 INT0 4 2 active LOW interrupt input 0 SD0 5 3 serial data 0 SC0 6 4 serial clock 0 INT1 7 5 active LOW interrupt input 1 SD1 8 6 serial data 1 SC1 9 7 serial clock 1 VSS 10 8[1] supply ground INT2 11 9 active LOW interrupt input 2 SD2 12 10 serial data 2 SC2 13 11 serial clock 2 INT3 14 12 active LOW interrupt input 3 SD3 15 13 serial data 3 SC3 16 14 serial clock 3 INT 17 15 active LOW interrupt output SCL 18 16 serial clock line SDA 19 17 serial data line VDD 20 18 supply voltage [1] address input 0 HVQFN20 package supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region. PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 5 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic 6. Functional description Refer to Figure 1 “Block diagram”. 6.1 Device addressing Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9544A is shown in Figure 5. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. 1 1 1 0 fixed A2 A1 A0 R/W hardware selectable 002aab189 Fig 5. Slave address The last bit of the slave address defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. 6.2 Control register Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9544A which will be stored in the Control register. If multiple bytes are received by the PCA9544A, it will save the last byte received. This register can be written and read via the I2C-bus. interrupt bits (read only) bit 7 6 5 channel selection bits (read/write) 4 INT3 INT2 INT1 INT0 3 2 1 0 X B2 B1 B0 enable bit Fig 6. 002aae297 Control register 6.2.1 Control register definition A SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This register is written after the PCA9544A has been addressed. The 3 LSBs of the control byte are used to determine which channel is to be selected. When a channel is selected, it will become active after a STOP condition has been placed on the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made active, so that no false conditions are generated at the time of connection. PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 6 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic Table 4. Control register: Write—channel selection; Read—channel status INT3 INT2 INT1 INT0 D3 B2 B1 B0 Command X X X X X 0 X x no channel selected X X X X X 1 0 0 channel 0 enabled X X X X X 1 0 1 channel 1 enabled X X X X X 1 1 0 channel 2 enabled X X X 0 X 1 1 1 channel 3 enabled 0 0 0 0 0 0 0 0 no channel selected; power-up default state 6.3 Interrupt handling The PCA9544A provides 4 interrupt inputs, one for each channel and one open-drain interrupt output. When an interrupt is generated by any device, it will be detected by the PCA9544A and the interrupt output will be driven LOW. The channel need not be active for detection of the interrupt. A bit is also set in the control byte. Bits 7:4 of the control byte correspond to channel 3 to channel 0 of the PCA9544A, respectively. Therefore, if an interrupt is generated by any device connected to channel 2, the state of the interrupt inputs is loaded into the control register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0 would cause bit 4 of the control register to be set on the read. The master can then address the PCA9544A and read the contents of the control byte to determine which channel contains the device generating the interrupt. The master can then reconfigure the PCA9544A to select this channel, and locate the device generating the interrupt and clear it. The interrupt clears when the device originating the interrupt clears. It should be noted that more than one device can be providing an interrupt on a channel, so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt. The interrupt inputs may be used as general purpose inputs if the interrupt function is not required. If unused, interrupt input(s) must be connected to VDD through a pull-up resistor. Table 5. Control register read — interrupt INT3 INT2 INT1 X X X X X X 0 1 0 1 X D3 B2 B1 B0 X X X X X X X X X X X X X X X X X X X X X 0 1 INT0 0 1 Command no interrupt on channel 0 interrupt on channel 0 no interrupt on channel 1 interrupt on channel 1 no interrupt on channel 2 interrupt on channel 2 no interrupt on channel 3 interrupt on channel 3 Remark: Several interrupts can be active at the same time. For example: INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0, means that there is no interrupt on channel 0 and channel 3, and there is an interrupt on channel 1 and on channel 2. PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 7 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic 6.4 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9544A in a reset condition until VDD has reached VPOR. At this point, the reset condition is released and the PCA9544A registers and I2C-bus state machine are initialized to their default states (all zeroes), causing all the channels to be deselected. Thereafter, VDD must be lowered below 0.2 V to reset the device. 6.5 Voltage translation The pass gate transistors of the PCA9544A are constructed such that the VDD voltage can be used to limit the maximum voltage that will be passed from one I2C-bus to another. 002aaa964 5.0 Vo(sw) (V) 4.0 (1) (2) 3.0 (3) 2.0 1.0 2.0 2.5 3.0 3.5 4.0 4.5 5.5 5.0 VDD (V) (1) maximum (2) typical (3) minimum Fig 7. Pass gate voltage versus supply voltage Figure 7 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data specified in Section 11 “Dynamic characteristics” of this data sheet). In order for the PCA9544A to act as a voltage translator, the Vo(sw) voltage should be equal to, or lower than the lowest bus voltage. For example, if the main bus was running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at Figure 7, we see that Vo(sw)(max) will be at 2.7 V when the PCA9544A supply voltage is 3.5 V or lower so the PCA9544A supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see Figure 14). More Information can be found in Application Note AN262, PCA954X family of I2C/SMBus multiplexers and switches. PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 8 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic 7. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 7.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 8). SDA SCL data line stable; data valid Fig 8. change of data allowed mba607 Bit transfer 7.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 9). SDA SCL S P START condition STOP condition mba608 Fig 9. Definition of START and STOP conditions 7.3 System configuration A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 10). PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 9 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER SLAVE 002aaa966 Fig 10. System configuration 7.4 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 S START condition 2 8 9 clock pulse for acknowledgement 002aaa987 Fig 11. Acknowledgement on the I2C-bus PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 10 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic 7.5 Bus transactions slave address SDA S 1 1 1 0 A2 control register A1 A0 START condition 0 R/W A X X X X X B2 acknowledge from slave B1 B0 A P acknowledge from slave STOP condition 002aae299 Fig 12. Write control register slave address SDA S 1 1 1 0 A2 START condition last byte control register A1 A0 1 R/W A INT INT INT INT 3 2 1 0 acknowledge from slave X B2 B1 B0 NA P no acknowledge from master STOP condition 002aae300 Fig 13. Read control register PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 11 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic 8. Application design-in information VDD = 2.7 V to 5.5 V VDD = 3.3 V V = 2.7 V to 5.5 V (1) SDA SDA SD0 SCL SCL SC0 INT INT0 PCA9544A channel 0 V = 2.7 V to 5.5 V (1) I2C-bus/SMBus master SD1 channel 1 SC1 INT1 V = 2.7 V to 5.5 V (1) SD2 channel 2 SC2 INT2 V = 2.7 V to 5.5 V (1) A2 A1 SD3 A0 SC3 VSS INT3 channel 3 002aae298 (1) If the device generating the interrupt has an open-drain output structure or can be 3-stated, a pull-up resistor is required. If the device generating the interrupt has a totem pole output structure and cannot be 3-stated, a pull-up resistor is not required. The interrupt inputs should not be left floating. Fig 14. Typical application PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 12 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic 9. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to ground (VSS = 0 V).[1] Symbol Parameter Conditions Max Unit VDD supply voltage −0.5 +7.0 V VI input voltage −0.5 +7.0 V II input current - ±20 mA IO output current - ±25 mA IDD supply current - ±100 mA ISS ground supply current - ±100 mA Ptot total power dissipation - 400 mW Tstg storage temperature −60 +150 °C Tamb ambient temperature −40 +85 °C [1] operating The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 125 °C. PCA9544A_4 Product data sheet Min © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 13 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic 10. Static characteristics Table 7. Static characteristics at VDD = 2.3 V to 3.6 V VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. See Table 8 for VDD = 4.5 V to 5.5 V.[1] Symbol Parameter Conditions Min Typ Max Unit Supply VDD supply voltage 2.3 - 3.6 V IDD supply current operating mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 100 kHz - 10 30 µA Istb standby current standby mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 0 kHz - 0.1 1 µA VPOR power-on reset voltage no load; VI = VDD or VSS - 1.5 2.1 V [2] Input SCL; input/output SDA VIL LOW-level input voltage −0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 6 V IOL LOW-level output current VOL = 0.4 V 3 7 - mA VOL = 0.6 V 6 10 - mA IL leakage current VI = VDD or VSS −1 - +1 µA Ci input capacitance VI = VSS - 10 13 pF −0.5 - +0.3VDD V Select inputs A0 to A2, INT0 to INT3 VIL LOW-level input voltage VIH HIGH-level input voltage 0.7VDD - VDD + 0.5 V ILI input leakage current VI = VDD or VSS −1 - +1 µA Ci input capacitance VI = VSS - 1.6 3 pF ON-state resistance VDD = 3.0 V to 3.6 V; VO = 0.4 V; IO = 15 mA 5 11 30 Ω VDD = 2.3 V to 2.7 V; VO = 0.4 V; IO = 10 mA 7 16 55 Ω Pass gate Ron Vo(sw) switch output voltage Vi(sw) = VDD = 3.3 V; Io(sw) = −100 µA - 1.9 - V Vi(sw) = VDD = 3.0 V to 3.6 V; Io(sw) = −100 µA 1.6 - 2.8 V Vi(sw) = VDD = 2.5 V; Io(sw) = −100 µA - 1.5 - V Vi(sw) = VDD = 2.3 V to 2.7 V; Io(sw) = −100 µA 1.1 - 2.0 V IL leakage current VI = VDD or VSS −1 - +1 µA Cio input/output capacitance VI = VSS - 3 5 pF IOL LOW-level output current VOL = 0.4 V 3 7 - mA IOH HIGH-level output current - - +10 µA INT output [1] For operation between published voltage ranges, refer to worst case parameter in both ranges. [2] VDD must be lowered to 0.2 V in order to reset part. PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 14 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic Table 8. Static characteristics at VDD = 4.5 V to 5.5 V VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. See Table 7 for VDD = 2.3 V to 3.6 V.[1] Symbol Parameter Conditions Min Typ Max Unit 4.5 - 5.5 V Supply VDD supply voltage IDD supply current operating mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 100 kHz - 25 100 µA Istb standby current standby mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 0 kHz - 0.3 1 µA VPOR power-on reset voltage no load; VI = VDD or VSS - 1.7 2.1 V [2] Input SCL; input/output SDA VIL LOW-level input voltage −0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 6 V IOL LOW-level output current 3 - - mA VOL = 0.6 V 6 - - mA IL leakage current VI = VDD or VSS −1 - +1 µA Ci input capacitance VI = VSS - 12 13 pF VOL = 0.4 V Select inputs A0 to A2, INT0 to INT3 VIL LOW-level input voltage −0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - VDD + 0.5 V ILI input leakage current pin at VDD or VSS −1 - +1 µA Ci input capacitance VI = VSS - 2 5 pF Ron ON-state resistance VDD = 4.5 V to 5.5 V; VO = 0.4 V; IO = 15 mA 4 9 24 Ω Vo(sw) switch output voltage Vi(sw) = VDD = 5.0 V; Io(sw) = −100 µA - 3.6 - V Vi(sw) = VDD = 4.5 V to 5.5 V; Io(sw) = −100 µA 2.6 - 4.5 V Pass gate IL leakage current VI = VDD or VSS −1 - +1 µA Cio input/output capacitance VI = VSS - 3 5 pF IOL LOW-level output current VOL = 0.4 V 3 - - mA IOH HIGH-level output current - - +10 µA INT output [1] For operation between published voltage ranges, refer to worst case parameter in both ranges. [2] VDD must be lowered to 0.2 V in order to reset part. PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 15 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic 11. Dynamic characteristics Table 9. Symbol Dynamic characteristics Parameter Conditions Standard-mode I2C-bus from SDA to SDx, or SCL to SCx Fast-mode I2C-bus Unit Min Max Min Max - 0.3[1] - 0.3[1] ns 0 100 0 400 kHz 4.7 - 1.3 - µs 4.0 - 0.6 - µs 4.7 - 1.3 - µs tPD propagation delay fSCL SCL clock frequency tBUF bus free time between a STOP and START condition tHD;STA hold time (repeated) START condition tLOW LOW period of the SCL clock tHIGH HIGH period of the SCL clock 4.0 - 0.6 - µs tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - µs tSU;STO set-up time for STOP condition 4.0 - 0.6 - µs tHD;DAT data hold time 0[3] 3.45 0[3] 0.9 µs tSU;DAT data set-up time 250 - 100 - ns 0.1Cb[4] 300 ns [2] tr rise time of both SDA and SCL signals - 1000 20 + tf fall time of both SDA and SCL signals - 300 20 + 0.1Cb[4] 300 ns Cb capacitive load for each bus line - 400 - 400 pF tSP pulse width of spikes that must be suppressed by the input filter - 50 - 50 ns tVD;DAT data valid time tVD;ACK HIGH-to-LOW [5] - 1 - 1 µs LOW-to-HIGH [5] - 0.6 - 0.6 µs - 1 - 1 µs data valid acknowledge time INT tv(INTnN-INTN) valid time from INTn to INT signal [5] - 4 - 4 µs td(INTnN-INTN) delay time from INTn to INT inactive [5] - 2 - 2 µs INTn inputs [5] 1 - 1 - µs INTn inputs [5] 0.5 - 0.5 - µs tw(rej)L tw(rej)H LOW-level rejection time HIGH-level rejection time [1] Pass gate propagation delay is calculated from the 20 Ω typical Ron and the 15 pF load capacitance. [2] After this period, the first clock pulse is generated. [3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. [4] Cb = total capacitance of one bus line in pF. [5] Measurements taken with 1 kΩ pull-up resistor and 50 pF load. PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 16 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic SDA tr tBUF tf tHD;STA tSP tLOW SCL tHD;STA P S tSU;STA tHD;DAT tHIGH tSU;DAT Sr tSU;STO P 002aaa986 Fig 15. Definition of timing on the I2C-bus PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 17 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 16. Package outline SOT163-1 (SO20) PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 18 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 17. Package outline SOT360-1 (TSSOP20) PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 19 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic HVQFN20: plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 5 x 5 x 0.85 mm A B D SOT662-1 terminal 1 index area A A1 E c detail X C e1 e b 6 y y1 C v M C A B w M C 10 L 11 5 e e2 Eh 1 15 terminal 1 index area 20 16 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.38 0.23 c D(1) Dh E(1) Eh 0.2 5.1 4.9 3.25 2.95 5.1 4.9 3.25 2.95 e e1 2.6 0.65 e2 L v w y y1 2.6 0.75 0.50 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT662-1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22 Fig 18. Package outline SOT662-1 (HVQFN20) PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 20 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 21 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 19) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 10 and 11 Table 10. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 11. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 19. PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 22 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 19. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged-Device Model ESD ElectroStatic Discharge HBM Human Body Model I/O Input/Output I2C-bus Inter-Integrated Circuit bus LSB Least Significant Bit MM Machine Model PCB Printed-Circuit Board POR Power-On Reset SMBus System Management Bus PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 23 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic 15. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9544A_4 20090615 Product data sheet - PCA9544A_3 Modifications: • Table 9 “Dynamic characteristics”: – Symbol tf: changed Unit from “µs” to “ns” – Symbol Cb: changed Unit from “µs” to “pF” PCA9544A_3 20081124 Product data sheet - PCA9544A_2 PCA9544A_2 (9397 750 13931) 20040929 Product data sheet - PCA9544A_1 PCA9544A_1 (9397 750 13301) 20040728 Objective data sheet - - PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 24 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCA9544A_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 15 June 2009 25 of 26 PCA9544A NXP Semiconductors 4-channel I2C-bus multiplexer with interrupt logic 18. Contents 1 2 3 3.1 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.3 6.4 6.5 7 7.1 7.2 7.3 7.4 7.5 8 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Device addressing . . . . . . . . . . . . . . . . . . . . . . 6 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 6 Control register definition . . . . . . . . . . . . . . . . . 6 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . 7 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8 Voltage translation . . . . . . . . . . . . . . . . . . . . . . 8 Characteristics of the I2C-bus. . . . . . . . . . . . . . 9 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 START and STOP conditions . . . . . . . . . . . . . . 9 System configuration . . . . . . . . . . . . . . . . . . . . 9 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 11 Application design-in information . . . . . . . . . 12 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13 Static characteristics. . . . . . . . . . . . . . . . . . . . 14 Dynamic characteristics . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Soldering of SMD packages . . . . . . . . . . . . . . 21 Introduction to soldering . . . . . . . . . . . . . . . . . 21 Wave and reflow soldering . . . . . . . . . . . . . . . 21 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 21 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 22 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 24 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Contact information. . . . . . . . . . . . . . . . . . . . . 25 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 15 June 2009 Document identifier: PCA9544A_4