Features • Data Rate up to 50 MHz (2 Outputs at 25 MHz Each) • Pixel Size: 10 µm x 10 µm (10 µm Pitch) • 300 to 1100 nm Spectral Range • High Sensitivity and Lag-free Photodiodes • Very Low Noise (30 pJ/cm2 Noise Equivalent Illumination) • Antiblooming • Exposure Control • 20-lead 0.4" DIL Package • Electrical, Mechanical and Optical Compatibility Between the Two Products The TH7813 and TH7814 linear arrays are based on Atmel’s most recent know-how in terms of design and technology. Flexibility and performance of these devices give the opportunity to use them in most vision systems for industrial applications (web inspection, process control, sorting and inspection of various parts), document scanning up to 200 dpi, metrology, etc. 50 MHz 1024/2048 Linear CCDs Pin Identification TH7813A TH7814A All pins must be connected Pin Number Symbol Function 4, 17 VDD1,2 Output Amplifiers Drain Supply 3, 18 VOS1,2 Video Outputs 5 VS 20 VDR Reset Drain Supply 2 VGS Output Gate Bias 14 ΦL1 13 ΦL2 15 ΦR Reset Clock 10 ΦA Antiblooming Gate Bias/Clock 7 VA Antiblooming Drain Bias 8 VST Storage Gate Bias 11 ΦP Transfer Gate Clock 1, 6, 9, 12, 16, 19 VSS Ground, Optical Shield Grounding (Internally Connected) VSS VGS VOS1 VDD1 VS VSS VA VST VSS ΦA Output Amplifiers Substrate Bias Readout Register Clocks 1 20 2 19 3 18 4 17 5 TH7813A 16 6 TH7814A 15 7 14 8 13 9 12 10 11 VDR VSS VOS2 VDD2 VSS ΦR ΦL1 ΦL2 VSS ΦP Rev. 1990A–IMAGE–05/02 1 Absolute Maximum Ratings* *NOTICE: Storage Temperature Range ......................... -55°C to +150°C Operating Temperature Range........................ -40°C to +85°C Thermal Cycling..........................................................15°C/mn Stresses above those listed under absolute maximum ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Maximum Applied Voltages: • Pin: 2, 8, 10, 11, 13, 14, 15 .................................. -0.3 to 15V • Pin: 4, 5, 7, 17, 20 ................................................ -0.3 to 16V • Pin: 1, 6, 9, 12, 16, 19 .........................................0V (ground) Note: Operating range defines the limits within which the functionality is guaranteed. Electrical limits of applied signals are given in operating conditions section. Operating Precautions Shorting the video outputs to any other pin, even temporarily, can permanently damage the on-chip output amplifier. Operating Conditions Table 1. DC Characteristics Value Parameter Symbol Min Typ Max Unit VDD1, VDD2 14.5 15 15.5 V Storage Gate Bias VST 2.2 2.4 2.6 V Antiblooming Gate (See Pixel Saturation Adjustment) ΦA 2 4 7 V VDR 13.5 14 14.5 V VA 14.5 15 15.5 V Output Amplifier Drain Supply Reset Bias Antiblooming Diode Bias 2 TH7813A/TH7814A 1990A–IMAGE–05/02 TH7813A/TH7814A Table 1. DC Characteristics (Continued) Value Parameter Symbol Min Typ Max Unit VGS 2.2 2.4 2.6 V Register Output Gate Bias Output Amplifier Source Supply Ground VS 0 VSS 0 V Table 2. Drive Clocks Characteristics Value Parameter Symbol Min. Typ. Max. Unit Remark 8.5 -0.1 9 0 9.5 0.4 V V Clock Capacitance < 25 pF ΦR Reset gate High level Low level ΦP Transfer gate High level Low level Readout register clocks Hilgh level Low level Maximum readout register frequency 8.5 -0.1 9 0 8.5 -0.1 9 0 9.5 0.4 ΦL1, 2 FH Clock Capacitance < 100 pF V V 9.5 0.4 10 see Figure 1 and Figure 2 V V 25 MHz Figure 1. Readout Register Clocks Capacitance TH7813 ΦL1 50 pF 120 pF ΦL2 140 pF Figure 2. Readout Register Clocks Capacitance TH7814 ΦL1 230 pF 100 pF ΦL2 230 pF 3 1990A–IMAGE–05/02 Timing Diagrams The following diagram shows the general clocking scheme for the TH7813A and TH7814A. The line is composed as follows: Synopsis Number of Prescan Pixels Per Output Number of Useful Pixels Per Output Total Number of Pixels Per Output TH7813A 4 512 516 TH7814A 4 1024 1028 Postscan elements may be added in order to either increase the exposure time, or to provide a voltage reference level. Figure 3. Line Timing Diagram Line Period A P L1 L2 R Transfer Period The following diagram shows the timing for the transfer period: Figure 4. Line Transfer Period > 300 ns > 10 ns A (700 ns typ.) > 10 ns P L1 L2 R first prescan pixel ΦR clock may also be held in high state during line transfer period. The following diagram shows the detailed timing for the pixel readout: 4 TH7813A/TH7814A 1990A–IMAGE–05/02 TH7813A/TH7814A Figure 5. Pixel Readout Timing Diagram Tpixel 90% tr L1 Duty cycle: 50% ± 10% Crossover at 50% ± 10% Rise and fall time 10 ns 10% 90% tf L2 10% ± 0 ns 50% R Rise and fall time 8 ns 10 ns floating diode level Reset Feedthrough Video outputs are synchronous Video signal occurs on Offset in darkness Video signal L2 falling edge First useful pixel occurs on 5th falling edge of L2 after P VIDEO OUTPUTS Exposure Time Reduction Antiblooming Gate The antiblooming structure of the TH7813A and TH7814A provides an electronic shutter capability by clocking phase fA during the line period. The timing diagram is described below: ΦA Min Typ Max Unit Clock Capacitance (see note) High Level 8.5 9 9.5 V Low Level Sets Saturation Level Low Level 2 4 7 V See Pixel Saturation Adjustment Pulse Min. 200 Note: ns Clock capacitance: TH7813A = 50 pF, TH7814A = 100 pF 5 1990A–IMAGE–05/02 Figure 6. Exposure Time Reduction Line Period ΦA exposure time ≥100 ns ΦP Φ L1 Φ L2 ΦR Transfer Period Electro-optical Performance • General test conditions: TCASE = 25°C Light source: 2854K with 2 mm BG38 filter (unless specified) + F/11 optical aperture. Typical operating conditions: 2 x 10 MHz All values are referred to prescan pixels level. Value Parameter Saturation Output Voltage Responsivity Symbol Min Typ Max Unit VSAT 1.65 2 3 V R 7.5 8.5 Responsivity Unbalance Photo Response Non Uniformity Peak-to-peak Dark Signal Dark Signal Non Uniformity (1σ) V/µJ/cm2 2 5 % PRNU ±5 ±10 %VOS DS 0.1 0.4 mV/ms 0.1 mV/ms DSNU Temporal RMS Noise in Darkness VN Dynamic Range DR CTF CTF LAG LAG 1 Charge Transfer Inefficiency (per stage) HCTI 8.10-5 6 300 5,500 Remarks VOS = 50 mV to 1.5V µV 6,600 65 % % TH7813A/TH7814A 1990A–IMAGE–05/02 TH7813A/TH7814A Static And Dynamic Electrical Characteristics Value Parameter Symbol Output Amplifier Supply Current IDD Output Impedance ZS Min Typ Max 10 200 225 Unit Remarks mA per amplifier Ω 259 DC Output Level VREF 10 V Output Conversion Factor CVF 5 µV/e- Offset in Darkness DC off 30 mV Reset Feedthrough Vft 400 mV Electro-optical Performances without Infrared Cutoff Filter The TH7813A and TH7814A special semiconductor process enables to exploit the silicon's high near infrared sensitivity while maintaining good imaging performances in terms of response uniformity and resolution. Typical changes in performance with and without IR filtering are summarized below: Parameter With IR Cut-off Filter Without IR Cut-off Filter Average Video Signal Due to a Given Illumination VOS 6 x VOS PRNU (Single Defects Excluded) ±5% 5% CTF at Nyquist Frequency 65% 49% Pixel Saturation Adjustment The TH7813A and TH7814A antiblooming structure can be used to adjust the maximum saturation voltage, by adjusting the ΦA bias voltage. The following curve shows the relation between VSAT and VΦA. Figure 7. Pixel Saturation vs. Antiblooming Bias (Typical Conditions) Typical conditions Saturation Voltage (V) 3 2 1 0 2 3 4 5 6 7 (V) Antiblooming Bias 7 1990A–IMAGE–05/02 Spectral Responsivity The following curve shows the typical responsivity for TH7813A and TH7814A. Figure 8. Spectral Responsivity 12 Responsivity (V/µJ/cm2) 10 8 6 4 2 0 200 300 400 500 600 700 800 900 1000 1100 Wavelength (nm) 8 TH7813A/TH7814A 1990A–IMAGE–05/02 TH7813A/TH7814A Package Drawing Both devices have the same optical center 3 Z = 1.61±0.30 0.9±0.1 4 Z = 2.01±0.30 Notes: 1. 2. 3. 4. 5. Window Photosensitive area Optical distance between external face of window and photosensitive area Optical distance between backside of package and photosensitive area First pixel position (mm): TH7813A TH7814A X = 9.6 ± 0.4 X = 4.5 ± 0.4 Y = 5.2 ± 0.35 Y = 5.2 ± 0.35 Ordering Code TH7813ACC TH7814ACC 9 1990A–IMAGE–05/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 Microcontrollers Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 RF/Automotive ASIC/ASSP/Smart Cards Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 1150 East Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ATMEL ® is the registered trademarks of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper. 1990A–IMAGE–05/02 0M