INTEGRATED CIRCUITS DATA SHEET SAA7112 Decoder with High-Performance Scaler (HPS) for Image Port (PELICAN) Preliminary specification File under Integrated Circuits, IC22 1996 Jun 20 Philips Semiconductors Preliminary specification Decoder with High-Performance Scaler (HPS) for Image Port (PELICAN) SAA7112 FEATURES The PELICAN SAA7112 is a video capture device for application at the image port of a VGA controller, with following feature highlights: Video Decoder • Six analog inputs, internal analog source selectors, (e.g. 6 × CVBS or(2 × YC and 2 × CVBS) or (1 × YC and 4 × CVBS) • Vertical scaling with linear phase interpolation (6-bit phase accuracy) and accumulating filter for anti-aliasing • Horizontal phase correct up- and down-scaling for improved signal quality of scaled data, especially for compression and video phone applications, with 6-bit phase accuracy • Two analog preprocessing channels, including built in analog anti-alias filters • Fully programmable static gain for the main channels or Automatic Gain Control (AGC) for the selected CVBS/Y channel • Two independent programming sets for scaler part, to define two ‘ranges’ per field or per frame • Two 8 bit video CMOS Analog-to-Digital Converters (ADCs) • Field-wise switching between decoder-part and expansion port input • Automatic Clamp Control (ACC) for CVBS, Y and C • Brightness, contrast and saturation controls for scaled outputs. • Switchable white peak control • On-chip line locked clock generation in accordance with CCIR-601 VBI-data decoder and text slicer • Digital PLL for synchronization and clock generation from all standards and non-standard video sources, e.g. consumer grade VTR • versatile VBI-data decoder, slicer, clock regeneration and byte synchronization; e.g. for WST, NABST, Close Caption, WSS, etc. • Requires only one crystal (32.11 MHz) for all standards Audio clock generation • Horizontal and vertical sync detection • Generation of a field locked audio master clock to support a constant number of audio clocks per video field • Automatic detection of 50/60Hz field frequency, and automatic switching between standards PAL and NTSC • Luminance and chrominance signal processing for PAL BGHI, PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43 and SECAM • Generation of an audio serial and left/right (channel) clock signal. • User programmable luminance peaking or aperture correction Digital I/O interfaces • Real time signal port (R-port), including continuous line locked reference clock and real time status information • Cross-colour reduction for NTSC by chrominance combination filtering • Bidirectional expansion port (X-port) with half duplex functionality (D1), 8-bit YUV • PAL delay line for correcting PAL phase errors • Real time status information output (RTCO) – output from decoder part, real time, or • Independent Brightness Contrast Saturation (BCS) adjustment for decoder part. – input to scaler part, e.g. video from MPEG-decoder • Video image port (I-port) configurable for 8-bit (16-bit) data in master mode (own clock), or slave mode (external clock), with auxiliary timing and hand shake signals Video Scaler • Horizontal and vertical down-scaling and up-scaling to randomly sized windows • 8-bit data Host port (H-port) for 16-bit extension of I-port • Horizontal and vertical scaling range: 2 (zoom) to 1⁄64 (icon); vertical zoom might be restricted • Discontinuous data streams supported • 32-word × 4 bytes FIFO register for video output data • Anti-alias- and accumulating filter for horizontal scaling 1996 Jun 20 2 Philips Semiconductors Preliminary specification Decoder with High-Performance Scaler (HPS) for Image Port (PELICAN) • 16-word × 4 bytes FIFO register for decoded VBI output data SAA7112 scaling and a brightness, contrast and saturation control circuit (see Fig.1). Scaled 4 : 2 : 2, 4 : 1 : 1 YUV output It is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into CCIR-601 compatible colour component values. The SAA7112 accepts as analog inputs CVBS or S-video (Y−C) from TV or VCR sources, including weak and distorted signals. An Expansion port for digital video (bidirectional half duplex, D1 compatible) is also supported to connect to MPEG or video phone CODEC. At the so called image port the SAA7112 supports 8-bit (16-bit) wide output data with auxiliary reference data for interfacing to VGA controllers • Scaled 8-bit luminance only and raw data output • Decoded VBI data output. miscellaneous • Power-on control • Programming via I2C-bus, or parallel image data port (full read-back ability by an external controller) • Chip enable function (reset for the clock generator). APPLICATIONS The target application for PELICAN is to capture and scale video images, to be provided as digital video stream through the image port of a VGA controller, for display via VGAs frame buffer, or for capture to system memory. • Desktop video • Multimedia • Digital television In parallel the SAA7112 incorporates also provisions for capturing the serially coded data in the vertical blanking interval (VBI-data). Two principal functions are available: to capture raw video samples and a versatile data slicer (data recovery) unit. • Image processing • Video phone. GENERAL DESCRIPTION The SAA7112 incorporates also a field locked audio clock generation. This function ensures that there is always the same number of audio samples associated with a field, or a set of fields. This prevents the loss of synchronization between video and audio, during capture or playback. The PELICAN SAA7112 is a video capture device for applications at the image port of VGA controllers. The SAA7112 is a combination of a two channel analog preprocessing circuit including source-selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder and a SAA7140B based scaler, including variable horizontal and vertical up and down The circuit can be controlled via the I2C-bus or via its fast parallel programming mode of the image port interface (full write/read capability). QUICK REFERENCE DATA SYMBOL PARAMETER MIN. MAX. UNIT VDDD digital supply voltage 3.0 3.6 V VDDA analog supply voltage 3.0 3.6 V Tamb ambient temperature 0 70 °C ORDERING INFORMATION TYPE NUMBER SAA7112 1996 Jun 20 PACKAGE NAME LQFP100 DESCRIPTION plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm 3 VERSION SOT407-1 Philips Semiconductors Preliminary specification Decoder with High-Performance Scaler (HPS) for Image Port (PELICAN) SAA7112 BLOCK DIAGRAMS handbook, full pagewidth XCLK LLC2 LLC XDQ RTS0 RTCA XRH XPD7 to XPD0 XREC XRV XTRI RTS1 RT OUT EXPANSION PORT PIN MAPPING D1 OUT D1 IN chroma of 16-bit mode from host port a RESIN RESON CE XOUT CLOCK GENERATION AND POWER ON CONTROL X PORT INPUT FORMATTER (SELECT) XTALI XTAL data, clock, H, V, FID and qualifier to scaler AI11 AI12 AI21 AI22 AI23 ANALOG DUAL ADC SAA7111A BASED DIGITAL DECODER b 4:2:2 OUTPUT INTERFACE AI24 AOUT AMCLK ALRCLK ASCLK AXMCLK AUDIO MASTER CLOCK GENERATION Vref Vref data, clock, H, V, FID and qualifier to text slicer AUDIO BIT BLOCK WORD SELECT GENERATION c MGE859 Fig.1 Block diagram (continued in Fig.2). 1996 Jun 20 4 Philips Semiconductors Preliminary specification Decoder with High-Performance Scaler (HPS) for Image Port (PELICAN) handbook, full pagewidth HRWNF HADP HPD7 to HPD0 HACNSD HDSNSC SAA7112 HCST HOST PORT PIN MAPPING chroma of 16-bit input mode I2C-BUS chroma of 16-bit output mode a LPB PROG from event controller PROG. PORT CONTROL PROGRAMMING REGISTER ARRAY data, clock, H, V, FID and qualifier from scaler input selector INPUT ACQUISITION CONTROL b A/B REGISTER MUX SLEEP MODE REGISTER CLOCK MULTIPLEXER INCLUDING TCB PRESCALING LUMINANCE VERTICAL SCALING PROCESSOR HORIZONTAL PHASE SCALING LUMINANCE LINE MEMORY 1H * 16 BIT HORIZONTAL PHASE SCALING CHROMINANCE FIR-FILTER LUMINANCE 4:2:2 BCS CONTROL FIR FILTER CHROMINANCE PRESCALING CHROMINANCE LINE FIFO BUFFER IPD7 to IPD0 IMAGE PORT PIN MAPPING IRH IRV EVENT CONTROLLER OUTPUT ACQUISITION CONTROL YUV OUTPUT FORMAT VIDEO FIFO 32 × 32 FIFO CONTROL data, clock and reference signals from text input selector c FIFO CONTROL GENERAL PURPOSE TEXTSLICER TEXT FIFO 16 × 32 TXT INTERFACE IDQE 32 TO 8 (16) MUX Fig.2 Block diagram (continued from Fig.1). 5 ITRDY ICLK 32 TO 8 (16) MUX VIDEO / TEXT ARBITER 1996 Jun 20 ICRQF FF IP OUT ITRI LPB VIDEO OUT MGE860 Philips Semiconductors Preliminary specification Decoder with High-Performance Scaler (HPS) for Image Port (PELICAN) SAA7112 PACKAGE OUTLINE LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 c y X A 51 75 50 76 ZE e Q E HE A A2 (A 3) A1 w M θ bp Lp L pin 1 index 100 detail X 26 1 25 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.20 0.05 1.5 1.3 0.25 0.28 0.16 0.18 0.12 14.1 13.9 14.1 13.9 0.5 HD HE 16.25 16.25 15.75 15.75 L Lp Q v w y 1.0 0.75 0.45 0.70 0.57 0.2 0.12 0.1 Z D (1) Z E (1) θ 1.15 0.85 7 0o 1.15 0.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-12-19 SOT407-1 1996 Jun 20 EUROPEAN PROJECTION 6 o Philips Semiconductors Preliminary specification Decoder with High-Performance Scaler (HPS) for Image Port (PELICAN) SAA7112 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1996 Jun 20 7 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 805 4455, Fax. +61 2 805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 2A Akademika Koroleva str., Office 165, 252148 KIEV, Tel. +380 44 476 0297/1642, Fax. +380 44 476 6991 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 825 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com/ps/ (1) ADDRESS CONTENT SOURCE July 9, 1997 © Philips Electronics N.V. 1996 SCA49 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 657021/01/pp8 Date of release: 1996 Jun 20 Document order number: 9397 750 00923