INTEGRATED CIRCUITS 74F168*, 74F169 4-bit up/down binary synchronous counter * Discontinued part. Please see the Discontinued Product List in Section 1, page 21. Product specification IC15 Data Handbook 1996 Jan 05 Philips Semiconductors Product specification 4-bit up/down binary synchronous counter FEATURES 74F169 PIN CONFIGURATION • Synchronous counting and loading • Up/Down counting • Modulo 16 binary counter • Two Count Enable inputs for n-bit cascading • Positive edge-triggered clock • Built-in carry look-ahead capability • Presettable for programmable operation U/D 1 16 VCC CP 2 15 TC D0 3 14 Q0 D1 4 13 Q1 D2 5 12 Q2 D3 6 11 Q3 CEP 7 10 CET GND 8 9 PE DESCRIPTION SF00766 The 74F169 is a 4-bit synchronous, presettable Modulo 16 up/down counter featuring an internal carry look-ahead for applications in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the Count Enable inputs and internal gating. This mode of operation eliminates the output spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the flip-flops on the Low-to-High transition of the clock. TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F169 115MHz 35mA ORDERING INFORMATION The counter is fully programmable; that is, the outputs may be preset to either level. ORDER CODE Presetting is synchronous with the clock and takes place regardless of the levels of the Count Enable inputs. A Low level on the Parallel Enable (PE) input disables the counter and causes the data at the Dn input to be loaded into the counter on the next Low-to-High transition of the clock. DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C PKG DWG # 16-pin plastic DIP N74F169N SOT38-4 16-pin plastic SO N74F169D SOT109-1 The direction of counting is controlled by the Up/Down (U/D) input; a High will cause the count to increase, a Low will cause the count to decrease. The carry look-ahead circuitry provides for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two Count Enable inputs (CET, CEP) and a Terminal Count (TC) output. Both Count Enable inputs must be Low to count. The CET input is fed forward to enable the TC output. The TC output thus enabled will produce a Low output pulse with a duration approximately equal to the High level portion of the Q0 output. The Low level TC pulse is used to enable successive cascaded stages. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D0 - D3 Parallel data inputs 1.0/1.0 20µA/0.6mA CEP Count Enable parallel input (active Low) 1.0/1.0 20µA/0.6mA CET Count Enable Trickle input (active Low) 1.0/2.0 20µA/1.2mA CP Clock input (active rising edge) 1.0/1.0 20µA/0.6mA PE Parallel Enable input (active Low) 1.0/1.0 20µA/0.6mA U/D Up/Down count control input 1.0/1.0 20µA/0.6mA Q 0 - Q3 Flip-flop outputs 50/33 1.0mA/20mA TC Terminal count output (active Low) 50/33 NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state. 1.0mA/20mA 1996 Jan 05 2 853–0350 16190 Philips Semiconductors Product specification 4-bit up/down binary synchronous counter LOGIC SYMBOL 74F169 LOGIC SYMBOL (IEEE/IEC) 3 4 5 CTR DIV 16 6 9 M1 [LOAD] M2 [COUNT] 9 PE 1 U/D D0 D1 D2 D3 1 M4 [DOWN] 10 2 CP 7 CEP 10 CET M3 [UP] 15 TC 7 G5 3, 5 CT=15 G6 4, 5 CT=0 2 Q0 Q1 Q2 Q3 14 13 12 11 2, 3, 5, 6+/C7 2, 4, 5, 6– 3 1, 7D 14 [1] 4 13 [2] 5 VCC = Pin 16 GND = Pin 8 15 12 [4] 6 11 [8] SF00786 SF00787 FUNCTIONAL DESCRIPTION when a counter reaches zero in the Count Down mode or reaches 15 in the Count Up mode. The TC output state is not a function of the Count Enable Parallel (CEP) input level. Since the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC as a clock signal is not recommended (see logic equations below). The 74F169 uses edge-triggered J-K-type flip-flops and have no constraints on changing the control or data input signals in either state of the clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the Mode Select Table. When PE is Low, the data on the D0 - D3 inputs enter the flip-flops on the next rising edge of the Clock. In order for counting to occur, both CEP and CET must be Low and PE must be High; the U/D input determines the direction of counting. The Terminal Count (TC) output is normally High and goes Low, provided that CET is Low, 1) Count Enable = CEP⋅CET⋅PE 2) Up: TC = Q0⋅Q3⋅(U/D)⋅CET 3) Down: TC = Q0⋅Q1⋅Q2⋅Q3⋅(U/D)⋅CET MODE SELECT — FUNCTION TABLE INPUTS H = h = L = l = q = X = ↑ = (1) = OUTPUTS OPERATING MODE CP U/D CEP CET PE Dn Qn TC ↑ X X X X X X l X l X L H (1) (1) Parallel load (Dn→Qn) ↑ ↑ h l l h X Count Up (1) Count Up (increment) ↑ l l l h X Count Down (1) Count Down (decrement) ↑ X h X h X qn (1) Hold (do nothing) ↑ X X X h X qn H High voltage level steady state High voltage level one setup time prior to the Low-to-High clock transition Low voltage level steady state Low voltage level one setup time prior to the Low-to-High clock transition Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition Don’t care Low-to-High clock transition The TC is Low when CET is Low and the counter is at Terminal Count. Terminal Count Up is (HHHH) and Terminal Count Down is (LLLL). 1996 Jan 05 3 Philips Semiconductors Product specification 4-bit up/down binary synchronous counter MODE SELECT TABLE 74F169 STATE DIAGRAM INPUTS PE CEP CET U/D L X X H L L H L L H H X H X H H = High Voltage L = Low Voltage Level X = Don’t care X H L X X OPERATING MODE 0 Load (Dn→Qn) Count Up (Increment) Count Down (Decrement) No Change (Hold) No Change (Hold) 1 2 3 4 15 5 14 6 13 7 12 11 10 9 8 COUNT DOWN COUNT UP SF00788 LOGIC DIAGRAM 3 D D0 Q CP Q D1 4 D D 5 PE D 6 Q1 12 Q2 Q CP Q 9 13 Q CP Q D3 Q0 Q CP Q D2 14 11 Q3 7 CEP 10 CET CP U/D 2 1 15 VCC = Pin 16 GND = Pin 8 1996 Jan 05 TC SF00789 4 Philips Semiconductors Product specification 4-bit up/down binary synchronous counter 74F169 APPLICATION CP U/D PE D0 D1 D2 D3 D0 D1 D2 D3 PE D0 D1 D2 D3 PE PE PE U/D U/D U/D U/D CP CP CP CP TC CEP CET Q0 Q1 Q2 Q3 TC CEP CET Q0 Q1 Q2 TC CEP CET Q3 Q0 Q1 Q2 D1 D0 D2 D3 TC CEP CET Q3 Q0 LEAST SIGNIFICANT 4-BIT COUNTER Q1 Q2 Q3 MOST SIGNIFICANT 4-BIT COUNTER SF00790 Figure 1. Synchronous Multistage Counting Scheme ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current VOUT Voltage applied to output in High output state IOUT Current applied to output in Low output state Tamb Operating free-air temperature range TSTG Storage temperature –30 to +5 mA –0.5 to +VCC V 40 mA 0 to +70 °C –65 to +150 °C LIMITS UNIT RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER Min Nom Max VCC Supply voltage 4.5 5.0 5.5 VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –1 mA IOL Low-level output current 20 mA Tamb Operating free-air temperature range 70 °C 1996 Jan 05 0 5 V V Philips Semiconductors Product specification 4-bit up/down binary synchronous counter 74F169 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) LIMITS SYMBOL TEST CONDITIONSNO TAG PARAMETER MIN VCC = MIN,, VIL = MAX,, VIH = MIN, IOH = MAX VOH O High level output voltage High-level VOL O Low level output voltage Low-level VCC = MIN,, VIL = MAX,, VIH = MIN, IOL = MAX VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage VCC = MAX, VI = 7.0V IIH High-level input current 2.7 ±10%VCC ±5%VCC 3.4 V 0.35 0.50 V 0.35 0.50 V –0.73 –1.2 V 100 µA 20 µA VCC = MAX, VI = 0.5V –1.2 mA Others VCC = MAX, VI = 0.5V IOS Short-circuit output currentNO TAG Supply current ±5%VCC V VCC = MAX, VI = 2.7V Low level input current Low-level ICC 2.5 UNIT MAX CET IIL (total)4 ±10%VCC TYP NO TAG VCC = MAX –60 VCC = MAX 35 –0.6 mA –150 mA 52 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. ICC is measured after applying a momentary 4.5V, then ground to the clock input with all other inputs grounded and all outputs open. 1996 Jan 05 6 Philips Semiconductors Product specification 4-bit up/down binary synchronous counter 74F169 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5V CL = 50pF, RL = 500Ω TEST CONDITIONS MIN TYP Tamb = 0°C to +70°C VCC = +5V ± 10% CL = 50pF, RL = 500Ω MAX MIN UNIT MAX fMAX Maximum clock frequency Waveform 1 100 115 tPLH tPHL Propagation delay CP to Qn (PE, High or Low) Waveform 1 3.0 4.0 6.5 9.0 8.5 11.5 3.0 4.0 90 9.5 13.0 MHz ns ns tPLH tPHL Propagation delay CP to TC Waveform 1 5.5 4.0 12.0 8.5 15.5 11.0 5.5 4.0 17.0 12.5 ns ns tPLH tPHL Propagation delay CET to TC Waveform 2 2.5 2.5 4.5 6.0 6.0 8.0 2.5 2.5 7.0 9.0 ns ns tPLH tPHL Propagation delay U/D to TC Waveform 3 3.5 4.0 8.5 8.0 15.0 10.5 3.5 4.0 15.5 12.0 ns ns AC SETUP REQUIREMENTS SYMBOL PARAMETER TEST CONDITIONS LIMITS LIMITS Tamb= +25°C VCC = +5.0V CL = 50pF, RL = 500Ω Tamb= 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN ts(H) ts(L) Setup time, High or Low Dn to CP th(H) th(L) TYP MIN UNIT MAX Waveform 4 4.0 4.0 4.5 4.5 ns ns Hold time, High or Low Dn to CP Waveform 4 3.0 3.0 3.5 3.5 ns ns ts(H) ts(L) Set-up time, High or Low CEP or CET to CP Waveform 5 5.0 5.0 5.5 5.5 ns ns th(H) th(L) Hold time, High or Low CEP or CET to CP Waveform 5 0 0 0 0 ns ns ts(H) ts(L) Set-up time, High or Low PE to CP Waveform 4 8.0 8.0 9.0 9.0 ns ns th(H) th(L) Hold time, High or Low PE to CP Waveform 4 0 0 0 0 ns ns ts(H) ts(L) Set-up time, High or Low U/D to CP Waveform 6 11.0 7.0 12.5 8.0 ns ns th(H) th(L) Hold time, High or Low U/D to CP Waveform 6 0 0 0 0 ns ns tw(H) tw(L) CPU or CPD pulse width, High or Low Waveform 1 5.0 5.0 5.5 5.5 ns ns 1996 Jan 05 7 Philips Semiconductors Product specification 4-bit up/down binary synchronous counter 74F169 AC WAVEFORMS For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fMAX CET CP VM VM tW(H) VM tPHL tW(L) tPLH tPHL tPLH TC VM Qn VM VM VM VM VM SF00792 tPLH tPHL TC VM Waveform 2. Propagation Delays CET Input to Terminal Count Output VM SF00791A Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency Dn VM VM th ts VM U/D PE VM tPHL ts(L) tPLH TC VM VM VM VM VM th = 0 VM ts(H) th = 0 VM CPn VM SF00793 SF00794 Waveform 3. Propagation Delay U/D Input to Terminal Count Output Waveform 4. Parallel Data and Parallel Enable Setup and Hold Times CET VM VM VM U/D VM VM VM VM VM CEP ts(L) CPn VM Qn NO CHANGE th(L) ts(H) ts(L) th(H) CPn VM VM COUNT VM Qn NO CHANGE SF00795 ts(H) VM COUNT DOWN th(H) VM COUNT UP SF00796 Waveform 5. Count Enable Setup and Hold Times 1996 Jan 05 th(L) Waveform 6. Up/Down Control Setup and Hold Times 8 Philips Semiconductors Product specification 4-bit up/down binary synchronous counter 74F169 TIMING DIAGRAM (Typical Load, Count, and Inhibit Sequences) PE D0 D1 D2 D3 CP U/D CEP and CET Q0 Q1 Q2 Q3 TC SEQUENCE 7 8 9 0 1 2 } COUNT UP LOAD 2 2 1 0 INHIBIT 9 8 7 COUNT DOWN SF00797 NOTES: The operation of the 74F169 is similar to the Illustration above. 1. Load (preset) to BCD seven 2. Count up to eight, nine (maximum), zero, one, and two 3. Inhibit 4. Count down to one, zero (minimum), nine, eight, and seven TEST CIRCUIT AND WAVEFORM VCC VIN tw 90% NEGATIVE PULSE 10% D.U.T. RT CL RL AMP (V) VM VM VOUT PULSE GENERATOR 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% POSITIVE PULSE VM VM 10% Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 90% 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00006 1996 Jan 05 9 Philips Semiconductors Product specification 4-bit up/down binary synchronous counter DIP16: plastic dual in-line package; 16 leads (300 mil) * Discontinued part. Please see the Discontinued Product List in Section 1, page 21. 1996 Jan 05 10 74F168*, 74F169 SOT38-4 Philips Semiconductors Product specification 4-bit up/down binary synchronous counter SO16: plastic small outline package; 16 leads; body width 3.9 mm * Discontinued part. Please see the Discontinued Product List in Section 1, page 21. 1996 Jan 05 11 74F168*, 74F169 SOT109-1 Philips Semiconductors Product specification 4-bit up/down binary synchronous counter 74F168*, 74F169 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A. (print code) Document order number: * Discontinued part. Please see the Discontinued Product List in Section 1, page 21. Date of release: July 1994 9397-750-05087