PHILIPS 74ALVC00

INTEGRATED CIRCUITS
DATA SHEET
74ALVC00
Quad 2-input NAND gate
Product specification
Supersedes data of 2003 Feb 06
2003 May 14
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74ALVC00
FEATURES
DESCRIPTION
• Wide supply voltage range from 1.65 to 3.6 V
The 74ALVC00 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
• 3.6 V tolerant inputs/outputs
• CMOS low power consumption
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall times.
• Direct interface with TTL levels (2.7 to 3.6 V)
• Power-down mode
The 74ALVC00 provides the 2-input NAND function.
• Latch-up performance exceeds 250 mA
• Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C.
SYMBOL
tPHL/tPLH
PARAMETER
propagation delay inputs
nA, nB to output nY
CONDITIONS
TYPICAL
UNIT
VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ
2.8
ns
VCC = 2.5 V; CL = 30 pF; RL = 500 Ω
2.1
ns
VCC = 2.7 V; CL = 50 pF; RL = 500 Ω
2.6
ns
VCC = 3.3 V; CL = 50 pF; RL = 500 Ω
2.1
ns
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per buffer VCC = 3.3 V; notes 1 and 2
28
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
2003 May 14
2
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74ALVC00
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
74ALVC00D
−40 to +85 °C
14
SO14
plastic
SOT108-1
74ALVC00PW
−40 to +85 °C
14
TSSOP14
plastic
SOT402-1
74ALVC00BQ
−40 to +85 °C
14
DHVQFN14
plastic
SOT762-1
FUNCTION TABLE
See note 1.
INPUT
OUTPUT
nA
nB
nY
L
L
H
L
H
H
H
L
H
H
H
L
Note
1. H = HIGH voltage level;
L = LOW voltage level.
PINNING
PIN
SYMBOL
DESCRIPTION
1
1A
data input
2
1B
data input
3
1Y
data output
4
2A
data input
5
2B
6
handbook, halfpage
1A
1
14 VCC
1B
2
13 4B
data input
1Y
3
12 4A
2Y
data output
2A
4
7
GND
ground (0 V)
2B
5
10 3B
8
3Y
data output
2Y
6
9
3A
9
3A
data input
GND
7
8
3Y
10
3B
data input
11
4Y
data output
12
4A
data input
13
4B
data input
14
VCC
supply voltage
2003 May 14
00
11 4Y
MNA210
Fig.1 Pin configuration SO14 and TSSOP14.
3
Philips Semiconductors
Product specification
Quad 2-input NAND gate
handbook, halfpage
1A
VCC
1
14
74ALVC00
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
GND(1)
handbook, halfpage
A
Y
B
Top view
7
8
GND
3Y
MNA211
MNA950
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.2 Pin configuration DHVQFN14.
Fig.3 Logic diagram (one gate).
handbook, halfpage
handbook, halfpage
1
&
3
&
6
&
8
&
11
2
1
2
1A
1B
4
5
2A
2B
2Y
6
5
9
10
3A
3B
3Y
8
9
1Y
3
4
10
12
13
4A
4B
4Y
11
12
13
MNA212
MNA246
Fig.4 Function diagram.
2003 May 14
Fig.5 IEC logic symbol.
4
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74ALVC00
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCC
supply voltage
1.65
3.6
V
VI
input voltage
0
3.6
V
VO
output voltage
VCC = 1.65 to 3.6 V
0
VCC
V
VCC = 0 V; Power-down mode
0
3.6
V
Tamb
operating ambient temperature
−40
+85
°C
tr, tf
input rise and fall times
VCC = 1.65 to 2.7 V
0
20
ns/V
VCC = 2.7 to 3.6 V
0
10
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
VCC
supply voltage
IIK
input diode current
VI
input voltage
IOK
output diode current
VO
output voltage
IO
output source or sink current
CONDITIONS
VI < 0
VO > VCC or VO < 0
MIN.
MAX.
UNIT
−0.5
+4.6
V
−
−50
mA
−0.5
+4.6
V
−
±50
mA
notes 1 and 2
−0.5
VCC + 0.5 V
Power-down mode; note 2
−0.5
+4.6
V
VO = 0 to VCC
−
±50
mA
ICC, IGND
VCC or GND current
−
±100
mA
Tstg
storage temperature
−65
+150
°C
Ptot
power dissipation per package
−
500
mW
Tamb = −40 to +125 °C; note 3
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When VCC = 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation.
3. For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.
2003 May 14
5
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74ALVC00
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
OTHER
TYP.(1)
MAX.
UNIT
VCC (V)
Tamb = −40 to +85 °C
VIH
VIL
VOL
VOH
HIGH-level input voltage
−
V
1.7
−
−
V
2
−
−
V
2.7 to 3.6
1.65 to 1.95 −
−
0.35 × VCC V
2.3 to 2.7
−
−
0.7
V
2.7 to 3.6
−
−
0.8
V
IO = 100 µA
1.65 to 3.6
−
−
0.2
V
IO = 6 mA
1.65
−
0.11
0.3
V
IO = 12 mA
2.3
−
0.17
0.4
V
IO = 18 mA
2.3
−
0.25
0.6
V
IO = 12 mA
2.7
−
0.16
0.4
V
IO = 18 mA
3.0
−
0.23
0.4
V
IO = 24 mA
3.0
−
0.30
0.55
V
IO = −100 µA
1.65 to 3.6
VCC − 0.2
−
−
V
IO = −6 mA
1.65
1.25
1.51
−
V
IO = −12 mA
2.3
1.8
2.10
−
V
IO = −18 mA
2.3
1.7
2.01
−
V
IO = −12 mA
2.7
2.2
2.53
−
V
IO = −18 mA
3.0
2.4
2.76
−
V
IO = −24 mA
3.0
2.2
2.68
−
V
LOW-level input voltage
LOW-level output voltage
1.65 to 1.95 0.65 × VCC −
2.3 to 2.7
VI = VIH or VIL
HIGH-level output voltage VI = VIH or VIL
ILI
input leakage current
VI = 3.6 V or GND
3.6
−
±0.1
±5
µA
Ioff
power OFF leakage
current
VI or VO = 3.6 V
0.0
−
±0.1
±10
µA
ICC
quiescent supply current
VI = VCC or GND;
IO = 0
3.6
−
0.2
20
µA
∆ICC
additional quiescent
supply current per input
pin
VI = VCC − 0.6 V;
IO = 0
3.0 to 3.6
−
5
750
µA
Note
1. All typical values are measured at Tamb = 25 °C.
2003 May 14
6
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74ALVC00
AC CHARACTERISTICS
TEST CONDITIONS
SYMBOL
PARAMETER
MIN.
WAVEFORMS
TYP.(1)
MAX.
UNIT
VCC (V)
Tamb = −40 to +85 °C
tPHL/tPLH
propagation delay
nA, nB to nY
see Figs 6 and 7
1.65 to 1.95
1.0
2.8
4.4
ns
2.3 to 2.7
1.0
2.1
2.8
ns
2.7
1.0
2.6
3.2
ns
3.0 to 3.6
1.0
2.1
3.0
ns
Note
1. All typical values are measured at Tamb = 25 °C.
AC WAVEFORMS
VI
handbook, halfpage
VM
nA, nB input
GND
tPHL
tPLH
VOH
VM
nY output
VOL
MNA218
INPUT
VCC
VM
VI
tr = tf
1.65 to 1.95 V
0.5 × VCC
VCC
≤ 2.0 ns
2.3 to 2.7 V
0.5 × VCC
VCC
≤ 2.0 ns
2.7 V
1.5 V
2.7 V
≤ 2.5 ns
3.0 to 3.6 V
1.5 V
2.7 V
≤ 2.5 ns
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.6 Inputs nA, nB to output nY propagation delay times.
2003 May 14
7
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74ALVC00
VEXT
handbook, full pagewidth
VCC
PULSE
GENERATOR
VI
RL
VO
D.U.T.
CL
RT
RL
MNA616
VCC
VEXT
CL
RL
VCC
30 pF
1 kΩ
open
GND
2 × VCC
2.3 to 2.7 V
VCC
30 pF
500 Ω
open
GND
2 × VCC
2.7 V
2.7 V
50 pF
500 Ω
open
GND
6V
3.0 to 3.6 V
2.7 V
50 pF
500 Ω
open
GND
6V
1.65 to 1.95 V
VI
tPLH/tPHL
tPZH/tPHZ
tPZL/tPLZ
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.7 Load circuitry for switching times.
2003 May 14
8
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74ALVC00
PACKAGE OUTLINES
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
HE
v M A
Z
8
14
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.010 0.057
0.004 0.049
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.05
0.028
0.024
0.01
0.01
0.004
0.028
0.012
inches 0.069
0.244
0.039
0.041
0.228
0.016
θ
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06
MS-012
2003 May 14
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
9
o
8
0o
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74ALVC00
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
E
D
A
X
c
y
HE
v M A
Z
8
14
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
2003 May 14
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
10
o
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74ALVC00
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT762-1
14 terminals; body 2.5 x 3 x 0.85 mm
A
B
D
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
2
6
y
y1 C
v M C A B
w M C
b
L
1
7
Eh
e
14
8
13
9
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
0.5
2
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT762-1
---
MO-241
---
2003 May 14
11
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74ALVC00
If wave soldering is used the following conditions must be
observed for optimal results:
SOLDERING
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferably be kept:
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
• below 220 °C for all the BGA packages and packages
with a thickness ≥ 2.5mm and packages with a
thickness <2.5 mm and a volume ≥350 mm3 so called
thick/large packages
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
• below 235 °C for packages with a thickness <2.5 mm
and a volume <350 mm3 so called small/thin packages.
Wave soldering
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
2003 May 14
12
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74ALVC00
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
not suitable
suitable(3)
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS
not
PLCC(4), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO, VSSOP
REFLOW(2)
suitable
suitable
suitable
not
recommended(4)(5)
suitable
not
recommended(6)
suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2003 May 14
13
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74ALVC00
DATA SHEET STATUS
LEVEL
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
Development
DEFINITION
I
Objective data
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Production
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 May 14
14
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74ALVC00
NOTES
2003 May 14
15
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
SCA75
© Koninklijke Philips Electronics N.V. 2003
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Printed in The Netherlands
613508/02/pp16
Date of release: 2003
May 14
Document order number:
9397 750 11262