PHILIPS SAA5281ZP

INTEGRATED CIRCUITS
DATA SHEET
SAA5281
Integrated Video input processor
and Teletext decoder (IVT1.8*)
Preliminary specification
Supersedes data of June 1994
File under Integrated Circuits, IC02
1996 Nov 04
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
FEATURES
• Complete Teletext and VPS decoding in a single
package
• Built-in 8K × 8 memory for up to 8 page storage
• Enhanced mode allows 7 Fastext pages and 8 pages of
TOP to be captured
• Ability to request only subtitle pages
DESCRIPTION
• Acquisition and decoding of VPS data
The IVT1.8* is a single-chip Teletext decoder IC for
decoding 625-line based World System Teletext
transmissions. The device is based on IVT1.0VPS and has
reception facilities for the 5 MHz biphase VPS signal. It is
intended for use in video recorders, in particular to
implement the VPT facility (VCR programming via
Teletext). With suitable software both VPT standards
(EBU PDC System A and System B) can be
accommodated to allow operation from any European VPT
transmission. Automatic processing of packet 26
transmissions is also possible. No external memory is
required as an 8K × 8 DRAM is included on-chip for up to
8 page storage. An enhanced mode allows 7 Fastext
pages to be stored, with one chapter used to store
extension packets.
• Data valid output available to indicate reception of
error-free VPS or packet 8/30/2 data
• Software and hardware compatible with SAA5246 and
SAA5248
• Meshing display within boxes
• Separate data checking algorithms and pointers for
each acquisition channel
• 24 : 18 Hamming checker
• Automatic packet 26 extension character processing
• Indication of Line 23 for external use
• 13.5 MHz clock output to drive external microcontroller
• Detection of Spanish transmissions to disable
flicker-stopper
• Compatible with Philips’ one-chip TV IC (TDA836X) for
scan-locking applications.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VDD
supply voltage
4.5
5.0
5.5
V
IDD
supply current
−
75
150
mA
Vsync
sync voltage amplitude
0.1
0.3
0.6
V
Vvid(p-p)
video input voltage amplitude
(peak-to-peak value)
0.7
1.0
1.4
V
fxtal
crystal frequency
−
27
−
MHz
Tamb
operating ambient temperature
−20
−
+70
°C
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA5281P
DESCRIPTION
VERSION
DIP48
plastic shrink dual in-line package; 32 leads (400 mil)
SOT240-1
SAA5281ZP
SDIP52
plastic shrink dual in-line package; 52 leads (600 mil)
SOT247-1
SAA5281GP
QFP64
plastic quad flat package; 64 leads
(lead length 1.95 mm); body 14 × 20 × 2.8 mm
SOT319-2
1996 Nov 04
2
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
BLOCK DIAGRAM
handbook, full pagewidth
V DD1
1
VDD2
BLAN RGBREF
COR
R
Y
22
10
POWER-ON
RESET
ODD/EVEN
(or DV)
19
20
18
G
15
B
16
17
DRAM
REFRESH
AND
TIMING
DISPLAY
8K x 8
DRAM
21
24 TO 18
HAMMING
DECODER
PACKET 26
PROCESSING
ENGINE
MEMORY
INTERFACE
TELETEXT
AQUISITION
AND DECODING
24
I 2 C-BUS
INTERFACE
23
VPS
ACQUISITION
AND
DECODING
SERIAL-TO
-PARALLEL
CONVERTER
44
TIMING
CHAIN
SAA5281
DATA SLICER
AND CLOCK
REGENERATOR
DISPLAY CLOCK
PHASE-LOCKED
LOOP
TELETEXT
OR
VPS CONTROL
13
11
REF
IREF
6
37
9
ANALOG
REFERENCE
GENERATOR
5
14
ANALOG
TO
DIGITAL
CONVERTER
25
INPUT
CLAMP
AND SYNC
SEPARATOR
8
7
ANALOG
OUTPUT
BUFFER
12
27 MHz
CLOCK
GENERATOR
36
2
4
SDA
SCL
LINE 23
VCR/FFB
POL
CLK O/P
OSCGND
3
MBD783
V SS1 VSS2
V SS3
CVBS
BLACK
STTV/LFB
CLK EN
OSCIN
OSCOUT
Fig.1 Block diagram; pin numbers for DIP48 (SOT240-1).
1996 Nov 04
3
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
PINNING
PIN
SYMBOL
DESCRIPTION
SOT240-1 SOT247-1 SOT319-2
VDD1
1
52
11
+5 V supply 1
OSCOUT
2
1
13
27 MHz crystal oscillator output
OSCIN
3
2
14
27 MHz crystal oscillator input
OSCGND
4
3
15
0 V crystal oscillator ground
VSS1
5
4 and 5
16
0 V ground
REF+
6
6
18
positive reference voltage for ADC; this pin should be connected
to ground via a 100 nF capacitor
BLACK
7
8
19
video black level storage input/output; this pin should be
connected to ground via a 100 nF capacitor
CVBS
8
9
20
composite video input; a positive-going 1 V (peak-to-peak) input
is required, connected via a 100 nF capacitor
IREF
9
10
21
reference current input, connected to ground via a 27 kΩ resistor
VDD2
10
11
22
+5 V supply 2
POL
11
12
23
STTV/LFB/FFB polarity selection input
STTV/LFB
12
13
24
sync to TV output line flyback input; function controlled by an
internal register bit (scan sync mode)
VCR/FFB
13
14
27
PLL time constant switch/field input; function controlled by an
internal register bit (scan sync mode)
VSS2
14
15
28
0 V ground; connected to VSS1 for normal operation
R
15
16
30
dot rate character output of the RED colour information
G
16
17
32
dot rate character output of the GREEN colour information
B
17
18
33
dot rate character output of the BLUE colour information
RGBREF
18
19
34
input DC voltage to define the output high level on the RGB pins
BLAN
19
20
35
dot rate fast blanking output
COR
20
21
36
programmable output to provide contrast reduction of the TV
picture for mixed text and picture displays or when viewing
newsflash/subtitle pages;
open-drain output
ODD/EVEN
(or DV)
21
22
37
in ODD/EVEN mode a 25 Hz output synchronized with the CVBS
input field sync pulses to produce a non-interlaced display by
adjustment of the vertical deflection currents; in DV mode a VPT
data valid signal is used to indicate reception of error-free VPS or
8/30 format 2 data
Y
22
23
38
dot rate character output of teletext foreground colour information;
open-drain output
SCL
23
24
39
serial clock input for I2C-bus; it can still be driven HIGH during
power-down of the device
SDA
24
25
40
serial data port for the I2C-bus, open-drain output; it can still be
driven HIGH during power-down of the device
VSS3
25
26
44
0 V ground
1996 Nov 04
4
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
PIN
SYMBOL
DESCRIPTION
SOT240-1 SOT247-1 SOT319-2
i.c.
26 to 35,
38 to 43,
45 to 48
27 to 32,
35 to 38,
41 to 46,
48 to 51
1 to 3,
5 to 8,
45 to 53,
55, 61,
63 to 64
36
39
56
clock enable input to enable the clock output (CLP O/P pin 37);
internal pull-down normally disables clock
CLK O/P
37
40
59
13.5 MHz clock output to drive an external microcontroller
LINE 23
44
47
4
output for indication of Line 23 for use with external circuitry
n.c.
−
7, 33, 34
CLK EN
1996 Nov 04
internally connected; normally open-circuit
9, 10, 12, not connected; normally open-circuit
17, 25, 26,
29, 31,
41 to 43,
54, 57, 58,
60, 62
5
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
handbook, halfpage
handbook, halfpage
OSCOUT
1
52
V DD1
VDD1
1
48
i.c.
OSCIN
2
51
i.c.
OSCOUT
2
47
i.c.
OSCGND
3
50
i.c.
OSCIN
3
46
i.c.
V SS1
4
49
i.c.
OSCGND
4
45
i.c.
V SS1
5
48
i.c.
V SS1
5
44
LINE 23
REF+
6
47
LINE 23
REF+
6
43
i.c.
n.c.
7
46
i.c.
BLACK
7
42
i.c.
BLACK
8
45
i.c.
CVBS
8
41
i.c.
CVBS
9
44
i.c.
IREF
9
40
i.c.
IREF
10
43
i.c.
V DD2
10
39
i.c.
V DD2
11
42
i.c.
POL
11
38
i.c.
POL
12
41
i.c.
SAA5281
STTV/LFB
12
37
CLK O/P
STTV/LFB
13
40
CLK O/P
VCR/FFB
14
39
CLK EN
SAA5281
VCR/FFB
13
36
CLK EN
V SS2
14
35
i.c.
V SS2
15
38
i.c.
R
15
34
i.c.
R
16
37
i.c.
G
16
33
i.c.
G 17
36
i.c.
B
17
32
i.c.
B 18
35
i.c.
RGBREF
18
31
i.c.
RGBREF
19
34
n.c.
BLAN
19
30
i.c.
BLAN
20
33
n.c.
COR
20
29
i.c.
COR
21
32
i.c.
ODD/EVEN
(or DV)
21
28
i.c.
22
31
i.c.
Y
22
27
i.c.
ODD/EVEN
(or DV)
Y
23
30
i.c.
SCL
23
26
i.c.
SCL
24
29
i.c.
SDA
24
25
V SS3
SDA
25
28
i.c.
V SS3 26
27
i.c.
MBD784
MBD785
Fig.2 Pin configuration; SOT240-1 (DIP48).
1996 Nov 04
Fig.3 Pin configuration; SOT247-1 (SDIP52).
6
Philips Semiconductors
Preliminary specification
52 i.c.
53 i.c.
54 n.c.
55 i.c.
56 CLK EN
57 n.c.
SAA5281
58 n.c.
60 n.c.
61 i.c.
62 n.c.
63 i.c.
64 i.c.
handbook, full pagewidth
59 CLK O/P
Integrated Video input processor and
Teletext decoder (IVT1.8*)
i.c.
1
51 i.c.
i.c.
2
50 i.c.
i.c.
3
49 i.c.
LINE 23
4
48 i.c.
i.c.
5
47 i.c.
i.c.
6
46 i.c.
i.c.
7
45 i.c.
i.c.
8
44 VSS3
n.c.
9
43 n.c.
SAA5281
n.c. 10
42 n.c.
VDD1 11
41 n.c.
n.c. 12
40 SDA
OSCOUT 13
39 SCL
OSCIN 14
38 Y
37 ODD/EVEN
(or DV)
OSCGND 15
VSS1 16
36 COR
35 BLAN
n.c. 17
REF+ 18
34 RGBREF
Fig.4 Pin configuration; SOT319-2 (QFP64).
1996 Nov 04
7
G 32
n.c. 31
R 30
n.c. 29
VSS2 28
VCR/FFB 27
n.c. 26
n.c. 25
STTV/LFB 24
POL 23
VDD2 22
IREF 21
33 B
CVBS 20
BLACK 19
MBH665
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
QUALITY AND RELIABILITY
This device will meet Philips Semiconductors General Quality Specification for Business group “Consumer Integrated
Circuits SNW-FQ-611-Part E”. The principal requirements are shown in Tables 1 to 4.
Group A
Table 1
Acceptance tests per lot
REQUIREMENTS(1)
TEST
Mechanical
cumulative target: <100 ppm
Electrical
cumulative target: <100 ppm
Group B
Table 2
Processability tests (by package family)
REQUIREMENTS(1)
TEST
Solderability
<7% LTPD
Mechanical
<15% LTPD
Solder heat resistance
<15% LTPD
Group C
Table 3
Reliability tests (by process family)
TEST
CONDITIONS
REQUIREMENTS(1)
Operational life
168 hours at Tj = 150 °C
<1500 FPM; equivalent to
<100 FITS at Tj = 70 °C
Humidity life
temperature, humidity, bias
1000 hours, 85 °C, 85% RH
(or equivalent test)
<2000 FPM
Temperature cycling performance
Tstg(min) to Tstg(max)
<2000 FPM
Table 4
Reliability tests (by device type)
TEST
ESD and latch-up
CONDITIONS
ESD Human body model
2000 V, 100 pF, 1.5 kΩ
<15% LTPD
ESD Machine model
200 V, 200 pF, 0 Ω
<15% LTPD
latch-up 100 mA, 1.5 × VDD
(absolute maximum)
<15% LTPD
Notes to Tables 1 to 4
1. ppm = fraction of defective devices, in parts per million.
LTPD = Lot Tolerance Percent Defective.
FPM = fraction of devices failing at test condition, in Failures Per Million.
FITS = Failures In Time Standard.
1996 Nov 04
REQUIREMENTS(1)
8
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
LIMITING VALUES
In accordance with Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage (all supplies)
−0.3
+6.5
V
VI
input voltage (any input)
−0.3
VDD + 0.5
V
VO
output voltage (any output)
−0.3
VDD + 0.5
V
IO
output current (each output)
−
±10
mA
IIOK
DC input or output diode current
−
±20
mA
Tamb
operating ambient temperature
−20
+70
°C
CHARACTERISTICS
VDD = 5 V ±10%; Tamb = −20 to +70 °C; pin numbers refer DIP48 package; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
supply voltage
4.5
5.0
5.5
V
IDDtot
total supply current
−
75
150
mA
Vsync
sync voltage amplitude
0.1
0.3
0.6
V
Vburst(p-p)
colour burst amplitude
(peak-to-peak value)
0.0
0.3
4.0
V
td(sync)
delay from CVBS to TCS
output from STTV buffer
(nominal video, average of
leading/trailing edge)
−150
0
+150
ns
∆td(sync)
change in sync delay between
all black and all white video
input at nominal levels
0
−
25
ns
Vvid(p-p)
video input voltage amplitude
(peak-to-peak value)
0.7
1.0
1.4
V
Vdat(text)
teletext data voltage amplitude
0.29
0.46
0.71
V
∆f/f
display PLL capture range
±7
−
−
%
Zsource
source impedance
−
−
250
Ω
VI
input switching voltage level of
sync separator
1.7
2.0
2.3
V
ZI
input impedance
2.5
5.0
−
kΩ
CI
input capacitance
−
−
10
pF
Rgnd
resistor to ground
−
27
−
kΩ
Vi
input voltage
−
0.5VDD
−
V
Inputs
CVBS
IREF
1996 Nov 04
9
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SYMBOL
PARAMETER
SAA5281
CONDITIONS
MIN.
TYP.
MAX.
UNIT
POL
VIL
LOW level input voltage
−0.3
−
+0.8
VIH
HIGH level input voltage
2.0
−
VDD + 0.5 V
ILI
input leakage current
−10
−
+10
µA
CI
input capacitance
−
−
10
pF
V
VI = 0 to VDD
V
LFB
VIL
LOW level input voltage
−0.3
−
tbf
VIH
HIGH level input voltage
tbf
−
VDD + 0.5 V
ILI
input leakage current
VI = 0 to VDD
−10
−
+10
µA
IImax
maximum input current
note 1
−1
−
+1
mA
tdLFB
delay between LFB front edge
and input video line sync
−
250
−
ns
V
VCR/FFB
VIL
LOW level input voltage
−0.3
−
+0.8
VIH
HIGH level input voltage
2.0
−
VDD + 0.5 V
ILI
input leakage current
VI = 0 to VDD
−10
−
+10
µA
IImax
maximum input current
note 1
−1
−
+1
mA
−0.3
−
VDD
V
−10
−
+10
µA
V
RGBREF
VIL
LOW level input voltage
ILI
input leakage current
VI = 0 to VDD
SCL
VIL
LOW level input voltage
−0.3
−
+1.5
VIH
HIGH level input voltage
3.0
−
VDD + 0.5 V
ILI
input leakage current
−10
−
+10
µA
CI
input capacitance
−
−
10
pF
fclk
clock frequency
0
−
100
kHz
tr
input rise time
between 10% and 90% −
−
2
µs
tf
input fall time
between 90% and 10% −
−
2
µs
V
VI = 0 to VDD
Inputs/outputs
CRYSTAL OSCILLATOR (OSCIN; OSCOUT)
Vosc(p-p)
oscillator voltage amplitude
(peak-to-peak value)
−
1.0
−
Gv
small signal voltage gain
−
1.0
−
Gm
mutual conductance
5.0
−
−
CI
input capacitance
−
−
10
pF
Cfb
feedback capacitance
−
1
−
pF
1996 Nov 04
10
mS
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SYMBOL
PARAMETER
SAA5281
CONDITIONS
MIN.
TYP.
MAX.
UNIT
BLACK
Cblack
storage capacitor to ground
−
100
−
nF
Vblack
black level voltage for nominal
sync amplitude
1.8
2.15
2.5
V
ILI
input leakage current
−10
−
+10
µA
−0.3
−
+1.5
V
VI = 0 to VDD
SDA (OPEN-DRAIN INPUT/OUTPUT)
VIL
LOW level input voltage
VIH
HIGH level input voltage
3.0
−
VDD + 0.5 V
VOL
LOW level output voltage
IOL = 3 mA
0
−
0.5
V
ILI
input leakage current
VI = 0 to VDD
−10
−
+10
µA
CI
input capacitance
−
−
10
pF
CL
load capacitance
−
−
400
pF
tr
input rise time
between 10% and 90% −
−
2
µs
tf
input fall time
between 90% and 10% −
−
2
µs
tf
output fall time
between 3 V and 1 V
−
−
200
ns
Outputs
STTV
Gsttv
gain of STTV relative to video
input
0.9
1.0
1.1
Vtcs
TCS voltage amplitude
0.2
0.3
0.45
V
∆Vtcs
DC shift between TCS output
and nominal video output
−
−
0.15
V
IO
output drive current
−
−
3.0
mA
CL
load capacitance
−
−
100
pF
R, G AND B
VOL
LOW level output voltage
IOL = 2 mA
0
−
0.2
V
VOH
HIGH level output voltage
IOH = −1.6 mA;
VRGBREF < VDD − 2 V;
note 2
VRGBREF
− 0.25
VRGBREF
VRGBREF
+ 0.5
V
|Zo|
output impedance
−
−
200
Ω
CL
load capacitance
−
−
50
pF
tr
output rise time
between 10% and 90% −
−
20
ns
tf
output fall time
between 90% and 10% −
−
20
ns
VOL
LOW level output voltage
IOL = 1.6 mA
0
−
0.4
V
VOH
HIGH level output voltage
IOH = − 0.2 mA
1.1
−
−
V
IOH = 0 mA
−
−
2.8
V
BLAN
CL
load capacitance
−
−
50
pF
tr
output rise time
between 10% and 90% −
−
20
ns
tf
output fall time
between 90% and 10% −
−
20
ns
1996 Nov 04
11
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SYMBOL
PARAMETER
SAA5281
CONDITIONS
MIN.
TYP.
MAX.
UNIT
ODD/EVEN OR DV
VOL
LOW level output voltage
IOL = 1.6 mA
0
−
0.4
V
VOH
HIGH level output voltage
IOH = −1.6 mA
VDD − 0.4
−
VDD
V
CL
load capacitance
−
−
120
pF
tr
output rise time
between 0.6 V and
2.2 V
−
−
50
ns
tf
output fall time
between 0.6 V and
2.2 V
−
−
50
ns
−
−
VDD
V
IOL = 2 mA
0
−
0.4
V
IOL = 5 mA
0
−
1.0
V
−
−
25
pF
−
−
50
ns
COR AND Y (OPEN-DRAIN OUTPUTS)
VOH
HIGH level pull-up output
voltage
VOL
LOW level output voltage
CL
load capacitance
tf
output fall time
load resistor of 1.2 kΩ
to VDD; measured
between VDD − 0.5 V
and 1.5 V
ILO
output leakage current
VI = 0 to VDD
tskew
skew delay between display
outputs R, G, B, COR, Y and
BLAN
−10
−
+10
µA
−
−
20
ns
I2C-bus timing (see Fig.5)
tLOW
SCL clock LOW time
4.0
−
−
µs
tHIGH
SCL clock HIGH time
4.0
−
−
µs
tSU;DAT
data set-up time
250
−
−
ns
tHD;DAT
data hold time
170
−
−
ns
tSU;STO
set-up time from clock HIGH
to STOP
4.0
−
−
µs
tBUF
START set-up time following a
STOP
4.0
−
−
µs
tHD;STA
START hold time
4.0
−
−
µs
tSU;STA
START set-up time following a
clock LOW-to-HIGH transition
4.0
−
−
µs
Notes
1. This current is the maximum allowed into the inputs when line and field flyback signals are connected to these inputs.
Series current limiting resistors must be used to limit the input currents to ±1 mA.
2. Voltage level VOH for R, G and B outputs is taken to be the mean value during the output HIGH time. If higher R, G
and B voltage VOH levels are required RGBREF voltage level may be raised and a pull-up resistor used at each of
these pins provided current specification (IOL) is not exceeded.
1996 Nov 04
12
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
handbook, full pagewidth
SDA
t LOW
t BUF
tf
SCL
t HD;STA
tr
t HD;DAT
t HIGH
t SU;DAT
SDA
MBC764
t SU;STA
t SU;STO
Fig.5 I2C-bus timing.
TIMING CHAIN
handbook, full pagewidth
LSP
(TCS)
0
64 µs
4.66
40 µs
R, G, B, Y
(1)
display period
0
56.67 µs
16.67
lines 42 to 291 inclusive (and 355 to 604 inclusive interlaced)
R, G, B, Y
(1)
display period
0
312
291
line numbers
41
MLA662 - 1
(1) Also BLAN in character and box blanking.
Fig.6 Display output timing (a) line rate (b) field rate.
1996 Nov 04
13
1996 Nov 04
14
0
0 2.33
308
309
621
(308)
309
310
622
(309)
310
311
623
(310)
311
312
624
(311)
312
313
625
(312)
1
314 (1)
1
27.33
2
34.33
3
3
316 (3)
Fig.7 Composite sync waveforms.
2
315 (2)
32
32
4
317 (4)
4
5
318 (5)
5
6
319 (6)
6
7
320 (7)
7
59.33
MLA037 - 2
64 µs
64 µs
64 µs
Integrated Video input processor and
Teletext decoder (IVT1.8*)
LSP, EP and BP are combined to give TCS as shown. All timings are measured from falling edge of LSP.
Line numbers placed in the middle of the line.
Equivalent count numbers in brackets.
TCS non-interlaced
TCS interlaced
TCS interlaced
BP
(Broad Pulse)
EP
(Equalizing Pulse)
LSP
(Line Sync Pulse)
4.66
handbook, full pagewidth
0
Philips Semiconductors
Preliminary specification
SAA5281
1996 Nov 04
15
309
310
311
623
(310)
2 µs
312
624
(311)
2
3
314 (1)
315 (2)
316 (3)
SECOND FIELD START (ODD)
48 µs
1
FIRST FIELD START (EVEN)
Fig.8 ODD/EVEN timing.
30 µs (1)
16 µs
313
30 µs (1)
2 µs
625
(312)
317 (4)
4
318 (5)
5
319 (6)
6
320 (7)
7
MLA416 - 2
Integrated Video input processor and
Teletext decoder (IVT1.8*)
Line numbers placed in the middle of the line.
Equivalent count numbers in brackets.
(1) Or 62 µs if Register 1 D2.D1.D0 equals 1 1 1.
ODD / EVEN output
(slave sync mode)
ODD / EVEN output
(normal sync mode
when VCS to SCS
mode active)
ODD / EVEN output
(normal sync mode)
TCS interlaced
ODD / EVEN output
(slave sync mode)
ODD / EVEN output
(normal sync mode
when VCS to SCS
mode active)
ODD / EVEN output
(normal sync mode)
TCS interlaced
622
(309)
handbook, full pagewidth
621
(308)
Philips Semiconductors
Preliminary specification
SAA5281
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
ON-CHIP MEMORY
Page memory organization
The organization of the page memory is illustrated by Fig.9. The IVT1.8* provides an additional row as compared with
first generation decoders; this brings the display format up to 40 characters by 25 rows. Rows 0 to 23 form the teletext
page; row 24 is the extra row available for software generated status messages and FLOF/FASTEXT prompt
information.
handbook, full pagewidth
7 characters
for status
7
fixed character
written by IVT hardware:
alphanumerics white for normal;
alphanumerics green when looking
for display page
8 characters
always rolling
(time)
24
8
1
24 characters from page header
rolling when display page looked for
MAIN PAGE DISPLAY AREA
0
1
2
3
4
5
to
20
21
22
23
24
25
PACKET X / 22
PACKET X / 23
PACKET X / 24 STORED HERE IF R0D7 = 1
10
14
if enabled 14 bytes reserved in
10 bytes for
chapter 5 for VPS data
received
page information
ROW
MBD789
Fig.9 Basic page memory organization.
REMARK TO Fig.9
Row 25
Row 0
The first 10 bytes of row 25 contain control data relating to
the received page as shown in Table 5. The remaining
14 bytes are free for use by the microcomputer.
Row 0 is for the page header. The first seven characters
(0 to 6) are free for status messages. Character 8 is an
alphanumeric white or green control character, written
automatically by IVT1.8* to give a green rolling header
when a page is being looked for. The last eight characters
are for rolling time.
1996 Nov 04
16
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
Table 5
SAA5281
Row 25 received control data format
ROW 25
D0
PU0
PT0
MU0
MT0
HU0
HT0
C7
C11
MAG0
0
D1
PU1
PT1
MU1
MT1
HU1
HT1
C8
C12
MAG1
0
D2
PU2
PT2
MU2
MT2
HU2
C5
C9
C13
MAG2
0
D3
PU3
PT3
MU3
C4
HU3
C6
C10
C14
0
0
D4
HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER FOUND
0
D5
0
0
0
0
0
0
0
0
0
PBLF
D6
0
0
0
0
0
0
0
0
0
0
D7
0
0
0
0
0
0
0
0
0
0
Column
0
1
2
3
4
5
6
7
8
9
Table 6
Page number and sub-code for Table 5
BIT NAME
DESCRIPTION
Page number
MAG
magazine
PU
page units
PT
page tens
PBLF
page being looked for
FOUND
LOW for page has been found
HAM.ER
Hamming error in corresponding byte
Page sub-code
MU
minutes units
MT
minutes tens
HU
hours units
HT
hours tens
C4 to C14
transmitted control bits
1996 Nov 04
17
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Extension packet memory organization
When in normal extension packet enabled mode the rows of information are organized as illustrated in Fig.10.
Row 23 of the extension page, as shown in Fig.10, contains packet 8/30. Packet 8/30 is mapped into the IVT1.8* memory
as follows:
8 / 30 / 0 and 8 / 30 / 1 to Chapter 4 Row 23
8 / 30 / 2 and 8 / 30 / 3 to Chapter 5 Row 23
8 / 30 / 4 to 8 / 30 / 15 to Chapter 6 Row 23.
ROW
handbook, full pagewidth
0
to
14
PACKETS X/26/0 to X/26/14
PACKET
X/28/2
15
16
PACKETS X/27/0 to X/27/1
17
18
PACKETS X/27/4 to X/27/5
PACKET
19
X/24 IF R0D7 = 0
PACKET
PACKET
X/25
21
X/28/0
22
8/30
23
X/28/1
24
PACKET
PACKET
20
RESERVED (1)
25
MBD791
(1) Row 25 reserved for VPS data in Chapter 5.
Fig.10 Organization of the extension memory.
1996 Nov 04
18
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
ENHANCED MODE
In enhanced mode, the number of extension packets captured is reduced to the minimum required for FASTEXT
operation. The first seven chapters can then be used for storage, using the system of pointers. The arrangement of
extension packets is shown in Fig.11.
When in enhanced mode and extension packets are disabled, normal 8-page mode is in operation, but the X/26 engine
is enabled (unlike normal 8-page mode).
ROW
handbook, halfpage
CHAPTER 0 PACKET 24
0
CHAPTER 0 PACKETS 27 / 0
1
CHAPTER 1 PACKET 24
2
CHAPTER 1 PACKETS 27 / 0
3
CHAPTER 2 PACKET 24
4
CHAPTER 2 PACKETS 27 / 0
5
CHAPTER 3 PACKET 24
6
CHAPTER 3 PACKETS 27 / 0
7
CHAPTER 4 PACKET 24
8
CHAPTER 4 PACKETS 27 / 0
9
CHAPTER 5 PACKET 24
10
CHAPTER 5 PACKETS 27 / 0
11
CHAPTER 6 PACKET 24
12
CHAPTER 6 PACKETS 27 / 0
13
not used
14
not used
15
PACKETS 8 / 30 / 0,1
16
PACKETS 8 / 30 / 2,3
17
PACKETS 8 / 30 / 4 to 15
18
not used
19 to 24
MBD788
Fig.11 Organization of the extension memory in enhanced mode.
1996 Nov 04
19
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
They are Word 15 (reserved) and Word 4 (Program
Source Identification, ASCII sequential) which may be
useful for future applications. Details of the memory
organization are shown in Fig.12.
VPT data memory organization
To simplify the software for dual-standard VPT decoders,
the VPS data from line 16 is stored in row 25 of Chapter 5
of the page memory, and is aligned to match the
packet 8/30 format 2 data as far as possible. The 8/30
format 2 packet is Hamming coded and by setting the
appropriate register control bit the data is stored after
hardware Hamming correction. There are 4 data bits
stored in each column address of memory with an
additional Hamming error bit. The data equivalent to the
VPS signal is found in columns 12 to 19.
The stored data can be read from memory via the I2C-bus
in the normal way. Multiple reception/majority error
correction of the VPS data is the responsibility of the
control software, the device simply stores the data as
transmitted after biphase decoding.
As both VPS and 8/30/2 signals are stored in separate
memory locations, it is possible to deal with future
situations where both System A and System B
transmissions may be present on the same TV channel,
the defaults and level of service chosen by the control
software.
Although the VPS data is not Hamming protected, it is
stored with 4 data bits per column address in the same
way with an additional biphase error bit. The extra space
in Row 25 is allocated to two more Line 16 words.
handbook, full pagewidth
column
0
8/30/2
D
1
3
5
6
7
8
20
21 22
23 24
9
10
11 12
13 14
25 26
B11
27 28
29 30
B12
11 12
B13
13 14
17 18
19
B14
15 16
B15
17 18
19
status display
B4
MBD787
B5
Fig.12 Detailed memory organization.
1996 Nov 04
15 16
b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25
received page information
8/30/2
VPS
4
initial page
VPS
column
2
20
1996 Nov 04
2
3
4
5
6
7
8
9
10
11
11B 625/525
SYNC
12
13
Page request
address
Page request data
Display chapter
Display control
(normal)
Display control
(newsflash /subtitle)
Display mode
Active chapter
Cursor row
Cursor column
Cursor data
Device status
Advanced control 2A
Advanced control 2B
FREE RUN
PLL
D6
−
−
21
ENHANC
MODE
H2
CURSOR
FREEZE/
DEVICE
IDENT
H1
MESHING
ENABLE
BOX ON 24
TEXT IN
TEXT IN
A2
PRD2
SC2
TCS ON
D4
C4
R4
D3
C3
R3
H0
S3
VPS ENABLE POINTS
ENABLE
HAM
CHECK
24 : 18
S2
ROM
VER R0
D2
C2
R2
D0
DISABLE
PKT X/26
S1
TEXT
SIGNAL
QUALITY
D1
C1
R1
A1
BOX ON 1
to 23
PON OUT
PON OUT
A1
PRD1
SC1
T1
AUTO
DISPLAY
PKT X/24
S0
VCS
SIGNAL
QUALITY
D0
C0
R0
A0
BOX ON 0
PON IN
PON IN
A0
PRD0
SC0
T0
VCR MODE R11/R11B
SELECT
D1
Integrated Video input processor and
Teletext decoder (IVT1.8*)
H3
D5
C5
−
SINGLE/
DOUBLE
HEIGHT
TEXT OUT
TEXT OUT
FREEZE
HEADER
ONLY
PRD3
D2
DISABLE
ODD/EVEN
VPS ENABLE CLEAR MEM A2
TOP/BTM
HALF
COR IN
COR IN
−
PRD4
ACQ CCT A0 0
DEW/ FULL
FIELD
CBB SLAVE
SYNC
D3
ROM VER R4 ROM VER R3 ROM VER R2 ROM VER
R1
D6
−
−
D7
−
−
−
−
−
COR OUT
COR OUT
−
−
ACQ CCT A1
CURSOR ON CONCEAL/
REVEAL ON
BKGND IN
DISABLE
HDR ROLL
D4
ACQ ON/OFF EXT PKT
ENABLE
AUTO
ODD/EVEN
D5
STATUS
BTM/TOP
BKGND OUT
BKGND IN
−
−
BKGND OUT
BANK
SELECT A2
HAM CHECK
27, 8/30
VCS TO SCS 7 + P/ 8-BIT
1
X/24 POS
D7
Mode
No.
0
NAME
REGISTER
Register map (notes 1 to 4)
Advanced control
Table 7
IVT1.8* mode registers R0 to R13 are shown in Table 7. R0 to R10, R12 and R13 are WRITE only; R11 is READ/WRITE, R11B is read only.
Register map (R3), for page requests, is shown in detail in Table 11.
Register maps
Philips Semiconductors
Preliminary specification
SAA5281
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Notes to Table 7
1. The dash (−) indicates these bits are inactive and must be written to logic 0 for future compatibility.
2. Certain registers are auto-incremented following an I2C-bus transmission byte. These are Register R0 to R3,
R4 to R7 and R8 to R12 or R13.
3. All bits in Registers R0 to R13 are cleared to logic 0 on power-up except bits D0 and D1 of Registers R1, R5 and R6
which are set to logic 1.
4. All memory is cleared to space (00100000) on power-up, except Row 0 Column 7 Chapter 0, which is alpha white
(00000111) as the acquisition circuit is enabled but all pages are on hold.
Table 8
Register description
REGISTER BIT D0 TO D7
FUNCTION
R0 AVANCED CONTROL - auto-increments to Register 1
R11/R11B SELECT
Selects reading of R11 if LOW or R11B if HIGH.
VCR MODE
If logic 1 selects short time constant mode of PLL.
DISABLE ODD/EVEN
Forces ODD/EVEN output LOW when logic 1 (see Table 9).
CBB SLAVE SYNC
When set will modify internal slave sync timing to allow connection to sandcastle of
Philips one-chip TV IC (TDA8362).
DISABLE HDR ROLL
Stops the display update of rolling time and green rolling header during page
requests when logic 1. Time updates on page reception only.
AUTO ODD/EVEN
If logic 1 then ODD/EVEN output only active when no TV picture displayed
(see Table 9).
FREE RUN PLL
Will force the display PLL to free run at 6 MHz when logic 1.
X/24 POS
Automatic display of FASTEXT prompt row when logic 1. Will also cause Row 24
data transmitted by packet 26 to be written to display, rather than extension
memory.
R1 MODE - auto-increments to Register 2
T0, T1
Interlace/non-interlace 312/313 line control (see Table 10).
TCS ON
Text composite sync or direct sync select (see Table 10 for FFB mode selection).
DEW/FULL FIELD
Field-flyback or full-channel mode.
EXT PKT ENABLE
Enables reception and storage of extension packets when logic 1.
ACQ ON/OFF
Acquisition circuits turned off when logic 1.
7 + P/8-BIT
7 bits with parity checking or 8-bit mode.
VCS TO SCS
Connects VCS from video sync separator to display field sync detector to enable
stable display of 60 Hz status messages when logic 1.
R2 PAGE REQUEST ADDRESS - auto-increments to Register 3
SC0 to SC2
Start column for page request data (see Table 11).
0
Must be logic 0 for normal operation.
ACQ CCT A0, A1
Selects one of four acquisition circuits.
BANK SELECT A2
Selects bank of four pages being addressed for acquisition.
HAM CHECK 27, 8/30
8/4 Hamming check packet 27 and 8/30 data.
R3 PAGE REQUEST DATA - does not auto-increment
PRD0 to PRD4
1996 Nov 04
See Table 11.
22
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
REGISTER BIT D0 TO D7
SAA5281
FUNCTION
R4 DISPLAY CHAPTER - auto-increments to Register 5
A0 to A2
Selects one of 8 display chapters.
FREEZE HEADER ONLY
Freezes the rolling header, but (unlike R0D4) allows the time to roll.
R5 NORMAL DISPLAY CONTROL - auto-increments to Register 6
R6 NEWSFLASH/SUBTITLE DISPLAY CONTROL - auto-increments to Register 7; note 1
PON
Picture on.
TEXT
Text on.
COR
Contrast reduction on.
BKGND
Background colour on.
R7 DISPLAY MODE - does not auto-increment
BOX ON 0
Boxing function allowed on Row 0.
BOX ON 1 to 23
Boxing function allowed on Rows1 to 23.
BOX ON 24
Boxing function allowed on Row 24.
SINGLE/DOUBLE HEIGHT
To display double height text.
TOP/BTM HALF
To select bottom half of page when DOUBLE HEIGHT is logic 1.
CONCEAL/REVEAL ON
To reveal concealed text.
CURSOR ON
To display cursor.
STATUS BTM/TOP
Row 25 displayed above or below the main text.
R8 ACTIVE CHAPTER - auto-increments to Register 9
A0 to A2
Active chapter for data written to or read from memory via the I2C-bus.
CLEAR MEM
When set to logic 1, clears the display memory. This bit is automatically reset.
VPS ENABLE
VPS acquisition enabled when logic 1.
R9 CURSOR ROW - auto-increments to Register 10
R0 to R4
Active row for data written to or read from memory via the I2C-bus.
R10 CURSOR COLUMN - auto-increments to Register 11 or 11B
C0 to C5
Active column for data written to or read from memory via the I2C-bus.
R11 CURSOR DATA - does not auto-increment
D0 to D7
Data read from/written to memory via I2C-bus, at location pointed to by R9 and
R10. This location automatically increments each time R11 is accessed.
R11B DEVICE STATUS - does not auto-increment
VCS SIGNAL QUALITY
Indicates that the video signal quality is good and PLL is phase-locked to input
video when logic 1.
TEXT SIGNAL QUALITY
If a good teletext signal is being received then logic 1.
ROM VER R0 to R4
Indicated language/ROM variant. For Western European is logic 0. R3 and R4 are
set HIGH if R13 D6 is logic 1.
625/525 SYNC
If the input video is a 525 line signal then logic 1.
R12 ADVANCED CONTROL 2A - does not auto-increment
S0 to S3, H0 to H3
1996 Nov 04
Each acquisition channel can be programmed to process its page in one of four
ways as shown in Table 12.
23
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
REGISTER BIT D0 TO D7
SAA5281
FUNCTION
R13 ADVANCED CONTROL 2B - does not auto-increment
AUTO DISPLAY PKT X/24
Status row will show the contents of the row of the extension memory (packet 24)
when logic 1.
DISABLE PKT X/26
Output taken from processing engine written to the display memory when logic 0.
Operates independent of the acquisition.
HAM CHECK 24 : 18
When logic 1 all packet 26 data is stored in extension memory unchecked.
POINTS ENABLE
Enable for acquisition pointers when logic 1.
VPS ENABLE
VPS acquisition enabled when logic 1.
MESHING ENABLE
Enables meshing display function in box mode.
CURSOR FREEZE/
DEVICE IDENT
When logic 1, cursor position not updated even if active row and column change.
This bit will also cause R3 and R4 of the ROM code in Register R11B to be set
HIGH. This allows software to identify the device as an IVT1.8*. An internal ‘1.8
mode’ flag is also set, which enables the operation of R0D4, R4D4 and the subtitle
bit in R3.
ENHANC MODE
When logic 1, extension packet data is mapped into the last chapter. Only packet
24, 27/0 and 8/30 are stored. Chapters 0 to 6 can then be used for page storage. If
extension packets are not enabled, 8 pages are stored as normal, but X/26 engine
is enabled.
Note
1. These functions have IN and OUT referring to inside and outside the boxing function respectively.
ODD/EVEN selection
Table 9
AUTO
ODD/EVEN
DISABLE
ODD/EVEN
0
0
ODD/EVEN output continuous
0
1
ODD/EVEN statically LOW
1
1
ODD/EVEN active only when no TV picture displayed
1
1
DV output to indicate reception of error-free 8/30/format 2 packet or VPS line
RESULT
Table 10 Interlace/non-interlace 312/313 line control and ODD/EVEN field detection option
TCS ON
FFB MODE(1)
T1
T0
X
0
0
interlaced 312.5/312.5 lines
X
0
1
non-interlaced 312/313 lines (note 2)
X
1
0
non-interlaced 312/313 lines (note 2)
0
1
1
SCS (scan composite sync) mode: FFB leading edge in first broad pulse of field
1
1
1
SCS (scan composite sync) mode: FFB leading edge in second broad pulse of field
RESULT
Notes
1. X = don't care.
2. Reverts to interlaced mode if a newsflash or subtitle is being displayed.
1996 Nov 04
24
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 11 Register map for page requests (R3); notes 1 to 6
START
COLUMN
0
PRD4
PRD3
PRD2
PRD1
PRD0
DO CARE
HOLD
MAG2
MAG1
MAG0
PT3
PT2
PT1
PT0
PU3
PU2
PU1
PU0
SUBTITLE
X
HT1
HT0
HU3
HU2
HU1
HU0
X
MT2
MT1
MT0
Minutes units
MU3
MU2
MU1
MU0
X
X
CH2
CH1
CH0
Magazine
1
DO CARE
Page tens
2
DO CARE
Page units
3
DO CARE
Hours tens
4
DO CARE
Hours units
5
DO CARE
Minutes tens
6
DO CARE
7
Notes
1. Abbreviations are as given in Table 6 except for DO CARE bits and CH = chapter address for acquisition chapter.
2. When the DO CARE bit is set to logic 1 this means the corresponding digit is to be taken into account for page
requests. If the DO CARE bit is set to logic 0 the digit is ignored. This allows, for example, normal or timed page
selection.
3. If HOLD is set LOW, the page is held and not updated.
4. Columns auto-increment on successive I2C-bus transmission bytes.
5. The SUBTITLE bit is only present when the device is in ‘1.8 mode’ (i.e. R13D6 has been set HIGH).
6. X = don’t care.
Table 12 Acquisition channel programming
H0 to H3(1)
S0 to S3(1)
0
0
7-bit + parity for whole page
0
1
8-bit for whole page
1
0
8/4 Hamming check for whole page
1
1
mixed 8/4 Hamming (columns 0 to 7, 20 to 27) and 7-bit + parity
(columns 8 to 19, 28 to 39)
CHECKING ALGORITHM FOR ACQUISITION CHANNEL X
Note
1. These register bits operate in conjunction with 7 + P/ 8-BIT (Register 1, Bit D6) which will over-ride the choice of data
checker if set, setting all channels to 8-bit only. If this bit is not set H0 to H3 and S0 to S3 will determine the data
checking (default to 7-bit + parity).
1996 Nov 04
25
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
frequency, and reduces the power dissipation in the quartz
crystal. It is capable of oscillating with both fundamental
and third overtone mode crystals. External components
should be used to suppress the fundamental output of the
third overtone as illustrated in Fig.13. The crystal
characteristics are given in Table 13.
CLOCK SYSTEMS
Crystal oscillator
The crystal is a conventional Colpitts 3-pin design
operating at 27 MHz. The oscillator is sinusoidal and
linear, with a controlled output amplitude. This reduces the
radiated and conducted level of the 27 MHz fundamental
handbook, full pagewidth
SAA5281
VDD1
OSCOUT
SAA5281
1 (52)
2 (1)
15 pF 8.2 pF 100 nF
3.3 µH
OSCIN
27 MHz
3rd
overtone
OSCGND
1 nF
3.3 kΩ
CRYSTAL
OSCILLATOR
3 (2)
4 (3)
MBD786
Fig.13 Crystal oscillator application diagram for SOT240-1; pins in parenthesis are for SOT247-1.
Table 13 Crystal characteristics (see Fig.13)
SYMBOL
PARAMETER
TYP.
MAX.
UNIT
Crystal (27 MHz, 3rd overtone)
C1
series capacitance
1.7
−
pF
C0
parallel capacitance
5.2
−
pF
CL
load capacitance
20
−
pF
Ω
Rr
resonance resistance
−
50
R1
series resistance
20
−
Ω
10−6
Xa
ageing
−
±5 ×
Xj
adjustment tolerance
−
±25 × 10−6
Xd
drift
−
±25 × 10−6
1996 Nov 04
26
year−1
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
CHARACTER SETS
Meshing
The WST specification allows the selection of national
character sets via the page header transmission bits,
C12 to C14. The basic 96 character sets differ only in
13 national option characters as indicated in the
Tables 21, 22 and 23 with reference to their table position
in the basic character matrix illustrated in Table 20.
The IVT1.8* automatically decodes transmission bits
C12 to C14. Tables 14, 15 and 16 illustrate the character
matrixes.
This is an alternative method of displaying teletext
subtitles, or similar boxed text superimposed on the TV
picture and operates by showing reduced contrast TV
pictures in place of the (black) background within the
boxed area. The Meshing effect is produced by toggling
the BLAN signal from IVT at pixel rate. By starting at the
same point each field, and toggling the start position each
line, a chequered pattern will result. This allows movement
to be seen behind the text information. The MESH
OFF/ON bit in Register 13 D5 controls this function.
Normally at zero, compatibility with IVT1.0 is maintained.
Character bytes are listed as transmitted from b1 to b7.
MLA663
handbook, full pagewidth
alphanumerics and
graphics 'space'
character
0000010
alphanumerics
character
1011010
alphanumerics or
blast-through
alphanumerics
character
0001001
alphanumerics
character
1111111
contiguous
graphics character
0110111
separated
graphics character
0110111
separated
graphics character
1111111
contiguous
graphics character
1111111
=
background
colour
Fig.14 Character format.
1996 Nov 04
27
display
= colour
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 14 SAA5281P/E character data input decoding, West European languages; notes 1 to 9
For character version number (11000) see Register 11B.
b8
B pagewidth
handbook, full
I
T
S
0
0
b7
0
b6
0 or 1
0
0
0
b5
0
0
b 4 b 3 b2 b 1
column
r
o
w
0
1
1
0
0
0
0
0
0
0
1
1
alpha numerics
red
graphics
red
0
0
1
0
2
alpha numerics
green
graphics
green
0
0
1
1
3
alpha numerics
yellow
graphics
yellow
0
1
0
0
4
alpha numerics
blue
graphics
blue
0
1
0
1
5
alpha numerics
magenta
graphics
magenta
0
1
1
0
6
alpha numerics
cyan
graphics
cyan
0
1
1
1
7
alpha numerics
white
graphics
white
1
0
0
0
8
flash
conceal
display
1
0
0
1
9
steady
1
0
1
0
10
end box
separated
graphics
1
0
1
1
11
start box
ESC
1
1
0
0
12
normal
height
1
1
0
1
13
double
height
1
1
1
0
14
SO
1
1
1
1
15
SI
graphics
black
0
0
1
0
2
0
0 or 1
0
1
alpha numerics
black
0
1
1
2a
0
0
1
1
3
0
1
0
1
3a
0
0
0
4
5
1
1
1
6a
1
0
1
7
7a
1
0
0
1
0
6
1
0
1
1
0
0
8
1
1
0
1
9
1
1
0
0
12
1
1
1
1
1
13
1
0
14
1
15
(2)
(2)
(2)
contiguous
graphics
(2)
(1)
(2)
black
back ground
(2)
new
back ground
(1)
hold
graphics
(1)
(2)
release
graphics
MBA429
1996 Nov 04
28
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 15 SAA5281P/H character data input decoding, East European languages; notes 1 to 9
For character version number (11001) see Register 11B.
handbook, full
B pagewidth
b8
I
T
S
0
0
b7
0
b6
4
b
3
b
2
b
0
0
b5
b
0 or 1
0
0
0
1
column
r
o
w
1
0
1
graphics
black
0
0
0
0
0
0
0
1
1
alpha numerics
red
graphics
red
0
0
1
0
2
alpha numerics
green
graphics
green
0
0
1
1
3
alpha numerics
yellow
graphics
yellow
0
1
0
0
4
alpha numerics
blue
graphics
blue
0
1
0
1
5
alpha numerics
magenta
graphics
magenta
0
1
1
0
6
alpha numerics
cyan
graphics
cyan
0
1
1
1
7
alpha numerics
white
graphics
white
1
0
0
0
8
flash
conceal
display
1
0
0
1
9
steady
1
0
1
0
10
end box
separated
graphics
1
0
1
1
11
start box
ESC
1
1
0
0
12
normal
height
1
1
0
1
13
double
height
1
1
1
0
14
SO
1
1
1
1
15
SI
0
0
1
0
2
0
0 or 1
0
1
alpha numerics
black
0
1
0
2a
0
0
1
1
3
0
1
0
1
3a
0
0
0
4
5
1
1
1
6a
1
0
1
7
7a
1
0
0
1
0
6
1
0
1
1
0
0
8
1
1
0
1
9
1
1
0
0
12
1
1
1
1
1
13
1
0
14
1
15
(2)
(2)
(2)
contiguous
graphics
(2)
(1)
(2)
black
back ground
(2)
new
back ground
(1)
hold
graphics
(1)
(2)
release
graphics
MLA961
1996 Nov 04
29
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 16 SAA5281P/T character data input decoding, West European and Turkish languages; notes 1 to 9
For character version number (11010) see Register 11B.
handbook, full
b8
B pagewidth
I
T
S
0
0
b7
0
b6
0 or 1
0
0
0
b5
0
0
b 4 b 3 b2 b 1
column
r
o
w
1
0
1
graphics
black
0
0
0
0
0
0
0
1
1
alpha numerics
red
graphics
red
0
0
1
0
2
alpha numerics
green
graphics
green
0
0
1
1
3
alpha numerics
yellow
graphics
yellow
0
1
0
0
4
alpha numerics
blue
graphics
blue
0
1
0
1
5
alpha numerics
magenta
graphics
magenta
0
1
1
0
6
alpha numerics
cyan
graphics
cyan
0
1
1
1
7
alpha numerics
white
graphics
white
1
0
0
0
8
flash
conceal
display
1
0
0
1
9
steady
1
0
1
0
10
end box
separated
graphics
1
0
1
1
11
start box
ESC
1
1
0
0
12
normal
height
1
1
0
1
13
double
height
1
1
1
0
14
SO
1
1
1
1
15
SI
0
0
1
0
2
0
0 or 1
0
1
alpha numerics
black
0
1
1
2a
0
0
1
1
3
0
1
0
1
3a
0
0
0
4
5
1
1
1
6a
1
0
1
7
7a
1
0
0
1
0
6
1
0
1
1
0
0
8
1
1
0
1
9
1
1
0
0
12
1
1
1
1
1
13
1
0
14
1
15
(2)
(2)
(2)
contiguous
graphics
(2)
(1)
(2)
black
back ground
(2)
new
back ground
(1)
hold
graphics
(1)
(2)
release
graphics
MBA431
1996 Nov 04
30
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 17 SAA5281P/R character data input decoding, Baltic and Cyrillic languages; notes 1 to 9
For character version number (00101) see Register 11B.
B
I
T
S
b8
0
0
b7
0
b6
4
b
3
b
2
b
0
0
b5
b
0 or 1
0
1
column
r
o
w
0
1
0
1
graphics
black
0
0
0
0
0
0
0
0
1
1
alpha numerics
red
graphics
red
0
0
1
0
2
alpha numerics
green
graphics
green
0
0
1
1
3
alpha numerics
yellow
graphics
yellow
0
1
0
0
4
alpha numerics
blue
graphics
blue
0
1
0
1
5
alpha numerics
magenta
graphics
magenta
handbook, full pagewidth
0 1 1 0
6
alpha numerics
cyan
graphics
cyan
0
0
1
0
2
alpha numerics
black
0 or 1
0
1
0
0
1
1
2a
0
0
1
1
3
0
1
0
1
3a
0
1
0
0
4
6a
1
0
1
0
6
1
1
1
1
5
0
1
0
7a
8
1
1
0
0
1
7
1
0
0
1
9
1
1
0
0
12
1
1
1
1
1
13
1
0
14
1
15
(2)
0
1
1
1
7
alpha numerics
white
graphics
white
1
0
0
0
8
flash
conceal
display
1
0
0
1
9
steady
1
0
1
0
10
end box
separated
graphics
1
0
1
1
11
start box
TWIST
(2)
(2)
contiguous
graphics
(2)
(2)
1
1
0
0
12
normal
height
1
1
0
1
13
double
height
1
1
1
0
14
SO
1
1
1
1
15
SI
black
back ground
(2)
new
back ground
(1)
hold
graphics
(1)
(2)
release
graphics
MBA648 - 1
1996 Nov 04
31
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 18 SAA5281P/L character data input decoding, Arabic and Hebrew languages; notes 1 to 9
For character version number (00100) see Register 11B.
B
I
T
S
b8
0
b7
0
0
b6
0
b5
b
4
b
3
b
2
b
0 or 1
0
0
0
0
1
column
r
o
w
1
0
1
graphics
black
0
0
0
0
0
0
0
1
1
alpha numerics
red
graphics
red
0
0
1
0
2
alpha numerics
green
graphics
green
0
0
1
1
3
alpha numerics
yellow
graphics
yellow
0
1
0
0
4
alpha numerics
blue
graphics
blue
0
1
0
1
5
alpha numerics
magenta
graphics
magenta
handbook, full 0pagewidth
1 1 0
6
alpha numerics
cyan
graphics
cyan
0
0
1
2a
0
0
1
0
0
2
0
0 or 1
0
1
alpha numerics
black
0
1
1
3
0
1
0
1
3a
0
1
0 or 1
1
0
0
4
1
6
0
0 or 1
1
1
0
1
5
1
1
0
6a
1
8
1
1
0
0
1
7a
1
0
0
1
1
7
1
0
1
0
1
9
1
1
0
0
12
1
1
1
1
1
13
1
0
14
1
15
(2)
0
1
1
1
7
alpha numerics
white
graphics
white
1
0
0
0
8
flash
conceal
display
1
0
0
1
9
steady
1
0
1
0
10
end box
separated
graphics
1
0
1
1
11
start box
TWIST
(2)
(2)
contiguous
graphics
(2)
(2)
1
1
0
0
12
normal
height
1
1
0
1
13
double
height
1
1
1
0
14
SO
1
1
1
1
15
SI
black
back ground
(2)
new
back ground
(1)
hold
graphics
(1)
(2)
release
graphics
MLA963 - 1
1996 Nov 04
32
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 19 SAA5281P/K character data input decoding, French and Arabic languages; notes 1 to 9
For character version number (00100) see Register 11B.
B
I
T
S
b8
0
0
b7
0
b6
4
b
3
b
2
b
0
0
b5
b
0 or 1
0
0
1
column
r
o
w
1
0
1
graphics
black
0
0
0
0
0
0
0
0
1
1
alpha numerics
red
graphics
red
0
0
1
0
2
alpha numerics
green
graphics
green
0
0
1
1
3
alpha numerics
yellow
graphics
yellow
0
1
0
0
4
alpha numerics
blue
graphics
blue
0
1
0
1
5
alpha numerics
magenta
graphics
magenta
1 1 0
handbook, full0 pagewidth
6
alpha numerics
cyan
graphics
cyan
0
0
1
0
2
alpha numerics
black
0 or 1
0
1
0
0
1
0
2a
0
0
1
1
3
0 or 1
1
1
0
1
3a
0
0
1
1
0
0
4
6
0
0 or 1
1
1
0
1
5
1
1
0
6a
1
1
0
1
1
7
1
0
1
7a
1
0
0
0
8
1
1
0
1
9
1
1
0
0
12
1
1
1
1
1
13
1
0
14
1
15
(2)
0
1
1
1
7
alpha numerics
white
graphics
white
1
0
0
0
8
flash
conceal
display
1
0
0
1
9
steady
1
0
1
0
10
end box
separated
graphics
1
0
1
1
11
start box
TWIST
1
1
0
0
12
normal
height
1
1
0
1
13
double
height
1
1
1
0
14
SO
1
1
1
1
15
SI
(2)
(2)
contiguous
graphics
(2)
(2)
(2)
black
back ground
new
back ground
(1)
hold
graphics
(1)
(2)
release
graphics
MLA972 - 1
1996 Nov 04
33
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Notes to Tables 14, 15, 16, 17, 18 and 19
1. These control characters are reserved for compatibility with other data codes.
2. These control characters are presumed before each row begins.
3. Control characters shown in Columns 0 and 1 are normally displayed as spaces.
4. Characters may be referred to by column and row (for example 2/5 refers to %).
5. Black represents displayed colour. White represents background.
6. The SAA5281 national option characters are illustrated in Tables 21, 22 and 23.
7. Characters 8/6, 8/7, 9/5, 9/6 and 9/7 are special characters for combining with character 8/5 (E, H and T codes only).
Characters 5/12, 5/13, 5/14 and 5/15 are combined with 5/11 (S code only).
8. National option characters will be displayed according to the setting of control bits C12 to C14. These will be mapped
into the basic code table into positions shown in Tables 21, 22 and 23.
9. Columns 2a, 3a, 6a and 7a are displayed in graphics mode.
1996 Nov 04
34
1996 Nov 04
35
2/14
2/15
2/6
2/7
3/7
3/6
3/5
3/4
3/3
3/2
3/1
3/0
3/15
3/14
3/13
3/12
3/11
3/10
3/9
3/8
4/7
4/6
4/5
4/4
4/3
4/2
4/1
4/0
NC
4/15
4/14
4/13
4/12
4/11
4/10
4/9
4/8
5/7
5/6
5/5
5/4
5/3
5/2
5/1
5/0
NC
5/15
NC
5/14
NC
5/13
NC
5/12
NC
5/11
5/10
5/9
5/8
6/7
6/6
6/5
6/4
6/3
6/2
6/1
6/0
NC
6/15
6/13
6/12
6/11
6/10
6/9
6/8
7/7
7/6
7/5
7/4
7/3
7/2
7/1
7/0
7/15
MLA630
NC
7/14
NC
7/13
NC
7/12
NC
7/11
7/10
7/9
7/8
Integrated Video input processor and
Teletext decoder (IVT1.8*)
1. Where NC = national option character position.
Note
2/13
2/5
NC
2/11
2/3
2/12
2/10
2/2
2/4
2/9
2/1
NC
2/8
2/0
Table 20 SAA5281 basic character matrix; note 1
Philips Semiconductors
Preliminary specification
SAA5281
full pagewidth
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 21 SAA5281P/E national option character set
handbook, full pagewidth
PHCB
(1)
CHARACTER POSITION (COLUMN / ROW)
LANGUAGE
C12 C13 C14 2 / 3
ENGLISH
0
0
0
GERMAN
0
0
1
SWEDISH
0
1
0
ITALIAN
0
1
1
FRENCH
1
0
0
SPANISH
1
0
1
2/4
4/0
5 / 11 5 / 12 5 / 13 5 / 14 5 / 15
6/0
7 / 11 7 / 12 7 / 13 7 / 14
MLB458
(1) PHCB are the Page Header Control Bits. Other combinations default to English.
Table 22 SAA5281P/H national option character set
handbook, full pagewidth
PHCB
(1)
CHARACTER POSITION (COLUMN / ROW)
LANGUAGE
C12 C13 C14 2 / 3
POLISH
0
0
0
GERMAN
0
0
1
SWEDISH
0
1
0
SERBO-CROAT
1
0
1
CZECHOSLOVAKIA
1
1
0
RUMANIAN
1
1
1
2/4
4/0
5 / 11 5 / 12 5 / 13 5 / 14 5 / 15
6/0
7 / 11 7 / 12 7 / 13 7 / 14
MLA966
(1) PHCB are the Page Header Control Bits. Other combinations default to German. Only the above characters change with the PHCB. All other
characters in the basic set are shown in Table 20.
1996 Nov 04
36
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 23 SAA5281P/T national option character set
andbook, full pagewidth
PHCB
(1)
CHARACTER POSITION (COLUMN / ROW)
LANGUAGE
C12 C13 C14 2 / 3
ENGLISH
0
0
0
GERMAN
0
0
1
TURKISH
1
1
0
ITALIAN
0
1
1
FRENCH
1
0
0
SPANISH
1
0
1
2/4
4/0
5 / 11 5 / 12 5 / 13 5 / 14 5 / 15
6/0
7 / 11 7 / 12 7 / 13 7 / 14
MBA430
(1) PHCB are the Page Header Control Bits. Other combinations default to English. Only the above characters change with the PHCB. All other
characters in the basic set are shown in Table 20.
1996 Nov 04
37
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 24 SAA5281P/R national option character set
handbook, full pagewidth
PHCB
(1)
CHARACTER POSITION (COLUMN / ROW)
LANGUAGE
C12 C13 C14 2 / 3
ESTONIAN
0
1
0
LETTISH /
LITHUANIAN
0
1
1
RUSSIAN
1
0
0
2
2/4
4/0
3
4
5 / 11 5 / 12 5 / 13 5 / 14 5 / 15
5
6
7
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MEA597
(1) PHCB are the Page Header Control Bits. Other combinations default to Estonian.
1996 Nov 04
38
6 / 0 7 / 11 7 / 12 7 / 13 7 / 14
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 25 SAA5281P/K national option character set
2
3
4
5
6
7
2
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
3
4
5
6
7
handbook, full pagewidth
LANGUAGE
PHCB
FRENCH
ARABIC
(1)
(C12, C13, C14)
1
0
0
1
1
1
MLA968 - 1
(1) PHCB are the Page Header Control Bits. Other combinations default to French.
1996 Nov 04
39
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 26 SAA5281P/L national option character set
2
4
5
6
7
2
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
handbook, full pagewidth
LANGUAGE
PHCB
3
3
4
HEBREW/ENGLISH
5
6
7
ARABIC
(1)
(C12, C13, C14)
1
0
1
1
1
1
MLA967
(1) PHCB are the Page Header Control Bits. Other combinations default to Hebrew English.
1996 Nov 04
40
1996 Nov 04
100
nF
41
ODD/EVEN
COR
BLAN
B
G
R
SYNC
5V
CVBS
3.3
kΩ
8.2
pF
MBD790
1 kΩ
330 nF
1.5 kΩ
33
µF
100 nF
27 MHz 3rd
overtone
3.3 µH
22 nF
handbook, full pagewidth
27 kΩ
100 nF
100 nF
15
pF
10 µF
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
n.c.
n.c.
i.c.
i.c.
i.c.
i.c.
CLK EN
CLK O/P
i.c.
i.c.
i.c.
i.c.
i.c.
i.c.
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
5V
5V
LINE 23
5V
470 Ω
4.7 kΩ
4.7 kΩ
220
Ω
SDA
PON
PL out
PDI
5V
address
select
1 µF
link
options
220
Ω
SCL
5V
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
4
3
2
1
V SS
XTAL1
XTAL2
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
RST
SDA
SCL
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
PCF8572
PCF8582
83C654
5
6
7
8
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
PSEN
ALE
EA
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
VDD
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
5V
3.3
nF
56
kΩ
5V
5V
Integrated Video input processor and
Teletext decoder (IVT1.8*)
Fig.15 Application diagram for SDIP52, SOT247-1.
V SS3
SDA
SCL
Y
ODD/EVEN
COR
BLAN
RGBREF
B
G
R
V SS2
i.c.
i.c.
i.c.
i.c.
V DD1
LINE 23
SAA5281
VCR/FFB
STTV/LFB
POL
V DD2
IREF
CVBS
BLACK
n.c.
REF+
V SS1
V SS1
OSCGND
OSCIN
OSCOUT
100 nF
Philips Semiconductors
Preliminary specification
SAA5281
APPLICATION INFORMATION
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
PACKAGE OUTLINES
seating plane
DIP48: plastic dual in-line package; 48 leads (600 mil)
SOT240-1
ME
D
A2
L
A
A1
c
e
Z
w M
b1
(e 1)
b
MH
25
48
pin 1 index
E
1
24
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.9
0.36
4.06
1.4
1.14
0.53
0.38
0.36
0.23
62.60
61.60
14.22
13.56
2.54
15.24
3.90
3.05
15.88
15.24
18.46
15.24
0.254
2.1
inches
0.19
0.014
0.16
0.055
0.045
0.021
0.015
0.014
0.009
2.46
2.42
0.56
0.53
0.10
0.60
0.15
0.12
0.63
0.60
0.73
0.60
0.01
0.083
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-01-25
SOT240-1
1996 Nov 04
EUROPEAN
PROJECTION
42
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
seating plane
SDIP52: plastic shrink dual in-line package; 52 leads (600 mil)
SOT247-1
ME
D
A2
L
A
A1
c
e
Z
b1
(e 1)
w M
MH
b
27
52
pin 1 index
E
1
26
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
5.08
0.51
4.0
1.3
0.8
0.53
0.40
0.32
0.23
47.9
47.1
14.0
13.7
1.778
15.24
3.2
2.8
15.80
15.24
17.15
15.90
0.18
1.73
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
90-01-22
95-03-11
SOT247-1
1996 Nov 04
EUROPEAN
PROJECTION
43
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT319-2
c
y
X
51
A
33
52
32
ZE
Q
e
E HE
A
A2
(A 3)
A1
θ
wM
pin 1 index
Lp
bp
L
20
64
detail X
19
1
ZD
w M
bp
e
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
Q
v
w
y
mm
3.20
0.25
0.05
2.90
2.65
0.25
0.50
0.35
0.25
0.14
20.1
19.9
14.1
13.9
1
24.2
23.6
18.2
17.6
1.95
1.0
0.6
1.4
1.2
0.2
0.2
0.1
Z D (1) Z E (1)
1.2
0.8
1.2
0.8
θ
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-02-04
SOT319-2
1996 Nov 04
EUROPEAN
PROJECTION
44
o
7
0o
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Repairing soldered joints
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
Soldering by dipping or by wave
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1996 Nov 04
45
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
NOTES
1996 Nov 04
46
SAA5281
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
NOTES
1996 Nov 04
47
SAA5281
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101, Fax. +43 1 60 101 1210
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 1949
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580/xxx
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.
Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722
Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,
Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 247 9145, Fax. +7 095 247 9144
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 829 1849
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 3 301 6312, Fax. +34 3 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 632 2000, Fax. +46 8 632 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 481 7730
Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,
Chung Hsiao West Road, Sec. 1, P.O. Box 22978,
TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1996
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1200/02/pp48
Date of release: 1996 Nov 04
Document order number:
9397 750 01461