INTEGRATED CIRCUITS PCK2509S 50–150 MHz 1:9 SDRAM clock driver Product specification 1999 Oct 19 Philips Semiconductors Product specification 50–150 MHz 1:9 SDRAM clock driver PCK2509S adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic–low state. FEATURES • Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM applications • Spread Spectrum clock compatible • Operating frequency 50 to 150 MHz • (tphase error – jitter) at 100 to133 MHz = ±50 ps • Jitter (peak-peak) at 100 to 133 MHz = ± 80 ps • Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps • Pin-to-pin skew < 200 ps • Available in plastic 24-Pin TSSOP • Distributes one clock input to one bank of ten outputs • External Feedback (FBIN) terminal Is used to synchronize the Unlike many products containing PLLs, the PCK2509S does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the PCK2509S requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. The PCK2509S is characterized for operation from 0°C to +70°C. PIN CONFIGURATION outputs to the clock input • On-Chip series damping resistors • No external RC network required • Operates at 3.3 V • Inputs compatible with 2.5 V and 3.3 V ranges DESCRIPTION The PCK2509S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLLto precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The PCK2509S operates at 3.3 V VCC and is input compatible with both 2.5 V and 3.3 V input voltage ranges. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. AGND 1 24 CLK VCC 2 23 AVCC 1Y0 3 22 VCC 1Y1 4 21 2Y0 1Y2 5 20 2Y1 GND 6 19 GND GND 7 18 GND 1Y3 8 17 2Y2 1Y4 9 16 2Y3 VCC 10 15 VCC 1G 11 14 2G FBOUT 12 13 FBIN SW00389 One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 24-Pin Plastic TSSOP 0°C to +70°C PCK2509S PW SOT355-1 1999 Oct 19 2 853–2180 22544 Philips Semiconductors Product specification 50–150 MHz 1:9 SDRAM clock driver PCK2509S PIN DESCRIPTIONS PIN NUMBER SYMBOL TYPE NAME, FUNCTION, and DIRECTION 1 AGND GND Analog ground. AGND provides the ground reference for the analog circuitry. 2, 10, 15, 22 VCC PWR Power supply 3, 4, 5, 8, 9 1Y (0–4) OUT Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0–4) is enabled via the1G input. These outputs can be disabled to a logic LOW state by de-asserting the 1G control input. Each output has an integrated 25 Ω series-damping resistor. 6, 7, 18, 19 GND GND Ground 11 1G IN Output bank enable. 1G is the output enable for outputs 1Y(0–4). When 1G is LOW, outputs 1Y(0–4) are disabled to a logic LOW state. When 1G is HIGH, all outputs 1Y(0–4) are enabled and switch at the same frequency as CLK. 12 FBOUT OUT Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an integrated 25 Ω series-damping resistor. 13 FBIN IN Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. 14 2G IN Output bank enable. 2G is the output enable for outputs 2Y(0–3). When 2G is LOW, outputs 2Y(0–3) are disabled to a logic LOW state. When 2G is HIGH, all outputs 2Y(0–3) are enabled and switch at the same frequency as CLK. 16, 17, 20, 21 2Y (0–3) OUT Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0–3) is enabled via the 2G input. These outputs can be disabled to a logic LOW state by de-asserting the 2G control input. Each output has an integrated 25 Ω series-damping resistor. 23 AVCC PWR Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. 24 CLK Clock input. CLK provides the clock signal to be distributed by the PCK2509S clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. IN FUNCTION TABLE INPUTS 1G 2G X L L OUTPUTS CLK 1Y (0–4) 2Y (0–3) X L L L L L H L L H H H L H H H L H H L H H H H H H H 1999 Oct 19 FBOUT 3 Philips Semiconductors Product specification 50–150 MHz 1:9 SDRAM clock driver PCK2509S FUNCTIONAL BLOCK DIAGRAM 1G 11 3 4 5 8 9 2G 20 FBIN 1Y2 1Y3 1Y4 2Y0 2Y1 24 17 PLL 13 16 AVCC 1Y1 14 21 CLK 1Y0 2Y2 2Y3 23 12 FBOUT SW00388 SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM 168-pin SDR SDRAM DIMM SDRAM BACK SIDE FRONT SIDE A[L]VC A[L]VC A[L]VC PCK2509S The PLL clock distribution device and A[L]VC registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation SW00410 1999 Oct 19 4 Philips Semiconductors Product specification 50–150 MHz 1:9 SDRAM clock driver PCK2509S ABSOLUTE MAXIMUM RATINGS1 In accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL PARAMETER CONDITION AVCC Supply voltage range Note 2 VCC Supply voltage range IIK Input clamp current LIMITS MIN MAX < VCC + 0.7 –0.5 VI < 0 VI Input voltage range Note 3 IOK Output clamp current VO > VCC or VO < 0 VO Output voltage range Notes 3, 4 IO DC output source or sink current VO = 0 to VCC TSTG Storage temperature range –0.5 UNIT V +4.6 V –50 mA 6.5 V ±50 mA –0.5 VCC + 0.5 V ±50 mA –65 +150 °C PTOT Power dissipation per package 700 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. AVCC must not exceed VCC 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 4. This value is limited to 4.6 V maximum. RECOMMENDED OPERATING CONDITIONS1 SYMBOL PARAMETER CONDITIONS LIMITS MIN MAX 3.6 VCC, AVCC Supply voltage 3 VIH HIGH level input voltage 2 VIL LOW level input voltage UNIT V V 0.8 V VI Input voltage 0 VCC V Tamb Operating ambient temperature range in free air 0 +70 °C NOTE: 1. Unused inputs must be held high or low to prevent them from floating. ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range (unless otherwise specified) SYMBOL PARAMETER VIK Input clamp voltage VOH HIGH level output voltage VOL LOW level output voltage TEST CONDITIONS LIMITS AVCC, VCC (V) OTHER MIN TYP MAX 3 II = –18mA MIN to MAX IOH = – 100µA VCC – 0.2 3 IOH = – 12mA 2.1 3 IOH = – 6mA 2.4 MIN to MAX IOL = 100µA – 3 IOL = 12mA – 0.8 3 IOL = 6mA – 0.55 –1.2 UNIT V V 0.2 V 3.6 VI = VCC or GND ±5 µA Quiescent supply current 3.6 VI = VCC or GND; IO = 0, outputs: LOW or HIGH 10 µA ICCA AVCC power supply current AVCC = 3.3 50 µA ∆ICC Additional supply current per input pin 3.3 to 3.6 500 µA CI Input capacitance 3.3 VI = VCC or GND 2.8 pF CO Output capacitance 3.3 VO= VCC or GND 5.4 pF II ICC 1999 Oct 19 Input current 30 One input at VCC – 0.6V; other inputs at VCC or GND 5 Philips Semiconductors Product specification 50–150 MHz 1:9 SDRAM clock driver PCK2509S TIMING REQUIREMENTS Over recommended ranges of supply voltage and operating free-air temperature. MIN MAX UNIT Clock frequency PARAMETER 50 150 MHz Input clock duty cycle 40 60 % 1 ms SYMBOL fCLK Stabilization time1 NOTE: 1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. SWITCHING CHARACTERISTICS Over recommended ranges of supply voltage and operating free-air temperature, CL = 30 pF 1 FROM (INPUT)/CONDITION PARAMETER CLKIN↑ = 100 MHz to 133 MHz tphase error 2 VCC, AVCC = 3.3 V ±0.3 V TO (OUTPUT) MIN FBIN↑ CLKIN↑ = 66 MHz TYP MAX UNIT –100 100 ps –125 125 ps –50 50 ps 200 ps tphase error, – jitter 3 CLKIN↑ = 100 MHz to 133 MHz FBIN↑ tSK(0) 4 Any Y or FBOUT Any Y or FBOUT CLKIN = 66 MHz to 133 MHz Any Y or FBOUT Duty cycle reference F(CLKIN > 60 MHz) Any Y or FBOUT 47 53 % tr VO = 0.4 to 2 V Any Y or FBOUT 2.5 1 V/ns tf VO = 0.4 to 2 V Any Y or FBOUT 2.5 1 V/ns jitter(peak-peak) jitter (cycle-cycle) –80 80 |65| NOTES: 1. These parameters are not production tested. 2. This is considered as static phase error. 3. Phase error does not include jitter. (tphase error = static tphase error – jitter (cycle-cycle)). 4. The tSK(0) specification is only valid for equal loading of all outputs. PARAMETER MEASUREMENT INFORMATION 3V 50% VCC INPUT 0V tpe FROM OUTPUT UNDER TEST 2V 30pF 500Ω OUTPUT 0.4V tr LOAD CIRCUIT FOR OUTPUTS 50% VCC VOH 2V 0.4V VOL tf VOLTAGE WAVEFORMS & PHASE ERROR TIMES NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100MHz, ZO = 50Ω , tr ≤ 1.2ns, tf ≤ 1.2ns. 3. The outputs are measured one at a time with one transition per measurement. SW00384 Figure 1. Load Circuit and Voltage Waveforms 1999 Oct 19 6 ps Philips Semiconductors Product specification 50–150 MHz 1:9 SDRAM clock driver PCK2509S CLKIN FBIN tphase error FBOUT ANY Y tSK(0) ANY Y ANY Y tSK(0) SW00385 Figure 2. Phase Error and Skew Calculations 1999 Oct 19 7 Philips Semiconductors Product specification 50–150 MHz 1:9 SDRAM clock driver PCK2509S TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm 1999 Oct 19 8 SOT355-1 Philips Semiconductors Product specification 50–150 MHz 1:9 SDRAM clock driver PCK2509S NOTES 1999 Oct 19 9 Philips Semiconductors Product specification 50–150 MHz 1:9 SDRAM clock driver PCK2509S Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 10-99 Document order number: 1999 Oct 19 10 9397–750–06505