INTEGRATED CIRCUITS DATA SHEET TDA4663T Baseband delay line Product specification Supersedes data of September 1993 File under Integrated Circuits, IC02 1996 Nov 22 Philips Semiconductors Product specification Baseband delay line TDA4663T FEATURES GENERAL DESCRIPTION • Two delay lines, using the switched-capacitor technique, for a delay time of one horizontal line (1H) minus 55 ns (64 µs − 55 ns) The TDA4663T is an integrated baseband delay line circuit with a delay time of one horizontal line (1H) minus 55 ns (64 µs − 55 ns). • Adjustment-free application • Handles negative or positive colour-difference input signals • Clamping of AC-coupled input signals [mostly colour-difference signals ±(R−Y) and ±(B−Y)] • VCO without external components • 3 MHz internal clock signal derived from a 6 MHz CCO, line-locked by the sandcastle pulse (64 µs line) • Sample-and-hold circuits and low-pass filters to suppress the 3 MHz clock signal • Output buffer amplifiers. QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VP1 analog supply voltage (pin 9) 4.75 5 5.25 V VP2 digital supply voltage (pin 1) 4.75 5 5.25 V IP(tot) total supply current − 5.9 7.0 mA Vi(p-p) input signal PAL/NTSC (peak-to-peak value) ±(R−Y); pin 16 − 1.3 − V ±(B−Y); pin 14 − 1.3 − V −1 0 +1 dB −1 0 +1 dB Gv Vo gain ------ of colour-difference output signals for PAL and NTSC Vi V 11 --------V 16 V 12 --------V 14 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA4663T SO16 1996 Nov 22 DESCRIPTION plastic small outline package; 16 leads; body width 3.9 mm 2 VERSION SOT109-1 1996 Nov 22 3 VP1 sandcastle pulse input ±(B−Y) mostly colour-difference input signals ±(R−Y) handbook, full pagewidth 5 9 14 16 GND1 10 SANDCASTLE DETECTOR analog supply SIGNAL CLAMPING SIGNAL CLAMPING pre-amplifiers 1 VP2 digital supply LP DIVIDER BY-192 LINE MEMORY LINE MEMORY 6 MHz CCO 3 MHz shifting clock SAMPLEAND-HOLD SAMPLEAND-HOLD GND2 11 3 4, 8 2 6 13 15 12 output buffers TDA4663T DIVIDER BY-2 LP LP MED800 n.c. n.c. n.c. n.c. ±(B−Y) mostly colour-difference output signals ±(R−Y) Baseband delay line Fig.1 Block diagram. FREQUENCY PHASE DETECTOR 7 clamping pulse Philips Semiconductors Product specification TDA4663T BLOCK DIAGRAM Philips Semiconductors Product specification Baseband delay line TDA4663T PINNING SYMBOL PIN DESCRIPTION VP2 1 supply voltage for digital part (+5 V) n.c. 2 not connected GND2 3 ground for digital part (0 V) i.c. 4 internally connected SAND 5 sandcastle pulse input n.c. 6 not connected VCL 7 clamping pulse input i.c. 8 internally connected VP1 9 supply voltage for analog part (+5 V) GND1 10 ground for analog part (0 V) Vo(R−Y) 11 ±(R−Y) output signal Vo(B−Y) 12 ±(B−Y) output signal n.c. 13 not connected Vi(B−Y) 14 ±(B−Y) input signal n.c. 15 not connected Vi(R−Y) 16 ±(R−Y) input signal handbook, halfpage VP2 1 16 Vi(R−Y) n.c. 2 15 n.c. GND2 3 14 Vi(B−Y) i.c. 4 13 n.c. TDA4663T SAND 5 12 Vo(B−Y) n.c. 6 11 Vo(R−Y) VCL 7 10 GND1 i.c. 8 9 VP1 MED801 Fig.2 Pin configuration. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). Ground pins 3 and 10 connected together. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VP1 supply voltage (pin 9) −0.5 +7 V VP2 supply voltage (pin 1) −0.5 +7 V V5 voltage on pin 5 −0.5 VP + 1.0 V Vn voltage on pins 7, 11, 12, 14 and 16 −0.5 VP V In current on pins 7, 11 and 12 − 20 mA Tstg storage temperature −25 +150 °C Tamb operating ambient temperature −20 +70 °C Ptot total power dissipation − 100 mW Ves electrostatic handling for all pins − ±500 V note 1 Note 1. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air 1996 Nov 22 4 VALUE UNIT 220 K/W Philips Semiconductors Product specification Baseband delay line TDA4663T CHARACTERISTICS VP = 5.0 V; input signals as specified in characteristics with 75% colour bars; super-sandcastle frequency of 15.625 kHz; Tamb = 25 °C; measurements taken in Fig.3; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VP1 analog supply voltage (pin 9) 4.75 VP2 digital supply voltage (pin 1) 4.75 5 5.25 V IP1 supply current − 5.1 5.9 mA IP2 supply current − 0.8 1.1 mA 5 5.25 V Colour-difference input signals Vi(p-p) Vi(max)(p-p) input signal (peak-to-peak value) pin 16 − 1.3 − V pin 14 − 1.3 − V 1.6 − − V maximum symmetrical input signal (peak-to-peak value) pin 16 before clipping pin 14 before clipping 1.6 − − V I14, 16 input leakage current (during picture content) 0.06 0.085 0.1 µA R14, 16 input resistance during clamping − − 40 kΩ C14, 16 input capacitance − − 10 pF V14, 16 input clamping voltage 1.3 1.5 1.7 V proportional to VP Colour-difference output signals Vo(p-p) output signal (peak-to-peak value) pin 11 − 1.3 − V pin 12 − 1.3 − V V11/V12 ratio of output amplitudes at equal input signals Vi14, 16 = 665 mV (p-p) −0.4 0 +0.4 dB V11, 12 DC output voltage proportional to VP 2.5 2.9 3.3 V R11, 12 output resistance − 300 400 Ω Gv Vo voltage gain -----Vi −1 0 +1 dB Vn(rms) noise voltage (RMS value; pins 11 and 12) Vi14, 16 = 0 V; note 1 − − 1.2 mV S/N(W) weighted signal-to-noise ratio (pins 11 and 12) Vo = 1 V (p-p); note 1 − 54 − dB tj jitter of output signal to external sandcastle reference V5 − − 20 ns αct(11, 12) crosstalk between channels V14 = 0 V; RS = 300 Ω; 30 V11 = 1.35 V (p-p) − − dB αct(12, 11) crosstalk between channels V16 = 0 V; RS = 300 Ω; 30 V12 = 1.35 V (p-p) − − dB αct(14, 12) crosstalk direct from input to output V16 = 0 V; RS = 300 Ω; 30 signal V14 = 1.35 V (p-p) − − dB 1996 Nov 22 5 Philips Semiconductors Product specification Baseband delay line SYMBOL TDA4663T PARAMETER CONDITIONS MIN. αct(16, 11) crosstalk direct from input to output V14 = 0 V; RS = 300 Ω; 30 signal V16 = 1.35 V (p-p) SVRR supply voltage ripple rejection ∆V11, 12/VR VR = 100 mV (p-p); fR = 10 Hz to 1 kHz; V11, 12 = 1.35 V (p-p) V11, 12(p-p) clamping offset during H-clamp (peak-to-peak value) V14 = V16 = 0 V; RS = 300 Ω V11, 12(p-p) unwanted signals (line-locked) (peak-to-peak value) V14 = V16 = 0 V; active video; RS = 300 Ω MAX. UNIT − − dB 34 − − dB − − 5 mV − − 6.25 mV meander − − 1.5 mV needles − − 2.5 mV residual clock (3 MHz) td TYP. line delay time for PAL signals 64 − 0.125 64 − 0.055 64 + 0.015 µs for NTSC signals 63.555 − 0.125 63.555 − 0.055 63.555 + 0.015 µs 14.2 15.625 17.0 kHz Sandcastle pulse input (pin 5) fBK burst-key frequency/sandcastle frequency V5 top pulse voltage 4.0 − VP + 1.0 V tBK top pulse duration − 2.5 − µs Vslice internal slicing level V5 − 1.0 − V5 − 0.5 V Ii input current − − 10 µA Ci input capacitance − − 10 pF tli lock-in time for PLL − − 1 ms note 2 Clamping pulse input (pin 7) clamping pulse ON 3.5 VP − 0.1 VP V clamping pulse OFF −0.5 +0.1 +1.5 V Ii input current − − 10 µA Ci input capacitance − − 10 pF Vclamp tclamp clamping pulse duration 0.1 2 3 µs tr rise time 10 − − ns tf fall time 10 − − ns Notes 1. Noise voltage at f = 10 kHz to 1 MHz; RS < 300 Ω. 2. The leading edge of the burst-key pulse or H-blanking pulse is used for timing. 1996 Nov 22 6 Philips Semiconductors Product specification Baseband delay line TDA4663T APPLICATION INFORMATION handbook, full pagewidth colourdifference signals Vi(R−Y) 1 nF Vi(B−Y) TDA4663T 16 11 LINE DELAY 14 12 LINE DELAY Vo(R−Y) Vo(B−Y) 1 nF 4 8 7 clamping pulse (CMOS) 2 n.c. 6 n.c. n.c. n.c. VCO SSC (5 V) 5 LINE-LOCKED PLL / PULSE PROCESSING 13 15 10 +5.1 V 9 +5.1 V 1 (1) 3 (1) 100 nF 10 Ω 10 Ω 22 µF 100 nF 560 Ω +12 V 5.1 V MED802 (1) Positioned close to pins. Fig.3 Application circuit. 1996 Nov 22 7 Philips Semiconductors Product specification Baseband delay line TDA4663T PACKAGE OUTLINE SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0098 0.39 0.014 0.0075 0.38 0.050 0.24 0.23 0.041 0.039 0.016 0.028 0.020 inches 0.0098 0.057 0.069 0.0039 0.049 0.16 0.15 0.01 0.01 0.028 0.004 0.012 θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07S MS-012AC 1996 Nov 22 EIAJ EUROPEAN PROJECTION ISSUE DATE 91-08-13 95-01-23 8 o 8 0o Philips Semiconductors Product specification Baseband delay line TDA4663T During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Reflow soldering Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream end. 1996 Nov 22 9 Philips Semiconductors Product specification Baseband delay line TDA4663T DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Nov 22 10 Philips Semiconductors Product specification Baseband delay line TDA4663T NOTES 1996 Nov 22 11 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/1200/02/pp12 Date of release: 1996 Nov 22 Document order number: 9397 750 01375