SAMSUNG K6R4004C1C-E12

K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E
PRELIMINARY
CMOS SRAM
Document Title
1Mx4 Bit High Speed Static RAM(5V Operating).
Operated at Extended and Industrial Temperature Ranges.
Revision History
Rev No.
History
Draft Data
Remark
Rev. 0.0
Initial release with Preliminary.
Feb. 12. 1999
Preliminary
Rev. 1.0
1.1 Removed Low power Version.
1.2 Removed Data Retention Characteristics
1.3 Changed ISB1 to 20mA
Mar. 29. 1999
Preliminary
Rev. 2.0
2.1 Relax D.C parameters.
Aug. 19. 1999
Preliminary
Mar. 27. 2000
Final
Item
Previous
160mA
155mA
150mA
12ns
15ns
20ns
ICC
Current
190mA
185mA
180mA
2.2 Relax Absolute Maximum Rating.
Item
Voltage on Any Pin Relative to Vss
Rev. 3.0
Previous
-0.5 to 7.0
Current
-0.5 to Vcc+0.5
3.1 Delete Preliminary
3.2 Update D.C parameters and 10ns part.
10ns
12ns
15ns
20ns
ICC
190mA
185mA
180mA
Previous
Isb
Isb1
70mA
20mA
ICC
160mA
150mA
140mA
130mA
Current
Isb
Isb1
60mA
10mA
3.3 Added Extended temperature range
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 3.0
March 2000
PRELIMINARY
CMOS SRAM
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E
1M x 4 Bit (with OE)High-Speed CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 10,12,15,20ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 60mA(Max.)
(CMOS) : 10mA(Max.)
Operating K6R4004C1C-10 : 160mA(Max.)
K6R4004C1C-12 : 150mA(Max.)
K6R4004C1C-15 : 140mA(Max.)
K6R4004C1C-20 : 130mA(Max.)
• Single 5.0V ±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
K6R4004C1C-J : 32-SOJ-400
The K6R4004C1C is a 4,194,304-bit high-speed Static Random
Access Memory organized as 1,048,576 words by 4 bits. The
K6R4004C1C uses 4 common input and output lines and has
an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAMSUNG′s advanced CMOS process and designed for highspeed circuit technology. It is particularly well suited for use in
high-density
high-speed
system
applications.
The
K6R4004C1C is packaged in a 400 mil 32-pin plastic SOJ.
PIN CONFIGURATION(Top View)
ORDERING INFORMATION
K6R4004C1C-C10/C12/C15/C20
Commercial Temp.
K6R4004C1C-E10/E12/E15/E20
Extended Temp.
K6R4004C1C-I10/I12/I15/I20
Industrial Temp.
FUNCTIONAL BLOCK DIAGRAM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O1 ~I/O4
Pre-Charge Circuit
Row Select
Clk Gen.
Memory Array
1024 Rows
1024 x 4 Columns
Data
Cont.
I/O Circuit
Column Select
A0
1
32
A19
A1
2
31
A18
A2
3
30
A17
A3
4
29
A16
A4
5
28
A15
CS
6
27
OE
I/O1
7
26 I/O4
Vcc
8
SOJ
25
Vss
Vcc
Vss
9
24
I/O2
10
23 I/O3
WE
11
22
A14
A5
12
21
A13
A6
13
20
A12
A7
14
19
A11
A8
15
18
A10
16
17 N.C
A9
PIN FUNCTION
Pin Name
A0 - A19
CLK
Gen.
A10 A12 A14 A16 A18
A11 A13 A15
A17 A19
WE
Write Enable
CS
Chip Select
OE
Output Enable
I/O1 ~ I/O4
CS
Pin Function
Address Inputs
Data Inputs/Outputs
VCC
Power(+5.0V)
WE
VSS
Ground
OE
N.C
No Connection
-2-
Rev 3.0
March 2000
PRELIMINARY
CMOS SRAM
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
Storage Temperature
Operating Temperature
Symbol
Rating
Unit
VIN, VOUT
-0.5 to VCC+0.5
V
VCC
-0.5 to 7.0
V
PD
1.0
W
TSTG
-65 to 150
°C
TA
0 to 70
°C
Extended
TA
-25 to 85
°C
Industrial
TA
-40 to 85
°C
Commercial
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
4.5
5.0
5.5
V
Ground
VSS
0
0
0
V
Input High Voltage
VIH
2.2
-
VCC+0.5***
V
Input Low Voltage
VIL
-0.5**
-
0.8
V
* The above parameters are also guaranteed at extended and industrial temperature range.
** VIL(Min) = -2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA.
*** VIH(Max) = VCC + 2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA.
DC AND OPERATING CHARACTERISTICS* (TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Min
Max
Unit
Input Leakage Current
Parameter
Symbol
ILI
VIN=VSS to VCC
Test Conditions
-2
2
µA
Output Leakage Current
ILO
CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
-2
2
µA
Operating Current
ICC
Min. Cycle, 100% Duty
CS=VIL, VIN=VIH or VIL, IOUT=0mA
10ns
-
160
mA
12ns
-
150
15ns
-
140
20ns
-
130
10ns
-
175
12ns
-
165
15ns
-
155
20ns
-
145
Com.
Ext.
Ind.
ISB
Min. Cycle, CS=VIH
-
60
ISB1
f=0MHz, CS≥VCC-0.2V,
VIN≥VCC-0.2V or VIN≤0.2V
-
10
Output Low Voltage Level
VOL
IOL=8mA
-
0.4
V
Output High Voltage Level
VOH
IOH=-4mA
2.4
-
V
-
3.95
V
Standby Current
VOH1**
IOH1=-0.1mA
mA
* The above parameters are also guaranteed at extended and industrial temperature range.
** VCC=5.0V±5%, Temp.=25°C.
CAPACITANCE* (TA=25°C, f=1.0MHz)
Item
Symbol
Test Conditions
MIN
Max
Unit
Input/Output Capacitance
CI/O
VI/O=0V
-
8
pF
Input Capacitance
CIN
VIN=0V
-
7
pF
* Capacitance is sampled and not 100% tested.
-3-
Rev 3.0
March 2000
PRELIMINARY
CMOS SRAM
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
* The above test conditions are also applied at extended and industrial temperature range.
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
Output Loads(A)
+5.0V
RL = 50Ω
DOUT
480Ω
VL = 1.5V
DOUT
30pF*
ZO = 50Ω
255Ω
* Capacitive Load consists of all components of the
test environment.
5pF*
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
Symbol
K6R4004C1C-10
Min
K6R4004C1C-12
Max
Min
K6R4004C1C-15
Max
Min
K6R4004C1C-20
Max
Min
Max
Unit
Read Cycle Time
tRC
10
-
12
-
15
-
20
-
ns
Address Access Time
tAA
-
10
-
12
-
15
-
20
ns
Chip Select to Output
tCO
-
10
-
12
-
15
-
20
ns
Output Enable to Valid Output
tOE
-
5
-
6
-
7
-
8
ns
Chip Enable to Low-Z Output
tLZ
3
-
3
-
3
-
3
-
ns
Output Enable to Low-Z Output
tOLZ
0
-
0
-
0
-
0
-
ns
Chip Disable to High-Z Output
tHZ
0
5
0
6
0
7
0
9
ns
Output Disable to High-Z Output
tOHZ
0
5
0
6
0
7
0
9
ns
Output Hold from Address Change
tOH
3
-
3
-
3
-
3
-
ns
Chip Selection to Power Up Time
tPU
0
-
0
-
0
-
0
-
ns
Chip Selection to Power DownTime
tPD
-
10
-
12
-
15
-
20
ns
* The above parameters are also guaranteed at extended and industrial temperature range.
-4-
Rev 3.0
March 2000
PRELIMINARY
CMOS SRAM
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E
WRITE CYCLE*
Parameter
Symbol
K6R4004C1C-10
K6R4004C1C-12
K6R4004C1C-15
K6R4004C1C-20
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Write Cycle Time
tWC
10
-
12
-
15
-
20
-
ns
Chip Select to End of Write
tCW
7
-
8
-
10
-
12
-
ns
Address Set-up Time
tAS
0
-
0
-
0
-
0
-
ns
Address Valid to End of Write
tAW
7
-
8
-
10
-
12
-
ns
Write Pulse Width(OE High)
tWP
7
-
8
-
10
-
12
-
ns
Write Pulse Width(OE Low)
tWP1
10
-
12
-
15
-
20
-
ns
Write Recovery Time
tWR
0
-
0
-
0
-
0
-
ns
Write to Output High-Z
tWHZ
0
5
0
6
0
7
0
9
ns
Data to Write Time Overlap
tDW
5
-
6
-
7
-
9
-
ns
Data Hold from Write Time
tDH
0
-
0
-
0
-
0
-
ns
End Write to Output Low-Z
tOW
3
-
3
-
3
-
3
-
ns
* The above parameters are also guaranteed at extended and industrial temperature range.
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Out
Valid Data
Previous Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tAA
tCO
CS
tHZ(3,4,5)
tOHZ
tOE
OE
tOH
tOLZ
tLZ(4,5)
Data out
Valid Data
VCC
ICC
Current
ISB
tPU
tPD
50%
50%
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL
levels.
4. At any given temperature and voltage condition, t HZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
-5-
Rev 3.0
March 2000
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E
PRELIMINARY
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
tWC
Address
tWR(5)
tAW
OE
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDW
Data in
High-Z
tDH
Valid Data
tOHZ(6)
High-Z(8)
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tAS(4)
tWP1(2)
WE
tDW
Data in
High-Z
tDH
Valid Data
tWHZ(6)
tOW
High-Z(8)
Data out
(10)
(9)
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDW
Data in
High-Z
Valid Data
tLZ
Data out
tDH
High-Z
tWHZ(6)
High-Z(8)
High-Z
-6-
Rev 3.0
March 2000
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E
PRELIMINARY
CMOS SRAM
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write
ends at the earliest transition CS going high or WE going high. t WP is measured from the beginning of write to the end of write.
3. t CW is measured from the later of CS going low to end of write.
4. t AS is measured from the address valid to the beginning of write.
5. t WR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the
output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
CS
WE
OE
Mode
I/O Pin
Supply Current
H
X
X*
Not Select
High-Z
ISB, ISB1
L
H
H
Output Disable
High-Z
ICC
L
H
L
Read
DOUT
ICC
L
L
X
Write
DIN
ICC
* X means Don′t Care.
-7-
Rev 3.0
March 2000
PRELIMINARY
CMOS SRAM
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E
PACKAGE DIMENSIONS
Units:millimeters/Inches
32-SOJ-400
#17
10.16
0.400
#32
11.18 ±0.12
0.440 ±0.005
9.40 ±0.25
0.370 ±0.010
0.20
#1
0.69
0.027 MIN
21.36 MAX
0.841
20.95 ±0.12
0.825 ±0.005
( 1.30 )
0.051
( 1.30 )
0.051
( 0.95 )
0.0375
0.43
+0.10
-0.05
0.017+0.004
-0.002
1.27
0.050
+0.10
-0.05
0.008 +0.004
-0.002
#16
0.71
3.76 MAX
0.148
0.10
MAX
0.004
+0.10
-0.05
0.028 +0.004
-0.002
-8-
Rev 3.0
March 2000