PHILIPS PCA9545PW

INTEGRATED CIRCUITS
PCA9545
4-channel I2C switch with interrupt logic
and reset
Product data
Supersedes data of 2001 Nov 08
2002 Mar 28
Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
passed by the PCA9545. This allows the use of different bus
voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can
communicate with 5 V parts without any additional protection.
External pull-up resistors pull the bus up to the desired voltage level
for each channel. All I/O pins are 5 V tolerant.
PIN CONFIGURATION
FEATURES
• 1-of-4 bi-directional translating switches
• I2C interface logic; compatible with SMBus standards
• 4 active low interrupt inputs
• Active low interrupt output
• Active low reset input
• 2 address pins allowing up to 4 devices on the I2C bus
• Channel selection via I2C bus, in any combination
• Power up with all switch channels deselected
• Low RDSON switches
• Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
A0 1
20 VDD
A1 2
19 SDA
RESET 3
18 SCL
INT0 4
17 INT
SD0 5
16 SC3
SC0 6
15 SD3
INT1 7
14 INT3
SD1 8
13 SC2
SC1 9
12 SD2
VSS 10
11 INT2
SW00762
Figure 1. Pin configuration
5 V buses
• No glitch on power-up
• Supports hot insertion
• Low stand-by current
• Operating power supply voltage range of 2.3 V to 5.5 V
• 5 V tolerant Inputs
• 0 to 400 kHz clock frequency
• ESD protection exceeds 2000 V HBM per JESD22-A114,
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
1
A0
Address input 0
2
A1
Address input 1
3
RESET
4
INT0
Active low interrupt input 0
5
SD0
Serial data 0
6
SC0
Serial clock 0
7
INT1
Active low interrupt input 1
8
SD1
Serial data 1
DESCRIPTION
9
SC1
Serial clock 1
The PCA9545 is a quad bi-directional translating switch controlled
via the I2C bus. The SCL/SDA upstream pair fans out to four
downstream pairs, or channels. Any individual SCx/SDx channel or
combination of channels can be selected, determined by the
contents of the programmable control register. Four interrupt inputs,
INT0 to INT3, one for each of the downstream pairs, are provided.
One interrupt output, INT, acts as an AND of the four interrupt
inputs.
10
VSS
Supply ground
11
INT2
Active low interrupt input 2
12
SD2
Serial data 2
13
SC2
Serial clock 2
14
INT3
Active low interrupt input 3
15
SD3
Serial data 3
An active-LOW reset input allows the PCA9545 to recover from a
situation where one of the downstream I2C buses is stuck in a LOW
state. Pulling the RESET pin LOW resets the I2C state machine and
causes all the channels to be deselected as does the internal power
on reset function.
The pass gates of the switches are constructed such that the VDD
pin can be used to limit the maximum high voltage which will be
16
SC3
Serial clock 3
17
INT
Active low interrupt output
18
SCL
Serial clock line
19
SDA
Serial data line
20
VDD
Supply voltage
150 V MM per JESD22-A115 and 1000 V per JESD22-C101
• Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
• Package Offer: SO20, TSSOP20
FUNCTION
Active low reset input
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
20-Pin Plastic SO
–40 to +85 °C
PCA9545D
SOT163-1
20-Pin Plastic TSSOP
–40 to +85 °C
PCA9545PW
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
2002 Mar 28
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Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
BLOCK DIAGRAM
PCA9545
SC0
SC1
SC2
SC3
SD0
SD1
SD2
SD3
SWITCH CONTROL LOGIC
VSS
VDD
RESET
POWER ON
RESET
SCL
SDA
INT[0–3]
INPUT
FILTER
I2C-BUS
CONTROL
A0
A1
INT LOGIC
INT
SW00758
Figure 2. Block diagram
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Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
DEVICE ADDRESS
CONTROL REGISTER DEFINITION
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9545 is
shown in Figure 3. To conserve power, no internal pullup resistors
are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.
One or several SCx/SDx downstream pair, or channel, is selected
by the contents of the control register. This register is written after
the PCA9545 has been addressed. The 2 LSBs of the control byte
are used to determine which channel is to be selected. When a
channel is selected, the channel will become active after a stop
condition has been placed on the I2C bus. This ensures that all
SCx/SDx lines will be in a HIGH state when the channel is made
active, so that no false conditions are generated at the time of
connection.
1
1
1
0
FIXED
0
A1 A0 R/W
HARDWARE SELECTABLE
SW00893
Table 1. Control Register; Write — Channel Selection/
Read — Channel Status
INT3 INT2 INT1 INT0
B3
B2
B1
B0
COMMAND
Channel 0
0
disabled
X
X
X
X
X
X
X
Channel 0
1
enabled
Channel 1
0
disabled
X
X
X
X
X
X
X
Channel 1
1
enabled
Channel 2
0
disabled
X
X
X
X
X
X
X
Channel 2
1
enabled
Channel 3
0
disabled
X
X
X
X
X
X
X
Channel 3
1
enabled
Figure 3. Slave address
The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read is selected while a logic 0
selects a write operation.
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9545, which will be stored
in the control register. If multiple bytes are received by the
PCA9545, it will save the last byte received. This register can be
written and read via the I2C bus.
INTERRUPT BITS CHANNEL SELECTION BITS
(READ ONLY)
(READ/WRITE)
7
6
5
4
INT3 INT2 INT1 INT0
3
2
1
0
B3
B2
B1
B0
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
INT0
INT1
INT2
INT3
SW00949
NOTE: Several channels can be enabled at the same time.
Ex: B3 = 0, B2 = 1, B1 = 1, B0 = 0, means that channel 0 and 3 are
disabled and channel 1 and 2 are enabled.
Care should be taken not to exceed the maximum bus capacity.
Figure 4. Control Register
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Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
INTERRUPT HANDLING
POWER-ON RESET
The PCA9545 provides 4 interrupt inputs, one for each channel, and
one open drain interrupt output. When an interrupt is generated by any
device, it will be detected by the PCA9545 and the interrupt output
will be driven LOW. The channel does not need to be active for
detection of the interrupt. A bit is also set in the control register.
When power is applied to VDD, an internal Power On Reset holds
the PCA9545 in a reset state until VDD has reached VPOR. At this
point, the reset condition is released and the PCA9545 registers and
I2C state machine are initialized to their default states, all zeroes
causing all the channels to be deselected.
Bits 4 – 7 of the control register correspond to channels 0 – 3 of the
PCA9545, respectively. Therefore, if an interrupt is generated by any
device connected to channel 1, the state of the interrupt inputs is
loaded into the control register when a read is accomplished.
Likewise, an interrupt on any device connected to channel 0 would
cause bit 4 of the control register to be set on the read. The master
can then address the PCA9545 and read the contents of the control
register to determine which channel contains the device generating the
interrupt. The master can then reconfigure the PCA9545 to select this
channel, and locate the device generating the interrupt and clear it.
VOLTAGE TRANSLATION
The pass gate transistors of the PCA9545 are constructed such that
the VDD voltage can be used to limit the maximum voltage that will
be passed from one I2C bus to another.
Vpass vs. VDD
It should be noted that more than one device can be providing an
interrupt on a channel, so it is up to the master to ensure that all
devices on a channel are interrogated for an interrupt.
5.0
4.5
MAXIMUM
4.0
The interrupt inputs may be used as general purpose inputs if the
interrupt function is not required.
TYPICAL
3.5
Vpass
3.0
If unused, interrupt input(s) must be connected to VDD through a
pull-up resistor.
2.5
2.0
Table 2. Control Register Read — Interrupt
INT3
INT2
INT1
INT0
B3
B2
B1
B0
0
X
X
X
X
X
X
X
1
0
X
X
X
X
X
X
X
1
0
X
X
X
X
X
X
X
1
0
X
X
1
X
X
X
X
X
COMMAND
1.5
No interrupt
on channel 0
1.0
MINIMUM
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD
Interrupt on
channel 0
No interrupt
on channel 1
5.5
SW00820
Figure 5. Vpass voltage vs. VDD
Interrupt on
channel 1
Figure 5 shows the voltage characteristics of the pass gate
transistors (note that the graph was generated using the data
specified in the DC Characteristics section of this datasheet). In
order for the PCA9545 to act as a voltage translator, the Vpass
voltage should be equal to, or lower than the lowest bus voltage. For
example, if the main bus was running at 5 V, and the downstream
buses were 3.3 V and 2.7 V, then Vpass should be equal to or below
2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 5, we see that Vpass (max.) will be at 2.7 V when the
PCA9545 supply voltage is 3.5 V or lower so the PCA9545 supply
voltage could be set to 3.3 V. Pull-up resistors can then be used to
bring the bus voltages to their appropriate levels (see Figure 12).
No interrupt
on channel 2
Interrupt on
channel 2
No interrupt
on channel 3
Interrupt on
channel 3
NOTE: Several interrupts can be active at the same time.
Ex: INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0, means that there is no
interrupt on channels 0 and 3, and there is interrupt on channels 1
and 2.
More Information can be found in Application Note AN262 PCA954X
family of I 2C/SMBus multiplexers and switches.
RESET INPUT
The RESET input is an active-LOW signal which may be used to
recover from a bus fault condition. By asserting this signal LOW for
a minimum of tWL, the PCA9545 will reset its registers and I2C state
machine and will deselect all channels. The RESET input must be
connected to VDD through a pull-up resistor.
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Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
CHARACTERISTICS OF THE I2C-BUS
Start and stop conditions
The I2C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 7).
Bit transfer
System configuration
One data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see Figure 6).
A device generating a message is a ‘transmitter’, a device receiving
is the ‘receiver’. The device that controls the message is the
‘master’ and the devices which are controlled by the master are the
‘slaves’ (see Figure 8).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
SW00363
Figure 6. Bit transfer
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
SW00365
Figure 7. Definition of start and stop conditions
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
I2C
MULTIPLEXER
SLAVE
SW00366
Figure 8. System configuration
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Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START condition
SW00368
Figure 9. Acknowledgement on the
I2C-bus
Bus transactions
Data is transmitted to the PCA9545 control register using the write mode as shown in Figure 10.
SLAVE ADDRESS
SDA
1
S
1
1
0
0
A1
CONTROL REGISTER
A0
start condition
0
R/W
A
X
X
X
X
B3
B2
acknowledge
from slave
B1
B0
A
acknowledge
from slave
P
stop condition
SW00760
Figure 10. WRITE control register
Data is read from PCA9545 control register using the read mode as shown in Figure 11.
CONTROL REGISTER
SLAVE ADDRESS
SDA
S
1
1
start condition
1
0
0
A1
A0
1
R/W
A INT3 INT2 INT1 INT0 B3
acknowledge
from slave
B2
last byte
B1
B0
NA
no acknowledge
from master
P
stop condition
SW00761
Figure 11. READ control register
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Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
TYPICAL APPLICATION
VDD = 2.7 – 5.5 V
VDD = 3.3 V
V = 2.7 – 5.5 V
SEE NOTE (1)
SDA
SDA
SD0
SCL
SCL
SC0
INT0
CHANNEL 0
INT
V = 2.7 – 5.5 V
RESET
SEE NOTE (1)
I2C/SMBus MASTER
SD1
CHANNEL 1
SC1
INT1
V = 2.7 – 5.5 V
SEE NOTE (1)
SD2
CHANNEL 2
SC2
INT2
V = 2.7 – 5.5 V
SEE NOTE (1)
A1
NOTE:
1.
If the device generating the Interrupt has an open-drain output structure or
can be tri-stated, a pull-up resistor is required.
SD3
A0
CHANNEL 3
SC3
VSS
If the device generating the Interrupt has a totem-pole output structure and
cannot be tri-stated, a pull-up resistor is not required.
INT3
PCA9545
The Interrupt inputs should not be left floating.
SW00810
Figure 12. Typical application
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Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
MIN
MAX
DC supply voltage
–0.5
+7.0
VI
DC input voltage
–0.5
+7.0
V
II
DC input current
—
±20
mA
VDD
V
IO
DC output current
—
±25
mA
IDD
DC Supply current
—
±100
mA
ISS
DC Supply current
—
±100
mA
Ptot
total power dissipation
—
400
mW
Tstg
Storage temperature range
–60
+150
°C
Tamb
Operating ambient temperature
–40
+85
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
DC CHARACTERISTICS
VDD = 2.3 to 3.6 V; VSS = 0 V; Tamb = –40 to +85 °C; unless otherwise specified. (See page 11 for VDD = 3.6 to 5.5 V.)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
Supply
VDD
Supply voltage
2.3
—
Operating mode; VDD = 3.6 V;
IDD
Supply current
—
30
no load; VI = VDD or VSS;
fSCL = 100 kHz
Standby mode; VDD = 3.6 V;
Istb
Standby current
—
20
no load; VI = VDD or VSS
VPOR
Power-on reset voltage
no load; VI = VDD or VSS
—
1.6
Input SCL; input/output SDA
VIL
LOW level input voltage
–0.5
—
VIH
HIGH level input voltage
0.7 VDD
—
VOL = 0.4 V
3
—
output
IOL
LOW level out
ut current
VOL = 0.6 V
6
—
IL
Leakage current
VI = VDD or VSS
–1
—
Ci
Input capacitance
VI = VSS
—
12
Select inputs A0 to A1 / INT0 to INT3 / RESET
VIL
LOW level input voltage
–0.5
—
VIH
HIGH level input voltage
0.7 VDD
—
ILI
Input leakage current
pin at VDD or VSS
–1
—
Ci
Input capacitance
VI = VSS
—
1.6
Pass Gate
VDD = 3.0 to 3.6 V, VO = 0.4 V, IO = 15 mA
5
20
RON
Switch resistance
VDD = 2.3 to 2.7 V, VO = 0.4 V, IO = 10 mA
7
26
Vswin = VDD = 3.3 V; Iswout = –100 µA
—
2.2
Vswin = VDD = 3.0 to 3.6 V; Iswout = –100 µA
1.6
—
VPass
Switch output
out ut voltage
P
Vswin = VDD = 2.5 V; Iswout = –100 µA
—
1.5
Vswin = VDD = 2.3 to 2.7 V; Iswout = –100 µA
1.1
—
IL
Leakage current
VI = VDD or VSS
–1
—
Cio
Input/output capacitance
VI = VSS
—
3
INT Output
IOL
LOW level output current
VOL = 0.4 V
3
—
IOH
HIGH level output current
—
—
2002 Mar 28
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MAX
UNIT
3.6
V
100
µA
100
µA
2.1
V
0.3 VDD
6
—
—
+1
13
V
V
mA
+0.3 VDD
VDD + 0.5
+1
3
V
V
µA
pF
30
55
—
2.8
—
2.0
+1
5
Ω
µA
pF
—
+100
mA
µA
µA
pF
V
853-2302 27311
Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
DC CHARACTERISTICS
VDD = 3.6 to 5.5 V; VSS = 0 V; Tamb = –40 to +85 °C; unless otherwise specified. (See page 10 for VDD = 2.3 to 3.6 V.)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
MIN
TYP
MAX
UNIT
Supply
VDD
Supply voltage
IDD
Supply current
Istb
Standby current
VPOR
Power-on reset voltage
3.6
—
5.5
V
Operating mode; VDD = 5.5 V;
no load; VI = VDD or VSS;
fSCL = 100 kHz
—
575
600
µA
Standby mode; VDD = 5.5 V;
no load; VI = VDD or VSS
—
130
200
µA
no load; VI = VDD or VSS
—
1.6
2.1
V
V
Input SCL; input/output SDA
VIL
LOW level input voltage
–0.5
—
0.3 VDD
VIH
HIGH level input voltage
0.7 VDD
—
6
V
3
—
—
mA
VOL = 0.4 V
IOL
output
LOW level out
ut current
VOL = 0.6 V
6
—
—
mA
IIL
LOW level input current
VI = VSS
–10
—
+10
µA
IIH
HIGH level input current
VI = VDD
—
—
+100
µA
VI = VSS
—
12
13
pF
pin at VDD or VSS
VI = VSS
–0.5
0.7 VDD
–1
—
—
—
—
1.6
+0.3 VDD
VDD + 0.5
+50
3
V
V
µA
pF
Ci
Input capacitance
Select inputs A0 to A1 / INT0 to INT3 / RESET
VIL
LOW level input voltage
VIH
HIGH level input voltage
ILI
Input leakage current
Ci
Input capacitance
Pass Gate
RON
VPass
P
IL
Cio
INT Output
IOL
IOH
2002 Mar 28
Switch resistance
Switch output
out ut voltage
Leakage current
Input/output capacitance
LOW level output current
HIGH level output current
VCC = 4.5 to 5.5 V, VO = 0.4 V, IO = 15 mA
4
11
24
Ω
Vswin = VDD = 5.0 V; Iswout = –100 µA
—
3.5
—
V
Vswin = VDD = 4.5 to 5.5 V; Iswout = –100 µA
VI = VDD or VSS
VI = VSS
2.6
–1
—
—
—
3
4.5
+100
5
V
µA
pF
VOL = 0.4 V
3
—
—
—
—
+100
mA
µA
10
853-2302 27311
Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
AC CHARACTERISTICS
SYMBOL
STANDARD-MODE
I2C-BUS
PARAMETER
FAST-MODE I2C-BUS
UNIT
MIN
MAX
MIN
MAX
Propagation delay from SDA to SDn or SCL to SCn
—
0.31
—
0.31
ns
fSCL
SCL clock frequency
0
100
0
400
kHz
tBUF
Bus free time between a STOP and START condition
4.7
—
1.3
—
µs
Hold time (repeated) START condition
After this period, the first clock pulse is generated
4.0
—
0.6
—
µs
tLOW
LOW period of the SCL clock
4.7
—
1.3
—
µs
tHIGH
HIGH period of the SCL clock
4.0
—
0.6
—
µs
tpd
tHD;STA
tSU;STA
Set-up time for a repeated START condition
4.7
—
0.6
—
µs
tSU;STO
Set-up time for STOP condition
4.0
—
0.6
—
µs
tHD;DAT
Data hold time
02
3.45
02
0.9
µs
tSU;DAT
Data set-up time
ns
250
—
100
—
tR
Rise time of both SDA and SCL signals
—
1000
20 + 0.1Cb3
300
ns
tF
Fall time of both SDA and SCL signals
—
300
20 + 0.1Cb3
300
µs
Cb
Capacitive load for each bus line
—
400
—
400
µs
tSP
Pulse width of spikes which must be suppressed
by the input filter
—
50
—
50
ns
tVD:DATL
Data valid (HL)
—
1
—
1
µs
tVD:DATH
Data valid (LH)
—
0.6
—
0.6
µs
tVD:ACK
Data valid Acknowledge
—
1
—
1
µs
tiv
INTn to INT active valid time
—
4
—
4
µs
tir
INTn to INT inactive delay time
—
2
—
2
µs
INT
Lpwr
LOW level pulse width rejection or INTn inputs
1
—
1
—
µs
Hpwr
HIGH level pulse width rejection or INTn inputs
0.5
—
0.5
—
µs
4
—
4
—
ns
500
—
500
—
ns
0
—
0
—
ns
RESET
tWL(rst)
trst
Pulse width low reset
Reset time (SDA clear)
tREC:STA
Recovery to Start
NOTES:
1. Pass gate propagation delay is calculated from the 20 Ω typical RON and the 15 pF load capacitance.
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) in order to bridge
the undefined region of the falling edge of SCL.
3. Cb = total capacitance of one bus line in pF.
SDA
tBUF
tLOW
tR
tF
tHD;STA
tSP
SCL
tHD;STA
P
S
tSU;STA
tHD;DAT
tHIGH
tSU;DAT
Sr
tSU;STO
P
SU00645
Figure 13. Definition of timing on the I2C-bus
2002 Mar 28
11
853-2302 27311
Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
SO20: plastic small outline package; 20 leads; body width 7.5 mm
2002 Mar 28
12
PCA9545
SOT163-1
853-2302 27311
Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
2002 Mar 28
13
PCA9545
SOT360-1
853-2302 27311
Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
Data sheet status
Data sheet status [1]
Product
status [2]
Definitions
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Koninklijke Philips Electronics N.V. 2002
All rights reserved. Printed in U.S.A.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 03-02
For sales offices addresses send e-mail to:
[email protected]
Document order number:
9397 750 09608
2002 Mar 28
14
853-2302 27311