FM22LD16 4-Mbit (256K × 16) F-RAM Memory 4-Mbit (256K × 16) F-RAM Memory Features Functional Overview ■ 4-Mbit ferroelectric random access memory (F-RAM) logically organized as 256K × 16 ❐ Configurable as 512K × 8 using UB and LB 14 ❐ High-endurance 100 trillion (10 ) read/writes ❐ 151-year data retention (see the Data Retention and Endurance table) ❐ NoDelay™ writes ❐ Page mode operation to 25-ns cycle time ❐ Advanced high-reliability ferroelectric process ■ SRAM compatible ❐ Industry-standard 256K × 16 SRAM pinout ❐ 55-ns access time, 110-ns cycle time ■ Advanced features ❐ Software-programmable block write-protect ■ Superior to battery-backed SRAM modules ❐ No battery concerns ❐ Monolithic reliability ❐ True surface mount solution, no rework steps ❐ Superior for moisture, shock, and vibration ■ Low power consumption ❐ Active current 8 mA (typ) ❐ Standby current 90 A (typ) ■ Low-voltage operation: VDD = 2.7 V to 3.6 V ■ Industrial temperature: –40 C to +85 C ■ 48-ball fine-pitch ball grid array (FBGA) package ■ Restriction of hazardous substances (RoHS) compliant The FM22LD16 is a 256K × 16 nonvolatile memory that reads and writes similar to a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 151 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and high write endurance make the F-RAM superior to other types of memory. The FM22LD16 operation is similar to that of other RAM devices and therefore, it can be used as a drop-in replacement for a standard SRAM in a system. Read and write cycles may be triggered by CE or simply by changing the address. The F-RAM memory is nonvolatile due to its unique ferroelectric memory process. These features make the FM22LD16 ideal for nonvolatile memory applications requiring frequent or rapid writes. The FM22LD16 includes a low voltage monitor that blocks access to the memory array when VDD drops below VDD min. The memory is protected against an inadvertent access and data corruption under this condition. The device also features software-controlled write protection. The memory array is divided into 8 uniform blocks, each of which can be individually write protected. The device is available in a 48-ball FBGA package. Device specifications are guaranteed over the industrial temperature range –40 °C to +85 °C. For a complete list of related documentation, click here. A 1-0 32 K x 16 block 32 K x 16 block 32 K x 16 block 32 K x 16 block 32 K x 16 block 32 K x 16 block 32 K x 16 block 32 K x 16 block ... A17-0 A 17-2 Block & Row Decoder Address Latch & Write Protect Logic Block Diagram ... CE Column Decoder WE Control Logic UB, LB I/O Latch & Bus Driver DQ15-0 OE Cypress Semiconductor Corporation Document Number: 001-86190 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 27, 2016 FM22LD16 Contents Pinout ................................................................................ 3 Pin Definitions .................................................................. 3 Device Operation .............................................................. 4 Memory Operation ....................................................... 4 Read Operation ........................................................... 4 Write Operation ........................................................... 4 Page Mode Operation ................................................. 4 Pre-charge Operation .................................................. 4 Software Write Protect ................................................ 4 Software Write-Protect Timing .................................... 7 SRAM Drop-In Replacement ....................................... 8 Maximum Ratings ............................................................. 9 Operating Range ............................................................... 9 DC Electrical Characteristics .......................................... 9 Data Retention and Endurance ....................................... 9 Capacitance .................................................................... 10 Thermal Resistance ........................................................ 10 AC Test Conditions ........................................................ 10 Document Number: 001-86190 Rev. *E AC Switching Characteristics ....................................... 11 SRAM Read Cycle .................................................... 11 SRAM Write Cycle ..................................................... 12 Power Cycle and Sleep Mode Timing ........................... 16 Functional Truth Table ................................................... 17 Ordering Information ...................................................... 18 Ordering Code Definitions ......................................... 18 Package Diagram ............................................................ 19 Acronyms ........................................................................ 20 Document Conventions ................................................. 20 Units of Measure ....................................................... 20 Document History Page ................................................. 21 Sales, Solutions, and Legal Information ...................... 22 Worldwide Sales and Design Support ....................... 22 Products .................................................................... 22 PSoC® Solutions ...................................................... 22 Cypress Developer Community ................................. 22 Technical Support ..................................................... 22 Page 2 of 22 FM22LD16 Pinout Figure 1. 48-ball FBGA pinout (× 16) Top View (not to scale) 1 2 3 4 5 6 LB OE A0 A1 A2 NC A DQ8 UB A3 A4 CE DQ0 B DQ9 DQ10 A5 A6 DQ1 DQ2 C VSS DQ11 A17 A7 DQ3 VDD D VDD DQ12 NC A16 DQ4 VSS E DQ14 DQ13 A14 A15 DQ5 DQ6 F DQ15 NC A12 A13 WE DQ7 G NC A8 A9 A10 A11 NC H Pin Definitions Pin Name I/O Type Description A17–A0 Input Address inputs: The 18 address lines select one of 262,144 words in the F-RAM array. The lowest two address lines A1–A0 may be used for page mode read and write operations. DQ15–DQ0 Input/Output Data I/O Lines: 16-bit bidirectional data bus for accessing the F-RAM array. WE Input Write Enable: A write cycle begins when WE is asserted. The rising edge causes the FM22LD16 to write the data on the DQ bus to the F-RAM array. The falling edge of WE latches a new column address for page mode write cycles. CE Input Chip Enable: The device is selected and a new memory access begins on the falling edge of CE. The entire address is latched internally at this point. Subsequent changes to the A1–A0 address inputs allow page mode operation. OE Input Output Enable: When OE is LOW, the FM22LD16 drives the data bus when the valid read data is available. Deasserting OE HIGH tristates the DQ pins. UB Input Upper Byte Select: Enables DQ15–DQ8 pins during reads and writes. These pins are HI-Z if UB is HIGH. If the user does not perform byte writes and the device is not configured as a 512K × 8, the UB and LB pins may be tied to ground. LB Input Lower Byte Select: Enables DQ7–DQ0 pins during reads and writes. These pins are HI-Z if LB is HIGH. If the user does not perform byte writes and the device is not configured as a 512K × 8, the UB and LB pins may be tied to ground. VSS Ground VDD NC Ground for the device. Must be connected to the ground of the system. Power supply Power supply input to the device. No connect No connect. This pin is not connected to the die. Document Number: 001-86190 Rev. *E Page 3 of 22 FM22LD16 Device Operation The FM22LD16 is a word wide F-RAM memory logically organized as 262,144 × 16 and accessed using an industry-standard parallel interface. All data written to the part is immediately nonvolatile with no delay. The device offers page mode operation, which provides high-speed access to addresses within a page (row). Access to a different page requires that either CE transitions LOW or the upper address (A17–A2) changes. See the Functional Truth Table on page 17 for a complete description of read and write modes. Memory Operation Users access 262,144 memory locations, each with 16 data bits through a parallel interface. The F-RAM array is organized as eight blocks, each having 8192 rows. Each row has four column locations, which allow fast access in page mode operation. When an initial address is latched by the falling edge of CE, subsequent column locations may be accessed without the need to toggle CE. When CE is deasserted HIGH, a pre-charge operation begins. Writes occur immediately at the end of the access with no delay. The WE pin must be toggled for each write operation. The write data is stored in the nonvolatile memory array immediately, which is a feature unique to F-RAM called NoDelay writes. Read Operation A read operation begins on the falling edge of CE. The falling edge of CE causes the address to be latched and starts a memory read cycle if WE is HIGH. Data becomes available on the bus after the access time is met. When the address is latched and the access completed, a new access to a random location (different row) may begin while CE is still LOW. The minimum cycle time for random addresses is tRC. Note that unlike SRAMs, the FM22LD16's CE-initiated access time is faster than the address access time. The FM22LD16 will drive the data bus when OE and at least one of the byte enables (UB, LB) is asserted LOW. The upper data byte is driven when UB is LOW, and the lower data byte is driven when LB is LOW. If OE is asserted after the memory access time is met, the data bus will be driven with valid data. If OE is asserted before completing the memory access, the data bus will not be driven until valid data is available. This feature minimizes supply current in the system by eliminating transients caused by invalid data being driven to the bus. When OE is deasserted HIGH, the data bus will remain in a HI-Z state. Write Operation In the FM22LD16, writes occur in the same interval as reads. The FM22LD16 supports both CE and WE controlled write cycles. In both cases, the address A17–A2 is latched on the falling edge of CE. In a CE-controlled write, the WE signal is asserted before beginning the memory cycle. That is, WE is LOW when CE falls. In this case, the device begins the memory cycle as a write. The FM22LD16 will not drive the data bus regardless of the state of OE as long as WE is LOW. Input data must be valid when CE is Document Number: 001-86190 Rev. *E deasserted HIGH. In a WE-controlled write, the memory cycle begins on the falling edge of CE. The WE signal falls some time later. Therefore, the memory cycle begins as a read. The data bus will be driven if OE is LOW; however, it will be HI-Z when WE is asserted LOW. The CE- and WE-controlled write timing cases are shown in the Figure 11 on page 14. Write access to the array begins on the falling edge of WE after the memory cycle is initiated. The write access terminates on the rising edge of WE or CE, whichever comes first. A valid write operation requires the user to meet the access time specification before deasserting WE or CE. The data setup time indicates the interval during which data cannot change before the end of the write access (rising edge of WE or CE). Unlike other nonvolatile memory technologies, there is no write delay with F-RAM. Because the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory operation occurs in a single bus cycle. Data polling, a technique used with EEPROMs to determine if a write is complete, is unnecessary. Page Mode Operation The F-RAM array is organized as eight blocks, each having 8192 rows. Each row has four column-address locations. Address inputs A1–A0 define the column address to be accessed. An access can start on any column address, and other column locations may be accessed without the need to toggle the CE pin. For fast access reads, after the first data byte is driven to the bus, the column address inputs A1–A0 may be changed to a new value. A new data byte is then driven to the DQ pins no later than tAAP, which is less than half the initial read access time. For fast access writes, the first write pulse defines the first write access. While CE is LOW, a subsequent write pulse along with a new column address provides a page mode write access. Pre-charge Operation The pre-charge operation is an internal condition in which the memory state is prepared for a new access. Pre-charge is user-initiated by driving the CE signal HIGH. It must remain HIGH for at least the minimum pre-charge time, tPC. Pre-charge is also activated by changing the upper addresses, A17–A2. The current row is first closed before accessing the new row. The device automatically detects an upper order address change, which starts a pre-charge operation. The new address is latched and the new read data is valid within the tAA address access time; see Figure 8 on page 13. A similar sequence occurs for write cycles; see Figure 13 on page 14. The rate at which random addresses can be issued is tRC and tWC, respectively. Software Write Protect The 256K × 16 address space is divided into eight sectors (blocks) of 32K × 16 each. Each sector can be individually software write-protected and the settings are nonvolatile. A unique address and command sequence invokes the write-protect mode. To modify write protection, the system host must issue six read commands, three write commands, and a final read command. Page 4 of 22 FM22LD16 The specific sequence of read addresses must be provided to access the write-protect mode. Following the read address sequence, the host must write a data byte that specifies the desired protection state of each sector. For confirmation, the system must then write the complement of the protection byte immediately after the protection byte. Any error that occurs including read addresses in the wrong order, issuing a seventh read address, or failing to complement the protection value will leave the write protection unchanged. The write-protect state machine monitors all addresses, taking no action until this particular read/write sequence occurs. During the address sequence, each read will occur as a valid operation and data from the corresponding addresses will be driven to the data bus. Any address that occurs out of sequence will cause the software protection state machine to start over. After the address sequence is completed, the next operation must be a write cycle. The lower data byte contains the write-protect settings. This value will not be written to the memory array, so the address is a don't-care. Rather it will be held pending the next cycle, which must be a write of the data complement to the protection settings. If the complement is correct, the write-protect settings will be adjusted. Otherwise, the process is aborted and the address sequence starts over. The data value written after the correct six addresses will not be entered into the memory. The protection data byte consists of eight bits, each associated with the write-protect state of a sector. The data byte must be driven to the lower eight bits of the data bus, DQ7–DQ0. Setting a bit to ‘1’ write-protects the corresponding sector; a ‘0’ enables writes for that sector. The following table shows the write-protect sectors with the corresponding bit that controls the write-protect setting. Table 1. Write Protect Sectors - 32K x 16 Blocks The write-protect address sequence follows: 1. Read address 24555h 2. Read address 3AAAAh 3. Read address 02333h 4. Read address 1CCCCh 5. Read address 000FFh 6. Read address 3EF00h 7. Write address 3AAAAh 8. Write address 1CCCCh 9. Write address 0FF00h 10.Read address 00000h Note If CE is LOw entering the sequence, then an address of 00000h must precede 24555h. The address sequence provides a secure way of modifying the protection. The write-protect sequence has a one in 3 × 1032 chance of randomly accessing exactly the first six addresses. The odds are further reduced by requiring three more write cycles, one that requires an exact inversion of the data byte. Figure 2 on page 6 shows a flow chart of the entire write-protect operation. The write-protect settings are nonvolatile. The factory default: all blocks are unprotected. For example, the following sequence write-protects addresses from 18000h to 27FFFh (sectors 3 and 4): Address Data Read 24555h – Read 3AAAAh – Read 02333h – Read 1CCCCh – Read 000FFh – Sectors Blocks Sector 7 3FFFFh–38000h Read 3EF00h – Sector 6 37FFFh–30000h Write 3AAAAh 18h; bits 3 and 4 = 1 Sector 5 2FFFFh–28000h Write 1CCCCh E7h; complement of 18h Sector 4 27FFFh–20000h Write 0FF00h Don’t care Sector 3 1FFFFh–18000h Read 00000h Sector 2 17FFFh–10000h Sector 1 0FFFFh–08000h Sector 0 07FFFh–00000h Document Number: 001-86190 Rev. *E Page 5 of 22 FM22LD16 Figure 2. Write-Protect State Machine Normal Memory Operation Any other operation Write 3AAAAh? n y Read 24555h? Hold Data Byte n Write 1CCCCh? n y Read 1AAAAh to drive write protect settings y n Read 3AAAAh? n Write 1CCCCh? Read 00000h y y n Read 02333h? n Data Complement? y y Read 1CCCCh? n n y Read 000FFh? Write 0FF00h? Read 00000h To enter new y write protect settings n y Read 3EF00h? n y Sequence Detector Document Number: 001-86190 Rev. *E Change Write Protect Settings Read Write Protect Settings Page 6 of 22 FM22LD16 Software Write-Protect Timing Figure 3. Sequence to Set Write-Protect Blocks [1] CE A17-0 24555 3AAAA 02333 1CCCC 000FF 3EF00 3AAAA 1CCCC 0FF00 00000 WE OE DQ 15-0 Data Data Figure 4. Sequence to Read Write-Protect Settings [1] CE A17-0 24555 3AAAA 02333 1CCCC 000FF 3EF00 1CCCC 3AAAA 00000 WE tCE (read access time) OE DQ 15-0 X Data Note 1. This sequence requires tAS > 10 ns and address must be stable while CE is LOW. Document Number: 001-86190 Rev. *E Page 7 of 22 FM22LD16 SRAM Drop-In Replacement The FM22LD16 is designed to be a drop-in replacement for standard asynchronous SRAMs. The device does not require CE to toggle for each new address. CE may remain LOW indefinitely. While CE is LOW, the device automatically detects address changes and a new access begins. This functionality allows CE to be grounded as you might with an SRAM. It also allows page mode operation at speeds up to 40 MHz. the current drawn when WE is LOW is not an issue. A 10-k resistor draws 330 µA when WE is LOW and VDD = 3.3 V. Figure 6. Use of Pull-up Resistor on WE VDD FM22LD16 CE Figure 5 shows a pull-up resistor on CE, which will keep the pin HIGH during power cycles, assuming the MCU / MPU pin tristates during the reset condition. The pull-up resistor value should be chosen to ensure the CE pin tracks VDD to a high enough value, so that the current drawn when CE is LOW is not an issue. A 10-k resistor draws 330 µA when CE is LOW and VDD = 3.3 V WE OE MCU / MPU A17-0 DQ15-0 Figure 5. Use of Pull-up Resistor on CE VDD FM22LD16 CE WE MCU / MPU OE A 17-0 DQ 15-0 Note that if CE is tied to ground, the user must be sure WE is not LOW at power-up or power-down events. If CE and WE are both LOW during power cycles, data will be corrupted. Figure 6 shows a pull-up resistor on WE, which will keep the pin HIGH during power cycles, assuming the MCU / MPU pin tristates during the reset condition.The pull-up resistor value should be chosen to ensure the WE pin tracks VDD to a high enough value, so that Note If CE is tied to ground, the user gives up the ability to perform the software write-protect sequence. For applications that require the lowest power consumption, the CE signal should be active (LOW) only during memory accesses. The FM22LD16 draws supply current while CE is LOW, even if addresses and control signals are static. While CE is HIGH, the device draws no more than the maximum standby current, ISB. CE toggling LOW on every address access is perfectly acceptable in FM22LD16. The UB and LB byte select pins are active for both read and write cycles. They may be used to allow the device to be wired as a 512K × 8 memory. The upper and lower data bytes can be tied together and controlled with the byte selects. Individual byte enables or the next higher address line A18 may be available from the system processor. Figure 7. FM22LD16 Wired as 512K x 8 CE WE OE A 18 A 17-0 Document Number: 001-86190 Rev. *E UB LB A 17-0 4-Mbit F-RAM FM22LD16 DQ 15-8 D DQ 7-0 7-0 Page 8 of 22 FM22LD16 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –55 C to +125 C Maximum accumulated storage time At 125 °C ambient temperature ................................. 1000 h At 85 °C ambient temperature ................................ 10 Years Ambient temperature with power applied ................................... –55 °C to +125 °C Supply voltage on VDD relative to VSS ........–1.0 V to + 4.5 V Voltage applied to outputs in High Z state .................................... –0.5 V to VDD + 0.5 V Input voltage .......... –1.0 V to + 4.5 V and VIN < VDD + 1.0 V Transient voltage (< 20 ns) on any pin to ground potential ................. –2.0 V to VCC + 2.0 V Package power dissipation capability (TA = 25 °C) ................................................. 1.0 W Surface mount Pb soldering temperature (3 seconds) ......................................... +260 C DC output current (1 output at a time, 1s duration) .... 15 mA Static discharge voltage Human Body Model (JEDEC Std JESD22-A114-D) ........ 2.5 kV Charged Device Model (JEDEC Std JESD22-C101-C) ... 1.5 kV Machine Model (JEDEC Std JESD22-A115-A) ................. 150 V Latch-up current ................................................... > 100 mA Operating Range Range Industrial Ambient Temperature (TA) VDD –40 C to +85 C 2.7 V to 3.6 V DC Electrical Characteristics Over the Operating Range Parameter Description Min Typ [2] Max Unit 2.7 3.3 3.6 V – 8 12 mA TA = 25 C – 90 150 µA TA = 85 C – – 270 µA Test Conditions VDD Power supply voltage IDD VDD supply current VDD = 3.6 V, CE cycling at min. cycle time. All inputs toggling at CMOS levels (0.2 V or VDD – 0.2 V), all DQ pins unloaded. ISB Standby current VDD = 3.6 V, CE at VDD, All other pins are static and at CMOS levels (0.2 V or VDD – 0.2 V) ILI Input leakage current VIN between VDD and VSS – – +1 µA ILO Output leakage current VOUT between VDD and VSS – – +1 µA VIH Input HIGH voltage 2.2 – VDD + 0.3 V VIL Input LOW voltage – 0.3 – 0.6 V VOH1 Output HIGH voltage IOH = –1.0 mA 2.4 – – V VOH2 Output HIGH voltage IOH = –100 µA VDD – 0.2 – – V VOL1 Output LOW voltage IOL = 2.1 mA – – 0.4 V VOL2 Output LOW voltage IOL = 100 µA – – 0.2 V Data Retention and Endurance Parameter TDR NVC Description Data retention Endurance Test condition Min Max Unit TA = 85 C 10 – Years TA = 75 C 38 – TA = 65 C 151 – Over operating temperature 1014 – Cycles Note 2. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested. Document Number: 001-86190 Rev. *E Page 9 of 22 FM22LD16 Capacitance Parameter Description CI/O Input/Output capacitance (DQ) CIN Input capacitance Test Conditions Max Unit 8 pF 6 pF Test Conditions 48-ball FBGA Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 41 C/W 10 C/W TA = 25 C, f = 1 MHz, VDD = VDD(Typ) Thermal Resistance Parameter Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) AC Test Conditions Input pulse levels ...................................................0 V to 3 V Input rise and fall times (10%–90%) ........................... < 3 ns Input and output timing reference levels ....................... 1.5 V Output load capacitance ............................................... 30 pF Document Number: 001-86190 Rev. *E Page 10 of 22 FM22LD16 AC Switching Characteristics Over the Operating Range Parameters [3] Cypress Parameter Description Alt Parameter Min Max Unit – 55 ns 110 – ns SRAM Read Cycle tCE tACE Chip enable access time tRC – Read cycle time tAA – Address access time – 110 ns tOH tOHA Output hold time 20 – ns tAAP – Page mode address access time – 25 ns tOHP – Page mode output hold time 5 – ns tCA – Chip enable active time 55 – ns tPC – Pre-charge time 55 – ns tBA tBW UB, LB access time – 20 ns tAS tSA Address setup time (to CE LOW) 0 – ns tAH tHA Address hold time (CE Controlled) 55 – ns tOE tDOE Output enable access time – 15 ns tHZ[4, 5] tHZCE Chip Enable to output HI-Z – 10 ns tOHZ[4, 5] tHZOE Output enable HIGH to output HI-Z – 10 ns tBHZ[4, 5] tHZBE UB, LB HIGHHIGH to output HI-Z – 10 ns Notes 3. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 0 to 3 V, output loading of the specified IOL/IOH and load capacitance shown in AC Test Conditions on page 10. 4. tHZ, tOHZ and tBHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state. 5. This parameter is characterized but not 100% tested. Document Number: 001-86190 Rev. *E Page 11 of 22 FM22LD16 AC Switching Characteristics (continued) Over the Operating Range Parameters [3] Cypress Parameter Description Alt Parameter Min Max Unit SRAM Write Cycle tWC tWC Write cycle time 110 – ns tCA – Chip enable active time 55 – ns tCW tSCE Chip enable to write enable HIGH 55 – ns tPC – Pre-charge time 55 – ns tPWC – Page mode write enable cycle time 25 – ns tWP tPWE Write enable pulse width 16 – ns tAS tSA Address setup time (to CE LOW) 0 – ns tASP – Page mode address setup time (to WE LOW) 8 – ns tAHP – Page mode address hold time (to WE LOW) 15 – ns tWLC tPWE Write enable LOW to chip disabled 25 – ns tBLC tBW UB, LB LOW to chip disabled 25 – ns tWLA – Write enable LOW to A17-2 change 25 – ns tAWH – A17-2 change to write enable HIGH 110 – ns tBS UB, LB setup time (to CE LOW) 2 – ns tBH UB, LB hold time (to CE HIGH) 0 – ns tSD Data input setup time 14 – ns tHD Data input hold time 0 – ns tHZWE Write enable LOW to output HI-Z – 10 ns tWX[7] – Write enable HIGH to output driven 10 – ns tWS[8] – Write enable to CE LOW setup time 0 – ns [8] – Write enable to CE HIGH hold time 0 – ns tDS tDH tWZ [6, 7] tWH Notes 6. tWZ is specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state. 7. This parameter is characterized but not 100% tested. 8. The relationship between CE and WE determines if a CE- or WE-controlled write occurs. The parameters tWS and tWH are not tested. Document Number: 001-86190 Rev. *E Page 12 of 22 FM22LD16 Figure 8. Read Cycle Timing 1 (CE LOW, OE LOW) tRC tRC A17-0 tOH tAA tAA tOH Previous Data DQ 15-0 Valid Data Valid Data Figure 9. Read Cycle Timing 2 (CE Controlled) tCA tPC CE tAH tAS A 17-0 tOE OE tHZ tCE tOHZ tOH DQ 15-0 tBA tBHZ UB / LB Figure 10. Page Mode Read Cycle Timing [9] tPC tCA CE tAS A 17-2 Col 0 A1-0 Col 1 tAAP tOE OE tHZ tOHZ tOHP tCE DQ15-0 Col 2 Data 0 Data 1 Data 2 Note 9. Although sequential column addressing is shown, it is not required Document Number: 001-86190 Rev. *E Page 13 of 22 FM22LD16 Figure 11. Write Cycle Timing 1 (WE Controlled) [10] tCA tPC tCW CE tAS tWLC A17-0 tWP tWX WE tDH DQ15-0 tHZ tDS tWZ D out D out D in tBS tBH UB, LB Figure 12. Write Cycle Timing 2 (CE Controlled) tCA tPC CE tBLC tAS A17-0 WE tDH tDS DQ 15-0 D in UB/LB Figure 13. Write Cycle Timing 3 (CE LOW) [10] tWC tAWH A17-0 tWLA tWX WE tWZ tDS DQ15-0 D out D in tDH D out D in Note 10. OE (not shown) is LOW only to show the effect of WE on DQ pins. Document Number: 001-86190 Rev. *E Page 14 of 22 FM22LD16 Figure 14. Page Mode Write Cycle Timing tCA tPC tCW CE tWLC tAS A17-2 tAHP A 1-0 Col 0 tASP Col 1 Col 2 tPWC tWP WE OE tDH tDS DQ15-0 Data 0 Data 1 Data 2 Note 11. UB and LB to show byte enable and byte masking cases. Document Number: 001-86190 Rev. *E Page 15 of 22 FM22LD16 Power Cycle and Sleep Mode Timing Over the Operating Range Parameter tPU Min Max Unit 450 – µs Last write (WE HIGH) to power down time 0 – µs VDD power-up ramp rate 50 – µs/V VDD power-down ramp rate 100 – µs/V Power-up (after VDD min. is reached) to first access time tPD tVR Description [12, 13] tVF[12, 13] Figure 15. Power Cycle and Sleep Mode Timing VDD VDD min VDD min t VR t VF t PU t PD Access Allowed Note 12. Slope measured at any point on the VDD waveform. 13. Cypress cannot test or characterize all VDD power ramp profiles. The behavior of the internal circuits is difficult to predict when VDD is below the level of a transistor threshold voltage. Cypress strongly recommends that VDD power up faster than 100 ms through the range of 0.4 V to 1.0 V. Document Number: 001-86190 Rev. *E Page 16 of 22 FM22LD16 Functional Truth Table Operation [14, 15] CE WE A17-2 A1-0 H X X X Standby/Idle ↓ H H V V V V Read L L H No Change Change L H Change V Random Read ↓ V V V V CE-Controlled Write[15] L L L L ↓ V V WE-Controlled Write [15, 16] L ↓ No Change V Page Mode Write [17] ↑ X X X X X X Starts pre-charge L Page Mode Read Notes 14. H = Logic HIGH, L = Logic LOW, V = Valid Data, X = Don't Care, ↓ = toggle LOW, ↑ = toggle HIGH. 15. For write cycles, data-in is latched on the rising edge of CE or WE, whichever comes first. 16. WE-controlled write cycle begins as a Read cycle and then A17-2 is latched. 17. Addresses A1-0 must remain stable for at least 10 ns during page mode operation. 18. The UB and LB pins may be grounded if 1) the system does not perform byte writes and 2) the device is not configured as a 512 K x 8. Document Number: 001-86190 Rev. *E Page 17 of 22 FM22LD16 Ordering Information Access time (ns) 55 Ordering Code FM22LD16-55-BG Package Diagram Package Type Operating Range 001-91158 48-ball FBGA Industrial FM22LD16-55-BGTR All the above parts are Pb-free. Ordering Code Definitions FM 22 LD 16 - 55 - BG TR Option: blank = Standard; TR = Tape and Reel Package Type: BG = 48-ball FBGA Access Time: 55 ns I/O Width: × 16 Voltage: 2.7 V to 3.6 V 4-Mbit Parallel F-RAM Cypress Document Number: 001-86190 Rev. *E Page 18 of 22 FM22LD16 Package Diagram Figure 16. 48-ball FBGA (6 mm × 8 mm × 1.2 mm) Package Outline, 001-91158 001-91158 ** Document Number: 001-86190 Rev. *E Page 19 of 22 FM22LD16 Acronyms Acronym CPU Document Conventions Description Units of Measure Central Processing Unit Symbol Unit of Measure CMOS Complementary Metal Oxide Semiconductor °C EIA Electronic Industries Alliance Hz hertz F-RAM Ferroelectric Random Access Memory kHz kilohertz I/O Input/Output k kilohm MCU Microcontroller Unit MHz megahertz MPU Microprocessor Unit A microampere RoHS Restriction of Hazardous Substances F microfarad R/W Read and Write s microsecond SRAM Static Random Access Memory mA milliampere ms millisecond TSOP Thin Small Outline Package M megaohm ns nanosecond ohm % percent pF picofarad V volt W watt Document Number: 001-86190 Rev. *E degree Celsius Page 20 of 22 FM22LD16 Document History Page Document Title: FM22LD16, 4-Mbit (256K × 16) F-RAM Memory Document Number: 001-86190 Rev. ECN No. Orig. of Change Submission Date Description of Change ** 3912933 GVCH 02/25/2013 New spec *A 4191807 GVCH 11/14/2013 Added watermark as “Not recommended for new designs.” *B 4274811 GVCH 03/11/2014 Converted to Cypress standard format Removed watermark as “Not recommended for new designs.” Updated Maximum Ratings table - Removed Moisture Sensitivity Level (MSL) - Added junction temperature and latch up current Updated Data Retention and Endurance table Added Thermal Resistance table Removed Package Marking Scheme (top mark) *C 4566147 GVCH 11/10/2014 Added related documentation hyperlink in page 1. *D 4879990 ZSK / PSR 08/11/2015 Updated Maximum Ratings: Removed “Maximum junction temperature”. Added “Maximum accumulated storage time”. Added “Ambient temperature with power applied”. Updated to new template. *E 5110110 01/27/2016 Updated Maximum Ratings: Changed value of “Latch-up current” from “> 140 mA” to “> 100 mA”. Completing Sunset Review. GVCH Document Number: 001-86190 Rev. *E Page 21 of 22 FM22LD16 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support © Cypress Semiconductor Corporation, 2013-2016. The information contained herein is subject to change without notice. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-86190 Rev. *E Revised January 27, 2016 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 22 of 22