CY7C65632, CY7C65634 HX2VL Very Low Power USB 2.0 Hub Controller Datasheet.pdf

CY7C65632, CY7C65634
HX2VL™ Very Low Power USB 2.0
Hub Controller
HX2VL™ Very Low Power USB 2.0 Hub Controller
Features
Integrated port status indicator control
12 MHz +/– 500 ppm external crystal with drive level 600 µW
(integrated PLL) clock input with optional 27/48 MHz
oscillator clock input
❐ Internal power failure detection for ESD recovery
❐
■
High performance, low-power USB 2.0 Hub, optimized for low
cost designs with minimum Bill-of-material
■
USB 2.0 hub controller
❐ Compliant with USB 2.0 specification
❐ Up to four downstream ports support
❐ Downstream ports are backward compatible with FS, LS
❐ Single transaction translator (TT) for low cost
■
Very low power consumption
❐ Supports bus-powered and self-powered modes
❐ Auto switching between bus-powered and self-powered
❐ Single MCU with 2K ROM and 64 byte RAM
❐ Lowest power consumption
■
Highly integrated solution for reduced BOM cost
❐ Internal regulator – single power supply 5 V required
❐ Provision of connecting 3.3 V with external regulator
❐ Integrated upstream pull-up resistor
❐ Integrated pull-down resistors for all downstream ports
❐ Integrated upstream/downstream termination resistors
❐
■
Downstream port management
❐ Support individual and ganged mode power management
❐ Overcurrent detection
❐ Two port status indicators per downstream port
❐ Slew rate control for EMI management
■
Maximum configurability
❐ VID and PID are configurable through external EEPROM
❐ Number of ports, removable/non-removable ports are
configurable through EEPROM and I/O pin configuration
❐ I/O pins can configure gang/individual mode power
switching, reference clock source and polarity of power
switch enable pin
❐ Configuration options also available through mask ROM
■
Available in space saving 48-pin (7 × 7 mm) TQFP and 28-pin
(5 × 5 mm) QFN packages
■
Supports 0 °C to 70 °C temperature range
Block Diagram – CY7C6563X
D+
12/27/48
MHz
OSC-in
OR 12
MHz
Crystal
I2C /
SPI
MCU
D-
RAM
USB 2.0 PHY
Serial
Interface
Engine
PLL
ROM
HS USB
Control Logic
USB Upstream Port
5V i/p (for internal regulator)
NC (for external regulator)
Transaction Translator
1.8V
Regulator
Hub Repeater
3.3V
3.3V i/p (with ext. reg. & 28 QFN)
NC (with ext. reg. & 48 TQFP)
3.3V o/p (for int. reg.)
Routing Logic
USB Downstream Port 3
USB Downstream Port 4
USB 2.0
PHY
USB 2.0
PHY
USB 2.0
PHY
Cypress Semiconductor Corporation
Document Number: 001-67568 Rev. *H
•
D+ D-
198 Champion Court
LED
D+ D-
•
Port
Control
O V R # [4]
LED
Port
Control
O V R # [3]
D+ D-
O V R # [2]
LED
Port
Control
P W R # [2]
O V R # [1]
P W R # [1]
D+ D-
Port
Control
P W R # [4]
USB Downstream Port 2
USB 2.0
PHY
P W R # [3]
USB Downstream Port 1
For two port version, USB Downstream
ports 3 and 4 are to be No connect from
the Chip I/O perspective.
LED
San Jose, CA 95134-1709
•
408-943-2600
Revised February 17, 2015
CY7C65632, CY7C65634
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right HX2VL device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
http://www.cypress.com/?id=2411.
■
■
■
Overview: USB Portfolio, USB Roadmap
USB 2.0 Hub Controller Selectors: HX2LP, HX2VL
Application notes: Cypress offers a large number of USB application notes covering a broad range of topics, from basic to
advanced level. Recommended application notes for getting
started with HX2VL are:
❐ AN15454 - Bus-Powered USB Hub Design Using EZ-USB
HX2LP™/HX2VL
❐ AN72332 - Guidelines on System Design using Cypress's
USB 2.0 Hub (HX2VL)
❐ AN69235 - Migrating from HX2/HX2LP to HX2VL
■
Reference Designs:
❐ CY4608 HX2VL Very Low-Power USB 2.0 Compliant 4-Port
Hub Development Kit
❐ CY4607 HX2VL Very Low-Power USB 2.0 Compliant 4-Port
Hub Development Kit
■
Models: HX2VL (CY7C65632/34/42) - IBIS
HX2VL Development Kit
HX2VL Development Kit board is a tool to demonstrate the features of HX2VL devices (CY7C65632, CY7C65634). In the initial phase
of the design, this board helps developers to understand the chip features and limitations before proceeding with a complete design.
The Development kit includes support documents related to board hardware, PC application software, and EEPROM configuration
data (.iic) files.
Document Number: 001-67568 Rev. *H
Page 2 of 28
CY7C65632, CY7C65634
Contents
Introduction ....................................................................... 4
HX2VL Architecture .......................................................... 4
USB Serial Interface Engine ........................................ 4
HS USB Control Logic ................................................. 4
Hub Repeater .............................................................. 4
MCU ............................................................................ 4
Transaction Translator ................................................ 4
Port Control ................................................................. 4
Applications ...................................................................... 4
Functional Overview ........................................................ 5
System Initialization ..................................................... 5
Enumeration ................................................................ 5
Upstream Port ............................................................. 5
Downstream Ports ....................................................... 5
Power Switching .......................................................... 5
Overcurrent Detection ................................................. 5
Port Indicators ............................................................. 5
Power Regulator .......................................................... 6
External Regulation Scheme ....................................... 6
Internal Regulation Scheme ........................................ 6
Pin Configurations ........................................................... 7
Pin Definitions ................................................................ 11
Pin Definitions ................................................................ 13
EEPROM Configuration Options ................................... 15
Pin Configuration Options ............................................. 16
Power ON Reset ....................................................... 16
Gang/Individual Power Switching Mode .................... 16
Power Switch Enable Pin Polarity ............................. 16
Document Number: 001-67568 Rev. *H
Port Number Configuration ........................................ 16
Non Removable Ports Configuration ......................... 16
Reference Clock Configuration ................................. 17
Absolute Maximum Ratings .......................................... 18
Operating Conditions ..................................................... 18
Electrical Characteristics ............................................... 18
DC Electrical Characteristics ..................................... 18
AC Electrical Characteristics ..................................... 20
Thermal Resistance ........................................................ 20
Ordering Information ...................................................... 21
Ordering Code Definitions ......................................... 21
Package Diagrams .......................................................... 22
Acronyms ........................................................................ 24
Document Conventions ................................................. 24
Units of Measure ....................................................... 24
Silicon Errata for the HX2VL, CY7C65632 Product
Family .............................................................................. 25
Part Numbers Affected .............................................. 25
HX2VL Qualification Status ....................................... 25
HX2VL Errata Summary ............................................ 25
Document History Page ................................................. 26
Sales, Solutions, and Legal Information ...................... 28
Worldwide Sales and Design Support ....................... 28
Products .................................................................... 28
PSoC® Solutions ....................................................... 28
Cypress Developer Community ................................. 28
Technical Support ..................................................... 28
Page 3 of 28
CY7C65632, CY7C65634
Introduction
MCU
HX2VL™ is Cypress’s next generation family of high
performance, very low power USB 2.0 hub controllers. HX2VL
has integrated upstream and downstream transceivers; a USB
Serial Interface Engine (SIE); USB Hub Control and Repeater
logic; and Transaction Translator (TT) logic. Cypress has also
integrated external components such as voltage regulator and
pull-up/pull-down resistors, reducing the overall bill of materials
required to implement a USB hub system.
HX2VL has MCU with 2K ROM and 64 byte RAM. The MCU
operates with a 12 MHz clock to decode USB commands from
host and respond to the host. It can also handle GPIO settings
to provide higher flexibility to the customers and control the read
interface to the EEPROM which has extended configuration
options. The MCU is programmable while manufacturing in the
factory as per customer needs.
The CY7C6563X is a part of the HX2VL portfolio. This device
option is for ultra low power but high performance applications
that require up to four downstream ports. All downstream ports
share a single transaction translator. The CY7C6563X is
available in 48-pin TQFP and 28-pin QFN package options.
All device options are supported by Cypress’s world class
reference design kits, which include board schematics, bill of
materials, Gerber files, Orcad files, and thorough design
documentation.
HX2VL Architecture
The Block Diagram – CY7C6563X on page 1 shows the HX2VL
single TT hub architecture.
USB Serial Interface Engine
The Serial Interface Engine (SIE) allows HX2VL to communicate
with the USB host. The SIE handles the following USB activities
independently of the Hub Control Block.
■
Bit stuffing and unstuffing
■
Checksum generation and checking
■
TOKEN type identification
■
Address checking
HS USB Control Logic
‘Hub Control’ block co-ordinates enumeration, suspend and
resume. It generates status and control signals for host access
to the hub. It also includes the frame timer that synchronizes the
hub to the host. It has status/control registers which function as
the interface to the firmware in the MCU.
Hub Repeater
The Hub Repeater manages the connectivity between upstream
and downstream facing ports that are operating at the same
speed. It supports full and high speed connectivity. According to
the USB 2.0 specification, the HUB Repeater provides the
following functions:
■
Sets up and tears down connectivity on packet boundaries
■
Ensures orderly entry into and out of ‘Suspend’ state, including
proper handling of remote wakeups.
Document Number: 001-67568 Rev. *H
Transaction Translator
The Transaction Translator translates data from one speed to
another. A TT takes high speed split transactions and translates
them to full or low speed transactions when the hub is operating
at high speed (the upstream port is connected to a high speed
host controller) and has full or low speed devices attached. The
operating speed of a device attached on a downstream port
determines whether the routing logic connects a port to the TT
or to hub repeater. When the upstream host and downstream
device are functioning at different speeds, the data is routed
through the TT. In all other cases, the data is routed through the
repeater. For example, If a full or low speed device is connected
to the high speed host upstream through the hub, then the data
transfer route includes TT. If a high speed device is connected to
the high speed host upstream through the hub, the transfer route
includes the repeater. When the hub is connected to a full speed
host controller upstream, then high speed peripheral does not
operate at its full capability. These devices only work at full
speed. Full and low speed devices connected to this hub operate
at their normal speed.
Port Control
The downstream ‘Port Control’ block handles the
connect/disconnect and over current detection as well as the
power enable and LED control. It also generates the control
signals for the downstream transceivers.
Applications
Typical applications for the HX2VL device family are:
■
Docking stations
■
Standalone hubs
■
Monitor hubs
■
Multi-function printers
■
Digital televisions
■
Advanced port replicators
■
Keyboard hubs
■
Gaming consoles
Page 4 of 28
CY7C65632, CY7C65634
Functional Overview
The Cypress CY7C6563X USB 2.0 Hubs are low power hub
solutions for USB which provide maximum transfer efficiency.
The CY7C6563X USB 2.0 Hubs integrate 1.5 kohm upstream
pull-up resistors for full speed operation and all downstream
15 kohm pull-down resistors and series termination resistors on
all upstream and downstream D+ and D– pins. This results in
optimization of system costs by providing built-in support for the
USB 2.0 specification.
System Initialization
On power up, CY7C6563X has an option to enumerate from the
default settings in the mask ROM or from reading an external
EEPROM for configuration information. At the most basic level,
this EEPROM has the Vendor ID (VID) and the Product ID (PID),
for the customer’s application. For more specialized
applications, other configuration options can be specified. See
EEPROM Configuration Options on page 15 for more details.
CY7C6563X verifies the checksum before loading the EEPROM
contents as the descriptors.
Enumeration
CY7C6563X enables the pull-up resistor on D+ to indicate its
presence to the upstream hub, after which a USB Bus Reset is
expected. After a USB Bus Reset, CY7C6563X is in an
unaddressed, unconfigured state (configuration value set to ’0’).
During the enumeration process, the host sets the hub's address
and configuration. After the hub is configured, the full hub
functionality is available.
Upstream Port
The upstream port includes the transmitter and the receiver state
machine. The transmitter and receiver operate in high speed and
full speed depending on the current hub configuration. The
transmitter state machine monitors the upstream facing port
while the Hub Repeater has connectivity in the upstream
direction. This machine prevents babble and disconnect events
on the downstream facing ports of this hub from propagating and
causing the hub to be disabled or disconnected by the hub to
which it is attached.
Downstream Ports
The CY7C6563X supports a maximum of four downstream ports,
each of which may be marked as usable or removable in the
EEPROM configuration, see EEPROM Configuration Options on
page 15. Additionallyit can also be configured by pin strapping,
see Pin Configuration Options on page 16.
Downstream D+ and D– pull-down resistors are incorporated in
CY7C6563X for each port. Before the hubs are configured, the
ports are driven SE0 (Single Ended Zero, where both D+ and D–
are driven low) and are set to the unpowered state. When the
hub is configured, the ports are not driven and the host may
power the ports by sending a SetPortPower command for each
port. After a port is powered, any connect or disconnect event is
detected by the hub. Any change in the port state is reported by
the hubs back to the host through the Status Change Endpoint
(endpoint 1).
Document Number: 001-67568 Rev. *H
On receipt of SetPortReset request for a port with a device
connected, the hub does as follows:
■
Performs a USB Reset on the corresponding port
■
Puts the port in an enabled state
■
Enables babble detection after the port is enabled.
Babble consists of a non idle condition on the port after EOF2. If
babble is detected on an enabled port, that port is disabled. A
ClearPortEnable request from the host also disables the
specified port.
Downstream ports can be individually suspended by the host
with the SetPortSuspend request. If the hub is not suspended, a
remote wakeup event on that port is reflected to the host through
a port change indication in the Hub Status Change Endpoint. If
the hub is suspended, a remote wakeup event on this port is
forwarded to the host. The host may resume the port by sending
a ClearPortSuspend command.
Power Switching
The CY7C6563X includes interface signals for external port
power switches. Both ganged and individual (per-port)
configurations are supported by pin strapping, see Pin
Configuration Options on page 16.
After enumerating, the host may power each port by sending a
SetPortPower request for that port. Power switching and
overcurrent detection are managed using respective control
signals (PWR#[n] and OVR#[n]) which are connected to an
external power switch device. Both High/Low enabled power
switches are supported and the polarity is configured through
GPIO setting, see Pin Configuration Options on page 16.
Overcurrent Detection
The OVR#[n] pins of the CY7C6563X series are connected to
the respective external power switch's port overcurrent
indication (output) signals. After detecting an overcurrent
condition, hub reports overcurrent condition to the host and
disables the PWR#[n] output to the external power device.
OVR#[n] has a setup time of 20 ns. It takes 3 to 4 ms from
overcurrent detection to de-assertion of PWR#[n]
Port Indicators
The USB 2.0 port indicators are also supported directly by
CY7C6563X. According to the specification, each downstream
port of the hub optionally supports a status indicator. The
presence of indicators for downstream facing ports is specified
by bit 7 of the wHub Characteristics field of the hub class
descriptor. The default CY7C6563X descriptor specifies that the
port indicators are supported. The CY7C6563X port indicators
has two modes of operation: automatic and manual.
On power up the CY7C6563X defaults to automatic mode, where
the color of the Port Indicator (green, amber, off) indicates the
functional status of the CY7C6563X port. The LEDs are turned
off when the device is suspended.
Page 5 of 28
CY7C65632, CY7C65634
Figure 2. External Regulation Scheme
Figure 1. Port Status Indicator LED
5V to 3.3V
Regulator
PORT STATUS
INDICATOR
5V to 3.3V
Regulator
LED
VCC
VREG
Power Regulator
CY7C6563X requires 3.3 V source power for normal operation
of internal core logic and USB physical layer (PHY). The
integrated low-drop power regulator converts 5 V power input
from USB cable (Vbus) to 3.3 V source power. The 3.3 V power
output is guaranteed by an internal voltage reference circuit
when the input voltage is within the 4.75 V to 5.25 V range. The
regulator’s maximum current loading is 150 mA, which provides
tolerance margin over CY7C6563X’s normal power consumption
of below 100 mA. The on chip regulator has a quiescent current
of 28 µA.
External Regulation Scheme
CY7C6563X supports both external regulation and internal
regulation schemes. When an external regulation is chosen,
then for the 48 Pin package, VCC and VREG are to be left open
with no connection. The external regulator output 3.3 V has to be
connected to VCC_A and VCC_D pins. This connection has to
be done externally, on board. For the 28-pin package, the 3.3 V
output from the external regulator has to be connected to VREG,
VCC_A and VCC_D. The VCC pin has to be left open with no
connection. From the external input 3.3 V, 1.8 V is internally
generated for the chip’s internal usage.
NC
NC
NC
VREG
CY7C65632
48 Pin
CY7C65632
28 Pin
VCC_D
VCC_A
VCC
VCC_A
VCC_D
External Regulation Scheme
Internal Regulation Scheme
When the built-in internal regulator is chosen, then the VCC pin
has to be connected to a 5 V, in both 48-pin and 28-pin packages.
Internally, the built-in regulator generates a 3.3 V and 1.8 V for
the chip’s internal usage. Also a 3.3 V output is available at
VREG pin, that has to be connected externally to VCC_A and
VCC_D.
Figure 3. Internal Regulation Scheme
5V
3.3V
VCC
VREG
CY7C65632
48 Pin
VCC_A
3.3V
5V
VREG
VCC
CY7C65632
28 Pin
VCC_D
VCC_A
VCC_D
Internal Regulation Scheme
Document Number: 001-67568 Rev. *H
Page 6 of 28
CY7C65632, CY7C65634
Pin Configurations
Figure 4. 48-pin TQFP (7 × 7 × 1.4 mm) pinout
VREG
VCC
AMBER[1] /
SPI_CS
GREEN[1] / SPI_SK /
FIXED_PORT1
SEL27
PWR#[1] /
I2C_SDA
OVR#[1]
PWR#[2]
OVR#[2]
GANG
VCC_D
SELFPWR
48
47
46
45
44
43
42
41
40
39
38
37
VCC_A
1
36
AMBER[2] / SPI_MOSI /
PWR_PIN_POL
GND
2
35
GREEN[2] /
SPI_MISO / FIXED_PORT2
D-
3
34
VCC_D
D+
4
33
AMBER[3] /
SET_PORT_NUM2
DD-[1]
5
32
GREEN[3] /
FIXED_PORT3
DD+[1]
6
31
PWR#[3]
VCC_A
7
30
OVR#[3]
GND
8
29
PWR#[4]
DD-[2]
9
28
OVR#[4]
DD+[2]
10
27
TEST / SCL
RREF
11
26
RESET#
VCC_A
12
25
SEL48
CY7C65632
48-pin TQFP
13
14
15
16
17
18
19
20
21
22
23
24
GND
XIN
XOUT
VCC_A
DD-[3]
DD+[3]
VCC_A
GND
DD-[4]
DD+[4]
GREEN[4] /
FIXED_PORT4
AMBER[4] /
SET_PORT_NUM1
Document Number: 001-67568 Rev. *H
Page 7 of 28
CY7C65632, CY7C65634
Pin Configurations (continued)
Figure 5. 48-pin TQFP (7 × 7 × 1.4 mm) pinout
VREG
VCC
AMBER[1] /
SPI_CS
GREEN[1] / SPI_SK /
FIXED_PORT1
SEL27
PWR#[1] /
I2C_SDA
OVR#[1]
PWR#[2]
OVR#[2]
GANG
VCC_D
SELFPWR
48
47
46
45
44
43
42
41
40
39
38
37
Two Port
VCC_A
1
36
AMBER[2] / SPI_MOSI /
PWR_PIN_POL
GND
2
35
GREEN[2] /
SPI_MISO/ FIXED_PORT2
D-
3
34
VCC_D
D+
4
33
NC
DD-[1]
5
32
NC
DD+[1]
6
31
NC
VCC_A
7
30
NC
GND
8
29
NC
DD-[2]
9
28
NC
DD+[2]
10
27
TEST / SCL
RREF
11
26
RESET#
VCC_A
12
25
SEL48
CY7C65634
48-pin TQFP
13
14
15
16
17
18
19
20
21
22
23
24
GND
XIN
XOUT
VCC_A
NC
NC
NC
GND
NC
NC
NC
NC
Document Number: 001-67568 Rev. *H
Page 8 of 28
CY7C65632, CY7C65634
Pin Configurations (continued)
Figure 6. 28-pin QFN (5 × 5 × 0.8 mm) pinout
VREG
VCC
PWR#/
I2C_SDA
OVR # [1]
OVR # [2]
GANG
SELFPWR
28
27
26
25
24
23
22
1
21
VCC_ D
D+
2
20
OVR # [3]
DD - [1]
3
19
OVR # [4]
DD + [1]
4
18
TEST/
I2C_SCL
VCC_ A
5
17
RESET#
DD - [2]
6
16
DD + [4]
DD + [2]
7
15
DD - [4]
CY7C65632
28-pin QFN
8
9
10
11
12
13
14
RREF
VCC_ A
XIN
XOUT
DD - [3]
DD + [3]
VCC_ A
Document Number: 001-67568 Rev. *H
-
D-
Page 9 of 28
CY7C65632, CY7C65634
Pin Configurations (continued)
Figure 7. 28-pin QFN (5 × 5 × 0.8 mm) pinout
VREG
VCC
PWR#/
I2C_SDA
OVR # [1]
OVR # [2]
GANG
SELFPWR
28
27
26
25
24
23
22
Two Port
1
21
D+
2
20
NC
DD - [1]
3
19
NC
DD + [1]
4
18
TEST/
I2C_SCL
VCC_ A
5
17
RESET#
DD - [2]
6
16
NC
DD + [2]
7
15
NC
CY7C65634
28-pin QFN
8
9
10
11
12
13
14
RREF
VCC_ A
XIN
XOUT
NC
NC
VCC_ A
Document Number: 001-67568 Rev. *H
-
D-
VCC_ D
Page 10 of 28
CY7C65632, CY7C65634
Pin Definitions
48-pin TQFP Package
Name
Power and Clock
VCC_A
VCC_A
VCC_A
VCC_A
VCC_A
VCC_D
VCC_D
VCC
Pin No.
Type [1]
1
7
12
16
19
34
38
47
P
P
P
P
P
P
P
P
VCC_A. 3.3 V analog power to the chip.
VCC_A. 3.3 V analog power to the chip.
VCC_A. 3.3 V analog power to the chip.
VCC_A. 3.3 V analog power to the chip.
VCC_A. 3.3 V analog power to the chip. NC in CY7C65634.
VCC_D. 3.3 V digital power to the chip.
VCC_D. 3.3 V digital power to the chip.
VCC. 5 V input to the internal regulator; NC if using external regulator
VREG
GND
GND
GND
GND
XIN
XOUT
48
2
8
13
20
14
15
P
P
P
P
P
I
O
SEL48/SEL27
25 / 44
I
RESET#
26
I
SELFPWR
37
I
GANG
39
I/O
RREF
System Interface
Test
I2C_SCL
11
I/O
VREG. 5–3.3 V regulator o/p during internal regulation; NC if using external regulator.
GND. Connect to Ground with as short a path as possible.
GND. Connect to Ground with as short a path as possible.
GND. Connect to Ground with as short a path as possible.
GND. Connect to Ground with as short a path as possible.
12 MHz crystal clock input, or 12/27/48 MHz clock input.
12 MHz Crystal OUT
Clock source selection inputs.
00: Reserved
01: 48 MHz OSC-in
10: 27 MHz OSC-in
11: 12 MHz Crystal or OSC-in
Active LOW Reset. External reset input, default pull high 10 k; When RESET = low,
whole chip is reset to the initial state.
Self Power. Input for selecting self/bus power. 0 is bus powered, 1 is self powered.
GANG. Default is input mode after power-on-reset.
Gang Mode: Input:1 -> Output is 0 for Normal Operation and 1 for Suspend
Individual Mode: Input:0 -> Output is 1 for Normal Operation and 0 for Suspend
Refer to Gang/Individual Power Switching Modes in Pin Configuration Options
Section for details
649 ohm resistor must be connected between RREF and Ground.
27
I(RDN)
I/O(RDN)
3
4
I/O/Z
I/O/Z
Upstream D– Signal.
Upstream D+ Signal.
5
I/O/Z
Downstream D– Signal. Downstream D- signal of port 1.
6
I/O/Z
Downstream D+ Signal. Downstream D+ signal of port 1.
Upstream Port
D–
D+
Downstream Port 1
DD–[1]
DD+[1]
Description
Test: 0: Normal Operation & 1: Chip will be put in test mode.
I2C_SCL: Can be used as I2C clock pin to access I2C EEPROM.
Notes
1. Pin Types: I = Input, O = Output, P = Power/Ground., Z = High Impedance, RDN = Pad internal Pull Down Resistor, RUP = Pad internal Pull Up Resistor.
2. The alternate function of these pins as LED indicator is not available if the pins are strapped to logic high, unless a separate circuit is designed to support logic high
disconnect after 60 ms of power-on reset (POR), when these pins are reconfigured as outputs.
Document Number: 001-67568 Rev. *H
Page 11 of 28
CY7C65632, CY7C65634
Pin Definitions (continued)
48-pin TQFP Package
Pin No.
Type [1]
SPI_CS
46
O(RDN)
O(RDN)
GREEN[1, 2]
SPI_SK
FIXED_PORT1
45
O(RDN)
O(RDN)
I(RDN)
OVR#[1]
42
I(RUP)
43
O/Z
I/O
Active LOW Overcurrent Condition Detection Input. Overcurrent condition
detection input for Port 1.
Power Switch Driver Output. Default is Active LOW.
I2C_SDA. Can be used as I2C Data pin, connected with I2C EEPROM.
9
10
I/O/Z
I/O/Z
Downstream D– Signal. Downstream D– signal of port 2.
Downstream D+ Signal. Downstream D+ signal of port 2.
36
O(RDN)
O(RDN)
I(RDN)
LED. Driver output for Amber LED. Port Indicator Support. Default is Active HIGH.
SPI_MOSI. Can be used as Data Out to access external SPI EEPROM.
PWR_PIN_POL. Used for power switch enable pin polarity setting. Refer
Configuration Section.
GREEN[2][2]
SPI_MISO
FIXED_PORT2
35
O(RDN)
I(RDN)
I(RDN)
LED. Driver output for Green LED. Port Indicator Support. Default is Active HIGH.
SPI_MISO. Can be used as Data In to access external SPI EEPROM.
FIXED_PORT2. At POR used to set Port2 as non removable port. Refer Configuration
Section.
OVR#[2]
40
I(RUP)
41
O/Z
17
18
I/O/Z
I/O/Z
AMBER[3][2]
SET_PORT_NUM2
33
O(RDN)
I(RDN)
GREEN[3][2]
FIXED_PORT3
32
O(RDN)
I(RDN)
OVR#[3]
30
I(RUP)
PWR#[3]
31
O/Z
21
I/O/Z
Downstream D– Signal. NC in CY7C65634.
22
I/O/Z
Downstream D+ Signal. NC in CY7C65634.
Name
AMBER[1][1, 2]
PWR#[1]
I2C_SDA
Downstream Port 2
DD–[2]
DD+[2]
AMBER[2][2]
SPI_MOSI
PWR_PIN_POL
PWR#[2]
Downstream Port 3
DD–[3]
DD+[3]
Downstream Port 4
DD–[4]
DD+[4]
Description
LED. Driver output for Amber LED. Port Indicator Support. Default is Active HIGH.
SPI_CS. Can be used as chip select to access external SPI EEPROM.
LED. Driver output for Green LED. Port Indicator Support. Default is Active HIGH.
SPI_SK. Can be used as SPI Clock to access external SPI EEPROM.
FIXED_PORT1. At POR used to set Port1 as non removable port. Refer pin
configuration Section.
Active LOW Overcurrent Condition Detection Input. Overcurrent condition
detection input for Port 2.
Power Switch Driver Output. Default is Active LOW.
Downstream D– Signal. NC in CY7C65634.
Downstream D+ Signal. NC in CY7C65634.
LED. Driver output for Amber LED. Port Indicator Support. Default is Active HIGH.
SET_PORT_NUM2. Used to set port numbering along with SET_PORT_NUM1.
Refer pin configuration section.
NC in CY7C65634.
LED. Driver output for Green LED. Port Indicator Support. Default is Active HIGH.
FIXED_PORT3. At POR used to set Port3 as non removable port. Refer pin
configuration section.
NC in CY7C65634.
Active LOW Overcurrent Condition Detection Input. Overcurrent condition
detection input for Port 3.
NC in CY7C65634.
Power Switch Driver Output. Default is Active LOW.
NC in CY7C65634.
Notes
1. Pin Types: I = Input, O = Output, P = Power/Ground., Z = High Impedance, RDN = Pad internal Pull Down Resistor, RUP = Pad internal Pull Up Resistor.
2. The alternate function of these pins as LED indicator is not available if the pins are strapped to logic high, unless a separate circuit is designed to support logic high
disconnect after 60 ms of power-on reset (POR), when these pins are reconfigured as outputs.
Document Number: 001-67568 Rev. *H
Page 12 of 28
CY7C65632, CY7C65634
Pin Definitions (continued)
48-pin TQFP Package
Type [1]
Description
24
O(RDN)
I(RDN)
LED. Driver output for Amber LED. Port Indicator Support. Default is Active HIGH.
SET_PORT_NUM1. Used to set port numbering along with SET_PORT_NUM2.
Refer configuration Section.
NC in CY7C65634.
GREEN[4][2]
FIXED_PORT4
23
O(RDN)
I(RDN)
OVR#[4]
28
I(RUP)
PWR#[4]
29
O/Z
Name
AMBER[4][2]
SET_PORT_NUM1
Pin No.
LED. Driver output for Green LED. Port Indicator Support. Default is Active HIGH.
FIXED_PORT4. At POR used to set Port4 as non removable port. Refer configuration
Section.
NC in CY7C65634.
Active LOW Overcurrent Condition Detection Input. Overcurrent condition
detection input for Port 4.
NC in CY7C65634.
Power Switch Driver Output. Default is Active LOW.
NC in CY7C65634.
Notes
1. Pin Types: I = Input, O = Output, P = Power/Ground., Z = High Impedance, RDN = Pad internal Pull Down Resistor, RUP = Pad internal Pull Up Resistor.
2. The alternate function of these pins as LED indicator is not available if the pins are strapped to logic high, unless a separate circuit is designed to support logic high
disconnect after 60 ms of power-on reset (POR), when these pins are reconfigured as outputs.
Pin Definitions
28-pin QFN Package
Name
Power and Clock
VCC_A
VCC_A
VCC_A
VCC_D
VCC
Pin No.
Type [2]
Description
5
9
14
21
27
P
P
P
P
P
VREG
28
P
XIN
XOUT
10
11
I
O
RESET#
17
I
SELFPWR
22
I
VCC_A. 3.3 V analog power to the chip.
VCC_A. 3.3 V analog power to the chip.
VCC_A. 3.3 V analog power to the chip.
VCC_D. 3.3 V digital power to the chip.
VCC. 5 V input to the internal regulator; NC if using external regulator
VCC. 5–3.3 V regulator o/p during internal regulation; 3.3 V I/P if using external
regulator.
12 MHz crystal clock input, or 12 MHz clock input
12 MHz Crystal OUT
Active LOW Reset. External reset input, default pull high 10 k; When RESET = low,
whole chip is reset to the initial state
Self Power. Input for selecting self/bus power. 0 is bus powered, 1 is self powered.
GANG[5]
23
I/O
RREF
System Interface
8
I/O
GANG. Default is input mode after power-on-reset.
Gang Mode: Input:1 -> Output is 0 for Normal Operation and 1 for Suspend
Individual Mode: Input:0 -> Output is 1 for Normal Operation and 0 for Suspend
Refer to Gang/Individual Power Switching Modes in Pin Configuration Options
Section for details
649 ohm resistor must be connected between RREF and Ground
Notes
3. Pin Types: I = Input, O = Output, P = Power/Ground., Z = High Impedance, RDN = Pad internal Pull Down Resistor, RUP = Pad internal Pull Up Resistor.
4. PWR#/I2C_SDA can be used as either PWR# or I2C_SDA but not as both. If EEPROM is connected then the pin will act as I2C_SDA, it will not switch to PWR#
mode (as it does in 48-pin TQFP package).
5. In Gang mode, only OVR#1 (pin 25) is enabled.
Document Number: 001-67568 Rev. *H
Page 13 of 28
CY7C65632, CY7C65634
Pin Definitions (continued)
28-pin QFN Package
Pin No.
Type [2]
18
I(RDN)
I/O(RDN)
26
I/O
1
2
I/O/Z
I/O/Z
Upstream D– Signal.
Upstream D+ Signal.
3
4
I/O/Z
I/O/Z
Downstream D– Signal.
Downstream D+ Signal.
25
I(RUP)
Active LOW Overcurrent Condition Detection Input. Overcurrent condition
detection input for Port 1.
6
7
I/O/Z
I/O/Z
Downstream D– Signal.
Downstream D+ Signal.
24
I(RUP)
Active LOW Overcurrent Condition Detection Input. Overcurrent condition
detection input for Port 2.
12
13
I/O/Z
I/O/Z
20
I(RUP)
Downstream D– Signal. NC in CY7C65634.
Downstream D+ Signal. NC in CY7C65634.
Overcurrent Condition Detection Input. Default is Active LOW.
NC in CY7C65634.
15
16
I/O/Z
I/O/Z
Downstream D– Signal. NC in CY7C65634.
Downstream D+ Signal. NC in CY7C65634.
OVR#[4]
19
I(RUP)
GND
PAD
P
Name
Test
I2C_SCL
PWR# [3]
I2C_SDA
Upstream Port
D–
D+
Downstream Port 1
DD–[1]
DD+[1]
OVR#[1]
Downstream Port 2
DD–[2]
DD+[2]
OVR#[2]
Downstream Port 3
DD–[3]
DD+[3]
OVR#[3]
Downstream Port 4
DD–[4]
DD+[4]
Description
Test: 0: Normal Operation & 1: Chip will be put in test mode
I2C_SCL: I2C Clock pin.
Power Switch Driver Output. Default is Active LOW.
I2C_SDA: I2C Data pin.
Overcurrent Condition Detection Input. Default is Active LOW.
NC in CY7C65634.
Ground pin for the chip. It is the solderable exposed pad beneath the chip. Refer
Figure 12 on page 23.
Notes
3. Pin Types: I = Input, O = Output, P = Power/Ground., Z = High Impedance, RDN = Pad internal Pull Down Resistor, RUP = Pad internal Pull Up Resistor.
4. PWR#/I2C_SDA can be used as either PWR# or I2C_SDA but not as both. If EEPROM is connected then the pin will act as I2C_SDA, it will not switch to PWR#
mode (as it does in 48-pin TQFP package).
5. In Gang mode, only OVR#1 (pin 25) is enabled.
Document Number: 001-67568 Rev. *H
Page 14 of 28
CY7C65632, CY7C65634
EEPROM Configuration Options
Systems using CY7C6563X have the option of using the default
descriptors to configure the hub. Otherwise, it must have an
external EEPROM for the device to have a unique VID, and PID.
The CY7C6563X can communicate with an SPI (microwire)
EEPROM like 93C46 or I2C EEPROM like 24C02. Example
EEPROM connections are as shown in the following figure.
Figure 8. EEPROM Connections
SPI EEPROM Connection
VDD
Table 1. EEPROM Configuration Options (continued)
Byte
Value
09h–0Fh
Reserved - FFh
10h
Vendor String Length
11h–3Fh
Vendor String (ASCII code)
40h
Product String Length
41h–6Fh
Product String (ASCII Code)
70h
Serial Number Length
71h to 80h onwards
Serial Number String
AMBER#[1]
CS
VCC
GREEN#[1]
SK
NC1
Default VID is 0x4B4, PID is 0x6570.
AMBER#[2]
DI
NC2
Byte 0: VID (LSB)
GREEN#[2]
DO
GND
Least Significant Byte of Vendor ID
Byte 1: VID (MSB)
AT93C46
Most Significant Byte of Vendor ID
I2C EEPROM Connection
A0
VDD
Byte2: PID (LSB)
Least Significant Byte of Product ID
VCC
Byte 3: PID (MSB)
A1
WP
A2
SCL
TEST
GND
SDA
PWR#[1]
Most Significant Byte of Product ID
Byte 4: ChkSum
CY7C6563X will ignore the EEPROM settings if ChkSum is
not equal to VID_LSB + VID_MSB + PID_LSB + PID_MSB +1
AT24C02
Byte 5: Reserved
Note The 28-pin QFN package includes only support for I2C
EEPROM like ATMEL/24C02N_SU27 D, MICROCHIP/4LC028
SN0509, SEIKO/S24CS02AVH9. The 48-pin TQFP package
includes both I2C and SPI EEPROM connectivity options. In this
case, user can use either SPI or I2C connectivity at a time for
communicating to EEPROM. The 48-pin package supports
ATMEL/AT93C46DN-SH-T, in addition to the above mentioned
families. HX2VL can only read from SPI EEPROM. So, field
programming of EEPROM is supported only for I2C EEPROM.
CY7C6563X verifies the check sum after power on reset and if
validated loads the configuration from the EEPROM. To prevent
this configuration from being overwritten, AMBER[1] is disabled
when SPI EEPROM is present.
Table 1. EEPROM Configuration Options
Byte
Value
00h
VID_LSB
01h
VID_MSB
02h
PID_LSB
03h
PID_MSB
04h
ChkSum
05h
Reserved - FEh
06h
Removable Ports
07h
Port Number
08h
Maximum Power
Document Number: 001-67568 Rev. *H
Set to FEh
Byte 6: RemovablePorts
RemovablePorts[4:1] are the bits that indicates whether the
device attached to the corresponding downstream port is
removable (set to 0) or non-removable (set to 1). Bit 1
corresponds to Port 1, Bit 2 to Port 2 and so on. Default value
is 0 (removable). These bit values are reported appropriately
in the HubDescriptor:DeviceRemovable field.
Bits 0,5,6,7 are set to 0.
Byte 7: Port Number
Port Number indicates the number of downstream ports. The
values must be 1 to 4. Default value is 4.
Byte 8: Maximum Power
This value is reported in the Configuration Descriptor:
bMax-Power field and is the current in 2 mA increments that
is required from the upstream hubs. The allowed range is 00h
(0 mA) to FAh(500 mA). Default value is 32h (100mA).
Byte 9–15: Reserved
Set to FFh
Byte 16: Vendor String Length
Length of the Vendor String
Byte 17–63: Vendor String
Value of Vendor String.
Page 15 of 28
CY7C65632, CY7C65634
Figure 10. Power Switching Mode
Byte 64: Product String Length
Length of the Product String
VDD (3.3V)
Byte 65–111: Product String
VDD (3.3V)
PCB
Silicon
GANG MODE
Value of Product String.
100K
GANG/SUSPEND
Byte 112: Serial Number Length
Length of the Serial Number
SUSPEND OUT
SUSPEND
INDICATOR
Byte 113 onwards: Serial Number String
Serial Number String.
100K
Pin Configuration Options
0 : INDIVIDUAL MODE
1: GANG MODE
INDIVIDUAL MODE
Power ON Reset
The power on reset can be triggered by external reset or internal
circuitry. The internal reset is initiated, when there is an unstable
power event for silicon’s internal core power (3.3 V ± 10%). The
internal reset is released 2.7 µs± 1.2% after supply reaches
power good voltage (2.5 V to 2.8 V). The external reset pin,
continuously senses the voltage level (5 V) on the upstream
VBUS as shown in the figure. In the event of USB plug/unplug or
drop in voltage, the external reset is triggered. This reset trigger
can be configured using the resistors R1 and R2. Cypress
recommends that the reset time applied in external reset circuit
should be longer than that of the internal reset time.
Table 2. Features Supported in 48-pin and 28-pin Packages
Figure 9. Power ON Reset Circuit
Power Switch Enable Pin Polarity
PCB
VBUS
(External 5V)
Silicon
R1
Ext. VBUS power-good
detection circuit input
(Pin"RESET#")
EXT
R2
INT
Global
Reset#
Int. 3.3V power-good
detection circuit input
(USB PHY reset)
48 Pin
28 Pin
Port number configuration
Supported Features
Yes
No
Non-Removable port configuration
Yes
No
Reference clock configuration
Yes
No
Power switch enable polarity
Yes
No
LED Indicator
Yes
No
The pin polarity is set Active-High by pin-strapping the
PWR_PIN_POL pin to 1 and Active-Low by pin-strapping the
PWR_PIN_POL pin to 0. Thus, both kinds of power switches are
supported. This feature is not supported in 28-pin QFN package.
Port Number Configuration
In addition to the EEPROM configuration, as described above,
configuring the hub for 2/3/4 ports is also supported using
pin-strapping SET_PORT_NUM1 and SET_PORT_NUM2, as
shown in following table. Pin strapping option is not supported in
the 28-pin QFN package.
Table 3. Port Number Configuration using Pinstrap
Gang/Individual Power Switching Mode
A single pin is used to set individual / gang mode as well as
output the suspend flag. This is done to reduce the pin count.
The individual or gang mode is decided within 20 µs after power
on reset. It has a setup time of 1 ns. 50 to 60 ms after reset, this
pin is changed to output mode. CY7C6563X outputs the suspend
flag, after it is globally suspended. Pull-down resistor of greater
than 100K is needed for Individual mode and a pull-up resistor
greater than 100K is needed for Gang mode. Figure below
shows the suspend LED indicator schematics. The polarity of
LED must be followed, otherwise the suspend current will be
over the spec limitation (2.5 mA).
Document Number: 001-67568 Rev. *H
SET_PORT_NUM2
SET_PORT_NUM1
# Ports
1
1
1 (Port 1)
1
0
2 (Port 1/2)
0
1
3 (Port 1/2/3)
0
0
4 (All ports)
Non Removable Ports Configuration
In embedded systems, downstream ports that are always
connected inside the system, can be set as non-removable
(always connected) ports, by pin-strapping the corresponding
FIXED_PORT# pins 1~4 to High, before power on reset. At POR,
if the pin is pull high, the corresponding port is set to
non-removable. This is not supported in the 28-pin QFN
package.
Page 16 of 28
CY7C65632, CY7C65634
Reference Clock Configuration
This hub can support, optional 27/48 MHz clock source. When
on-board 27/48 MHz clock is present, then using this feature,
system integrator can further reduce the BOM cost by eliminating
the external crystal. This is available through GPIO pin
configuration shown as follows. This is not supported in the
28-pin QFN package.
Table 4. Reference Clock Options
SEL48
SEL27
Clock Source
0
1
48 MHz OSC-in
1
0
27 MHz OSC-in
1
1
12 MHz X’tal/OSC-in
Document Number: 001-67568 Rev. *H
Page 17 of 28
CY7C65632, CY7C65634
Absolute Maximum Ratings
Operating Conditions
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Ambient temperature ..................................... 0 °C to +70 °C
Storage temperature ................................ –55 °C to +100 °C
5 V supply voltage to ground potential ......4.75 V to +5.25 V
Ambient temperature ..................................... 0 °C to +70 °C
Ambient max junction temperature .............. 0 °C to +125 °C
3.3 V supply voltage to ground potential .....3.15 V to +3.6 V
5 V supply voltage to ground potential ........–0.5 V to +6.0 V
Input voltage for USB signal pins ..................0.5 V to +3.6 V
3.3 V supply voltage to ground potential .....–0.5 V to +3.6 V
Voltage at open drain input pins ..................–0.5 V to +5.0 V
Voltage at open drain input pins
(OVR#1-4, SELFPWR, RESET#) ................–0.5 V to +5.5 V
Thermal characteristics 48-pin TQFP ................... 78.7 °C/W
Thermal characteristics 28-pin QFN ..................... 33.3 °C/W
3.3 V input voltage for digital I/O ..................–0.5 V to +3.6 V
FOSC (oscillator or crystal frequency) ........ 12 MHz ± 0.05%
Electrical Characteristics
DC Electrical Characteristics
Max
Parameter
Description
Conditions
Min
Typ
External
regulator
Internal
regulator
PD
Power dissipation
Excluding USB signals
366.5
–
VIH
Input high voltage
–
2
–
–
VIL
Input low voltage
–
–
–
0.8
Full speed / Low speed
(0 < VIN < VCC)
–10
–
+10
High speed mode
(0 < VIN < VCC)
–5
0
+5
Il
Input leakage current
426.5
Output voltage high
IOH = 8 mA
2.4
–
–
VOL
Output low voltage
IOL= 8 mA
–
–
0.4
RDN
Pad internal pull-down Resistor
–
29
59
135
RUP
Pad internal pull-up Resistor
–
80
108
140
CIN
Input pin capacitance
Full speed / Low speed
mode
–
–
20
High speed mode
4
4.5
5
–
0.786
Suspend current
–
mW
V
A
VOH
ISUSP
Unit
1.043
V
K
pF
1.3
mA
Notes
6. Current measurement is with device attached and enumerated.
7. No devices attached.
Document Number: 001-67568 Rev. *H
Page 18 of 28
CY7C65632, CY7C65634
Electrical Characteristics (continued)
DC Electrical Characteristics (continued)
Max
Parameter
Description
Conditions
Min
Typ
External
regulator
Internal
regulator
Full speed host, full
speed devices
–
88.7
103.9
105.4
High speed host, high
speed devices
–
81.9
88.2
89.3
High speed host, full
speed devices
–
88.2
101.2
102.3
Full speed host, full
speed devices
–
79.1
91.6
93
High speed host, high
speed devices
–
72.9
78.5
78.6
High speed host, full
speed devices
–
75.9
88.7
88.8
Full speed host, full
speed devices
–
68.1
78.4
78.6
High speed host, high
speed devices
–
61.9
67.6
69.6
High speed host, full
speed devices
–
64.9
75.4
76.1
Full speed host, full
speed devices
–
57.1
66.3
66.7
High speed host, high
speed devices
–
51.9
57.6
59.3
High speed host, full
speed devices
–
54.7
61.1
62.5
Unit
Supply Current
4 Active ports[6]
3 Active ports
ICC
2 Active ports
1 Active port
No Active Ports[7]
Full speed host
–
42.8
48.9
50.3
High speed host
–
44.2
49.1
50.6
mA
Notes
6. Current measurement is with device attached and enumerated.
7. No devices attached.
Document Number: 001-67568 Rev. *H
Page 19 of 28
CY7C65632, CY7C65634
AC Electrical Characteristics
USB Transceiver is USB 2.0 certified in low, full and high speed modes.
Both the upstream USB transceiver and all four downstream transceivers have passed the USB-IF USB 2.0 Electrical Certification
Testing.
The 48-pin TQFP package can support communication to EEPROM using either I2C or SPI. The 28-pin QFN package can support
only I2C communication to EEPROM.
AC Characteristics of these two interfaces to EEPROM are summarized in tables below:
AC Characteristics of SPI EEPROM Interface
Parameter
Parameter
Min
Typ
Max
tCSS
CS setup time
3.0
–
–
tCSH
CS hold time
3.0
–
–
tSKH
SK high time
1.0
–
–
tSKL
SK low time
2.2
–
–
tDIS
DI setup time
1.8
–
–
tDIH
DI hold time
2.4
–
–
tPD1
Output delay to ‘1’
–
–
1.8
tPD0
Output delay to ‘0’
–
–
1.8
Units
µs
AC Characteristics of I2C EEPROM Interface
Parameter
Parameter
1.8 V–5.5 V
2.5 V–5.5 V
Min
Max
Min
Max
Units
fSCL
SCL clock frequency
0.0
100
0.0
400
tLOW
Clock LOW Period
4.7
–
1.2
–
tHIGH
Clock HIGH Period
4.0
–
0.6
–
tSU:STA
Start condition setup time
4.7
–
0.6
–
tSU:STO
Stop condition setup time
4.7
–
0.6
–
tHD:STA
Start condition hold time
4.0
–
0.6
–
tHD:STO
Stop condition hold time
4.0
–
0.6
–
tSU:DAT
Data in setup time
200.0
–
100.0
–
tHD:DAT
Data in hold time
0
–
0
–
tDH
Data out hold time
100
–
50
–
tAA
Clock to output
0.1
4.5
0.1
–
µs
tWR
Write cycle time
–
10
–
5
ns
kHz
µs
ns
Thermal Resistance
Parameter
Description
48-pin TQFP
Package
28-pin QFN
Package
JA
Thermal resistance (junction to ambient)
78.7
33.3
JC
Thermal resistance (junction to case)
35.3
18.4
Document Number: 001-67568 Rev. *H
Unit
°C/W
Page 20 of 28
CY7C65632, CY7C65634
Ordering Information
Ordering Code
Device
Package Type
CY7C65632-48AXC
4 port Single-TT hub (configurable with
GPIOs and EEPROM)
48-pin TQFP Bulk
CY7C65632-28LTXC
4 port Single-TT hub (configurable with
GPIOs and EEPROM)
28-pin QFN Bulk
CY7C65632-48AXCT
4 port Single-TT hub (configurable with
GPIOs and EEPROM)
48-pin TQFP Tape and Reel
CY7C65632-28LTXCT
4 port Single-TT hub (configurable with
GPIOs and EEPROM)
28-pin QFN Tape and Reel
CY7C65634-48AXC
2 port Single-TT hub (configurable with
GPIOs and EEPROM)
48-pin TQFP Bulk
CY7C65634-28LTXC
2 port Single-TT hub (configurable with
GPIOs and EEPROM)
28-pin QFN Bulk
CY7C65634-48AXCT
2 port Single-TT hub (configurable with
GPIOs and EEPROM)
48-pin TQFP Tape and Reel
CY7C65634-28LTXCT
2 port Single-TT hub (configurable with
GPIOs and EEPROM)
28-pin QFN Tape and Reel
Ordering Code Definitions
CY
7
C 656 3X -
XX XX
X
C
X
X = T or blank
T = Tape and Reel; blank = Bulk
Temperature Grade: C = Commercial
Pb-free
Package Type: XX = A or LT
A = TQFP
LT = QFN
Pin Count: XX = 48 or 28
48 = 48 pins, 28 = 28 pins
Specific Product Identifier: 3X = 32 or 34
Part Identifier
Technology Code: C = CMOS
Marketing Code
Company ID: CY = Cypress
Document Number: 001-67568 Rev. *H
Page 21 of 28
CY7C65632, CY7C65634
Package Diagrams
The CY7C65632 is available in following packages:
Figure 11. 48-pin TQFP (7 × 7 × 1.4 mm) A48 Package Outline, 51-85135
51-85135 *C
Document Number: 001-67568 Rev. *H
Page 22 of 28
CY7C65632, CY7C65634
Package Diagrams (continued)
The CY7C65632 is available in following packages:
Figure 12. 28-pin QFN (5 × 5 × 0.8 mm), LT28A (3.5 × 3.5 E-Pad), Sawn Package Outline, 001-64621
001-64621 *A
Document Number: 001-67568 Rev. *H
Page 23 of 28
CY7C65632, CY7C65634
Acronyms
Acronym
Document Conventions
Description
AC
alternating current
ASCII
american standard code for information
interchange
EEPROM
Units of Measure
Symbol
Unit of Measure
°C
degree Celsius
electrically erasable programmable read only
memory
kHz
kilohertz
k
kilohm
EMI
electromagnetic interference
MHz
megahertz
ESD
electrostatic discharge
A
microampere
GPIO
general purpose input/output
s
microsecond
I/O
input/output
W
microwatt
LED
light emitting diode
mA
milliampere
LSB
least significant bit
mm
millimeter
MSB
most significant bit
ms
millisecond
PCB
printed circuit board
mW
milliwatt
PLL
phase-locked loop
ns
nanosecond
POR
power on reset
PSoC®

ohm
Programmable System-on-Chip™
%
percent
QFN
quad flat no leads
pF
picofarad
RAM
random access memory
ppm
parts per million
ROM
read only memory
V
volt
SIE
serial interface engine
W
watt
TQFP
thin quad flat pack
TT
transaction translator
USB
universal serial bus
Document Number: 001-67568 Rev. *H
Page 24 of 28
CY7C65632, CY7C65634
Silicon Errata for the HX2VL, CY7C65632 Product Family
This section describes the errata for the HX2VL, CY7C65632. The details include errata trigger conditions, scope of impact, available
workarounds, and silicon revision applicability.
Contact your local Cypress Sales Representative, if you have any questions.
Part Numbers Affected
Part Number
Device Characteristics
CY7C65632
USB 2.0 Single TT Hub
HX2VL Qualification Status
Product Status: In production
HX2VL Errata Summary
This is the initial version of the HX2VL Errata. As of now, there is no known issue with respect to the HX2VL.
Document Number: 001-67568 Rev. *H
Page 25 of 28
CY7C65632, CY7C65634
Document History Page
Document Title: CY7C65632/CY7C65634, HX2VL™ Very Low Power USB 2.0 Hub Controller
Document Number: 001-67568
Revision
ECN
Orig. of
Change
Submission
Date
**
3183649
SSJO /
SWAK
03/02/2011
New data sheet.
*A
3250883
SWAK /
AASI
05/06/2011
Updated Functional Overview (Updated Port Indicators (Added a Note
“Pin-strapping GREEN#[1] and GREEN#[2] enables proprietary function that
may affect the normal functionality of HX2VL. Configuring Port #1 and #2 as
non-removable by pin-strapping should be avoided.”).
Updated Pin Configurations (Updated Figure 4 and Figure 5 (Pin 37 of the
48-pin TQFP package was named SELF_PWR. It is changed to SELFPWR.)).
Updated Pin Definitions (changed value from 680  to 650 in description of
RREF pin).
Updated Functional Overview (Updated Power Regulator on page 6 (Changed
regulator’s maximum current loading from 200 mA to 150 mA)).
Updated Pin Configuration Options (Updated Power Switch Enable Pin Polarity
(Replaced first two occurrences of the word “setting” with “pin-strapping”)).
Updated Electrical Characteristics (Updated DC Electrical Characteristics
(Changed typical value of ISUSP parameter from 693.3 µA to 786 µA, changed
maximum value of ISUSP parameter 693.7 µA to 903 µA, and updated typical
and maximum values of ICC parameter)).
*B
3324484
AASI
07/25/2011
Changed status from Preliminary to Final.
Updated Pin Configurations (Included CY7C65634 related information).
Updated Pin Definitions (Changed description of OVR# pins from “Default is
Active LOW” to “Active LOW Overcurrent Condition Detection Input” (since the
polarity is not configurable)).
Updated Pin Definitions (Changed description of OVR# pins from “Default is
Active LOW” to “Active LOW Overcurrent Condition Detection Input” (since the
polarity is not configurable)).
Updated Electrical Characteristics (Updated DC Electrical Characteristics
(Updated minimum, typical, and maximum values of RDN and RUP parameters
to 81 k103 k and 181 k)).
*C
3336689
SWAK
08/04/2011
No technical updates.
*D
3412885
AASI
10/18/2011
Updated Pin Configurations (Updated Figure 4 and Figure 5 (Renamed
SPI_DI to SPI_MOSI, renamed SPI_DO to SPI_MISO respectively for clarity),
updated Figure 6 (Updated pin 26 to describe the alternate function
I2C_SDA.), updated Figure 7 (Updated to reflect pin 20 as NC)).
Updated Pin Definitions (Renamed SPI_DI to SPI_MOSI, renamed SPI_DO
to SPI_MISO respectively for clarity).
Updated Pin Definitions (Added Note 3 and referred the same note in PWR#).
Minor text edits to add clarity.
*E
3508597
AASI
01/25/2011
Updated EEPROM Configuration Options (Removed text, “Strings must
comply with the USB specification. The first byte (Byte 16) must be the length
of the string in bytes, the second must be 0x03, and the string must be in
ASCII code.” below “Vendor string”, “Product string” and “Serial Number
string”.).
Updated Functional Overview (Updated Overcurrent Detection (Included the
text, “OVR#[n] has a setup time of 20 ns. It takes 3 to 4 ms from overcurrent
detection to de-assertion of PWR#[n].”).
Document Number: 001-67568 Rev. *H
Description of Change
Page 26 of 28
CY7C65632, CY7C65634
Document History Page (continued)
Document Title: CY7C65632/CY7C65634, HX2VL™ Very Low Power USB 2.0 Hub Controller
Document Number: 001-67568
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
*F
3660597
AASI
07/02/2012
Updated EEPROM Configuration Options (Changed the value of Byte 5 to
FEh to match with the tabular column).
Updated Electrical Characteristics (Updated DC Electrical Characteristics
(Splitted the Max column into two columns namely External regulator and
Internal regulator for ISUSP and ICC parameters and updated the
corresponding values)).
Added Thermal Resistance.
Updated in new template.
*G
3995708
PRJI
05/09/2013
Added Silicon Errata for the HX2VL, CY7C65632 Product Family.
*H
4661191
PRJI
02/17/2015
Added More Information.
Removed the note in Port Indicators.
Updated the term “LOW” to “HIGH” in LED descriptions, in Pin Definitions as
LEDs are active HIGH by default.
Added Note 1 and 2, and referred it in Pin Definitions.
Updated RDN and RDUP values in DC Electrical Characteristics.
Added Note 5 for GANG pin in DC Electrical Characteristics.
Added Note 6 and 7 for Active ports and No active ports, and referred it in DC
Electrical Characteristics.
Updated Figure 11 (spec 51-85135 *B to *C) and Figure 12 (spec 001-64621
** to *A) in Package Diagrams.
Updated the Production Status “Sampling” to “In production” in HX2VL
Qualification Status.
Document Number: 001-67568 Rev. *H
Page 27 of 28
CY7C65632, CY7C65634
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/memory
cypress.com/go/psoc
cypress.com/go/touch
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2011-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-67568 Rev. *H
Revised February 17, 2015
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 28 of 28
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