AN69235 - Migrating from HX2/HX2LP to HX2VL.pdf

AN69235
Migrating from HX2/HX2LP to HX2VL
Author: Anand Srinivasan
Associated Project: No
Associated Part Family:
CY7C65640A,CY7C65630/20,CY7C65642/32/34
Software Version: N/A
Related Application Notes: None
Abstract
AN69235 is intended to help the developer migrate a hub design based on EZ-USB® HX2™ (CY7C65640A)/
EZ-USB® HX2LP™ (CY7C65630/20) to use the HX2VL™ (CY7C65642/32/34) hub. It also provides a feature
comparison between HX2, HX2LP, and HX2VL to aid in the selection of the appropriate part number for migration.
One must note that HX2 (TetraHub) is now not recommended for new designs.
Introduction
package based on the requirement. All comments below
pertaining to HX2VL are applicable to package options.
The HX2VL family is the next generation of USB
high-speed hubs. This family of hubs includes:
Based on the above mentioned consideration, the
appropriate part number (CY7C65642 or CY7C65632/34)
in the HX2VL family for migration can be chosen.


Four-port hubs:

CY7C65632 with a single transaction translator
(TT).

CY7C65642 with four TTs.
Two-port hub: CY7C65634 with single TT.
The HX2VL family is not pin-compatible with HX2/HX2LP,
and it consumes less power than HX2/HX2LP. This
application note highlights the difference between the
products, and aids the designer in migrating existing
designs to the HX2VL family.
For designs in which downstream devices are all highspeed or just a single full-speed/low-speed device, the
performance of single TT and 4 TT is the same. For this
reason, a single TT hub should be considered for these
designs. For more details on single TT and multiple TT,
refer to Single Versus Multiple Transaction Translator AN1071.
Both the HX2LP and HX2 families are 56 pin, QFN
packaged parts. The HX2VL family of chips is available in
two different package options:


48-pin TQFP package
28-pin QFN package
Both are the same in terms of the core hub functionality.
This allows the designer to migrate to an appropriate
www.cypress.com
For more details on HX2VL, refer to the HX2VL datasheet.
For a schematic review checklist, refer to the “Schematic
review checklist for HX2VL” application note (AN69025).
Note In this application note, HX2LP is used to refer HX2
and HX2LP except where noted.HX2VL is used to refer to
CY7C65642 and CY7C65632/34 except where noted.
Hardware Changes
This section presents information on the required changes
when using either configuration of the HX2VL chip.
Changes to the Crystal Specification
With the use of HX2VL, one primary change required is
the crystal. When a crystal is used in the design, the load
capacitance of the crystal must change for proper
operation. This affects both the load capacitors and the
crystal being used. HX2LP uses a crystal with the
following specifications:




24 MHz ± 100 ppm
Parallel resonant
Fundamental mode
500 μW drive level
Document No. 001-69235 Rev. *A
1
Migrating from HX2/HX2LP to HX2VL

HX2 requires a crystal with load capacitors that are
between 20 pF and 33 pF (5% tolerance). The HX2LP
requires a crystal with load capacitors of 12 pF
(5% tolerance).
Following are the specifications for the crystal used with
HX2VL:





HX2VL supports loading of configuration data from either
2
I C EEPROM or SPI EEPROM (only by 48-pin TQFP
package). The size of configuration data for HX2VL can be
up to 128 bytes. The size and/or type of EEPROM can be
changed based on requirement.
Regulator
HX2LP can be powered from a single 3.3 V supply. For a
bus-powered design or a self-powered design with a
supply other than 3.3 V, this mandates an external
regulator.
12 MHz ± 500 ppm
Parallel resonant
Fundamental mode
HX2VL supports a 5 V to 3.3 V internal regulator. For a
bus-powered or self-powered design with a 5 V supply,
this results in system cost reduction. HX2VL can be
powered from a single 3.3 V supply as well.
600 μW drive level
20-pF (5% tolerance) load capacitor
These specifications must be taken into consideration
when selecting both the load capacitors and the crystal.
Using a different crystal load capacitance with a crystal
specified for 20 pF is expected to have some effect on the
frequency shift.
The designer should always ensure that the power
dissipated by the crystal is within the crystal
manufacturer’s specifications. Overdriving the crystal may
damage it.
HX2VL supports 12/27/48 MHz oscillators (12/27/48 MHz
supported in 48-TQFP package; 28-QFN part supports
only 12MHz) as clock source. The frequency tolerance
remains the same regardless of the clock source.
EEPROM
The internal regulator of HX2VL can supply only up to
150 mA. This can be a bottleneck if the output of this
regulator is used to supply other components of the
design. Based on these considerations, the regulator
configuration can be chosen.
Pin-strapping
Pin-strapping is the method of configuring HX2VL based
on the state of certain pins at power on reset (POR) or at a
strapping period after POR. This is used to configure
power management mode (ganged or individual), power
enable switch polarity, number of ports, and nonremovable port configuration. Through pin-strapping, the
28-pin QFN package supports only power management
mode configuration.
HX2LP supports loading of configuration data from SPI
EEPROM. The size of configuration data for HX2LP can
be up to 512 bytes.
www.cypress.com
Document No. 001-69235 Rev. *A
2
Migrating from HX2/HX2LP to HX2VL
Features
For a clear picture of the trade-offs during migration, Table 1 shows a comparison between HX2, HX2LP, and HX2VL.
Table 1. Feature Comparison between HX2, HX2LP and HX2VL
Item
HX2
HX2VL (48-pin TQFP
package)
HX2LP
HX2VL (28-pin QFN
package)
Power consumption**
High (460mA)
Lower than HX2 (231mA)
Lower than HX2LP
(82mA)
Lower than HX2LP
(82mA)
Bus-powered mode
Not supported
Can support up to 3
downstream ports
Can support up to 4
downstream ports
1.CY7C65632/42 can
support up to 4
downstream ports
2.CY7C65634 can
support up to 2
downstream ports
Power management
mode
Yes (EEPROM
configuration data)
Yes (EEPROM configuration
data)
Yes (Pin-strapping GANG
pin)
Yes (Pin-strapping GANG
pin)
Self-powered mode
Yes (SELFPWR pin)
Yes (SELFPWR pin)
Yes (SELFPWR pin)
Yes (SELFPWR pin)
VBUS monitoring
Yes (VBUSPOWER
pin)
Yes (VBUSPOWER pin)
Yes (RESET# pin)
Yes (RESET# pin)
Multiple TT
Yes
No
1.Yes for CY7C65642
1.Yes for CY7C65642
2.No for CY7C65632 and
CY7C65634
2.No for CY7C65632 and
CY7C65634
Number of ports
Yes (EEPROM
configuration data)
Yes (EEPROM configuration
data)
Yes (pin-strapping
SET_PORT_NUMx
(x=1,2) pins or EEPROM
configuration data)
Yes (EEPROM
configuration data)
Non-removable port
Yes (EEPROM
configuration data)
Yes (EEPROM configuration
data)
Yes (pin-strapping
Yes (EEPROM
configuration data)
No
No
Yes (GANG pin)
Suspend indication
FIXED PORTx (x=1..4)
pins or EEPROM
configuration data)
2
Yes (GANG pin)
EEPROM
SPI
SPI
I C and SPI
I2C
Power enable pin
Yes
Yes
Yes
Yes
LED indicators
Yes
Yes
Yes
No
Modulated indicators
No
Yes
No
No
Power polarity control
No
Yes (EEPROM configuration
data)
Yes (Pin-strapping
PWR_PIN_POL pin)
No
Dual power descriptors
No
Yes
No
No
Multiple string
descriptors
No
Yes
No
No
**These are typical values of supply current (ICC) when the device is connected to HS host and all 4 downstream ports are
connected to HS peripherals.
Summary
About the Author
This application note discusses the migration of an
HX2/HX2LP–based hub design to an HX2VL-based hub
design and the considerations associated with the
migration.
www.cypress.com
Name:
Anand Srinivasan
Title:
Applications Engineer Sr
Contact:
[email protected]
Document No. 001-69235 Rev. *A
3
Migrating from HX2/HX2LP to HX2VL
Document History
Document Title: Migrating from HX2/HX2LP to HX2VL
Document Number: 001-69235
Revision
**
*A
ECN
3237432
3551005
Orig. of
Change
AASI
PDAV
Submission
Date
04/21/2011
03/15/2012
Description of Change
New application note
Updated to latest template
Including CY7C65634
Under “Number of Port” and “Non-removable port” features for 48-TQFP
part : Changing SEL_PORT_NUM1 to SEL_PORT_NUMx (x=1..4)
Adding ICC values in the part comparison grid
Adding: HX2 moved to NRND
Asserting “Power Enable Pin” feature under the 28-QFN part
www.cypress.com
Document No. 001-69235 Rev. *A
4
Migrating from HX2/HX2LP to HX2VL
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Document No. 001-69235 Rev. *A
5
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