CY7C68053 MoBL-USB™ FX2LP18 USB Microcontroller Features ■ USB 2.0 9 V USB-IF high speed and full speed compliant (TID# 40000188) ■ Single-chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor ■ Ideal for mobile applications (cell phone, smart phones, PDAs, MP3 players) ❐ Ultra low power ❐ Suspend current: 20 µA (typical) ■ Software: 8051 Code runs from: ❐ Internal RAM, which is loaded from EEPROM ■ 16 kBytes of on-chip code/data RAM ■ Four programmable BULK/INTERRUPT/ISOCHRONOUS endpoints ❐ Buffering options: double, triple, and quad ■ Additional Programmable (BULK/INTERRUPT) 64-Byte Endpoint ■ 8 or 16-Bit External Data Interface ■ Smart Media Standard ECC Generation ■ GPIF (General Programmable Interface) ❐ Allows direct connection to most parallel interface ❐ Programmable waveform descriptors and configuration registers to define waveforms ❐ Supports multiple Ready and Control outputs Logic Block Diagram ■ Integrated, Industry Standard Enhanced 8051 ❐ 48 MHz, 24 MHz, or 12 MHz CPU operation ❐ Four clocks per instruction cycle ❐ Three counter/timers ❐ Expanded interrupt system ❐ Two data pointers ■ 1.8 V Core Operation ■ 1.8 V to 3.3 V I/O Operation ■ Vectored USB Interrupts and GPIF/FIFO Interrupts ■ Separate Data Buffers for Setup and Data Portions of a CONTROL Transfer ■ Integrated I2C Controller, runs at 100 or 400 kHz ■ Four Integrated FIFOs ❐ Integrated glue logic and FIFOs lower system cost ❐ Automatic conversion to and from 16-bit buses ❐ Master or slave operation ❐ Uses external clock or asynchronous strobes ❐ Easy interface to ASIC and DSP ICs ■ Available in Industrial Temperature Grade ■ Available in one Pb-free Package with up to 24 GPIOs ❐ 56-pin VFBGA (24 GPIOs) High-performance microprocessor using standard tools with lower-power options 24 MHz Ext. XTAL MoBL-USB FX2LP18 x20 PLL 2 /0.5 /1.0 /2.0 8051 Core 12/24/48 MHz, Four Clocks/Cycle 1.5K Connected for Full-Speed D+ D– USB 2.0 XCVR CY Smart USB 1.1/2.0 Engine Integrated Full- and High-Speed XCVR 16 KB RAM A ddre ss ( 16) / Data Bu s (8) VCC I C Master GPIF RDY (2) CTL (3) ECC 4 KB FIFO Enhanced USB Core Simplifies 8051 Code Cypress Semiconductor Corporation Document Number: 001-06120 Rev *L • “Soft Configuration” Easy Firmware Changes 198 Champion Court Abundant IO Additional IOs (24) 8/16 General Programmable I/F To Baseband Processors/ Application Processors/ ASICS/DSPs Up to 96 MBytes/sec Burst Rate FIFO and Endpoint Memory (Master or Slave Operation) • San Jose, CA 95134-1709 • 408-943-2600 Revised October 28, 2015 CY7C68053 More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right device for your design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article AN65209 - Getting Started with FX2LP. ■ ■ ■ Overview: USB Portfolio, USB Roadmap USB 3.0 Product Selectors: FX2LP, AT2LP, NX2LP-Flex, SX2 Application notes: Cypress offers a large number of USB application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with FX3 are: ❐ AN65209 - Getting Started with FX2LP ❐ AN15652 - Interfacing a Cypress MoBL-USB™ FX2LP18 with an Intel PXA27x Processor ® ❐ AN6076 - Differences between EZ-USB FX2LP™ and MoBL-USB™ FX2LP18 ❐ For complete list of Application notes, click here ■ Code Examples: ❐ USB Hi-Speed ■ Technical Reference Manual (TRM): ❐ MoBL-USB™ FX2LP18 Technical Reference Manual ■ Reference Designs: ❐ CY4661 - External USB Hard Disk Drives (HDD) with Fingerprint Authentication Security ❐ FX2LP DMB-T/H TV Dongle Reference Design ■ Models: IBIS MoBL-USB FX2LP18 Development Kit The CY3687 MoBL-USB™ FX2LP18 Development Kit is a complete development resource for FX2LP18. It provides a platform to develop and test custom projects using FX2LP18. The development kit contains collateral materials for the firmware, hardware, and software aspects of a design using FX2LP18. GPIF™ II Designer FX2LP™ General Programmable Interface (GPIF) provides an independent hardware unit, which creates the data and control signals required by an external interface. FX2LP GPIF Designer allows users to create and modify GPIF waveform descriptors for EZ-USB FX2/ FX2LP family of chips using a graphical user interface. Extensive discussion of general GPIF discussion and programming using GPIF Designer is included in FX2LP18 Technical Reference Manual and GPIF Designer User Guide, distributed with GPIF Designer. AN66806 - Getting Started with EZ-USB® FX2LP™ GPIF can be a good starting point. Document Number: 001-06120 Rev *L Page 2 of 44 CY7C68053 Contents Functional Description..................................................... 4 Applications ...................................................................... 4 Functional Overview ........................................................ 4 USB Signaling Speed.................................................. 4 8051 Microprocessor................................................... 4 I2C™ Bus .................................................................... 5 Buses .......................................................................... 5 USB Boot Methods...................................................... 5 ReNumeration™.......................................................... 5 Bus-Powered Applications .......................................... 5 Interrupt System .......................................................... 6 Reset and Wakeup...................................................... 8 Program/Data RAM ..................................................... 9 Register Addresses ..................................................... 9 Endpoint RAM ............................................................. 9 External FIFO Interface ............................................. 11 GPIF .......................................................................... 11 ECC Generation[6] ................................................................... 12 USB Uploads and Downloads ................................... 12 Autopointer Access ................................................... 12 I2C Controller............................................................. 12 Pin Assignments ............................................................ 13 CY7C68053 Pin Descriptions.................................... 15 Register Summary.......................................................... 19 Absolute Maximum Ratings .......................................... 26 Operating Conditions..................................................... 26 DC Characteristics ......................................................... 26 Document Number: 001-06120 Rev *L AC Electrical Characteristics ........................................ 27 USB Transceiver ....................................................... 27 GPIF Synchronous Signals ....................................... 27 Slave FIFO Synchronous Read................................. 28 Slave FIFO Asynchronous Read............................... 29 Slave FIFO Synchronous Write................................. 30 Slave FIFO Asynchronous Write ............................... 31 Slave FIFO Synchronous Packet End Strobe ........... 32 Slave FIFO Asynchronous Packet End Strobe ......... 33 Slave FIFO Output Enable ........................................ 33 Slave FIFO Address to Flags/Data............................ 34 Slave FIFO Synchronous Address ............................ 34 Slave FIFO Asynchronous Address .......................... 34 Sequence Diagram.................................................... 35 Ordering Information...................................................... 39 Ordering Code Definitions ......................................... 39 Package Diagram............................................................ 40 PCB Layout Recommendations .................................... 41 Acronyms ........................................................................ 42 Document Conventions ................................................. 42 Units of Measure ....................................................... 42 Document History Page ................................................. 43 Sales, Solutions, and Legal Information ...................... 44 Worldwide Sales and Design Support....................... 44 Products .................................................................... 44 PSoC® Solutions ...................................................... 44 Cypress Developer Community................................. 44 Technical Support ..................................................... 44 Page 3 of 44 CY7C68053 Functional Description Cypress Semiconductor Corporation’s MoBL-USB FX2LP18 (CY7C68053) is a low voltage (1.8 V) version of the EZ-USB® FX2LP(CY7C68013A), which is a highly integrated, low power USB 2.0 microcontroller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very cost effective solution that provides superior time-to-market advantages with low power to enable bus powered applications. The ingenious architecture of MoBL-USB FX2LP18 results in data transfer rates of over 53 Mbytes per second, the maximum allowable USB 2.0 bandwidth, while still using a low cost 8051 microcontroller in a package as small as a 56VFBGA (5 mm x 5 mm). Because it incorporates the USB 2.0 transceiver, the MoBL-USB FX2LP18 is more economical, providing a smaller footprint solution than USB 2.0 SIE or external transceiver implementations. With MoBL-USB FX2LP18, the Cypress Smart SIE handles most of the USB 1.1 and 2.0 protocol in hardware, freeing the embedded microcontroller for application-specific functions and decreasing development time to ensure USB compatibility. The General Programmable Interface (GPIF) and Master/Slave Endpoint FIFO (8 or 16-bit data bus) provide an easy and glueless interface to popular interfaces such as ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors. The MoBL-USB FX2LP18 is also referred to as FX2LP18 in this document. Applications There are a wide variety of applications for the MoBL-USB FX2LP18. It is used in cell phones, smart phones, PDAs, and MP3 players, to name a few. The ‘Reference Designs’ section of the Cypress web site provides additional tools for typical USB 2.0 applications. Each reference design comes complete with firmware source and object code, schematics, and documentation. For more information, visit http://www.cypress.com. Functional Overview The functionality of this chip is described in the sections below. USB Signaling Speed FX2LP18 operates at two of the three rates defined in the USB Specification Revision 2.0, dated April 27, 2000. ■ Full speed, with a signaling bit rate of 12 Mbps ■ High speed, with a signaling bit rate of 480 Mbps 8051 Microprocessor The 8051 microprocessor embedded in the FX2LP18 family has 256 bytes of register RAM, an expanded interrupt system, and three timer/counters. 8051 Clock Frequency FX2LP18 has an on-chip oscillator circuit that uses an external 24 MHz (±100-ppm) crystal with the following characteristics: ■ Parallel resonant ■ Fundamental mode ■ 500 µW drive level ■ 12 pF (5% tolerance) load capacitors An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz, as required by the transceiver/PHY; internal counters divide it down for use as the 8051 clock. The default 8051 clock frequency is 12 MHz. The clock frequency of the 8051 can be changed by the 8051 through the CPUCS register, dynamically. Figure 1. Crystal Configuration C1 24 MHz 12 pF C2 12 pF 20 × PLL 12 pF capacitor values assumes a trace capacitance of 3 pF per side on a four-layer FR4 PCA The CLKOUT pin, which can be tristated and inverted using internal control bits, outputs the 50% duty cycle 8051 clock, at the selected 8051 clock frequency — 48, 24, or 12 MHz. Special Function Registers Certain 8051 Special Function Register (SFR) addresses are populated to provide fast access to critical FX2LP18 functions. These SFR additions are shown in Table 1 on page 5. Bold type indicates non standard, enhanced 8051 registers. The two SFR rows that end with ‘0’ and ‘8’ contain bit-addressable registers. The four I/O ports A–D use the SFR addresses used in the standard 8051 for ports 0–3, which are not implemented in FX2LP18. Because of the faster and more efficient SFR addressing, the FX2LP18 I/O ports are not addressable in external RAM space (using the MOVX instruction). FX2LP18 does not support the low speed signaling mode of 1.5 Mbps. Document Number: 001-06120 Rev *L Page 4 of 44 CY7C68053 Table 1. Special Function Registers x 8x 9x Ax Bx Cx Dx Ex Fx 0 IOA IOB IOC IOD SCON1 PSW ACC B INT2CLR IOE SBUF1 EICON EIE EIP 1 SP EXIF 2 DPL0 MPAGE 3 DPH0 OEB 4 DPL1 OEC 5 DPH1 OED 6 DPS OEE 7 PCON 8 TCON 9 TMOD SBUF0 A TL0 AUTOPTRH1 B TL1 C TH0 D TH1 AUTOPTRH2 GPIFSGLDATH E CKCON AUTOPTRL2 GPIFSGLDATLX F SCON0 OEA IE IP T2CON EP2468STAT EP01STAT RCAP2L AUTOPTRL1 EP24FIFOFLGS GPIFTRIG RCAP2H Reserved EP68FIFOFLGS Reserved AUTOPTRSET-UP I2C™ Bus FX2LP18 supports the I2C bus as a master only at 100 or 400 KHz. SCL and SDA pins have open-drain outputs and hysteresis inputs. These signals must be pulled up to either VCC or VCC_IO, even if no I2C device is connected. (Connecting to VCC_IO may be more convenient.) Buses This 56-pin package has an 8- or 16-bit ‘FIFO’ bidirectional data bus, multiplexed on I/O ports B and D. USB Boot Methods During the power up sequence, internal logic checks the I2C port for the connection of an EEPROM whose first byte is 0xC2. If found, it boot-loads the EEPROM contents into internal RAM (0xC2 load). If no EEPROM is present, an external processor must emulate an I2C slave. The FX2LP18 does not enumerate using internally stored descriptors (for example, Cypress’s VID/PID/DID is not used for enumeration).[1] ReNumeration™ TL2 TH2 GPIFSGLDATLNOX When first plugged into USB, the FX2LP18 enumerates automatically and downloads firmware and USB descriptor tables over the USB cable. Next, the FX2LP18 enumerates again, this time as a device defined by the downloaded information. This patented two-step process, called ReNumeration, happens instantly when the device is plugged in, with no hint that the initial download step has occurred. Two control bits in the USBCS (USB Control and Status) register control the ReNumeration process: DISCON and RENUM. To simulate a USB disconnect, the firmware sets DISCON to 1. To reconnect, the firmware clears DISCON to 0. Before reconnecting, the firmware sets or clears the RENUM bit to indicate whether the firmware or the Default USB Device handles device requests over endpoint zero: if RENUM = 0, the Default USB Device handles device requests; if RENUM = 1, the firmware does. Bus-Powered Applications The FX2LP18 fully supports bus-powered designs by enumerating with less than 100 mA as required by the USB 2.0 specification. Because the FX2LP18’s configuration is soft, one chip can take on the identities of multiple distinct USB devices. Note 1. The I2C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly. Document Number: 001-06120 Rev *L Page 5 of 44 CY7C68053 Interrupt System The FX2LP18 interrupts are described in this section. INT2 Interrupt Request and Enable Registers FX2LP18 implements an autovector feature for INT2. There are 27 INT2 (USB) vectors. See the MoBL-USB™ Technical Reference Manual (TRM) for more details. USB Interrupt Autovectors The main USB interrupt is shared by 27 interrupt sources. To save the code and processing time that is normally required to identify the individual USB interrupt source, the FX2LP18 provides a second level of interrupt vectoring, called ‘Autovectoring.’ When a USB interrupt is asserted, the FX2LP18 pushes the program counter onto its stack then jumps to address 0x0043, where it expects to find a ‘jump’ instruction to the USB interrupt service routine. The FX2LP18 jump instruction is encoded, as shown in Table 2. If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP18 substitutes its INT2VEC byte. Therefore, if the high byte (‘page’) of a jump-table address is preloaded at location 0x0044, the automatically inserted INT2VEC byte at 0x0045 directs the jump to the correct address out of the 27 addresses within the page. Table 2. INT2 USB Interrupts Priority INT2VEC Value Source Notes 1 00 SUDAV Setup data available 2 04 SOF Start of frame (or microframe) 3 08 SUTOK Setup token received 4 0C SUSPEND USB suspend request 5 10 USB RESET Bus reset 6 14 HISPEED Entered high speed operation 7 18 EP0ACK FX2LP18 ACK’d the control handshake 8 1C Reserved 9 20 EP0-IN EP0-IN ready to be loaded with data 10 24 EP0-OUT EP0-OUT has USB data 11 28 EP1-IN EP1-IN ready to be loaded with data 12 2C EP1-OUT EP1-OUT has USB data 13 30 EP2 IN: buffer available. OUT: buffer has data 14 34 EP4 IN: buffer available. OUT: buffer has data 15 38 EP6 IN: buffer available. OUT: buffer has data 16 3C EP8 IN: buffer available. OUT: buffer has data 17 40 IBN IN-Bulk-NAK (any IN endpoint) 18 44 Reserved 19 48 EP0PING EP0 OUT was pinged and it NAK’d 20 4C EP1PING EP1 OUT was pinged and it NAK’d 21 50 EP2PING EP2 OUT was pinged and it NAK’d 22 54 EP4PING EP4 OUT was pinged and it NAK’d 23 58 EP6PING EP6 OUT was pinged and it NAK’d 24 5C EP8PING EP8 OUT was pinged and it NAK’d 25 60 ERRLIMIT Bus errors exceeded the programmed limit 26 64 Reserved 27 68 28 6C 29 70 EP2ISOERR ISO EP2 OUT PID sequence error 30 74 EP4ISOERR ISO EP4 OUT PID sequence error 31 78 EP6ISOERR ISO EP6 OUT PID sequence error 32 7C EP8ISOERR ISO EP8 OUT PID sequence error Document Number: 001-06120 Rev *L Reserved Page 6 of 44 CY7C68053 Figure 2. Reset Timing Plots RESET# VIL RESET# VIL 1.8 V 1.62 V 1.8 V VCC VCC 0V 0V TRESET Power on Reset Document Number: 001-06120 Rev *L TRESET Powered Reset Page 7 of 44 CY7C68053 Reset and Wakeup Lowering Suspend Current The reset and wakeup pins are described in detail in this section. Good design practices for CMOS circuits dictate that any unused input pins must not be floating between VIL and VIH. Floating input pins will not damage the chip, but can substantially increase suspend current. To achieve the lowest suspend current, configure unused port pins as outputs. Connect unused input pins to ground. Some examples of pins that need attention during suspend are: Reset Pin The input pin, RESET#, resets the FX2LP18 when asserted. This pin has hysteresis and is active LOW. When a crystal is used with the CY7C68053, the reset period must allow for the stabilization of the crystal and the PLL. This reset period must be approximately 5 ms after VCC has reached 3.0 V. If the crystal input pin is driven by a clock signal the internal PLL stabilizes in 200 s after VCC has reached 3.0 V[2]. Figure 2 shows a power on reset condition and a reset applied during operation. A power on reset is defined as the time reset is asserted while power is being applied to the circuit. A powered reset is defined as a reset in which the FX2LP18 has previously been powered on and operating and the RESET# pin is asserted. Cypress provides an application note which describes and recommends power on reset implementation, which can be found on the Cypress web site. For more information on reset implementation for the MoBL-USB family of products, visit the Cypress web site at http://www.cypress.com. ■ Port pins. For Port A, B, D pins, take extra care in shared bus situations. ❐ Connect completely unused pins to VCC_IO or GND. ❐ In a single-master system, the firmware must output enable all the port pins and drive them high or low, before FX2LP18 enters the suspend state. ❐ In a multi-master system (FX2LP18 and another processor sharing a common data bus), when FX2LP18 is suspended, the external master must drive the pins high or low. The external master must not let the pins float. ■ CLKOUT. If CLKOUT is not used, it must be tri-stated during normal operation, but driven during suspend. ■ IFCLK, RDY0, RDY1. These pins must be pulled to VCC_IO or GND or driven by another chip. ■ CTL0-2. If tri-stated via GPIFIDLECTL, these pins must be pulled to VCC_IO or GND or driven by another chip. ■ RESET#, WAKEUP#. These pins must be pulled to VCC_IO or GND or driven by another chip during suspend. Table 3. Reset Timing Values Condition TRESET Power on reset with crystal 5 ms Power on reset with external clock 200 s + clock stability time Powered reset 200 s Wakeup Pins The 8051 puts itself and the rest of the chip into a power-down mode by setting PCON.0 = 1. This stops the oscillator and PLL. When WAKEUP is asserted by external logic, the oscillator restarts, after the PLL stabilizes, and then the 8051 receives a wakeup interrupt. This applies whether or not FX2LP18 is connected to the USB. Figure 3. FX2LP18 Internal Code Memory FFFF 7.5 kBytes USB regs and 4K FIFO buffers E200 E1FF 0.5 kBytes RAM E000 Data . The FX2LP18 exits the power down (USB suspend) state using one of the following methods: ■ . USB bus activity (if D+/D– lines are left floating, noise on these lines may indicate activity to the FX2LP18 and initiate a wakeup) ■ External logic asserts the WAKEUP pin ■ External logic asserts the PA3/WU2 pin . 3FFF The second wakeup pin, WU2, can also be configured as a general purpose I/O pin. This allows a simple external R-C network to be used as a periodic wakeup source. Note that WAKEUP is active LOW by default. 16 kBytes RAM Code and Data 0000 Note 2. If the external clock is powered at the same time as the CY7C680xx and has a stabilization wait period, it must be added to the 200 s. Document Number: 001-06120 Rev *L Page 8 of 44 CY7C68053 Program/Data RAM Endpoint RAM This section describes the FX2LP18 RAM. This section describes the FX2LP18 Endpoint RAM. Size Size The FX2LP18 has 16 kBytes of internal program/data RAM. No USB control registers appear in this space. ■ 3 × 64 bytes (Endpoints 0, 1) ■ 8 × 512 bytes (Endpoints 2, 4, 6, 8) Memory maps are shown in Figure 3 and Figure 4. Organization Internal Code Memory This mode implements the internal 16-kByte block of RAM (starting at 0) as combined code and data memory. Only the internal 16 kBytes and scratch pad 0.5 kBytes RAM spaces have the following access: ■ EP0 ■ Bidirectional endpoint zero, 64-byte buffer ■ EP1IN, EP1OUT ■ USB download ■ 64-byte buffers: bulk or interrupt ■ USB upload ■ EP2, 4, 6, 8 ■ Setup data pointer ■ ■ I2C interface boot load Eight 512-byte buffers: bulk, interrupt, or isochronous. EP4 and EP8 can be double buffered, while EP2 and 6 can be double, triple, or quad buffered. For high speed endpoint configuration options, see Figure 5. Register Addresses Figure 4. Register Address Memory FFFF 4 kBytes EP2-EP8 buffers (8 x 512) F000 EFFF 2 kBytes RESERVED E800 E7FF E7C0 E7BF E780 E77F E740 E73F E700 E6FF E500 E4FF E480 E47F E400 E3FF E200 E1FF 64 Bytes EP1IN 64 Bytes EP1OUT 64 Bytes EP0 IN/OUT 64 Bytes RESERVED Setup Data Buffer A separate 8-byte buffer at 0xE6B8-0xE6BF holds the setup data from a CONTROL transfer. Endpoint Configurations (High Speed Mode) Endpoints 0 and 1 are the same for every configuration. Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can be either BULK or INTERRUPT. The endpoint buffers can be configured in any one of the 12 configurations shown in the vertical columns of Figure 5. When operating in full speed BULK mode only the first 64 bytes of each buffer are used. For example, in high speed the maximum packet size is 512 bytes, but in full speed it is 64 bytes. Even though a buffer is configured to be a 512 byte buffer, in full speed only the first 64 bytes are used. The unused endpoint buffer space is not available for other operations. An example endpoint configuration is: EP2–1024 double buffered; EP6–512 quad buffered (column 8). 8051 Addressable Registers (512) Reserved (128) 128 Bytes GPIF Waveforms Reserved (512) 512 Bytes E000 8051 xdata RAM Document Number: 001-06120 Rev *L Page 9 of 44 CY7C68053 Figure 5. Endpoint Configuration EP0 IN&OUT 64 64 64 64 64 64 64 64 64 64 64 64 EP1 IN 64 64 64 64 64 64 64 64 64 64 64 64 EP1 OUT 64 64 64 64 64 64 64 64 64 64 64 64 EP2 EP2 EP2 EP2 EP2 EP2 EP2 EP2 EP2 EP2 512 512 512 512 512 512 512 512 512 512 512 512 EP4 EP4 512 512 512 512 512 512 512 512 512 512 512 512 EP6 EP6 EP6 EP6 EP6 EP6 512 512 512 512 512 512 512 512 512 1024 1024 512 512 1 2 1024 1024 512 512 512 512 4 5 3 1024 1024 EP6 EP6 EP6 512 512 512 512 EP6 512 1024 512 EP8 512 1024 1024 1024 512 EP8 512 1024 1024 512 EP4 EP8 1024 EP2 EP2 512 512 1024 512 512 512 7 8 6 1024 9 1024 1024 EP8 EP8 512 512 512 512 10 11 1024 1024 1024 12 Default Full Speed Alternate Settings Table 4. Default Full Speed Alternate Settings[3, 4] Alternate Setting 0 1 2 3 ep0 64 64 64 64 ep1out 0 64 bulk 64 int 64 int ep1in 0 64 bulk 64 int 64 int ep2 0 64 bulk out (2×) 64 int out (2×) 64 iso out (2×) ep4 0 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×) ep6 0 64 bulk in (2×) 64 int in (2×) 64 iso in (2×) ep8 0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×) Default High Speed Alternate Settings Table 5. Default High Speed Alternate Settings[3, 4] Alternate Setting 0 1 2 3 ep0 64 64 64 64 ep1out 0 512 bulk[5] 64 int 64 int ep1in 0 512 bulk[5] ep2 0 512 bulk out (2×) 64 int 64 int 512 int out (2×) 512 iso out (2×) ep4 0 512 bulk out (2×) 512 bulk out (2×) 512 bulk out (2×) ep6 0 512 bulk in (2×) 512 int in (2×) 512 iso in (2×) ep8 0 512 bulk in (2×) 512 bulk in (2×) 512 bulk in (2×) Notes 3. ‘0’ means ‘not implemented.’ 4. ‘2×’ means ‘double buffered.’ 5. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. Nnever transfer packets larger than 64 bytes to EP1. Document Number: 001-06120 Rev *L Page 10 of 44 CY7C68053 External FIFO Interface GPIF and FIFO Clock Rates The architecture, control signals, and clock rates are presented in this section. An 8051 register bit selects one of two frequencies for the internally supplied interface clock: 30 MHz and 48 MHz. Alternatively, an externally supplied clock of 5 MHz–48 MHz feeding the IFCLK pin can be used as the interface clock. IFCLK can be configured to function as an output clock when the GPIF and FIFOs are internally clocked. An output enable bit in the IFCONFIG register turns this clock output off. Another bit within the IFCONFIG register inverts the IFCLK signal whether internally or externally sourced. Architecture The FX2LP18 slave FIFO architecture has eight 512-byte blocks in the endpoint RAM that directly serve as FIFO memories and are controlled by FIFO control signals (such as IFCLK, SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags). In operation, some of the eight RAM blocks fill or empty from the SIE while the others are connected to the I/O transfer logic. The transfer logic takes two forms: the GPIF for internally generated control signals or the slave FIFO interface for externally controlled transfers. Master/Slave Control Signals The FX2LP18 endpoint FIFOs are implemented as eight physically distinct 256x16 RAM blocks. The 8051/SIE can switch any of the RAM blocks between two domains, the USB (SIE) domain and the 8051-I/O Unit domain. This switching is instantaneous, giving zero transfer time between ‘USB FIFOs’ and ‘Slave FIFOs’. Because they are physically the same memory, no bytes are actually transferred between buffers. At any given time, some RAM blocks are filling and emptying with USB data under SIE control, while other RAM blocks are available to the 8051, the I/O control unit, or both. The RAM blocks operate as single port in the USB domain, and dual port in the 8051-I/O domain. The blocks can be configured as single, double, triple, or quad buffered as previously shown. The I/O control unit implements either an internal master (M for master) or external master (S for Slave) interface. In Master (M) mode, the GPIF internally controls FIFOADR[1:0] to select a FIFO. The two ready (RDY) pins can be used as flag inputs from an external FIFO or other logic. The GPIF can be run from either an internally derived clock or externally supplied clock (IFCLK), at a rate that transfers data up to 96 megabytes/s (48 MHz IFCLK with 16-bit interface). In Slave (S) mode, the FX2LP18 accepts either an internally derived clock or externally supplied clock (IFCLK, maximum frequency 48 MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals from external logic. When using an external IFCLK, the external clock must be present before switching to the external clock with the IFCLKSRC bit. Each endpoint can individually be selected for byte or word operation by an internal configuration bit, and a Slave FIFO Output Enable signal (SLOE) enables data of the selected width. External logic must insure that the output enable signal is inactive when writing data to a slave FIFO. The slave interface can also operate asynchronously, where the SLRD and SLWR signals act directly as strobes, rather than a clock qualifier as in synchronous mode. The signals SLRD, SLWR, SLOE, and PKTEND are gated by the signal SLCS#. Document Number: 001-06120 Rev *L GPIF The GPIF is a flexible 8- or 16-bit parallel interface driven by a user programmable finite state machine. It allows the CY7C68053 to perform local bus mastering, and can implement a wide variety of protocols such as ATA interface, parallel printer port, and Utopia. The GPIF has three programmable control outputs (CTL), and two general purpose ready inputs.The data bus width can be 8 or 16 bits. Each GPIF vector defines the state of the control outputs, and determines what state a ready input (or multiple inputs) must be before proceeding. The GPIF vector can be programmed to advance a FIFO to the next data value, advance an address, and so on. A sequence of the GPIF vectors makes up a single waveform that is executed to perform the desired data move between the FX2LP18 and the external device. Three Control OUT Signals The 56-pin package brings out three of these signals, CTL0–CTL2. The 8051 programs the GPIF unit to define the CTL waveforms. CTLx waveform edges can be programmed to make transitions as fast as once per clock cycle (20.8 ns using a 48 MHz clock). Two Ready IN Signals The FX2LP18 package brings out all two Ready inputs (RDY0–RDY1). The 8051 programs the GPIF unit to test the RDY pins for GPIF branching. Long Transfer Mode In master mode, the 8051 appropriately sets GPIF transaction count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or GPIFTCB0) for unattended transfers of up to 232 transactions. The GPIF automatically throttles data flow to prevent under or overflow until the full number of requested transactions complete. The GPIF decrements the value in these registers to represent the current status of the transaction. Page 11 of 44 CY7C68053 ECC Generation[6] I2C Controller The MoBL-USB can calculate Error Correcting Codes (ECCs) on data that passes across its GPIF or Slave FIFO interfaces. There are two ECC configurations: two ECCs, each calculated over 256 bytes (SmartMedia Standard) and one ECC calculated over 512 bytes. FX2LP18 has one I2C port that is driven by two internal controllers. One controller automatically operates at boot time to load the VID/PID/DID, configuration byte, and firmware. The second controller is used by the 8051, once running, to control external I2C devices. The I2C port operates in master mode only. The ECC can correct any 1-bit error or detect any 2-bit error. I2C Port Pins ECC Implementation The I2C pins SCL and SDA must have external 2.2K ohm pull up resistors even if no EEPROM is connected to the FX2LP18. The value of the pull up resistors required may vary, depending on the combination of VCC_IO and the supply used for the EEPROM. The pull up resistors used must be such that when the EEPROM pulls SDA low, the voltage level meets the VIL specification of the FX2LP18. For example, if the EEPROM runs off a 3.3 V supply and VCC_IO is 1.8 V, the pull up resistors recommended are 10K ohmThis requirement may also vary depending on the devices being run on the I2C pins. Refer to the I2C specifications for details. The two ECC configurations are selected by the ECCM bit. ECCM = 0 Two 3-byte ECCs are each calculated over a 256-byte block of data. This configuration conforms to the SmartMedia Standard. This configuration writes any value to ECCRESET, then passes data across the GPIF or Slave FIFO interface. The ECC for the first 256 bytes of data is calculated and stored in ECC1. The ECC for the next 256 bytes is stored in ECC2. After the second ECC is calculated, the values in the ECCx registers do not change until ECCRESET is written again, even if more data is subsequently passed across the interface. ECCM = 1 One 3-byte ECC is calculated over a 512-byte block of data. This configuration writes any value to ECCRESET then passes data across the GPIF or Slave FIFO interface. The ECC for the first 512 bytes of data is calculated and stored in ECC1; ECC2 is unused. After the ECC is calculated, the value in ECC1 does not change until ECCRESET is written again, even if more data is subsequently passed across the interface. External EEPROM device address pins must be configured properly. See Table 6 for configuring the device address pins. If no EEPROM is connected to the I2C port, EEPROM emulation is required by an external processor. This is because the FX2LP18 comes out of reset with the DISCON bit set, so the device will not enumerate without an EEPROM (C2 load) or EEPROM emulation. Table 6. Strap Boot EEPROM Address Lines to these Values Bytes Example EEPROM A2 A1 A0 16 24AA00[8] N/A N/A N/A USB Uploads and Downloads 128 24AA01 0 0 0 The core has the ability to directly edit the data contents of the internal 16-kByte RAM and of the internal 512-byte scratch pad RAM using a vendor-specific command. This capability is normally used when ‘soft’ downloading user code and is available only to and from internal RAM, only when the 8051 is held in reset. The available RAM spaces are 16 kBytes from 0x0000–0x3FFF (code/data) and 512 bytes from 0xE000–0xE1FF (scratch pad data RAM)[7]. 256 24AA02 0 0 0 4K 24AA32 0 0 1 8K 24AA64 0 0 1 16K 24AA128 0 0 1 Autopointer Access FX2LP18 provides two identical autopointers. They are similar to the internal 8051 data pointers, but with an additional feature: they can optionally increment after every memory access. The autopointers are available in external FX2LP18 registers, under control of a mode bit (AUTOPTRSET-UP.0). Using the external FX2LP18 autopointer access (at 0xE67B – 0xE67C) allows the autopointer to access all RAM. Also, the autopointers can point to any FX2LP18 register or endpoint buffer space. I2C Interface Boot Load Access At power on reset the I2C interface boot loader loads the VID/PID/DID and configuration bytes and up to 16 kBytes of program/data. The available RAM spaces are 16 kBytes from 0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The 8051 is reset. I2C interface boot loads only occur after power on reset. I2C Interface General Purpose Access The 8051 can control peripherals connected to the I2C bus using the I2CTL and I2DAT registers. FX2LP18 provides I2C master control only, it is never an I2C slave. Notes 6. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation. 7. After the data is downloaded from the host, a ‘loader’ can execute from internal RAM in order to transfer downloaded data to external memory. 8. This EEPROM does not have address pins. Document Number: 001-06120 Rev *L Page 12 of 44 CY7C68053 Pin Assignments Figure 6 identifies all signals for the package. It is followed by the pin diagram.Three modes are available: Port, GPIF master, and Slave FIFO. These modes define the signals on the right edge of the diagram. The 8051 selects the interface mode using the IFCONFIG[1:0] register bits. Port mode is the power on default configuration. Figure 6. Signals Port XTALIN XTALOUT RESET# WAKEUP# SCL SDA Document Number: 001-06120 Rev *L PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GPIF Master FD[15] FD[14] FD[13] FD[12] FD[11] FD[10] FD[9] FD[8] FD[7] FD[6] FD[5] RDY0 RDY1 CTL0 CTL1 CTL2 INT0#/PA0 INT1#/PA1 Slave FIFO FD[15] FD[14] FD[13] FD[12] FD[11] FD[10] FD[9] FD[8] FD[7] FD[6] FD[5] FD[4] FD[3] FD[2] FD[1] FD[0] SLRD SLWR Page 13 of 44 CY7C68053 Figure 7. CY7C68053 56-pin VFBGA Pin Assignment - Top View 1 2 3 4 5 6 7 8 A 1A 2A 3A 4A 5A 6A 7A 8A B 1B 2B 3B 4B 5B 6B 7B 8B C 1C 2C 3C 4C 5C 6C 7C 8C D 1D 2D 7D 8D E 1E 2E 7E 8E F 1F 2F 3F 4F 5F 6F 7F 8F G 1G 2G 3G 4G 5G 6G 7G 8G H 1H 2H 3H 4H 5H 6H 7H 8H Document Number: 001-06120 Rev *L Page 14 of 44 CY7C68053 CY7C68053 Pin Descriptions Table 7. FX2LP18 Pin Descriptions[9] 56 VFBGA Name Type Default Description 2D AVCC Power N/A Analog VCC. Connect this pin to 3.3 V power source. This signal provides power to the analog section of the chip. Provide an appropriate bulk/bypass capacitance for this supply rail. 1D AVCC Power N/A Analog VCC. Connect this pin to 3.3 V power source. This signal provides power to the analog section of the chip. 2F AGND Ground N/A Analog Ground. Connect this pin to ground with as short a path as possible. Analog Ground. Connect to this pin ground with as short a path as possible. 1F AGND Ground N/A 1E DMINUS I/O/Z Z USB D– Signal. Connect this pin to the USB D– signal. 2E DPLUS I/O/Z Z USB D+ Signal. Connect this pin to the USB D+ signal. 8B RESET# Input N/A Active LOW Reset. This pin resets the entire chip. See Reset and Wakeup on page 8 for details. Input N/A Crystal Input. Connect this signal to a 24 MHz parallel resonant, fundamental mode crystal and load capacitor to GND. It is also correct to drive XTALIN with an external 24 MHz square wave derived from another clock source. Crystal Output. Connect this signal to a 24 MHz parallel resonant, fundamental mode crystal and load capacitor to GND. If an external clock is used to drive XTALIN, leave this pin open. 1C XTALIN 2C XTALOUT Output N/A 2B CLKOUT O/Z 12 MHz CLKOUT. 12, 24, or 48 MHz clock, phase locked to the 24 MHz input clock. The 8051 defaults to 12 MHz operation. The 8051 may tri-state this output by setting CPUCS.1 = 1. I/O/Z I (PA0) Multiplexed pin whose function is selected by PORTACFG.0 PA0 is a bidirectional I/O port pin. INT0# is the active LOW 8051 INT0 interrupt input signal, which is either edge triggered (IT0 = 1) or level triggered (IT0 = 0). I/O/Z I (PA1) Multiplexed pin whose function is selected by PORTACFG.1 PA1 is a bidirectional I/O port pin. INT1# is the active LOW 8051 INT1 interrupt input signal, which is either edge triggered (IT1 = 1) or level triggered (IT1 = 0). I/O/Z I (PA2) Multiplexed pin whose function is selected by two bits: IFCONFIG[1:0]. PA2 is a bidirectional I/O port pin. SLOE is an input-only output enable with programmable polarity (FIFOPINPOLAR.4) for the slave FIFO’s connected to FD[7:0] or FD[15:0]. I (PA3) Multiplexed pin whose function is selected by: WAKEUP.7 and OEA.3 PA3 is a bidirectional I/O port pin. WU2 is an alternate source for USB Wakeup, enabled by WU2EN bit (WAKEUP.1) and polarity set by WU2POL (WAKEUP.4). If the 8051 is in suspend and WU2EN = 1, a transition on this pin starts up the oscillator and interrupts the 8051 to allow it to exit the suspend mode. Asserting this pin inhibits the chip from suspending, if WU2EN = 1. Port A 8G PA0 or INT0# 6G PA1 or INT1# 8F PA2 or SLOE 7F PA3 or WU2 I/O/Z Note 9. Do not leave unused inputs floating. Tie either HIGH or LOW as appropriate. Only pull outputs up or down to ensure signals at power up and in standby. Do not drive any pins while the device is powered down. Document Number: 001-06120 Rev *L Page 15 of 44 CY7C68053 Table 7. FX2LP18 Pin Descriptions[9] (continued) 56 VFBGA Name Type Default Description I/O/Z I (PA4) Multiplexed pin whose function is selected by IFCONFIG[1:0]. PA4 is a bidirectional I/O port pin. FIFOADR0 is an input-only address select for the slave FIFOs connected to FD[7:0] or FD[15:0]. I/O/Z I (PA5) Multiplexed pin whose function is selected by IFCONFIG[1:0]. PA5 is a bidirectional I/O port pin. FIFOADR1 is an input-only address select for the slave FIFOs connected to FD[7:0] or FD[15:0]. I/O/Z I (PA6) Multiplexed pin whose function is selected by the IFCONFIG[1:0] bits. PA6 is a bidirectional I/O port pin. PKTEND is an input that commits the FIFO packet data to the endpoint and whose polarity is programmable using FIFOPINPOLAR.5. 6F PA4 or FIFOADR0 8C PA5 or FIFOADR1 7C PA6 or PKTEND 6C PA7 or FLAGD or SLCS# I/O/Z I (PA7) Multiplexed pin whose function is selected by the IFCONFIG[1:0] and PORTACFG.7 bits. PA7 is a bidirectional I/O port pin. FLAGD is a programmable slave FIFO output status flag signal. SLCS# gates all other slave FIFO enable/strobes 3H PB0 or FD[0] I/O/Z I (PB0) Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB0 is a bidirectional I/O port pin. FD[0] is the bidirectional FIFO/GPIF data bus. 4F PB1 or FD[1] I/O/Z I (PB1) Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB1 is a bidirectional I/O port pin. FD[1] is the bidirectional FIFO/GPIF data bus. 4H PB2 or FD[2] I/O/Z I (PB2) Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB2 is a bidirectional I/O port pin. FD[2] is the bidirectional FIFO/GPIF data bus. 4G PB3 or FD[3] I/O/Z I (PB3) Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB3 is a bidirectional I/O port pin. FD[3] is the bidirectional FIFO/GPIF data bus. 5H PB4 or FD[4] I/O/Z I (PB4) Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB4 is a bidirectional I/O port pin. FD[4] is the bidirectional FIFO/GPIF data bus. 5G PB5 or FD[5] I/O/Z I (PB5) Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB5 is a bidirectional I/O port pin. FD[5] is the bidirectional FIFO/GPIF data bus. 5F PB6 or FD[6] I/O/Z I (PB6) Multiplexed pin whose function is selected by IFCONFIG[1:0]. PB6 is a bidirectional I/O port pin. FD[6] is the bidirectional FIFO/GPIF data bus. 6H PB7 or FD[7] I/O/Z I (PB7) Multiplexed pin whose function is selected IFCONFIG[1:0]. PB7 is a bidirectional I/O port pin. FD[7] is the bidirectional FIFO/GPIF data bus. Port B Document Number: 001-06120 Rev *L Page 16 of 44 CY7C68053 Table 7. FX2LP18 Pin Descriptions[9] (continued) 56 VFBGA Name Type Default Description PORT D 8A PD0 or FD[8] I/O/Z I (PD0) Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[8] is the bidirectional FIFO/GPIF data bus. 7A PD1 or FD[9] I/O/Z I (PD1) Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[9] is the bidirectional FIFO/GPIF data bus. 6B PD2 or FD[10] I/O/Z I (PD2) Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[10] is the bidirectional FIFO/GPIF data bus. 6A PD3 or FD[11] I/O/Z I (PD3) Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[11] is the bidirectional FIFO/GPIF data bus. 3B PD4 or FD[12] I/O/Z I (PD4) Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[12] is the bidirectional FIFO/GPIF data bus. 3A PD5 or FD[13] I/O/Z I (PD5) Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[13] is the bidirectional FIFO/GPIF data bus. 3C PD6 or FD[14] I/O/Z I (PD6) Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[14] is the bidirectional FIFO/GPIF data bus. 2A PD7 or FD[15] I/O/Z I (PD7) Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[15] is the bidirectional FIFO/GPIF data bus. 1A RDY0 or SLRD 1B RDY1 or SLWR 7H CTL0 or FLAGA 7G CTL1 or FLAGB 8H CTL2 or FLAGC 2G IFCLK Input Input O/Z O/Z O/Z I/O/Z Document Number: 001-06120 Rev *L N/A Multiplexed pin whose function is selected by IFCONFIG[1:0]. RDY0 is a GPIF input signal. SLRD is the input only read strobe with programmable polarity (FIFOPINPOLAR.3) for the slave FIFOs connected to FD[7:0] or FD[15:0]. N/A Multiplexed pin whose function is selected by IFCONFIG[1:0]. RDY1 is a GPIF input signal. SLWR is the input only write strobe with programmable polarity (FIFOPINPOLAR.2) for the slave FIFOs connected to FD[7:0] or FD[15:0]. H Multiplexed pin whose function is selected by IFCONFIG[1:0]. CTL0 is a GPIF control output. FLAGA is a programmable slave FIFO output status flag signal. Defaults to programmable for the FIFO selected by the FIFOADR[1:0] pins. H Multiplexed pin whose function is selected by IFCONFIG[1:0]. CTL1 is a GPIF control output. FLAGB is a programmable slave FIFO output status flag signal. Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins. H Multiplexed pin whose function is selected IFCONFIG[1:0]. CTL2 is a GPIF control output. FLAGC is a programmable slave FIFO output status flag signal. Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins. Z Interface clock, used to synchronous clock data into or out of the slave FIFOs. IFCLK also serves as a timing reference for all slave FIFO control signals and GPIF. When internal clocking is used (IFCONFIG.7 = 1) the IFCLK pin can be configured to output 30 or 48 MHz by bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be inverted, whether internally or externally sourced, by setting the bit IFCONFIG.4 =1. Page 17 of 44 CY7C68053 Table 7. FX2LP18 Pin Descriptions[9] (continued) 56 VFBGA Name Type Default Description Input N/A USB Wakeup. If the 8051 is in suspend, asserting this pin starts up the oscillator and interrupts the 8051 to allow it to exit the suspend mode. Holding WAKEUP asserted inhibits the MoBL-USB chip from suspending. This pin has programmable polarity (WAKEUP.4). 7B WAKEUP 3F SCL OD Z Clock for the I2C interface. Connect to VCC_IO or VCC with a 2.2K–10K pull up resistor. (An I2C peripheral is required.) 3G SDA OD Z Data for the I2C interface. Connect to VCC_IO or VCC with a 2.2K–10K pull up resistor. (An I2C peripheral is required.) 5A VCC_IO Power N/A VCC. Connect this pin to 1.8V to 3.3 V power source. Provide the appropriate bulk and bypass capacitance for this supply rail. 5B VCC_IO Power N/A VCC. Connect this pin to 1.8V to 3.3 V power source. 7E VCC_IO Power N/A VCC. Connect this pin to 1.8 V to 3.3 V power source. 8E VCC_IO Power N/A VCC. Connect this pin to 1.8V to 3.3 V power source. 5C VCC_D Power N/A VCC. Connect this pin to 1.8V power source. (Supplies power to internal digital 1.8 V circuits.) Provide the appropriate bulk and bypass capacitance for this supply rail. 1G VCC_A Power N/A VCC. Connect this pin to 1.8V power source. (Supplies power to internal analog 1.8 V circuits.) 1H GND Ground N/A Ground 2H GND Ground N/A Ground 4A GND Ground N/A Ground 4B GND Ground N/A Ground 4C GND Ground N/A Ground 7D GND Ground N/A Ground 8D GND Ground N/A Ground Document Number: 001-06120 Rev *L Page 18 of 44 CY7C68053 Register Summary FX2LP18 register bit definitions are described in the MoBL-USB FX2LP18 TRM in greater detail. Table 8. FX2LP18 Register Summary Hex E400 E480 E50D E600 E601 E602 E603 E604 E605 E606 E607 E608 E609 Size Name Description GPIF Waveform Memories GPIF Waveform 128 WAVEDATA descriptor 0, 1, 2, 3 data 128 Reserved GENERAL CONFIGURATION General Purpose ConfiguraGPCR2 tion Register 2 1 CPUCS CPU Control and Status Interface Configuration 1 IFCONFIG (Ports, GPIF, Slave FIFOs) [10] Slave FIFO FLAGA and 1 PINFLAGSAB FLAGB pin configuration Slave FIFO FLAGC and 1 PINFLAGSCD[10] FLAGD pin configuration [10] Restore FIFOs to default 1 FIFORESET state 1 BREAKPT Breakpoint control 1 BPADDRH Breakpoint address H 1 BPADDRL Breakpoint address L 1 Reserved Reserved [10] Slave FIFO interface pins 1 FIFOPINPOLAR polarity E60A 1 REVID Chip revision E60B 1 REVCTL[10] UDMA Chip revision control E60C 1 hold time GPIFHOLDAMOUNT MSTB (for UDMA) 3 Reserved ENDPOINT CONFIGURATION Endpoint 1-OUT EP1OUTCFG configuration Endpoint 1-IN EP1INCFG configuration EP2CFG Endpoint 2 configuration EP4CFG Endpoint 4 configuration EP6CFG Endpoint 6 configuration EP8CFG Endpoint 8 configuration Reserved EP2FIFOCFG[10] Endpoint 2/Slave FIFO configuration [10] EP4FIFOCFG Endpoint 4/Slave FIFO configuration EP6FIFOCFG[10] Endpoint 6/Slave FIFO configuration [10] EP8FIFOCFG Endpoint 8/Slave FIFO configuration Reserved 2 AUTOIN EP2AUTOINLENH[10 Endpoint packet length H 2 AUTOIN EP2AUTOINLENL[10] Endpoint packet length L [10 EP4AUTOINLENH Endpoint 4 AUTOIN ] packet length H 4 AUTOIN EP4AUTOINLENL[10] Endpoint packet length L EP6AUTOINLENH[10 Endpoint 6 AUTOIN ] packet length H 6 AUTOIN EP6AUTOINLENL[10] Endpoint packet length L [10 EP8AUTOINLENH Endpoint 8 AUTOIN ] packet length H E610 1 E611 1 E612 E613 E614 E615 1 1 1 1 2 E618 1 E619 1 E61A 1 E61B 1 E61C 4 E620 1 E621 1 E622 1 E623 1 E624 1 E625 1 E626 1 [10] Endpoint E627 1 EP8AUTOINLENL E628 E629 E62A E62B 1 1 1 1 ECCCFG ECCRESET ECC1B0 ECC1B1 8 AUTOIN packet length L ECC Configuration ECC Reset ECC1 Byte 0 address ECC1 Byte 1 address b7 b6 b5 b4 b3 b2 b1 b0 Default D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW Reserved Reserved Reserved Reserved Reserved Reserved 00000000 R 0 0 CLKINV CLKOE 8051RES 00000010 rrbbbbbr IFCLKSRC 3048MHZ IFCLKOE IFCLKPOL ASYNC GSTATE IFCFG1 IFCFG0 10000000 RW FLAGB3 FLAGB2 FLAGB1 FLAGB0 FLAGA3 FLAGA2 FLAGA1 FLAGA0 00000000 RW FLAGD3 FLAGD2 FLAGD1 FLAGD0 FLAGC3 FLAGC2 FLAGC1 FLAGC0 00000000 RW NAKALL 0 0 0 EP3 EP2 EP1 EP0 0 A15 A7 0 0 A14 A6 0 0 A13 A5 0 0 A12 A4 0 BREAK A11 A3 0 BPPULSE A10 A2 0 BPEN A9 A1 0 0 A8 A0 0 00000000 rrrrbbbr xxxxxxxx RW xxxxxxxx RW 00000000 rrrrrrbb FULL_SPEED Reserved _ONLY PORTCSTB CLKSPD1 CLKSPD0 Access xxxxxxxx W 0 0 PKTEND SLOE SLRD SLWR EF FF 00000000 rrbbbbbb rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 0 0 0 0 0 0 dyn_out enh_pkt RevA 00000001 R 00000000 rrrrrrbb 0 0 0 0 0 0 VALID 0 TYPE1 TYPE0 0 0 VALID 0 TYPE1 TYPE0 0 0 VALID VALID VALID VALID DIR DIR DIR DIR TYPE1 TYPE1 TYPE1 TYPE1 TYPE0 TYPE0 TYPE0 TYPE0 SIZE 0 SIZE 0 0 0 0 0 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb 0 0 0 0 0 PL10 PL9 PL8 00000010 rrrrrbbb PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW 0 0 0 0 0 0 PL9 PL8 00000010 rrrrrrbb PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW 0 0 0 0 0 PL10 PL9 PL8 00000010 rrrrrbbb PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW 0 0 0 0 0 0 PL9 PL8 00000010 rrrrrrbb PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW 0 x LINE15 LINE7 0 x LINE14 LINE6 0 x LINE13 LINE5 0 x LINE12 LINE4 0 x LINE11 LINE3 0 x LINE10 LINE2 0 x LINE9 LINE1 ECCM x LINE8 LINE0 HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb 0 0 10100000 brbbrrrr 0 0 10100000 brbbrrrr BUF1 0 BUF1 0 BUF0 0 BUF0 0 10100010 bbbbbrbb 10100000 bbbbrrrr 11100010 bbbbbrbb 11100000 bbbbrrrr 00000000 rrrrrrrb 00000000 W 00000000 R 00000000 R Note 10. Read and writes to these registers may require synchronization delay, see MoBL-USB FX2LP18 Technical Reference Manual for ‘Synchronization Delay.’ Document Number: 001-06120 Rev *L Page 19 of 44 CY7C68053 Table 8. FX2LP18 Register Summary (continued) Hex Size Name E62C 1 ECC1B2 E62D 1 ECC2B0 E62E 1 ECC2B1 Description ECC1 Byte 2 address ECC2 Byte 0 address ECC2 Byte 1 address E62F E630 H.S. E630 F.S. E631 H.S. E631 F.S E632 H.S. E632 F.S E633 H.S. E633 F.S ECC2 Byte 2 address Endpoint 2/Slave FIFO programmable flag H Endpoint 2/Slave FIFO programmable flag H Endpoint 2/Slave FIFO programmable flag L Endpoint 2/Slave FIFO programmable flag L Endpoint 4/Slave FIFO programmable flag H Endpoint 4/Slave FIFO programmable flag H Endpoint 4/Slave FIFO programmable flag L Endpoint 4/Slave FIFO programmable flag L 1 ECC2B2 EP2FIFOPFH[10] 1 EP2FIFOPFH[10] 1 EP2FIFOPFL[10] 1 EP2FIFOPFL[10] 1 EP4FIFOPFH[10] 1 EP4FIFOPFH[10] 1 EP4FIFOPFL[10] 1 EP4FIFOPFL[10] 1 EP6FIFOPFH[10] 1 EP6FIFOPFH[10] 1 EP6FIFOPFL[10] 1 EP6FIFOPFL[10] 1 EP8FIFOPFH[10] 1 EP8FIFOPFH[10] 1 EP8FIFOPFL[10] 1 EP8FIFOPFL[10] 8 Reserved E640 1 EP2ISOINPKTS E641 1 EP4ISOINPKTS E642 1 EP6ISOINPKTS E643 1 EP8ISOINPKTS E644 E648 E649 4 1 7 E650 1 Reserved INPKTEND[10] OUTPKTEND[10] INTERRUPTS EP2FIFOIE[10] E634 H.S. E634 F.S E635 H.S. E635 F.S E636 H.S. E636 F.S E637 H.S. E637 F.S 1 [10,11] E651 1 EP2FIFOIRQ E652 1 EP4FIFOIE[10] E653 1 EP4FIFOIRQ[10,11] 1 EP6FIFOIE[10] E654 [10,11] E655 1 EP6FIFOIRQ E656 1 EP8FIFOIE[10] E657 1 EP8FIFOIRQ[10,11] E658 1 IBNIE E659 1 IBNIRQ[11] E65A 1 NAKIE E65B 1 NAKIRQ[11] E65C E65D 1 1 USBIE USBIRQ[11] Endpoint 6/Slave FIFO programmable flag H Endpoint 6/Slave FIFO programmable flag H Endpoint 6/Slave FIFO programmable flag L Endpoint 6/Slave FIFO programmable flag L Endpoint 8/Slave FIFO programmable flag H Endpoint 8/Slave FIFO programmable flag H Endpoint 8/Slave FIFO programmable flag L Endpoint 8/Slave FIFO programmable flag L EP2 (if ISO) IN packets per frame (1-3) EP4 (if ISO) IN packets per frame (1-3) EP6 (if ISO) IN packets per frame (1-3) EP8 (if ISO) IN packets per frame (1-3) Force IN packet end Force OUT packet end Endpoint 2 Slave FIFO flag interrupt enable Endpoint 2 Slave FIFO flag interrupt request Endpoint 4 Slave FIFO flag interrupt enable Endpoint 4 Slave FIFO flag interrupt request Endpoint 6 Slave FIFO flag interrupt enable Endpoint 6 Slave FIFO flag interrupt request Endpoint 8 Slave FIFO flag interrupt enable Endpoint 8 Slave FIFO flag interrupt request IN-BULK-NAK interrupt enable IN-BULK-NAK interrupt request Endpoint Ping-NAK/IBN interrupt enable Endpoint Ping-NAK/IBN interrupt request USB interrupt enables USB interrupt requests b7 COL5 LINE15 LINE7 b6 COL4 LINE14 LINE6 b5 COL3 LINE13 LINE5 b4 COL2 LINE12 LINE4 b3 COL1 LINE11 LINE3 b2 COL0 LINE10 LINE2 b1 LINE17 LINE9 LINE1 b0 LINE16 LINE8 LINE0 Default Access 00000000 R 00000000 R 00000000 R COL5 COL4 COL2 COL1 IN:PKTS[1] IN:PKTS[0] OUT:PFC11 OUT:PFC10 0 0 PKTSTAT COL3 IN:PKTS[2] OUT:PFC12 COL0 DECIS 0 PFC9 PFC8 DECIS PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10 0 PFC9 PFC7 PFC6 PFC5 PFC3 PFC2 PFC1 PFC0 00000000 RW IN:PKTS[1] OUT:PFC7 IN:PKTS[0] OUT:PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW IN: PKTS[0] OUT:PFC9 PFC4 00000000 R 10001000 bbbbbrbb IN:PKTS[2] 10001000 bbbbbrbb OUT:PFC8 DECIS PKTSTAT 0 IN: PKTS[1] OUT:PFC10 0 0 PFC8 10001000 bbrbbrrb DECIS PKTSTAT 0 OUT:PFC10 OUT:PFC9 0 0 PFC8 10001000 bbrbbrrb PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW IN: PKTS[1] OUT:PFC7 IN: PKTS[0] OUT:PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW DECIS PKTSTAT IN:PKTS[2] OUT:PFC12 IN:PKTS[1] IN:PKTS[0] OUT:PFC11 OUT:PFC10 0 PFC9 PFC8 00001000 bbbbbrbb DECIS PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10 0 PFC9 PFC7 PFC6 PFC5 PFC3 PFC2 PFC1 PFC0 00000000 RW IN:PKTS[1] OUT:PFC7 IN:PKTS[0] OUT:PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW IN: PKTS[0] OUT:PFC9 PFC4 IN:PKTS[2] 00001000 bbbbbrbb OUT:PFC8 DECIS PKTSTAT 0 IN: PKTS[1] OUT:PFC10 0 0 PFC8 00001000 bbrbbrrb DECIS PKTSTAT 0 OUT:PFC10 OUT:PFC9 0 0 PFC8 00001000 bbrbbrrb PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW IN: PKTS[1] OUT:PFC7 IN: PKTS[0] OUT:PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW AADJ 0 0 0 0 0 INPPF1 INPPF0 00000001 brrrrrbb AADJ 0 0 0 0 0 INPPF1 INPPF0 00000001 brrrrrrr AADJ 0 0 0 0 0 INPPF1 INPPF0 00000001 brrrrrbb AADJ 0 0 0 0 0 INPPF1 INPPF0 00000001 brrrrrrr Skip Skip 0 0 0 0 0 0 EP3 EP3 EP2 EP2 EP1 EP1 EP0 EP0 0 0 0 0 EDGEPF PF EF FF 00000000 RW 0 0 0 0 0 PF EF FF 00000000 rrrrrbbb 0 0 0 0 EDGEPF PF EF FF 00000000 RW 0 0 0 0 0 PF EF FF 00000000 rrrrrbbb 0 0 0 0 EDGEPF PF EF FF 00000000 RW 0 0 0 0 0 PF EF FF 00000000 rrrrrbbb 0 0 0 0 EDGEPF PF EF FF 00000000 RW 0 0 0 0 0 PF EF FF 00000000 rrrrrbbb 0 0 EP8 EP6 EP4 EP2 EP1 EP0 00000000 RW 0 0 EP8 EP6 EP4 EP2 EP1 EP0 00xxxxxx rrbbbbbb EP8 EP6 EP4 EP2 EP1 EP0 0 IBN 00000000 RW xxxxxxxx W xxxxxxxx W EP8 EP6 EP4 EP2 EP1 EP0 0 IBN xxxxxx0x bbbbbbrb 0 0 EP0ACK EP0ACK HSGRANT HSGRANT URES URES SUSP SUSP SUTOK SUTOK SOF SOF SUDAV SUDAV 00000000 RW 0xxxxxxx rbbbbbbb Note 11. The register can only be reset, it cannot be set. Document Number: 001-06120 Rev *L Page 20 of 44 CY7C68053 Table 8. FX2LP18 Register Summary (continued) Hex Size Name E65E 1 EPIE E65F 1 EPIRQ[11] E660 E661 1 1 GPIFIE[10] GPIFIRQ[10] E662 1 USBERRIE E663 1 USBERRIRQ[11] E664 E665 1 1 ERRCNTLIM CLRERRCNT E666 1 INT2IVEC E667 E668 E669 1 1 7 Reserved INTSET-UP Reserved INPUT/OUTPUT E670 1 PORTACFG E671 1 PORTCCFG E672 1 PORTECFG E673 E677 E678 E679 E67A 4 1 1 1 1 Reserved Reserved I2CS I2DAT I2CTL E67B 1 XAUTODAT1 E67C 1 XAUTODAT2 E67D E67E 1 1 E67F 1 E680 E681 E682 E683 E684 E685 E686 E687 E688 1 1 1 1 1 1 1 1 2 E68A E68B E68C E68D E68E E68F E690 E691 E692 E694 E695 E696 E698 E699 E69A E69C E69D E69E 1 1 1 1 1 1 1 1 2 1 1 2 1 1 2 1 1 2 UDMA CRC UDMACRCH[10] UDMACRCL[10] UDMACRCQUALIFIER USB CONTROL USBCS SUSPEND WAKEUPCS TOGCTL USBFRAMEH USBFRAMEL MICROFRAME FNADDR Reserved ENDPOINTS EP0BCH[10] EP0BCL[10] Reserved EP1OUTBC Reserved EP1INBC EP2BCH[10] EP2BCL[10] Reserved EP4BCH[10] EP4BCL[10] Reserved EP6BCH[10] EP6BCL[10] Reserved EP8BCH[10] EP8BCL[10] Reserved E6A0 1 EP0CS E6A1 1 EP1OUTCS Description Endpoint interrupt enables Endpoint interrupt requests b7 b6 b5 b4 b3 b2 b1 b0 EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN 00000000 RW EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIFWF GPIFWF GPIFDONE 00000000 RW GPIFDONE 000000xx RW ISOEP8 ISOEP6 ISOEP4 ISOEP2 0 0 0 ERRLIMIT 00000000 RW ISOEP8 ISOEP6 ISOEP4 ISOEP2 0 0 0 ERRLIMIT 0000000x bbbbrrrb EC3 x EC2 x EC1 x EC0 x LIMIT3 x LIMIT2 x LIMIT1 x LIMIT0 x 0 I2V4 I2V3 I2V2 I2V1 I2V0 0 0 1 0 0 0 0 0 0 0 0 AV2EN 0 0 0 Reserved 0 AV4EN 10000000 R 00000000 RW I/O PORTA alternate configuration FLAGD SLCS 0 0 0 0 INT1 INT0 00000000 RW I/O PORTC alternate configuration I/O PORTE alternate configuration GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFA0 00000000 RW GPIFA8 T2EX INT6 RXD1OUT RXD0OUT T2OUT T1OUT T0OUT 00000000 RW I²C bus control and status I²C bus data I²C bus control Autoptr1 MOVX access, when APTREN = 1 Autoptr2 MOVX access, when APTREN = 1 START d7 0 STOP d6 0 LASTRD d5 0 ID1 d4 0 ID0 d3 0 BERR d2 0 ACK d1 STOPIE DONE d0 400KHZ 000xx000 bbbrrrrr xxxxxxxx RW 00000000 RW D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW UDMA CRC MSB UDMA CRC LSB CRC15 CRC7 CRC14 CRC6 CRC13 CRC5 CRC12 CRC4 CRC11 CRC3 CRC10 CRC2 CRC9 CRC1 CRC8 CRC0 01001010 RW 10111010 RW QENABLE 0 0 0 QSTATE QSIGNAL2 QSIGNAL1 HSM x WU2 Q 0 FC7 0 0 0 x WU S 0 FC6 0 FA6 0 x WU2POL R 0 FC5 0 FA5 0 x WUPOL I/O 0 FC4 0 FA4 DISCON x 0 EP3 0 FC3 0 FA3 NOSYNSOF x DPEN EP2 FC10 FC2 MF2 FA2 RENUM x WU2EN EP1 FC9 FC1 MF1 FA1 SIGRSUME x WUEN EP0 FC8 FC0 MF0 FA0 (BC15) (BC7) (BC14) BC6 (BC13) BC5 (BC12) BC4 (BC11) BC3 (BC10) BC2 (BC9) BC1 (BC8) BC0 xxxxxxxx RW xxxxxxxx RW 0 BC6 BC5 BC4 BC3 BC2 BC1 BC0 0xxxxxxx RW Endpoint 1 IN byte count Endpoint 2 byte count H Endpoint 2 byte count L 0 0 BC7/SKIP BC6 0 BC6 BC5 0 BC5 BC4 0 BC4 BC3 0 BC3 BC2 BC10 BC2 BC1 BC9 BC1 BC0 BC8 BC0 0xxxxxxx RW 00000xxx RW xxxxxxxx RW Endpoint 4 byte count H Endpoint 4 byte count L 0 BC7/SKIP 0 BC6 0 BC5 0 BC4 0 BC3 0 BC2 BC9 BC1 BC8 BC0 000000xx RW xxxxxxxx RW Endpoint 6 byte count H Endpoint 6 byte count L 0 BC7/SKIP 0 BC6 0 BC5 0 BC4 0 BC3 BC10 BC2 BC9 BC1 BC8 BC0 00000xxx RW xxxxxxxx RW Endpoint 8 byte count H Endpoint 8 byte count L 0 BC7/SKIP 0 BC6 0 BC5 0 BC4 0 BC3 0 BC2 BC9 BC1 BC8 BC0 000000xx RW xxxxxxxx RW HSNAK 0 0 0 0 0 BUSY STALL 10000000 bbbbbbrb 0 0 0 0 0 0 BUSY STALL 00000000 bbbbbbrb GPIF interrupt enable GPIF interrupt request USB error interrupt enables USB error interrupt requests USB error counter and limit Clear error counter EC3:0 Interrupt 2 (USB) autovector Interrupt 2 and 4 setup UDMA CRC qualifier USB control and status Put chip into suspend Wakeup control and status Toggle control USB frame count H USB frame count L Microframe count, 0-7 USB function address Endpoint 0 byte count H Endpoint 0 byte count L Endpoint 1 OUT byte count Endpoint 0 control and status Endpoint 1 OUT control and status Document Number: 001-06120 Rev *L Default Access RW xxxx0100 rrrrbbbb xxxxxxxx W 00000000 R QSIGNAL0 00000000 brrrbbbb x0000000 rrrrbbbb xxxxxxxx W xx000101 bbbbrbbb x0000000 rrrbbbbb 00000xxx R xxxxxxxx R 00000xxx R 0xxxxxxx R Page 21 of 44 CY7C68053 Table 8. FX2LP18 Register Summary (continued) Hex Size Name E6A2 1 EP1INCS E6A3 1 EP2CS E6A4 1 EP4CS E6A5 1 EP6CS E6A6 1 EP8CS E6A7 E6A8 E6A9 E6AA 1 1 1 1 EP2FIFOFLGS EP4FIFOFLGS EP6FIFOFLGS EP8FIFOFLGS E6AB 1 EP2FIFOBCH E6AC 1 EP2FIFOBCL E6AD 1 EP4FIFOBCH E6AE 1 EP4FIFOBCL E6AF 1 EP6FIFOBCH E6B0 1 EP6FIFOBCL E6B1 1 EP8FIFOBCH E6B2 1 EP8FIFOBCL E6B3 1 SUDPTRH E6B4 1 SUDPTRL E6B5 E6B8 1 2 8 SUDPTRCTL Reserved SET-UPDAT E6C0 1 GPIF GPIFWFSELECT E6C1 1 GPIFIDLECS E6C2 E6C3 E6C4 E6C5 1 1 1 1 GPIFIDLECTL GPIFCTLCFG Reserved Reserved FLOWSTATE E6C6 1 FLOWSTATE E6C7 1 FLOWLOGIC E6C8 1 FLOWEQ0CTL E6C9 1 FLOWEQ1CTL E6CA 1 FLOWHOLDOFF E6CB 1 FLOWSTB E6CC 1 FLOWSTBEDGE E6CD 1 FLOWSTBPERIOD E6CE 1 GPIFTCB3[10] E6CF 1 GPIFTCB2[10] E6D0 1 GPIFTCB1[10] E6D1 1 GPIFTCB0[10] 2 Reserved Reserved Description Endpoint 1 IN control and status Endpoint 2 control and status b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 BUSY STALL Default 00000000 bbbbbbrb Access 0 NPAK2 NPAK1 NPAK0 FULL EMPTY 0 STALL 00101000 rrrrrrrb Endpoint 4 control and status Endpoint 6 control and status Endpoint 8 control and status Endpoint 2 Slave FIFO flags Endpoint 4 Slave FIFO flags Endpoint 6 Slave FIFO flags Endpoint 8 Slave FIFO flags Endpoint 2 Slave FIFO total byte count H Endpoint 2 Slave FIFO total byte count L Endpoint 4 Slave FIFO total byte count H 0 0 NPAK1 NPAK0 FULL EMPTY 0 STALL 00101000 rrrrrrrb 0 NPAK2 NPAK1 NPAK0 FULL EMPTY 0 STALL 00000100 rrrrrrrb 0 0 NPAK1 NPAK0 FULL EMPTY 0 STALL 00000100 rrrrrrrb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PF PF PF PF EF EF EF EF FF FF FF FF 00000010 R 00000010 R 00000110 R 00000110 R 0 0 0 BC12 BC11 BC10 BC9 BC8 00000000 R BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R 0 BC10 BC9 BC8 00000000 R 0 0 0 0 Endpoint 4 Slave FIFO total byte count L Endpoint 6 Slave FIFO total byte count H Endpoint 6 Slave FIFO total byte count L Endpoint 8 Slave FIFO total byte count H Endpoint 8 Slave FIFO total byte count L Setup data pointer high address byte Setup data pointer low address byte Setup data pointer auto mode BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R 0 0 0 0 BC11 BC10 BC9 BC8 00000000 R BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R 0 0 0 0 0 BC10 BC9 BC8 00000000 R BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 0 0 0 0 0 0 0 8 bytes of setup data SET-UPDAT[0] = bmRequestType SET-UPDAT[1] = bmRequest SET-UPDAT[2:3] = wValue SET-UPDAT[4:5] = wIndex SET-UPDAT[6:7] = wLength D7 D6 D5 D4 D3 D2 D1 Waveform selector GPIF Done, GPIF Idle drive mode Inactive bus, CTL states CTL drive type SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 xxxxxxx0 bbbbbbbr SDPAUTO 00000001 RW D0 xxxxxxxx R FIFOWR1 FIFOWR0 FIFORD1 FIFORD0 11100100 RW DONE 0 0 0 0 0 0 IDLEDRV 10000000 RW 0 TRICTL 0 0 0 0 0 0 0 0 CTL2 CTL2 CTL1 CTL1 CTL0 CTL0 11111111 RW 00000000 RW 00000000 00000000 Flowstate enable and FSE 0 0 0 selector Flowstate logic LFUNC1 LFUNC0 TERMA2 TERMA1 CTL-pin states in flow state CTL0E3 CTL0E2 CTL0E1 CTL0E0 (when Logic = 0) CTL-pin states in flow state CTL0E3 CTL0E2 CTL0E1 CTL0E0 (when Logic = 1) Holdoff configuration HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD0 Flowstate strobe SLAVE RDYASYNC CTLTOGL SUSTAIN configuration Flowstate rising/falling edge 0 0 0 0 configuration Master strobe half period D7 D6 D5 D4 GPIF transaction count TC31 TC30 TC29 TC28 Byte 3 GPIF transaction count TC23 TC22 TC21 TC20 Byte 2 GPIF transaction count TC15 TC14 TC13 TC12 Byte 1 GPIF transaction count TC7 TC6 TC5 TC4 Byte 0 Document Number: 001-06120 Rev *L 0 xxxxxxxx RW 0 FS2 FS1 FS0 TERMA0 TERMB2 TERMB1 TERMB0 00000000 RW 00000000 brrrrbbb 0 CTL2 CTL1 CTL0 00000000 RW 0 CTL2 CTL1 CTL0 00000000 RW HOSTATE HOCTL2 HOCTL1 HOCTL0 00010010 RW 0 MSTB2 MSTB1 MSTB0 00100000 RW 00000001 rrrrrrbb 0 0 FALLING RISING D3 D2 D1 D0 00000010 RW TC27 TC26 TC25 TC24 00000000 RW TC19 TC18 TC17 TC16 00000000 RW TC11 TC10 TC9 TC8 00000000 RW TC3 TC2 TC1 TC0 00000001 RW 00000000 RW Page 22 of 44 CY7C68053 Table 8. FX2LP18 Register Summary (continued) Hex Size Name Reserved E6D2 1 E6D3 1 E6D4 1 3 E6DA 1 E6DB 1 E6DC 1 3 E6E2 1 Description b7 b6 b5 b4 b3 b2 b1 b0 2 GPIF flag EP2GPIFFLGSEL[10] Endpoint select Endpoint 2 GPIF stop transEP2GPIFPFSTOP action on program flag [10] EP2GPIFTRIG Endpoint 2 GPIF trigger Reserved Reserved Reserved 4 GPIF flag EP4GPIFFLGSEL[10] Endpoint select Endpoint 4 GPIF stop transEP4GPIFPFSTOP action on GPIF flag EP4GPIFTRIG[10] Endpoint 4 GPIF trigger Reserved Reserved Reserved 6 GPIF flag EP6GPIFFLGSEL[10] Endpoint select 0 0 0 0 0 0 FS1 FS0 0 0 0 0 0 0 0 x x x x x x x x 0 0 0 0 0 0 FS1 FS0 0 0 0 0 0 0 0 x x x x x x x x 0 0 0 0 0 0 FS1 FS0 Endpoint 6 GPIF stop transaction on program flag Endpoint 6 GPIF trigger 0 0 0 0 0 0 0 x x x x x x x x 0 0 0 0 0 0 FS1 FS0 0 0 0 0 0 0 0 x x x x x x x x D15 D14 D13 D12 D11 D10 D9 D8 xxxxxxxx RW D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R INTRDY SAS TCXRDY5 0 0 0 0 0 0 x 0 x 0 x 0 x 0 x 0 x RDY1 x RDY0 x D7 D7 D7 D6 D6 D6 D5 D5 D5 D4 D4 D4 D3 D3 D3 D2 D2 D2 D1 D1 D1 D0 D0 D0 xxxxxxxx RW xxxxxxxx RW xxxxxxxx RW RW D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW 0 DISCON 0 0 0 0 0 400KHZ xxxxxxxx n/a [12] E6E3 1 EP6GPIFPFSTOP E6E4 1 3 EP6GPIFTRIG[10] Reserved Reserved Reserved E6EA 1 E6EB 1 E6EC 1 3 E6F0 1 E6F1 1 E6F2 1 E6F3 1 8 GPIF flag EP8GPIFFLGSEL[10] Endpoint select Endpoint 8 GPIF stop transEP8GPIFPFSTOP action on program flag EP8GPIFTRIG[10] Endpoint 8 GPIF trigger Reserved GPIF Data H XGPIFSGLDATH (16-bit mode only) Read/Write GPIF Data L and XGPIFSGLDATLX trigger transaction XGPIFSGLDATLRead GPIF Data L, no transNOX action trigger Internal RDY, sync/async, GPIFREADYCFG RDY pin states E6F4 E6F5 E6F6 1 1 2 E740 E780 E7C0 E800 F000 F400 F600 F800 FC00 FE00 xxxx GPIFREADYSTAT GPIF ready status GPIFABORT Abort GPIF waveforms Reserved ENDPOINT BUFFERS 64 EP0BUF EP0-IN/-OUT buffer 64 EP10UTBUF EP1-OUT buffer 64 EP1INBUF EP1-IN buffer 2048 Reserved 512/1024-byte EP 2/Slave 1024 EP2FIFOBUF FIFO buffer (IN or OUT) 512 byte EP 4/Slave FIFO 512 EP4FIFOBUF buffer (IN or OUT) 512 Reserved 512/1024-byte EP 6/Slave 1024 EP6FIFOBUF FIFO buffer (IN or OUT) 512 byte EP 8/Slave FIFO 512 EP8FIFOBUF buffer (IN or OUT) 512 Reserved I²C Configuration Byte Default Access 00000000 RW FIFO2FLAG 00000000 RW xxxxxxxx W 00000000 RW FIFO4FLAG 00000000 RW xxxxxxxx W 00000000 RW FIFO6FLAG 00000000 RW xxxxxxxx W 00000000 RW FIFO8FLAG 00000000 RW xxxxxxxx W 00000000 bbbrrrrr 00xxxxxx R xxxxxxxx W Note 12. If no EEPROM is detected by the SIE then the default is 00000000. Document Number: 001-06120 Rev *L Page 23 of 44 CY7C68053 Table 8. FX2LP18 Register Summary (continued) Hex 80 81 Size Name Description Special Function Registers (SFRs) [13] 1 IOA Port A (bit addressable) 1 SP Stack Pointer b7 b6 b5 b4 b3 b2 b1 b0 Default D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 xxxxxxxx RW 00000111 RW A7 A15 A7 A15 0 SMOD0 A6 A14 A6 A14 0 x A5 A13 A5 A13 0 1 A4 A12 A4 A12 0 1 A3 A11 A3 A11 0 x A2 A10 A2 A10 0 x A1 A9 A1 A9 0 x A0 A8 A0 A8 SEL IDLE 00000000 RW 00000000 RW 00000000 RW 00000000 RW 00000000 RW 00110000 RW TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00000000 RW GATE CT M1 M0 GATE CT M1 M0 00000000 RW D7 D7 D15 D15 x D6 D6 D14 D14 x D5 D5 D13 D13 T2M D4 D4 D12 D12 T1M D3 D3 D11 D11 T0M D2 D2 D10 D10 MD2 D1 D1 D9 D9 MD1 D0 D0 D8 D8 MD0 00000000 RW 00000000 RW 00000000 RW 00000000 RW 00000001 RW D7 IE5 D6 IE4 D5 I²CINT D4 USBNT D3 1 D2 0 D1 0 D0 0 xxxxxxxx RW 00001000 RW A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW Serial Port 0 Control (bit addressable) Serial Port 0 data buffer Autopointer 1 address H Autopointer 1 address L SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00000000 RW D7 A15 A7 D6 A14 A6 D5 A13 A5 D4 A12 A4 D3 A11 A3 D2 A10 A2 D1 A9 A1 D0 A8 A0 00000000 RW 00000000 RW 00000000 RW Autopointer 2 address H Autopointer 2 address L A15 A7 A14 A6 A13 A5 A12 A4 A11 A3 A10 A2 A9 A1 A8 A0 00000000 RW 00000000 RW Port C (bit addressable) Interrupt 2 Clear D7 x x D6 x x D5 x x D4 x x D3 x x D2 x x D1 x x D0 x x xxxxxxxx RW xxxxxxxx W xxxxxxxx W Interrupt Enable (bit addressable) EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 00000000 RW 82 83 84 85 86 87 1 1 1 1 1 1 DPL0 DPH0 DPL1[13] DPH1[13] DPS[13] PCON 88 1 TCON 89 1 TMOD 8A 8B 8C 8D 8E 1 1 1 1 1 TL0 TL1 TH0 TH1 CKCON[13] 8F 90 91 1 1 1 Reserved IOB[13] EXIF[13] 92 1 MPAGE[13] 93 5 Reserved 98 1 SCON0 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 1 1 1 1 1 1 1 1 1 1 5 SBUF0 AUTOPTRH1[13] AUTOPTRL1[13] Reserved AUTOPTRH2[13] AUTOPTRL2[13] Reserved IOC[13] INT2CLR[13] Reserved Reserved A8 1 IE A9 AA 1 1 AB 1 Reserved EP2468STAT[13] EP24FIFOFLGS AC 1 EP68FIFOFLGS AD AF B0 2 1 1 B1 1 B2 B3 B4 B5 B6 B7 1 1 1 1 1 1 B8 1 B9 BA 1 1 BB 1 BC 1 BD 1 BE 1 BF 1 Reserved AUTOPTRSETUP[13] Autopointer 1 and 2 Setup IOD[13] Port D (bit addressable) Port E IOE[13] (NOT bit addressable) OEA[13] Port A Output Enable OEB[13] Port B Output Enable OEC[13] Port C Output Enable OED[13] Port D Output Enable OEE[13] Port E Output Enable Reserved Interrupt Priority (bit addressIP able) Reserved EP01STAT[13] Endpoint 0 and 1 Status Endpoint 2,4,6,8 GPIF Slave GPIFTRIG[13, 10] FIFO trigger Reserved Data H (16-bit mode GPIFSGLDATH[13] GPIF only) [13] GPIFSGLDATLX GPIF Data L w/trigger GPIFSGLDATLGPIF Data L w/no trigger [13] NOX [13] [13] Data Pointer 0 L Data Pointer 0 H Data Pointer 1 L Data Pointer 1 H Data Pointer 0/1 select Power control Timer/Counter control (bit addressable) Timer/Counter mode control Timer 0 reload L Timer 1 reload L Timer 0 reload H Timer 1 reload H Clock control Port B (bit addressable) External interrupt flags Upper address byte of MOVX using @R0/@R1 Endpoint 2,4,6,8 status flags Endpoint 2,4 Slave FIFO status flags Endpoint 6,8 Slave FIFO status flags Access EP8F EP8E EP6F EP6E EP4F EP4E EP2F EP2E 01011010 R 0 EP4PF EP4EF EP4FF 0 EP2PF EP2EF EP2FF 00100010 R 0 EP8PF EP8EF EP8FF 0 EP6PF EP6EF EP6FF 01100110 R 0 D7 0 D6 0 D5 0 D4 0 D3 APTR2INC D2 APTR1INC D1 APTREN D0 00000110 RW xxxxxxxx RW D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW D7 D7 D7 D7 D7 D6 D6 D6 D6 D6 D5 D5 D5 D5 D5 D4 D4 D4 D4 D4 D3 D3 D3 D3 D3 D2 D2 D2 D2 D2 D1 D1 D1 D1 D1 D0 D0 D0 D0 D0 00000000 RW 00000000 RW 00000000 RW 00000000 RW 00000000 RW 1 PS1 PT2 PS0 PT1 PX1 PT0 PX0 10000000 RW 0 0 0 0 0 DONE 0 0 0 0 EP1INBSY EP1OUTBSY RW EP1 EP0BSY EP0 00000000 R D15 D14 D13 D12 D11 D10 D9 D8 xxxxxxxx RW D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R 10000xxx brrrrbbb Note 13. SFRs not part of the standard 8051 architecture. Document Number: 001-06120 Rev *L Page 24 of 44 CY7C68053 Table 8. FX2LP18 Register Summary (continued) Hex Size Name b7 b6 b5 b4 b3 b2 b1 b0 SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00000000 RW D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW Timer/Counter 2 Control (bit addressable) TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2 00000000 RW Capture for Timer 2, auto-reload, up counter Capture for Timer 2, auto-reload, up counter Timer 2 Reload L Timer 2 Reload H D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW D7 D15 D6 D14 D5 D13 D4 D12 D3 D11 D2 D10 D1 D9 D0 D8 00000000 RW 00000000 RW PSW Program Status Word (bit addressable) CY AC F0 RS1 RS0 OV F1 P 00000000 RW 7 1 7 Reserved EICON[13] Reserved External Interrupt Control SMOD1 1 ERESI RESI INT6 0 0 0 01000000 RW E0 1 ACC Accumulator (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW E1 E8 E9 F0 F1 7 1 7 1 7 Reserved EIE[13] Reserved B Reserved External Interrupt Enables 1 1 1 EX6 EX5 EX4 EI²C EUSB 11100000 RW D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW F8 1 EIP[13] 1 1 1 PX6 PX5 PX4 PI²C PUSB 11100000 RW F9 7 Reserved C0 1 SCON1[13] C1 C2 1 6 SBUF1[13] Reserved C8 1 T2CON C9 1 Reserved CA 1 RCAP2L CB 1 RCAP2H CC CD CE 1 1 2 TL2 TH2 Reserved D0 1 D1 D8 D9 Description Serial Port 1 Control (bit addressable) Serial Port 1 Data Buffer B (bit addressable) External Interrupt Priority control Default Access Ledgend R = All bits read only W = All bits write only r = Read-only bit w = Write-only bit b = Both read/write bit Document Number: 001-06120 Rev *L Page 25 of 44 CY7C68053 Absolute Maximum Ratings Maximum power dissipation Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. From AVcc Supply ..................................................... 90 mW From I/O supply ......................................................... 36 mW Storage temperature ................................ –65 °C to +150 °C From core supply ....................................................... 95 mW Ambient temperature with power supplied Static discharge voltage ........................................... >2000 V Industrial .................................................... –40 °C to +85 °C (I2C SCL and SDA pins only ................................. >1500 V) Supply voltage to ground potential Maximum output current, per I/O port ......................... 10 mA For 3.3 V power domain ..............................–0.5 V to +4.0 V Operating Conditions For 1.8 V power domain ..............................–0.5 V to +2.0 V TA (Ambient temperature under bias) industrial .................................................... –40 °C to +85 °C DC input voltage to any input pin For pins under 3.3 V power domain ........................ 3.6 V[14] Supply voltage For pins under 1.8 V to 3.3 V Power Domain (GPIOs) .................................................... 1.89 V to 3.6 V[14] 3.3 V Power Supply .........................................3.0 V to 3.6 V 1.8 V Power Supply ......................................1.71 V to1.89 V (The GPIOs are not over voltage tolerant, except the SCL and SDA pins, which are 3.3 V tolerant) Ground Voltage ................................................................ 0 V FOSC (Oscillator or Crystal Frequency).... 24 MHz ± 100 ppm ................................................................... Parallel Resonant .................................................................. 500 W drive level ............................................................ Load capacitors 12 pF DC voltage applied to outputs in high Z State .................................... –0.5 V to VCC +0.5 V DC Characteristics Parameter Description Conditions Min Typ Max Unit AVCC 3.3 V supply (to oscillator and PHY) 3.3 3.60 V 1.8 V to 3.3 V supply (to I/O) 1.71 1.8 3.60 V VCC_A 1.8 V supply to analog core 1.71 1.8 1.89 V VCC_D 1.8 V supply to digital core 3.00 VCC_IO 1.71 1.8 1.89 V 0.6 * VCC_IO VIH Input HIGH voltage VIL Input LOW voltage VIH_X Crystal input HIGH voltage VIL_X Crystal input LOW voltage II Input leakage current Hysteresis VOH Output voltage HIGH IOUT = 4 mA Output LOW voltage IOUT = –4 mA IOH Output current HIGH IOL Output current LOW CIN Input pin capacitance Except D+/D– D+/D– ISUSP Suspend current Connected Disconnected 2.0 –0.5 50 0< VIN < VCC_IO VOL 0 VCC_IO – 0.4 VCC_IO+10% V 0.3 * VCC_IO V 3.60 V 0.8 V mV ±10 A V 0.4 V 4 mA 4 mA 10 pF 15 pF 220 380[15] A 20 150[15] A Notes 14. Do not power I/O when chip power is OFF. 15. Measured at maximum VCC, 25°C. Document Number: 001-06120 Rev *L Page 26 of 44 CY7C68053 DC Characteristics (continued) Parameter Description ICC_AVcc Supply current (AVCC) ICC_IO Supply current (VCC_IO) ICC_CORE Supply current (VCC_CORE) TRESET Conditions Min Typ Max Unit 8051 running, connected to USB HS 15 25 mA 10 20 mA 3 10 mA 1 5 mA 32 50 mA 24 40 mA ms 8051 running, connected to USB FS Reset time after valid power Pin reset after powered on 8051 running, connected to USB HS 8051 running, connected to USB FS 8051 running, connected to USB HS 8051 running, connected to USB FS 5.0 VCC min = 3.0 V 200 s AC Electrical Characteristics USB Transceiver USB 2.0-compliant in full and high speed modes. GPIF Synchronous Signals Figure 8. GPIF Synchronous Signals Timing Diagram[16] tIFCLK IFCLK tSGA GPIFADR[8:0] RDYX tSRY tRYH DATA(input) valid tSGD tDAH CTLX tXCTL DATA(output) N N+1 tXGD Table 9. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK[16,17] Parameter Description tIFCLK IFCLK period tSRY RDYX to clock setup time tRYH Clock to RDYX tSGD GPIF data to clock setup time tDAH GPIF data hold time tXGD Clock to GPIF data output propagation delay tXCTL Clock to CTLX output propagation delay Min Max Unit 20.83 ns 0 11 ns 6.7 ns 8.9 0 9.2 ns ns ns ns Notes 16. Dashed lines denote signals with programmable polarity. 17. GPIF asynchronous RDYx signals have a minimum setup time of 50 ns when using internal 48 MHz IFCLK. Document Number: 001-06120 Rev *L Page 27 of 44 CY7C68053 8 Table 10. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK[18] Parameter Description period[19] Min Max Unit tIFCLK IFCLK 20.83 200 ns tSRY RDYX to clock setup time 2.9 ns tRYH Clock to RDYX 3.7 tSGD GPIF data to clock setup time 3.2 tDAH GPIF data hold time 4.5 tXGD Clock to GPIF data output propagation delay tXCTL Clock to CTLX output propagation delay ns ns ns 15 ns 13.06 ns Min Max Unit ns ns Slave FIFO Synchronous Read Figure 9. Slave FIFO Synchronous Read Timing Diagram[20] tIFCLK IFCLK tSRD tRDH SLRD tXFLG FLAGS DATA N tOEon N+1 tXFD tOEoff SLOE Table 11. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK[18] Parameter Description tIFCLK IFCLK period 20.83 tSRD SLRD to clock setup time 18.7 tRDH Clock to SLRD hold time 0 tOEon SLOE turn-on to FIFO data valid 10.5 tOEoff SLOE turn-off to FIFO data hold 2.15 10.5 ns tXFLG Clock to FLAGS output propagation delay 9.5 ns tXFD Clock to FIFO data output propagation delay 11 ns ns ns Notes 18. GPIF asynchronous RDYx signals have a minimum setup time of 50 ns when using internal 48 MHz IFCLK. 19. IFCLK must not exceed 48 MHz. 20. Dashed lines denote signals with programmable polarity. Document Number: 001-06120 Rev *L Page 28 of 44 CY7C68053 Table 12. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK[21] Min Max Unit tIFCLK Parameter IFCLK period Description 20.83 200 ns ns tSRD SLRD to clock setup time 12.7 tRDH Clock to SLRD hold time 3.7 tOEon SLOE turn-on to FIFO data valid 10.5 ns tOEoff SLOE turn-off to FIFO data hold 2.15 10.5 ns tXFLG Clock to FLAGS output propagation delay ns Clock to FIFO data output propagation delay 13.5 tXFD 17.31 ns ns Slave FIFO Asynchronous Read Figure 10. Slave FIFO Asynchronous Read Timing Diagram[22] tRDpwh SLRD tRDpwl tXFLG tXFD FLAGS DATA SLOE N+1 N tOEon tOEoff Table 13. Slave FIFO Asynchronous Read Parameters[23] Min Max Unit tRDpwl Parameter SLRD pulse width LOW Description 50 ns tRDpwh SLRD pulse width HIGH 50 tXFLG SLRD to FLAGS output propagation delay 70 ns tXFD SLRD to FIFO data output propagation delay 15 ns tOEon SLOE turn-on to FIFO data valid 10.5 ns tOEoff SLOE turn-off to FIFO data hold 2.15 10.5 ns ns Notes 21. GPIF asynchronous RDYx signals have a minimum setup time of 50 ns when using internal 48 MHz IFCLK. 22. Dashed lines denote signals with programmable polarity. 23. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz. Document Number: 001-06120 Rev *L Page 29 of 44 CY7C68053 Slave FIFO Synchronous Write Figure 11. Slave FIFO Synchronous Write Timing Diagram[24] tIFCLK IFCLK SLWR DATA tSWR tWRH N Z tSFD Z tFDH FLAGS tXFLG Table 14. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK[25] Min Max Unit tIFCLK Parameter IFCLK period Description 20.83 ns tSWR SLWR to clock setup time 18.1 tWRH Clock to SLWR hold time 0 tSFD FIFO data to clock setup time 10.64 tFDH Clock to FIFO data hold time 0 tXFLG Clock to FLAGS output propagation time 9.5 ns ns ns ns ns Table 15. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK[26] Min Max Unit tIFCLK Parameter IFCLK period Description 20.83 200 ns ns 13.5 ns tSWR SLWR to clock setup time 12.1 tWRH Clock to SLWR hold time 3.6 tSFD FIFO data to clock setup time 3.2 tFDH Clock to FIFO data hold time 4.5 tXFLG Clock to FLAGS output propagation time ns ns ns Notes 24. Dashed lines denote signals with programmable polarity. 25. GPIF asynchronous RDYx signals have a minimum setup time of 50 ns when using internal 48 MHz IFCLK. 26. Read and writes to these registers may require synchronization delay, see MoBL-USB FX2LP18 Technical Reference Manual for ‘Synchronization Delay.’ Document Number: 001-06120 Rev *L Page 30 of 44 CY7C68053 Slave FIFO Asynchronous Write Figure 12. Slave FIFO Asynchronous Write Timing Diagram[27] tWRpwh SLWR tWRpwl tSFD tFDH DATA FLAGS tXFD Table 16. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK[28] Parameter Description Min Max Unit 50 ns 70 ns tWRpwl SLWR pulse LOW tWRpwh SLWR pulse HIGH 50 tSFD SLWR to FIFO data setup time 10 tFDH FIFO data to SLWR hold time 10 tXFD SLWR to FLAGS output propagation delay ns ns ns Notes 27. Dashed lines denote signals with programmable polarity. 28. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz. Document Number: 001-06120 Rev *L Page 31 of 44 CY7C68053 Slave FIFO Synchronous Packet End Strobe Figure 13. Slave FIFO Synchronous Packet End Strobe Timing Diagram[29] IFCLK tPEH PKTEND tSPE FLAGS tXFLG Table 17. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK[30] Min Max Unit tIFCLK Parameter IFCLK period Description 20.83 ns tSPE PKTEND to clock setup time 14.6 tPEH Clock to PKTEND hold time 0 tXFLG Clock to FLAGS output propagation delay 9.5 ns ns ns Table 18. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK[30] Parameter Description tIFCLK IFCLK period Min Max Unit 20.83 200 ns ns 13.5 ns tSPE PKTEND to clock setup time 8.6 tPEH Clock to PKTEND hold time 3.04 tXFLG Clock to FLAGS output propagation delay There is no specific timing requirement to be met for asserting the PKTEND pin with regards to asserting SLWR. PKTEND can be asserted with the last data value clocked into the FIFOs or thereafter. The only consideration is that the setup time tSPE and the hold time tPEH must be met. Although there are no specific timing requirements for the PKTEND assertion, there is a specific corner case condition that needs attention while using the PKTEND to commit a one byte/word packet. There is an additional timing requirement to be met when the FIFO is configured to operate in auto mode and you want to send two packets back to back: a full packet (full defined as the number of bytes in the FIFO meeting the level set in AUTOINLEN register) committed automatically followed by a short one byte/word packet committed manually using the PKTEND pin. In this scenario, make sure to assert PKTEND at least one clock cycle after the rising edge that caused the last byte/word to be clocked into the previous auto committed packet. Figure 14 shows this scenario. X is the value the AUTOINLEN register is set to when the IN endpoint is configured to be in auto mode. ns Figure 14 shows a scenario where two packets are committed. The first packet is committed automatically when the number of bytes in the FIFO reaches X (value set in AUTOINLEN register) and the second one byte/word short packet is committed manually using PKTEND. Note that there is at least one IFCLK cycle timing between the assertion of PKTEND and clocking of the last byte of the previous packet (causing the packet to be committed automatically). Failing to adhere to this timing, results in the FX2LP18 failing to send the one byte/word short packet. Notes 29. Dashed lines denote signals with programmable polarity. 30. Read and writes to these registers may require synchronization delay, see MoBL-USB FX2LP18 Technical Reference Manual for ‘Synchronization Delay.’ Document Number: 001-06120 Rev *L Page 32 of 44 CY7C68053 Figure 14. Slave FIFO Synchronous Write Sequence and Timing Diagram[31] tIFCLK IFCLK tSFA tFAH FIFOADR >= tWRH >= tSWR SLWR tSFD tFDH tSFD X-4 DATA tFDH X-3 tFDH tSFD tFDH tSFD X-2 X-1 tSFD tFDH tSFD tFDH 1 X At least one IFCLK cycle tSPE tPEH PKTEND Slave FIFO Asynchronous Packet End Strobe Figure 15. Slave FIFO Asynchronous Packet End Strobe Timing Diagram[31] tPEpwh PKTEND tPEpwl FLAGS tXFLG Table 19. Slave FIFO Asynchronous Packet End Strobe Parameters[32] Min Max Unit tPEpwl Parameter PKTEND pulse width LOW Description 50 ns tPWpwh PKTEND pulse width HIGH 50 tXFLG PKTEND to FLAGS output propagation delay 115 ns Min Max Unit ns Slave FIFO Output Enable Figure 16. Slave FIFO Output Enable Timing Diagram[33] SLOE DATA tOEon tOEoff Table 20. Slave FIFO Output Enable Parameters Parameter Description tOEon SLOE assert to FIFO data output 10.5 ns tOEoff SLOE deassert to FIFO data hold 2.15 10.5 ns Notes 31. Dashed lines denote signals with programmable polarity. 32. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz. Document Number: 001-06120 Rev *L Page 33 of 44 CY7C68053 Slave FIFO Address to Flags/Data Figure 17. Slave FIFO Address to Flags/Data Timing Diagram[33] FIFOADR [1.0] tXFLG FLAGS tXFD DATA N N+1 Table 21. Slave FIFO Address to Flags/Data Parameters Parameter Description tXFLG FIFOADR[1:0] to flags output propagation delay tXFD FIFOADR[1:0] to FIFO data output propagation delay Min Max Unit 10.7 ns 14.3 ns Slave FIFO Synchronous Address Figure 18. Slave FIFO Synchronous Address Timing Diagram[33] IFCLK SLCS/FIFOADR [1:0] tSFA tFAH Table 22. Slave FIFO Synchronous Address Parameters[34] Parameter Description Min Max Unit tIFCLK Interface clock period 20.83 200 ns tSFA FIFOADR[1:0] to clock setup time 25 ns tFAH Clock to FIFOADR[1:0] hold time 10 ns Slave FIFO Asynchronous Address Figure 19. Slave FIFO Asynchronous Address Timing Diagram[33] SLCS/FIFOADR [1:0] tSFA tFAH SLRD/SLWR/PKTEND Slave FIFO Asynchronous Address Parameters[35] Min Max Unit tSFA Parameter FIFOADR[1:0] to SLRD/SLWR/PKTEND setup time Description 10 ns tFAH RD/WR/PKTEND to FIFOADR[1:0] hold time 10 ns Note 33. Dashed lines denote signals with programmable polarity. 34. Read and writes to these registers may require synchronization delay, see MoBL-USB FX2LP18 Technical Reference Manual for ‘Synchronization Delay.’ 35. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz. Document Number: 001-06120 Rev *L Page 34 of 44 CY7C68053 Sequence Diagram Various sequence diagrams and examples are presented in this section. Single and Burst Synchronous Read Example Figure 20. Slave FIFO Synchronous Read Sequence and Timing Diagram[36] tIFCLK IFCLK tSFA tSFA tFAH tFAH FIFOADR t=0 tSRD T=0 tRDH >= tSRD >= tRDH SLRD t=3 t=2 T=3 T=2 SLCS tXFLG FLAGS tXFD tXFD Data Driven: N DATA N+1 N+1 N+2 N+3 tOEon tOEoff tOEon tXFD tXFD N+4 tOEoff SLOE t=4 t=1 T=4 T=1 Figure 21. Slave FIFO Synchronous Sequence of Events Diagram IFCLK FIFO POINTER N IFCLK IFCLK N N+1 FIFO DATA BUS Not Driven Driven: N ■ N+1 N+1 Not Driven At t = 0 the FIFO address is stable and the signal SLCS is asserted (SLCS may be tied low in some applications). Note tSFA has a minimum of 25 ns. This means that when IFCLK is running at 48 MHz, the FIFO address setup time is more than one IFCLK cycle. At t = 1, SLOE is asserted. SLOE is an output enable only whose sole function is to drive the data bus. The data that is driven on the bus is the data that the internal FIFO pointer is currently pointing to. In this example, it is the first data value in the FIFO. Note The data is prefetched and driven on the bus when SLOE is asserted. IFCLK N+2 IFCLK N+3 IFCLK N+4 SLRD SLOE Figure 20 shows the timing relationship of the SLAVE FIFO signals during a synchronous FIFO read using IFCLK as the synchronizing clock. The diagram illustrates a single read followed by a burst read. ■ IFCLK N+1 SLOE SLRD SLRD SLOE IFCLK N+1 IFCLK N+4 SLRD N+2 N+3 N+4 IFCLK N+4 SLOE N+4 Not Driven ■ At t = 2, SLRD is asserted. SLRD must meet the setup time of tSRD (time from asserting the SLRD signal to the rising edge of the IFCLK) and maintain a minimum hold time of tRDH (time from the IFCLK edge to the deassertion of the SLRD signal). If the SLCS signal is used, it must be asserted before SLRD (that is, the SLCS and SLRD signals must both be asserted to start a valid read condition). ■ The FIFO pointer is updated on the rising edge of the IFCLK while SLRD is asserted. This starts the propagation of data from the newly addressed location to the data bus. After a propagation delay of tXFD (measured from the rising edge of IFCLK) the new data value is present. N is the first data value read from the FIFO. To have data on the FIFO data bus, SLOE must also be asserted. Notes 36. Dashed lines denote signals with programmable polarity. Document Number: 001-06120 Rev *L Page 35 of 44 CY7C68053 The same sequence of events is shown for a burst read and is marked with the time indicators of T = 0 through 5. Note For the burst mode, the SLRD and SLOE are left asserted during the entire duration of the read. In the burst read mode, when SLOE is asserted, data indexed by the FIFO pointer is on the data bus. During the first read cycle on the rising edge of the clock, the FIFO pointer is updated and increments to point to address N+1. For each subsequent rising edge of IFCLK while the SLRD is asserted, the FIFO pointer is incremented and the next data value is placed on the data bus. Single and Burst Synchronous Write Figure 22. Slave FIFO Synchronous Write Sequence and Timing Diagram[37] tIFCLK IFCLK tSFA tSFA tFAH tFAH FIFOADR t=0 tSWR tWRH >= tWRH >= tSWR T=0 SLWR t=2 T=2 t=3 T=5 SLCS tXFLG tXFLG FLAGS tFDH tSFD tSFD N+1 N DATA t=1 tFDH T=1 tSFD tSFD tFDH N+3 N+2 T=3 tFDH T=4 tSPE tPEH PKTEND Figure 22 shows the timing relationship of the SLAVE FIFO signals during a synchronous write using IFCLK as the synchronizing clock. The diagram illustrates a single write followed by burst write of 3 bytes and committing all 4 bytes as a short packet using the PKTEND pin. ■ At t = 0 the FIFO address is stable and the signal SLCS is asserted. (SLCS may be tied low in some applications) Note tSFA has a minimum of 25 ns. This means that when IFCLK is running at 48 MHz, the FIFO address setup time is more than one IFCLK cycle. ■ At t = 1, the external master/peripheral must output the data value onto the data bus with a minimum setup time of tSFD before the rising edge of IFCLK. ■ At t = 2, SLWR is asserted. The SLWR must meet the setup time of tSWR (time from asserting the SLWR signal to the rising edge of IFCLK) and maintain a minimum hold time of tWRH (time from the IFCLK edge to the deassertion of the SLWR signal). If the SLCS signal is used, it must be asserted before SLWR is asserted. (That is, the SLCS and SLWR signals must both be asserted to start a valid write condition). ■ While the SLWR is asserted, data is written to the FIFO and on the rising edge of the IFCLK, the FIFO pointer is incremented. The FIFO flag is also updated after a delay of tXFLG from the rising edge of the clock. The same sequence of events is also shown for a burst write and is marked with the time indicators of T = 0 through 5. Note For the burst mode, SLWR and SLCS are left asserted for the entire duration of writing all the required data values. In this burst write mode, when the SLWR is asserted, the data on the FIFO data bus is written to the FIFO on every rising edge of IFCLK. The FIFO pointer is updated on each rising edge of IFCLK. In Figure 22, when the four bytes are written to the FIFO, SLWR is deasserted. The short 4-byte packet can be committed to the host by asserting the PKTEND signal. There is no specific timing requirement that needs to be met for asserting the PKTEND signal with regards to asserting the SLWR signal. PKTEND can be asserted with the last data value or thereafter. The only requirement is that the setup time tSPE and the hold time tPEH must be met. In the scenario of Figure 22, the number of data values committed includes the last value written to the FIFO. In this example, both the data value and the PKTEND signal are clocked on the same rising edge of IFCLK. PKTEND can also be asserted in subsequent clock cycles. The FIFOADDR lines must be held constant during the PKTEND assertion. Note 37. Dashed lines denote signals with programmable polarity. Document Number: 001-06120 Rev *L Page 36 of 44 CY7C68053 packet committed manually using the PKTEND pin. In this case, the external master must make sure to assert the PKTEND pin at least one clock cycle after the rising edge that caused the last byte/word to be clocked into the previous auto committed packet (the packet with the number of bytes equal to what is set in the AUTOINLEN register). Refer to Figure 14 on page 33 for further details about this timing. Although there are no specific timing requirements for the PKTEND assertion, there is a specific corner case condition that needs attention while using the PKTEND to commit a one byte/word packet. Additional timing requirements exist when the FIFO is configured to operate in auto mode and you want to send two packets: a full packet (full defined as the number of bytes in the FIFO meeting the level set in AUTOINLEN register) committed automatically followed by a short one byte/word Sequence Diagram of a Single and Burst Asynchronous Read Figure 23. Slave FIFO Asynchronous Read Sequence and Timing Diagram[38] tSFA tFAH tSFA tFAH FIFOADR t=0 tRDpwl tRDpwh tRDpwl T=0 tRDpwl tRDpwh tRDpwl tRDpwh tRDpwh SLRD t=2 t=3 T=3 T=2 T=4 T=5 T=6 SLCS tXFLG tXFLG FLAGS tXFD Data (X) Driven DATA tXFD tXFD N N tXFD N+3 N+2 tOEon tOEoff tOEon N+1 tOEoff SLOE t=4 t=1 T=7 T=1 Figure 24. Slave FIFO Asynchronous Read Sequence of Events Diagram SLOE FIFO POINTER N FIFO DATA BUS Not Driven SLRD SLRD SLOE SLOE SLRD SLRD SLRD SLOE N N+1 N+1 N+1 N+1 N+2 N+2 N+3 N+3 Driven: X N N Not Driven N N+1 N+1 N+2 N+2 Not Driven Figure 23 illustrates the timing relationship of the SLAVE FIFO signals during an asynchronous FIFO read. It shows a single read followed by a burst read. ■ At t = 0, the FIFO address is stable and the SLCS signal is asserted. ■ At t = 1, SLOE is asserted. This results in the data bus being driven. The data that is driven on to the bus is previous data; it is data that was in the FIFO from a prior read cycle. ■ SLRD N At t = 2, SLRD is asserted. The SLRD must meet the minimum active pulse of tRDpwl and minimum inactive pulse width of tRDpwh. If SLCS is used then, SLCS must be asserted before SLRD is asserted (that is, the SLCS and SLRD signals must both be asserted to start a valid read condition). ■ The data that is driven, after asserting SLRD, is the updated data from the FIFO. This data is valid after a propagation delay of tXFD from the activating edge of SLRD. In Figure 23, data N is the first valid data read from the FIFO. For data to appear on the data bus during the read cycle (for example, SLRD is asserted), SLOE MUST be in an asserted state. SLRD and SLOE can also be tied together. The same sequence of events is also shown for a burst read marked with T = 0 through 5. Note In burst read mode, during SLOE assertion, the data bus is in a driven state and outputs the previous data. Once SLRD is asserted, the data from the FIFO is driven on the data bus (SLOE must also be asserted) and then the FIFO pointer is incremented. Note 38. Dashed lines denote signals with programmable polarity. Document Number: 001-06120 Rev *L Page 37 of 44 CY7C68053 Sequence Diagram of a Single and Burst Asynchronous Write Figure 25. Slave FIFO Asynchronous Write Sequence and Timing Diagram[39] tSFA tFAH tSFA tFAH FIFOADR t=0 tWRpwl tWRpwh T=0 tWRpwl tWRpwl tWRpwh tWRpwl tWRpwh tWRpwh SLWR t=3 t =1 T=1 T=3 T=4 T=6 T=7 T=9 SLCS tXFLG tXFLG FLAGS tSFD tFDH tSFD tFDH tSFD tFDH tSFD tFDH N+1 N+2 N+3 N DATA t=2 T=2 T=5 T=8 tPEpwl tPEpwh PKTEND Figure 25 illustrates the timing relationship of the SLAVE FIFO write in an asynchronous mode. The diagram shows a single write followed by a burst write of 3 bytes and committing the 4-byte-short packet using PKTEND. ■ At t = 0 the FIFO address is applied, ensuring that it meets the setup time of tSFA. If SLCS is used, it must also be asserted (SLCS may be tied low in some applications). ■ At t = 1 SLWR is asserted. SLWR must meet the minimum active pulse of tWRpwl and minimum inactive pulse width of tWRpwh. If the SLCS is used, it must be asserted before SLWR is asserted. ■ At t = 2, data must be present on the bus tSFD before the deasserting edge of SLWR. ■ At t = 3, deasserting SLWR causes the data to be written from the data bus to the FIFO and then the FIFO pointer is incremented. The FIFO flag is also updated after tXFLG from the deasserting edge of SLWR. The same sequence of events is shown for a burst write and is indicated by the timing marks of T = 0 through 5. Note In the burst write mode, once SLWR is deasserted, the data is written to the FIFO and then the FIFO pointer is incremented to the next byte in the FIFO. The FIFO pointer is post incremented. In Figure 25 when the four bytes are written to the FIFO and SLWR is deasserted, the short 4-byte packet can be committed to the host using the PKTEND. The external device must be designed to not assert SLWR and the PKTEND signal at the same time. It must be designed to assert the PKTEND after SLWR is deasserted and meet the minimum deasserted pulse width. The FIFOADDR lines are to be held constant during the PKTEND assertion. Note 39. Dashed lines denote signals with programmable polarity. Document Number: 001-06120 Rev *L Page 38 of 44 CY7C68053 Ordering Information Table 23 lists the key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Table 23. Key Features and Ordering Information Ordering Code CY7C68053-56BAXI Package Type RAM Size Number of Prog I/Os 8051 Address/Data Buses 16 K 24 – 56-ball VFBGA (Pb-free) Development Tool Kit CY3687 MoBL-USB FX2LP18 Development Kit Ordering Code Definitions CY 7 C 68 XXXX - 56BAX (C, I) (T) Tape and Reel Thermal Rating: C = Commercial I = Industrial Package type: 56-pin VFBGA Pb-free Part Number Family Code: 68 = USB Technology Code: C = CMOS Marketing Code: 7 = Cypress Products Company ID: CY = Cypress Document Number: 001-06120 Rev *L Page 39 of 44 CY7C68053 Package Diagram The FX2LP18 is available in a 56-ball VFBGA package. Figure 26. 56-ball VFBGA (5 × 5 × 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56 Package Outline, 001-03901 001-03901 *F Document Number: 001-06120 Rev *L Page 40 of 44 CY7C68053 PCB Layout Recommendations ■ Connections between the USB connector shell and signal ground must be done near the USB connector. The following recommendations must be followed to ensure reliable high performance operation. ■ Bypass or flyback caps on VBus, near connector, are recommended. ■ At least a four-layer impedance controlled board is required to maintain signal quality. ■ DPLUS and DMINUS trace lengths must be kept within 2 mm of each other in length, with preferred length of 20 to 30 mm. ■ Specify impedance targets (ask your board vendor what they can achieve). ■ Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to be split under these traces. ■ To control impedance, maintain trace widths and trace spacing to within specifications. ■ It is preferable to have no vias placed on the DPLUS or DMINUS trace routing. ■ Minimize stubs to minimize reflected signals. ■ Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm. Document Number: 001-06120 Rev *L Page 41 of 44 CY7C68053 Acronyms Document Conventions Table 24. Acronyms Used in this Document Units of Measure Acronym Description Table 25. Units of Measure ATA Advanced Technology Attachment ASIC Application Specific Integrated Circuit KHz CPU Central Processing Unit Mbytes megabyte DID Device Identifier MHz megahertz DSP Digital Signal Processor µA microampere ECC Error Correction Code µs microsecond EEPROM Electrically Erasable Programmable Read Only Memory µW microwatt mA milliampere EPP Enhanced Parallel Port mW milliwatt FIFO First In First Out ns nanosecond GPIF General Programmable Interface ppm parts per million GPIO General Purpose Input/Output pF picofarad I/O Input/Output V volt I2C Inter-Integrated Circuit PDA Personal Digital Assistant PLL Phase-Locked Loop PID Product Identifier RAM Random Access Memory SIE Serial Interface Engine SOF Start Of Frame USB Universal Serial Bus VID Vendor Identifier VFBGA Very Fine-Pitch Ball Grid Array UTOPIA Universal Test and Operations Physical-Layer Document Number: 001-06120 Rev *L Symbol Unit of Measure kilohertz Page 42 of 44 CY7C68053 Document History Page Document Title: CY7C68053, MoBL-USB™ FX2LP18 USB Microcontroller Document Number: 001-06120 Revision ECN Orig. of Change Submission Date ** 430449 OSG 03/03/06 New data sheet 03/24/06 In Section 3.3, stated that SCL and SDA pins can be connected to VCC or VCC_IO Chnged sections 3.5, 3.18.1 and pin descriptions of SCL, SDA to indicate that since DISCON=1 after reset, an EEPROM or EEPROM emulation is required on the I2C interface In pin description table, renamed pin 2H (Reserved) to Ground In Section 6, added statement “The GPIO’s are not over voltage tolerant, except the SCL and SDA pins, which are 3.3 V tolerant“ In Section 8,added a footnote to the DC char table stating that AVcc can be floated in low power mode In Section 8, changed VIHmax in DC char table from 3.6 V to VCC_IO + 10% See ECN Changed the recommendation for the pull up resistors on I2C Split Icc into 4 different values, corresponding to the different voltage supplies Changed Isus typical to 20uA and 220uA Added section 3.9.3 on suspend current considerations See ECN Removed all references the part number CY7C68055. Corrected the bullet in Features to state that 24 GPIO’s are available. Added the Test ID (TID#) to the Features on the front page. Made changes to the block diagram on the first page (this is now a Visio drawing instead of a Framemaker drawing). Corrected the Ambient Temperature with Power Supplied. Moved figure titles to meet the new template. Checked grammar. Took out 9-bit address bus from the block diagram on the first page. Corrected Figure 4.1 *A *B *C 434754 465471 484726 OSG OSG ARI Description of Change *D 492009 OSG See ECN Added Icc data in DC Characteristics and Maximum Power dissipation *E 500408 OSG See ECN Changed ESD spec to 1500 V *F 502115 OSG See ECN Changed ESD spec to 2000 V and 1500 V only for SCL and SDA pins. Added min spec for tOEoff Changed Icc and power dissipation numbers 1128404 OSG / ARI See ECN Removed SLCS from figure in Section 9.6 Slave FIFO Asynchronous Write Changed SLWR Pulse HIGH parameter to 50ns Section 9.13.1 9 V Removed the indication that SLCS and SLRD can be asserted together Section 9.13.3 - Removed the indication that SLCS and SLRD can be asserted together Implemented the latest template. *H 1349903 AESA See ECN Section 7 - Changed -0°C to -40°C *I 2728476 ODC 07/02/09 Deleted Note on AVcc parameter in DC Characteristics table *J 3072698 ODC 10/27/10 Template update and styles update. Included Table of Contents, Ordering Code Definitions, Acronyms, and Units of measure. Updated package diagram revision from *B to *C. *K 4212673 DBIR 12/06/2013 Updated Package Diagram: spec 001-03901 – Changed revision from *C to *E. Updated in new template. Completing Sunset Review. *L 4791911 MDDD 10/28/2015 Added More Information. Updated Figure 26 (spec 001-03901 *E to *F) in Package Diagram. *G Document Number: 001-06120 Rev *L Page 43 of 44 CY7C68053 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory PSoC Touch Sensing cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2006-2015. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-06120 Rev *L Revised October 28, 2015 Page 44 of 44 Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. MoBL-USB FX2LP18, EZ-USB FX2LP and ReNumeration are trademarks, and MoBL-USB is a registered trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.