CY7C68033/CY7C68034:EZ-USB® NX2LP-Flex™ Flexible USB NAND Flash Controller Datasheet.pdf

CY7C68033
CY7C68034
EZ-USB® NX2LP-Flex™ Flexible USB
NAND Flash Controller
EZ-USB® NX2LP-Flex™ Flexible USB NAND Flash Controller
CY7C68033/CY7C68034 Silicon Features
■
Certified compliant for bus- or self-powered USB 2.0 operation
(TID# 40490118)
■
Single-chip, integrated USB 2.0 transceiver and smart SIE
■
Ultra low power – 43 mA typical current draw in any mode
■
Enhanced 8051 core
❐ Firmware runs from internal RAM that is downloaded from
NAND Flash at startup
❐ No external EEPROM required
■
15 KBytes of on-chip code/data RAM
❐ Default NAND firmware – 8 kB
❐ Default free space – 7 kB
■
Four programmable bulk/interrupt/isochronous endpoints
❐ Buffering options: double, triple, and quad
■
Additional programmable (bulk/interrupt) 64-byte endpoint
■
SmartMedia standard hardware ECC generation with 1-bit
correction and 2-bit detection
■
■
■
Integrated, industry-standard enhanced 8051
❐ 48-MHz, 24-MHz, or 12-MHz CPU operation
❐ Four clocks for each instruction cycle
❐ Three counter/timers
❐ Expanded interrupt system
❐ Two data pointers
■
3.3-V operation with 5 V tolerant inputs
■
Vectored USB interrupts and GPIF/FIFO interrupts
■
Separate data buffers for the setup and data portions of a
control transfer
■
Integrated I2C controller, runs at 100 or 400 kHz
■
Four integrated FIFOs
❐ Integrated glue logic and FIFOs lower system cost
❐ Automatic conversion to and from 16-bit buses
❐ Master or slave operation
❐ Uses external clock or asynchronous strobes
❐ Easy interface to ASIC and DSP ICs
■
Available in space saving 56-pin QFN package
General programmable interface (GPIF)
❐ Enables direct connection to most parallel interfaces
❐ Programmable waveform descriptors and configuration
registers to define waveforms
❐ Supports multiple ready (RDY) inputs and control (CTL)
outputs
CY7C68034 Only Silicon Features
12 fully programmable general purpose I/O (GPIO) pins
■
■
Ideal for battery powered applications
❐ Suspend current: 100 A (typ)
CY7C68033 Only Silicon Features
Ideal for non-battery powered applications
❐ Suspend current: 300 A (typ)
Logic Block Diagram
High-performance,
enhanced 8051 core
with low power options
24 MHz
Ext. Xtal
NX2LP-Flex
/0.5
/1.0
/2.0
8051 Core
12/24/48 MHz,
four clocks/cycle
VCC
Connected for
full speed USB
1.5k
NAND
Boot Logic
(ROM)
D+
D–
USB
2.0
XCVR
Integrated full- and
high speed XCVR
CY
Smart
USB
1.1/2.0
Engine
15 kB
RAM
I 2C
Master
Address (16)/Data Bus (8)
x 20
PLL
Additional I/Os
GPIF
RDY (2)
CTL (3)
ECC
Up to 96 MB/s burst rate
4 kB
FIFO
Enhanced USB core
simplifies 8051 code
Cypress Semiconductor Corporation
Document Number: 001-04247 Rev. *N
•
General Programmable
I/F to ASIC/DSP or bus
standards such as 8-bit
NAND, EPP, and so on.
‘Soft Configuration’ enables
easy firmware changes
198 Champion Court
8/16
FIFO and USB endpoint memory
(master or slave modes)
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 21, 2015
CY7C68033
CY7C68034
■
Because the NX2LP-Flex is intended for NAND Flash-based
USB mass storage applications, a default firmware image is
included in the development kit with the following features:
Industry standard (SmartMedia) page management for wear
leveling algorithm, bad block handling, and physical to logical
management.
■
8-bit NAND Flash interface support
■
High-Speed (480 Mbps) or Full-Speed (12 Mbps) USB support
■
Support for 30 ns, 50 ns, and 100 ns NAND Flash timing
■
NAND sizes supported per chip select
❐ 512 bytes for up to 1 Gb capacity
❐ 2K bytes for up to 8 Gb capacity
❐ 4K bytes for up to 16 Gb capacity
■
Complies with the USB mass storage class specification
revision 1.0
Default NAND Firmware Features
®
■
■
12 configurable GPIO pins
❐ Two dedicated chip enable (CE#) pins
❐ Six configurable CE#/GPIO pins
• Up to eight NAND Flash single-device (single-die) chips
are supported
• Up to four NAND Flash dual-device (dual-die) chips are
supported
• Compile option enables unused CE# pins to be configured
as GPIOs
❐ Four dedicated GPIO pins
Industry-standard ECC NAND flash correction
❐ 1-bit error correction for every 256 bytes
❐ 2-bit error detection for every 256 bytes
Document Number: 001-04247 Rev. *N
The default firmware image implements a USB 2.0 NAND Flash
controller. This controller adheres to the Mass Storage Class
Bulk-Only Transport Specification. The USB port of the
NX2LP-Flex is connected to a host computer directly or through
the downstream port of a USB hub. The host software issues
commands and data to the NX2LP-Flex and receives status and
data from the NX2LP-Flex using standard USB protocol.
The default firmware image supports industry leading 8-bit
NAND Flash interfaces and both common NAND page sizes of
512 and 2k bytes. Up to eight CE# pins enable the NX2LP-Flex
to be connected to up to eight single or four dual-die NAND Flash
chips.
Complete source code and documentation for the default
firmware image are included in the NX2LP-Flex development kit
to enable customization for meeting design requirements.
Additionally, compile options for the default firmware enable
quick configuration of some features to decrease design effort
and increase time-to-market advantages.
Page 2 of 40
CY7C68033
CY7C68034
Contents
Overview ............................................................................ 4
Applications ...................................................................... 4
Functional Overview ........................................................ 4
USB Signaling Speed .................................................. 4
8051 Microprocessor ................................................... 4
I2C Bus ........................................................................ 5
Buses .......................................................................... 6
Enumeration ................................................................ 6
Default Silicon ID Values ............................................. 7
ReNumeration™ .......................................................... 7
Bus-powered Applications ........................................... 7
Interrupt System .......................................................... 7
Reset and Wakeup ...................................................... 9
Program/Data RAM ................................................... 10
Register Addresses ................................................... 10
Endpoint RAM ........................................................... 11
External FIFO Interface ............................................. 13
GPIF .......................................................................... 13
ECC Generation[5] ..................................................... 13
Autopointer Access ................................................... 14
I2C Controller ............................................................ 14
Pin Assignments ............................................................ 15
Register Summary .......................................................... 21
Absolute Maximum Ratings .......................................... 28
Operating Conditions ..................................................... 28
DC Electrical Characteristics ........................................ 28
USB Transceiver ....................................................... 28
Document Number: 001-04247 Rev. *N
AC Electrical Characteristics ........................................ 29
USB Transceiver ....................................................... 29
Slave FIFO Asynchronous Read ............................... 29
Slave FIFO Asynchronous Write ............................... 29
Slave FIFO Asynchronous Packet End Strobe ......... 30
Slave FIFO Output Enable ........................................ 30
Slave FIFO Address to Flags/Data ............................ 31
Slave FIFO Asynchronous Address .......................... 31
Sequence Diagram .................................................... 32
Ordering Information ...................................................... 34
Ordering Code Definitions ......................................... 34
Package Diagrams .......................................................... 35
PCB Layout Recommendations .................................... 36
Quad Flat Package No Leads (QFN)
Package Design Notes ................................................... 36
Acronyms ........................................................................ 38
Document Conventions ................................................. 38
Units of Measure ....................................................... 38
Document History Page ................................................. 39
Sales, Solutions, and Legal Information ...................... 40
Worldwide Sales and Design Support ....................... 40
Products .................................................................... 40
PSoC® Solutions ...................................................... 40
Cypress Developer Community ................................. 40
Technical Support ..................................................... 40
Page 3 of 40
CY7C68033
CY7C68034
Overview
Figure 1. Example DVB Block Diagram
Cypress Semiconductor Corporation’s EZ-USB® NX2LP-Flex
(CY7C68033/CY7C68034) is a firmware-based, programmable
version of the EZ-USB NX2LP (CY7C68023/CY7C68024),
which is a fixed-function, low power USB 2.0 NAND Flash
controller. By integrating the USB 2.0 transceiver, serial interface
engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created
a very cost-effective solution that enables feature-rich NAND
Flash-based applications.
I/O
Buttons
LCD
I/O
CTL
NX2LPFlex
D+/-
DVB
Decoder
Figure 2. Example GPS Block Diagram
NAND-Based
GPS Unit
I/O
D+/-
NAND Flash-based DVB video capture devices
■
Wireless pointer/presenter tools with NAND Flash storage
■
NAND Flash-based MPEG/TV conversion devices
■
Legacy conversion devices with NAND Flash storage
■
NAND Flash-based cameras
■
NAND Flash mass storage device with biometric (for example,
fingerprint) security
■
Home PNA devices with NAND Flash storage
■
Wireless LAN with NAND Flash storage
■
NAND Flash-based MP3 players
■
LAN networking with NAND Flash storage
CTL
NX2LPFlex
CE[7:0]
NAND Bank(s)
I/O
I/O
The NX2LP-Flex enables designers to add extra functionality to
basic NAND Flash mass storage designs, or to interface them
with other peripheral devices. Applications may include:
■
Buttons
I/O
LCD
Applications
NAND Flash-based GPS devices
NAND Bank(s)
I/O
Audio / Video I/O
The GPIF and master/slave endpoint FIFO (8- or 16-bit data bus)
provide an easy and glueless interface to popular interfaces such
as UTOPIA, EPP, I2C, PCMCIA, and most DSP processors.
■
CE[7:0]
I/O
The ingenious architecture of NX2LP-Flex results in USB data
transfer rates of over 53 Mbytes per second, the maximum
allowable USB 2.0 bandwidth, while still using a low cost 8051
microcontroller in a small 56-pin QFN package. Because it
incorporates the USB 2.0 transceiver, the NX2LP-Flex is more
economical, providing a smaller footprint solution than external
USB 2.0 SIE or transceiver implementations. With EZ-USB
NX2LP-Flex, the Cypress Smart SIE handles most of the USB
1.1 and 2.0 protocol, freeing the embedded microcontroller for
application-specific functions and decreasing development time
while ensuring USB compatibility.
NAND-Based
DVB Unit
GPS
The “Reference Designs” section of the Cypress web site
provides additional tools for typical USB 2.0 applications. Each
reference design comes complete with firmware source and
object code, schematics, and documentation.
Functional Overview
USB Signaling Speed
NX2LP-Flex operates at two of the three rates defined in the USB
Specification Revision 2.0, dated April 27, 2000:
■
Full speed, with a signaling bit rate of 12 Mbps
■
High speed, with a signaling bit rate of 480 Mbps.
NX2LP-Flex does not support the low speed signaling mode of
1.5 Mbps.
8051 Microprocessor
The 8051 microprocessor embedded in the NX2LP-Flex has
256 bytes of register RAM, an expanded interrupt system and
three timer/counters.
Document Number: 001-04247 Rev. *N
Page 4 of 40
CY7C68033
CY7C68034
8051 Clock Frequency
Special Function Registers
NX2LP-Flex has an on-chip oscillator circuit that uses an
external 24 MHz (±100 ppm) crystal with the following
characteristics:
Certain 8051 SFR addresses are populated to provide fast
access to critical NX2LP-Flex functions. These SFR additions
are shown in Table 1 on page 6. Bold type indicates
non-standard, enhanced 8051 registers. The two SFR rows that
end with ‘0’ and ‘8’ contain bit-addressable registers. The four I/O
ports A–D use the SFR addresses used in the standard 8051 for
ports 0–3, which are not implemented in NX2LP-Flex. Because
of the faster and more efficient SFR addressing, the NX2LP-Flex
I/O ports are not addressable in external RAM space (using the
MOVX instruction).
■
Parallel resonant
■
Fundamental mode
■
500 W drive level
■
12 pF (5% tolerance) load capacitors.
An on-chip PLL multiplies the 24-MHz oscillator up to 480 MHz,
as required by the transceiver/PHY, and internal counters divide
it down for use as the 8051 clock. The default 8051 clock
frequency is 12 MHz. The clock frequency of the 8051 can be
changed by the 8051 through the CPUCS register, dynamically
Figure 3. Crystal Configuration
C1 24 MHz C2
12 pF
I2C Bus
NX2LP supports the I2C bus as a master only at 100/400 kHz.
SCL and SDA pins have open-drain outputs and hysteresis
inputs. These signals must be pulled up to 3.3 V, even if no I2C
device is connected. The I2C bus is disabled at startup and only
available for use after the initial NAND access.
12 pF
20 × PLL
12-pF capacitor values assumes a trace capacitance
of 3 pF per side on a four-layer FR4 PCA
Document Number: 001-04247 Rev. *N
Page 5 of 40
CY7C68033
CY7C68034
Table 1. Special Function Registers
x
8x
9x
Ax
Bx
Cx
Dx
Ex
Fx
0
IOA
IOB
IOC
IOD
SCON1
PSW
ACC
B
SBUF1
EICON
EIE
EIP
1
SP
EXIF
INT2CLR
IOE
2
DPL0
MPAGE
INT4CLR
OEA
3
DPH0
OEB
4
DPL1
OEC
5
DPH1
OED
6
DPS
OEE
7
PCON
8
TCON
9
TMOD
SBUF0
A
TL0
AUTOPTRH1
B
TL1
C
TH0
D
TH1
AUTOPTRH2
GPIFSGLDATH
E
CKCON
AUTOPTRL2
GPIFSGLDATLX
F
SCON0
IE
IP
T2CON
EP2468STAT
EP01STAT
RCAP2L
AUTOPTRL1
EP24FIFOFLGS
GPIFTRIG
RCAP2H
RESERVED
EP68FIFOFLGS
RESERVED
AUTOPTRSETUP
TL2
TH2
GPIFSGLDATLNOX
Buses
The NX2LP-Flex features an 8- or 16-bit ‘FIFO’ bidirectional data bus, multiplexed on I/O ports B and D.
The default firmware image implements an 8-bit data bus in GPIF master mode. It is recommended that additional interfaces added
to the default firmware image use this 8-bit data bus.
Enumeration
During the startup sequence, internal logic checks for the presence of NAND Flash with valid firmware. If valid firmware is found, the
NX2LP-Flex loads it and operates according to the firmware. If no NAND Flash is detected, or if no valid firmware is found, the
NX2LP-Flex uses the default values from internal ROM space for manufacturing mode operation. The two modes of operation are
described in the section Normal Operation Mode on page 7 and Manufacturing Mode on page 7.
Document Number: 001-04247 Rev. *N
Page 6 of 40
CY7C68033
CY7C68034
Figure 4. NX2LP-Flex Enumeration Sequence
Start-up
Yes
NAND Flash
Present?
No
Default Silicon ID Values
To facilitate proper USB enumeration when no programmed
NAND Flash is present, the NX2LP-Flex has default silicon ID
values stored in ROM space. The default silicon ID values should
only be used for development purposes. Designers must use
their own Vendor ID for final products. A Vendor ID is obtained
through registration with the USB Implementor’s Forum
(USB-IF). If the NX2LP-Flex is used as a mass storage class
device, a unique USB serial number is required for each device
to comply with the USB Mass Storage class specification.
Cypress provides all the software tools and drivers necessary to
properly programme and test the NX2LP-Flex. Refer to the
documentation in the development kit for more information on
these topics.
NAND Flash
Programmed?
Table 2. Default Silicon ID Values
No
Default VID/PID/DID
Yes
Load Firmware
From NAND
Load Default
Descriptors and
Configuration Data
Vendor ID
0x04B4
Cypress Semiconductor
Product ID
0x8613
EZ-USB® Default
Device release
0xAnnn
Depends on chip revision
(nnn = chip revision, where first
silicon = 001)
ReNumeration™
Cypress’s ReNumeration feature is used in conjunction with the
NX2LP-Flex manufacturing software tools to enable first-time
NAND programming. It is only available when used in
conjunction with the NX2LP-Flex manufacturing tools, and is not
enabled during normal operation.
Enumerate
According To
Firmware
Enumerate As
Unprogrammed
NX2LP-Flex
Normal Operation
Mode
Manufacturing
Mode
Bus-powered Applications
The NX2LP-Flex fully supports bus-powered designs by
enumerating with less than 100 mA, as required by the USB 2.0
specification.
Interrupt System
Normal Operation Mode
In normal operation mode, the NX2LP-Flex behaves as a
USB 2.0 Mass Storage Class NAND Flash controller. This
includes all typical USB device states (powered, configured, and
so on). The USB descriptors are returned according to the data
stored in the configuration data memory area. Normal read and
write access to the NAND Flash is available in this mode.
Manufacturing Mode
In manufacturing mode, the NX2LP-Flex enumerates using the
default descriptors and configuration data that are stored in
internal ROM space. This mode enables for first time
programming of the configuration data memory area, and board
level manufacturing tests.
Document Number: 001-04247 Rev. *N
INT2 Interrupt Request and Enable Registers
NX2LP-Flex implements an autovector feature for INT2 and
INT4. There are 27 INT2 (USB) vectors and 14 INT4
(FIFO/GPIF) vectors. For more details, refer to the EZ-USB
Technical Reference Manual (TRM).
USB-Interrupt Autovectors
The main USB interrupt is shared by 27 interrupt sources. To
save the code and processing time normally required to identify
the individual USB interrupt source, the NX2LP-Flex provides a
second level of interrupt vectoring, called Autovectoring. When
a USB interrupt is asserted, the NX2LP-Flex pushes the program
counter to its stack and then jumps to address 0x0500; it expects
to find a ‘jump’ instruction to the USB Interrupt service routine
here.
Developers familiar with Cypress’s programmable USB devices
should note that these interrupt vector values differ from those
used in other EZ-USB microcontrollers. This is due to the
additional NAND boot logic that is present in the NX2LP-Flex
ROM space. Also, these values are fixed and cannot be changed
in the firmware.
Page 7 of 40
CY7C68033
CY7C68034
Table 3. INT2 USB Interrupts
USB Interrupt Table For INT2
Priority
INT2VEC Value
Source
Notes
1
0x500
SUDAV
Setup data available
2
0x504
SOF
Start of frame (or microframe)
3
0x508
SUTOK
Setup token received
4
0x50C
SUSPEND
USB suspend request
5
0x510
USB RESET
Bus reset
6
0x514
HISPEED
Entered high speed operation
7
0x518
EP0ACK
NX2LP ACK’d the CONTROL handshake
8
0x51C
Reserved
9
0x520
EP0-IN
EP0-IN ready to be loaded with data
10
0x524
EP0-OUT
EP0-OUT has USB data
11
0x528
EP1-IN
EP1-IN ready to be loaded with data
12
0x52C
EP1-OUT
EP1-OUT has USB data
13
0x530
EP2
IN: buffer available. OUT: buffer has data
14
0x534
EP4
IN: buffer available. OUT: buffer has data
15
0x538
EP6
IN: buffer available. OUT: buffer has data
16
0x53C
EP8
IN: buffer available. OUT: buffer has data
17
0x540
IBN
18
0x544
IN-Bulk-NAK (any IN endpoint)
Reserved
19
0x548
EP0PING
EP0 OUT was pinged and it NAK’d
20
0x54C
EP1PING
EP1 OUT was pinged and it NAK’d
21
0x550
EP2PING
EP2 OUT was pinged and it NAK’d
22
0x554
EP4PING
EP4 OUT was pinged and it NAK’d
23
0x558
EP6PING
EP6 OUT was pinged and it NAK’d
24
0x55C
EP8PING
EP8 OUT was pinged and it NAK’d
25
0x560
ERRLIMIT
Bus errors exceeded the programmed limit
26
0x564
Reserved
27
0x568
Reserved
28
0x56C
Reserved
29
0x570
EP2ISOERR
ISO EP2 OUT PID sequence error
30
0x574
EP4ISOERR
ISO EP4 OUT PID sequence error
31
0x578
EP6ISOERR
ISO EP6 OUT PID sequence error
32
0x57C
EP8ISOERR
ISO EP8 OUT PID sequence error
If autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the NX2LP-Flex substitutes its INT2VEC byte. Therefore, if the
high byte (‘page’) of a jump-table address is preloaded at location 0x544, the automatically inserted INT2VEC byte at 0x545 directs
the jump to the correct address out of the 27 addresses within the page.
FIFO/GPIF Interrupt (INT4)
Just as the USB Interrupt is shared among 27 individual USB-interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual
FIFO/GPIF sources. The FIFO/GPIF Interrupt, such as the USB Interrupt, can employ autovectoring. Table 4 on page 9 shows the
priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources.
Document Number: 001-04247 Rev. *N
Page 8 of 40
CY7C68033
CY7C68034
Table 4. Individual FIFO/GPIF Interrupt Sources
Priority
INT4VEC Value
Source
1
0x580
EP2PF
Endpoint 2 programmable flag
Notes
2
0x584
EP4PF
Endpoint 4 programmable flag
3
0x588
EP6PF
Endpoint 6 programmable flag
4
0x58C
EP8PF
Endpoint 8 programmable flag
5
0x590
EP2EF
Endpoint 2 empty flag
6
0x594
EP4EF
Endpoint 4 empty flag
7
0x598
EP6EF
Endpoint 6 empty flag
8
0x59C
EP8EF
Endpoint 8 empty flag
9
0x5A0
EP2FF
Endpoint 2 full flag
10
0x5A4
EP4FF
Endpoint 4 full flag
11
0x5A8
EP6FF
Endpoint 6 full flag
12
0x5AC
EP8FF
13
0x5B0
GPIFDONE
14
0x5B4
GPIFWF
If autovectoring is enabled (AV4EN = 1 in the INTSET-UP
register), the NX2LP-Flex substitutes its INT4VEC byte.
Therefore, if the high byte (‘page’) of a jump-table address is
preloaded at location 0x554, the automatically inserted
INT4VEC byte at 0x555 directs the jump to the correct address
out of the 14 addresses within the page. When the ISR occurs,
the NX2LP-Flex pushes the program counter to its stack and
then jumps to address 0x553; it expects to find a ‘jump’
instruction to the ISR Interrupt service routine here.
Reset and Wakeup
Reset Pin
The input pin RESET#, resets the NX2LP-Flex when asserted.
This pin has hysteresis and is active LOW. When a crystal is
Endpoint 8 full flag
GPIF operation complete
GPIF waveform
used as the clock source for the NX2LP-Flex, the reset period
must enable the stabilization of the crystal and the PLL. This
reset period should be approximately 5 ms after VCC has
reached 3.0V. If the crystal input pin is driven by a clock signal,
the internal PLL stabilizes in 200 s after VCC has reached
3.0 V[1]. Figure 5 shows a POR condition and a reset applied
during operation. A POR is defined as the time reset is asserted
while power is being applied to the circuit. A powered reset is
defined to be when the NX2LP-Flex has previously been
powered on and operating and the RESET# pin is asserted.
For more information on power on reset implementation for the
EZ-USB family of products, refer to the application note
EZ-USB FX2™/AT2™/SX2™.
Figure 5. Reset Timing Plots
RESET#
RESET#
VIL
VIL
3.3 V
3.0 V
3.3 V
VCC
VCC
0V
0V
TRESET
Power-on Reset
TRESET
Powered Reset
Note
1. If the external clock is powered at the same time as the CY7C68033/CY7C68034 and has a stabilization wait period, it must be added to the 200 s.
Document Number: 001-04247 Rev. *N
Page 9 of 40
CY7C68033
CY7C68034
Figure 6. Internal Code Memory
Table 5. Reset Timing Values
Condition
TRESET
Power-on reset with crystal
Power-on reset with external
clock source
FFFF
7.5 kBytes
USB registers
and 4 kBytes
FIFO buffers
(RD#, WR#)
5 ms
200 s + Clock stability time
Powered reset
E200
E1FF
200 s
E000
512 Bytes RAM Data
(RD#, WR#)*
Wakeup Pins
The 8051 puts itself and the rest of the chip into a power down
mode by setting PCON.0 = 1. This stops the oscillator and PLL.
When WAKEUP is asserted by external logic, the oscillator
restarts, after the PLL stabilizes, and then the 8051 receives a
wakeup interrupt. This applies whether or not NX2LP-Flex is
connected to the USB.
3FFF
15 kBytes RAM
Code and Data
(PSEN#, RD#,
WR#)*
The NX2LP-Flex exits the power down (USB suspend) state
using one of the following methods:
■
USB bus activity (if D+/D– lines are left floating, noise on these
lines may indicate activity to the NX2LP-Flex and initiate a
wakeup).
■
External logic asserts the WAKEUP pin
■
External logic asserts the PA3/WU2 pin.
The second wakeup pin, WU2, can also be configured as a GPIO
pin. This enables a simple external R-C network to be used as a
periodic wakeup source. Note that WAKEUP is, by default, active
LOW.
Program/Data RAM
0500
*SUDPTR, USB download, NAND boot access
Register Addresses
Figure 7. Internal Register Addresses
FFFF
4 KBytes EP2-EP8
buffers
(8 × 512)
Internal ROM/RAM Size
The NX2LP-Flex has 1 kBytes ROM and 15 kBytes of internal
program/data RAM, where PSEN#/RD# signals are internally
ORed to enable the 8051 to access it as both program and data
memory. No USB control registers appear in this space.
Internal Code Memory
This mode implements the internal block of RAM (starting at
0x0500) as combined code and data memory, as shown in
Figure 6.
Only the internal and scratch pad RAM spaces have the following
access:
■
USB download (only supported by the Cypress manufacturing
tool)
■
Setup data pointer
■
NAND boot access.
1 kbyte ROM
0000
F000
EFFF
2 KBytes RESERVED
E800
E7FF
E7C0
E7BF
E780
E77F
E740
E73F
E700
E6FF
E500
E4FF
E480
E47F
E400
E3FF
E200
E1FF
64 Bytes EP1IN
64 Bytes EP1OUT
64 Bytes EP0 IN/OUT
64 Bytes RESERVED
8051 Addressable Registers
(512)
Reserved (128)
128 bytes GPIF Waveforms
Reserved (512)
512 bytes
8051 xdata RAM
E000
Document Number: 001-04247 Rev. *N
Page 10 of 40
CY7C68033
CY7C68034
Endpoint RAM
Setup Data Buffer
Size
A separate 8-byte buffer at 0xE6B8-0xE6BF holds the setup data
from a CONTROL transfer.
■
3 × 64 bytes
(Endpoints 0 and 1)
■
8 × 512 bytes
(Endpoints 2, 4, 6, 8)
Endpoint Configurations (High Speed Mode)
Organization
■
EP0
❐ Bidirectional endpoint zero, 64-byte buffer
■
EP1IN, EP1OUT
❐ 64-byte buffers, bulk or interrupt
■
EP2, 4, 6, 8
❐ Eight 512-byte buffers, bulk, interrupt, or isochronous.
❐ EP4 and EP8 can be double buffered, while EP2 and 6 can
be either double, triple, or quad buffered.
For high speed endpoint configuration options, see Figure 8.
Endpoints 0 and 1 are the same for every configuration. Endpoint
0 is the only control endpoint, and endpoint 1 can be either bulk
or interrupt. The endpoint buffers can be configured in any 1 of
the 12 configurations shown in the vertical columns. When
operating in full speed bulk mode, only the first 64 bytes of each
buffer are used. For example, in high speed the max packet size
is 512 bytes, but in full speed it is 64 bytes. Even though a buffer
is configured to be a 512 byte buffer, in full speed only the first
64 bytes are used. The unused endpoint buffer space is not
available for other operations. The following is an example
endpoint configuration:
EP2–1024 double buffered; EP6–512 quad buffered (column 8
in Figure 8).
Figure 8. Endpoint Configuration
EP0 IN&OUT
64
64
64
64
64
64
64
64
64
64
64
64
EP1 IN
64
64
64
64
64
64
64
64
64
64
64
64
EP1 OUT
64
64
64
64
64
64
64
64
64
64
64
64
EP2
EP2
EP2
EP2
EP2
EP2
EP2
EP2
EP2
EP2
512
512
512
512
512
512
512
512
512
512
512
512
EP4
EP4
512
512
512
512
512
512
512
512
512
512
512
512
EP6
EP6
EP6
EP6
EP6
EP6
512
512
512
512
512
512
EP8
512
512
512
1024
512
512
1
2
1024
Document Number: 001-04247 Rev. *N
3
1024
1024
512
512
1024
1024
1024
1024
1024
512
512
512
4
5
1024
6
EP6
1024
1024
512
EP6
EP6
512
512
512
512
EP6
512
1024
512
EP8
EP8
512
1024
512
EP4
1024
EP2 EP2
512
512
512
512
512
7
8
1024
9
1024
1024
EP8
EP8
512
512
512
512
10
11
1024
1024
12
Page 11 of 40
CY7C68033
CY7C68034
Default Full Speed Alternate Settings
Table 6. Default Full Speed Alternate Settings [2, 3]
Alternate Setting
ep0
ep1out
ep1in
ep2
ep4
ep6
ep8
0
64
0
0
0
0
0
0
1
64
64 bulk
64 bulk
64 bulk out (2×)
64 bulk out (2×)
64 bulk in (2×)
64 bulk in (2×)
2
64
64 int
64 int
64 int out (2×)
64 bulk out (2×)
64 int in (2×)
64 bulk in (2×)
3
64
64 int
64 int
64 iso out (2×)
64 bulk out (2×)
64 iso in (2×)
64 bulk in (2×)
Default High Speed Alternate Settings
Table 7. Default High Speed Alternate Settings[2, 3]
Alternate Setting
0
1
2
3
ep0
64
64
64
64
ep1out
0
512 bulk[4]
64 int
64 int
ep1in
0
512 bulk[4]
64 int
64 int
ep2
0
512 bulk out (2×)
512 int out (2×)
512 iso out (2×)
ep4
0
512 bulk out (2×)
512 bulk out (2×)
512 bulk out (2×)
ep6
0
512 bulk in (2×)
512 int in (2×)
512 iso in (2×)
ep8
0
512 bulk in (2×)
512 bulk in (2×)
512 bulk in (2×)
Notes
2. ‘0’ means ‘not implemented.’
3. ‘2×’ means ‘double buffered.’
4. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.
Document Number: 001-04247 Rev. *N
Page 12 of 40
CY7C68033
CY7C68034
External FIFO Interface
same configuration to implement 100-ns timing on the NAND bus
to support proper detection of all NAND Flash types.
Architecture
The NX2LP-Flex slave FIFO architecture has eight 512-byte
blocks in the endpoint RAM that directly serve as FIFO
memories, and are controlled by FIFO control signals (such as
SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags).
In operation, some of the eight RAM blocks fill or empty from the
SIE, while the others are connected to the I/O transfer logic. The
transfer logic takes two forms: the GPIF for internally generated
control signals or the slave FIFO interface for externally
controlled transfers.
Master/Slave Control Signals
The NX2LP-Flex endpoint FIFOS are implemented as eight
physically distinct 256 × 16 RAM blocks. The 8051/SIE can
switch any of the RAM blocks between two domains, the USB
(SIE) domain and the 8051-I/O Unit domain. This switching is
done virtually instantaneously, giving essentially zero transfer
time between ‘USB FIFOS’ and ‘Slave FIFOS’. Since they are
physically the same memory, no bytes are actually transferred
between buffers.
At any time, some RAM blocks are filling/emptying with USB data
under SIE control, while other RAM blocks are available to the
8051 and/or the I/O control unit. The RAM blocks operate as
single-port in the USB domain and dual-port in the 8051-I/O
domain. The blocks can be configured as single, double, triple,
or quad buffered as previously shown.
The I/O control unit implements either an internal-master (M for
master) or external-master (S for Slave) interface.
In master (M) mode, the GPIF internally controls FIFOADR[1:0]
to select a FIFO. The two RDY pins can be used as flag inputs
from an external FIFO or other logic if desired. The GPIF can be
run from an internally derived clock (IFCLK), at a rate that
transfers data up to 96 Megabytes/s (48 MHz IFCLK with 16-bit
interface).
In slave (S) mode, the NX2LP-Flex accepts an internally derived
clock (IFCLK, max. frequency 48 MHz) and SLCS#, SLRD,
SLWR, SLOE, PKTEND signals from external logic. Each
endpoint can individually be selected for byte or word operation
by an internal configuration bit and a Slave FIFO output enable
signal SLOE enables data of the selected width. External logic
must ensure that the output enable signal is inactive when writing
data to a slave FIFO. The slave interface must operate
asynchronously, where the SLRD and SLWR signals act directly
as strobes, rather than a clock qualifier as in a synchronous
mode. The signals SLRD, SLWR, SLOE and PKTEND are gated
by the signal SLCS#.
GPIF
The GPIF is a flexible 8- or 16-bit parallel interface driven by a
user-programmable finite state machine. It enables the
NX2LP-Flex to perform local bus mastering and can implement
a wide variety of protocols such as 8-bit NAND interface, printer
parallel port, and Utopia. The default NAND firmware and boot
logic uses GPIF functionality to interface with NAND Flash.
The GPIF on the NX2LP-Flex features three programmable
control outputs (CTL) and two general purpose ready inputs
(RDY). The GPIF data bus width can be 8 or 16 bits. Because
the default NAND firmware image implements an 8-bit data bus
and up to eight chip enable pins on the GPIF ports, it is
recommended that designs based upon the default firmware
image also use an 8-bit data bus.
Each GPIF vector defines the state of the control outputs and
determines what state a ready input (or multiple inputs) must be
before proceeding. The GPIF vector can be programmed to
advance a FIFO to the next data value, advance an address, and
so on. A sequence of the GPIF vectors make up a single
waveform that is executed to perform the desired data move
between the NX2LP-Flex and the external device.
Three Control OUT Signals
The NX2LP-Flex exposes three control signals, CTL[2:0]. CTLx
waveform edges can be programmed to make transitions as fast
as once per clock (20.8 ns using a 48 MHz clock).
Two Ready IN Signals
The 8051 programs the GPIF unit to test the RDY pins for GPIF
branching. The 56-pin package brings out two signals, RDY[1:0].
Long Transfer Mode
In GPIF master mode, the 8051 appropriately sets GPIF
transaction count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1,
or GPIFTCB0) for unattended transfers of up to 232 transactions.
The GPIF automatically throttles data flow to prevent underflow
or overflow until the full number of requested transactions
complete. The GPIF decrements the value in these registers to
represent the current status of the transaction.
ECC Generation[5]
The NX2LP-Flex can calculate error correcting codes (ECCs) on
data that passes across its GPIF or slave FIFO interfaces. There
are two ECC configurations:
■
Two ECCs, each calculated over 256 bytes (SmartMedia
Standard)
■
One ECC calculated over 512 bytes.
GPIF and FIFO Clock Rates
An 8051 register bit selects one of two frequencies for the
internally supplied interface clock: 30 MHz and 48 MHz. A bit
within the IFCONFIG register inverts the IFCLK signal.
The default NAND firmware image implements a 48 MHz
internally supplied interface clock. The NAND boot logic uses the
The following two ECC configurations are selected by the ECCM
bit. The ECC can correct any one-bit error or detect any two-bit
error.
Note
5. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.
Document Number: 001-04247 Rev. *N
Page 13 of 40
CY7C68033
CY7C68034
ECCM = 0
Autopointer Access
Two 3-byte ECCs, each calculated over a 256-byte block of data.
This configuration conforms to the SmartMedia Standard and is
used by both the NAND boot logic and default NAND firmware
image.
NX2LP-Flex provides two identical autopointers. They are
similar to the internal 8051 data pointers, but with an additional
feature: they can optionally increment after every memory
access. Also, the autopointers can point to any NX2LP-Flex
register or endpoint buffer space.
When any value is written to ECCRESET and data is then
passed across the GPIF or slave FIFO interface, the ECC for the
first 256 bytes of data is calculated and stored in ECC1. The ECC
for the next 256 bytes of data is stored in ECC2. After the second
ECC is calculated, the values in the ECCx registers do not
change until ECCRESET is written again, even if more data is
subsequently passed across the interface.
I2C Controller
NX2LP has one I2C port that the 8051, once running uses to
control external I2C devices. The I2C port operates in master
mode only. The I2C post is disabled at startup and only available
for use after the initial NAND access.
ECCM = 1
I2C Port Pins
One 3-byte ECC calculated over a 512-byte block of data.
The I2C pins SCL and SDA must have external 2.2-k pull up
resistors even if no EEPROM is connected to the NX2LP.
When any value is written to ECCRESET and data is then
passed across the GPIF or slave FIFO interface, the ECC for the
first 512 bytes of data is calculated and stored in ECC1; ECC2
is unused. After the ECC is calculated, the value in ECC1 does
not change until ECCRESET is written again, even if more data
is subsequently passed across the interface
Document Number: 001-04247 Rev. *N
I2C Interface General-Purpose Access
The 8051 can control peripherals connected to the I2C bus using
the I2CTL and I2DATA registers. NX2LP provides I2C master
control only and is never an I2C slave.
Page 14 of 40
CY7C68033
CY7C68034
Pin Assignments
Figure 9 and Figure 10 on page 16 identify all signals for the
56-pin NX2LP-Flex package.
Three modes of operation are available for the NX2LP-Flex: Port
mode, GPIF Master mode, and Slave FIFO mode. These modes
define the signals on the right edge of each column in Figure 9.
The right-most column details the signal functionality from the
default NAND firmware image, which actually utilizes GPIF
Master mode. The signals on the left edge of the ‘Port’ column
are common to all modes of the NX2LP-Flex. The 8051 selects
the interface mode using the IFCONFIG[1:0] register bits. Port
mode is the power-on default configuration.
Figure 10 on page 16 details the pinout of the 56-pin package
and lists pin names for all modes of operation. Pin names with
an asterisk (*) feature programmable polarity.
Figure 9. Port and Signal Mapping
Port
GPIF Master
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
XTALIN
XTALOUT
RESET#
WAKEUP#
SCL
SDATA
DPLUS
DMINUS
PA7
PA6
PA5
PA4
WU2/PA3
PA2
INT1#/PA1
INTO#/PA0
PE0
PE1
Document Number: 001-04247 Rev. *N
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
RDY0
RDY1
CTL0
CTL1
 CTL2
PA7
PA6
 PA5
PA4
 PA3/WU2
 PA2
 PA1/INT1#
 PA0/INT0#
GPIO8
GPIO9
Slave FIFO
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
SLRD
SLWR
FLAGA
FLAGB
FLAGC
FLAGD/SLCS#/PA7
PKTEND
FIFOADR1
FIFOADR0
PA3/WU2
SLOE
PA1/INT1#
PA0/INT0#
GPIO8
GPIO9
Default NAND
Firmware Use
CE7#/GPIO7
CE6#/GPIO6
CE5#/GPIO5
CE4#/GPIO4
CE3#/GPIO3
CE2#/GPIO2
CE1#
CE0#
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
 R_B1#
R_B2#
WE#
RE0#
RE1#
GPIO1
GPIO0
WP_SW#
WP_NF#
LED2#
LED1#
ALE
CLE
GPIO8
GPIO9
Page 15 of 40
CY7C68033
CY7C68034
Figure 10. CY7C68033/CY7C68034 56-pin QFN Pin Assignment
GND
VCC
GPIO9
GND
PD7/FD15
PD6/FD14
PD5/FD13
PD4/FD12
PD3/FD11
PD2/FD10
PD1/FD9
PD0/FD8
*WAKEUP
VCC
56
55
54
53
52
51
50
49
48
47
46
45
44
43
RDY0/*SLRD
1
42
RESET#
RDY1/*SLWR
2
41
GND
AVCC
3
40
PA7/*FLAGD/SLCS#
XTALOUT
4
39
PA6/*PKTEND
XTALIN
5
38
PA5/FIFOADR1
AGND
6
37
PA4/FIFOADR0
AVCC
7
36
PA3/*WU2
DPLUS
8
35
PA2/*SLOE
DMINUS
9
34
PA1/INT1#
AGND 10
33
PA0/INT0#
VCC 11
32
VCC
GND 12
31
CTL2/*FLAGC
GPIO8 13
30
CTL1/*FLAGB
RESERVED# 14
29
CTL0/*FLAGA
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SCL
SDATA
VCC
PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3
PB4/FD4
PB5/FD5
PB6/FD6
PB7/FD7
GND
VCC
GND
Document Number: 001-04247 Rev. *N
Page 16 of 40
CY7C68033
CY7C68034
Table 8. NX2LP-Flex Pin Descriptions [6]
56-pin
QFN Pin
Number
Default Pin
Name
NAND
Firmware
Usage
Pin
Type
Default
State
Description
9
DMINUS
N/A
I/O/Z
Z
USB D– Signal. Connect to the USB D– signal.
8
DPLUS
N/A
I/O/Z
Z
USB D+ Signal. Connect to the USB D+ signal.
42
RESET#
N/A
Input
N/A
Active LOW Reset. Resets the entire chip. See section Reset and
Wakeup on page 9 for more details.
5
XTALIN
N/A
Input
N/A
Crystal Input. Connect this signal to a 24 MHz parallel-resonant,
fundamental mode crystal and load capacitor to GND.
It is also correct to drive XTALIN with an external 24 MHz square
wave derived from another clock source. When driving from an
external source, the driving signal should be a 3.3 V square wave.
4
XTALOUT
N/A
Output
N/A
Crystal Output. Connect this signal to a 24 MHz parallel-resonant,
fundamental mode crystal and load capacitor to GND.
If an external clock is used to drive XTALIN, leave this pin open.
54
PE1 or GPIO9
GPIO9
O/Z
1
RDY0 or SLRD
R_B1#
Input
N/A
Multiplexed pin whose function is selected by IFCONFIG[1:0].
RDY0 is a GPIF input signal.
SLRD is the input-only read strobe with programmable polarity
(FIFOPINPOLAR[3]) for the slave FIFOs connected to FD[7:0] or
FD[15:0].
R_B1# is a NAND Ready/Busy input signal.
2
RDY1 or SLWR
R_B2#
Input
N/A
Multiplexed pin whose function is selected by IFCONFIG[1:0].
RDY1 is a GPIF input signal.
SLWR is the input-only write strobe with programmable polarity
(FIFOPINPOLAR[2]) for the slave FIFOs connected to FD[7:0] or
FD[15:0].
R_B2# is a NAND Ready/Busy input signal.
29
CTL0 or
FLAGA
WE#
O/Z
H
Multiplexed pin whose function is selected by IFCONFIG[1:0].
CTL0 is a GPIF control output.
FLAGA is a programmable slave-FIFO output status flag signal.
Defaults to programmable for the FIFO selected by the
FIFOADR[1:0] pins.
WE# is the NAND write enable output signal.
30
CTL1 or
FLAGB
RE0#
O/Z
H
Multiplexed pin whose function is selected by IFCONFIG[1:0].
CTL1 is a GPIF control output.
FLAGB is a programmable slave-FIFO output status flag signal.
Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins.
RE0# is a NAND read enable output signal.
31
CTL2 or
FLAGC
RE1#
O/Z
H
Multiplexed pin whose function is selected by IFCONFIG[1:0].
CTL2 is a GPIF control output.
FLAGC is a programmable slave-FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins.
RE1# is a NAND read enable output signal.
12 MHz GPIO9 is a bidirectional I/O port pin.
Note
6. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power up and in
standby. Note also that no pins should be driven while the device is powered down.
Document Number: 001-04247 Rev. *N
Page 17 of 40
CY7C68033
CY7C68034
Table 8. NX2LP-Flex Pin Descriptions (continued)[6]
56-pin
QFN Pin
Number
Default Pin
Name
NAND
Firmware
Usage
Pin
Type
Default
State
13
PE0 or GPIO8
GPIO8
I/O/Z
I
Description
GPIO8: is a bidirectional I/O port pin.
14
Reserved#
N/A
Input
N/A
15
SCL
N/A
OD
Z
Clock for the I2C interface. Connect to VCC with a 2.2K resistor,
even if no I2C peripheral is attached.
Reserved. Connect to ground.
16
SDATA
N/A
OD
Z
Data for the I2C interface. Connect to VCC with a 2.2K resistor, even
if no I2C peripheral is attached.
44
WAKEUP
Unused
Input
N/A
USB Wakeup. If the 8051 is in suspend, asserting this pin starts up
the oscillator and interrupts the 8051 to allow it to exit the suspend
mode. Holding WAKEUP asserted inhibits the EZ-USB chip from
suspending. This pin has programmable polarity, controlled by
WAKEUP[4].
Port A
33
PA0 or INT0#
CLE
I/O/Z
I (PA0) Multiplexed pin whose function is selected by PORTACFG[0]
PA0 is a bidirectional I/O port pin.
INT0# is the active-LOW 8051 INT0 interrupt input signal, which is
either edge triggered (IT0 = 1) or level triggered (IT0 = 0).
CLE is the NAND Command Latch Enable signal.
34
PA1 or INT1#
ALE
I/O/Z
I (PA1) Multiplexed pin whose function is selected by PORTACFG[1]
PA1 is a bidirectional I/O port pin.
INT1# is the active-LOW 8051 INT1 interrupt input signal, which is
either edge triggered (IT1 = 1) or level triggered (IT1 = 0).
ALE is the NAND Address Latch Enable signal.
35
PA2 or SLOE
LED1#
I/O/Z
I (PA2) Multiplexed pin whose function is selected by IFCONFIG[1:0].
PA2 is a bidirectional I/O port pin.
SLOE is an input-only output enable with programmable polarity
(FIFOPINPOLAR[4]) for the slave FIFOs connected to FD[7:0] or
FD[15:0].
LED1# is the data activity indicator LED sink pin.
36
PA3 or WU2
LED2#
I/O/Z
I (PA3) Multiplexed pin whose function is selected by WAKEUP[7] and
OEA[3]
PA3 is a bidirectional I/O port pin.
WU2 is an alternate source for USB Wakeup, enabled by WU2EN
bit (WAKEUP[1]) and polarity set by WU2POL (WAKEUP[4]). If the
8051 is in suspend and WU2EN = 1, a transition on this pin starts
up the oscillator and interrupts the 8051 to allow it to exit the suspend
mode. Asserting this pin inhibits the chip from suspending, if
WU2EN = 1.
LED2# is the chip activity indicator LED sink pin.
37
PA4 or
FIFOADR0
WP_NF#
I/O/Z
I (PA4) Multiplexed pin whose function is selected by IFCONFIG[1:0].
PA4 is a bidirectional I/O port pin.
FIFOADR0 is an input-only address select for the slave FIFOs
connected to FD[7:0] or FD[15:0].
WP_NF# is the NAND write-protect control output signal.
38
PA5 or
FIFOADR1
WP_SW#
I/O/Z
I (PA5) Multiplexed pin whose function is selected by IFCONFIG[1:0].
PA5 is a bidirectional I/O port pin.
FIFOADR1 is an input-only address select for the slave FIFOs
connected to FD[7:0] or FD[15:0].
WP_SW# is the NAND write-protect switch input signal.
Document Number: 001-04247 Rev. *N
Page 18 of 40
CY7C68033
CY7C68034
Table 8. NX2LP-Flex Pin Descriptions (continued)[6]
56-pin
QFN Pin
Number
Default Pin
Name
NAND
Firmware
Usage
Pin
Type
Default
State
Description
39
PA6 or
PKTEND
GPIO0 (Input)
I/O/Z
I (PA6) Multiplexed pin whose function is selected by the IFCONFIG[1:0]
bits.
PA6 is a bidirectional I/O port pin.
PKTEND is an input used to commit the FIFO packet data to the
endpoint
and
whose
polarity
is
programmable
via
FIFOPINPOLAR[5].
GPIO1 is a general purpose I/O signal.
40
PA7 or FLAGD
or SLCS#
GPIO1 (Input)
I/O/Z
I (PA7) Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and PORTACFG[7] bits.
PA7 is a bidirectional I/O port pin.
FLAGD is a programmable slave-FIFO output status flag signal.
SLCS# gates all other slave FIFO enable/strobes
GPIO0 is a general purpose I/O signal.
Port B
18
PB0 or FD[0]
DD0
I/O/Z
I (PB0) Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB0 is a bidirectional I/O port pin.
FD[0] is the bidirectional FIFO/GPIF data bus.
DD0 is a bidirectional NAND data bus signal.
19
PB1 or FD[1]
DD1
I/O/Z
I (PB1) Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB1 is a bidirectional I/O port pin.
FD[1] is the bidirectional FIFO/GPIF data bus.
DD1 is a bidirectional NAND data bus signal.
20
PB2 or FD[2]
DD2
I/O/Z
I (PB2) Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB2 is a bidirectional I/O port pin.
FD[2] is the bidirectional FIFO/GPIF data bus.
DD2 is a bidirectional NAND data bus signal.
21
PB3 or FD[3]
DD3
I/O/Z
I (PB3) Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB3 is a bidirectional I/O port pin.
FD[3] is the bidirectional FIFO/GPIF data bus.
DD3 is a bidirectional NAND data bus signal.
22
PB4 or FD[4]
DD4
I/O/Z
I (PB4) Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB4 is a bidirectional I/O port pin.
FD[4] is the bidirectional FIFO/GPIF data bus.
DD4 is a bidirectional NAND data bus signal.
23
PB5 or FD[5]
DD5
I/O/Z
I (PB5) Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB5 is a bidirectional I/O port pin.
FD[5] is the bidirectional FIFO/GPIF data bus.
DD5 is a bidirectional NAND data bus signal.
24
PB6 or FD[6]
DD6
I/O/Z
I (PB6) Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB6 is a bidirectional I/O port pin.
FD[6] is the bidirectional FIFO/GPIF data bus.
DD6 is a bidirectional NAND data bus signal.
25
PB7 or FD[7]
DD7
I/O/Z
I (PB7) Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB7 is a bidirectional I/O port pin.
FD[7] is the bidirectional FIFO/GPIF data bus.
DD7 is a bidirectional NAND data bus signal.
PD0 or FD[8]
CE0#
I/O/Z
I (PD0) Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and EPxFIFOCFG.0 (wordwide) bits.
FD[8] is the bidirectional FIFO/GPIF data bus.
CE0# is a NAND chip enable output signal.
PORT D
45
Document Number: 001-04247 Rev. *N
Page 19 of 40
CY7C68033
CY7C68034
Table 8. NX2LP-Flex Pin Descriptions (continued)[6]
56-pin
QFN Pin
Number
Default Pin
Name
NAND
Firmware
Usage
Pin
Type
Default
State
Description
46
PD1 or FD[9]
CE1#
I/O/Z
I (PD1) Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and EPxFIFOCFG.0 (wordwide) bits.
FD[9] is the bidirectional FIFO/GPIF data bus.
CE1# is a NAND chip enable output signal.
47
PD2 or FD[10]
CE2# or GPIO2
I/O/Z
I (PD2) Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and EPxFIFOCFG.0 (wordwide) bits.
FD[10] is the bidirectional FIFO/GPIF data bus.
CE2# is a NAND chip enable output signal.
GPIO2 is a general purpose I/O signal.
48
PD3 or FD[11]
CE3# or GPIO3
I/O/Z
I (PD3) Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and EPxFIFOCFG.0 (wordwide) bits.
FD[11] is the bidirectional FIFO/GPIF data bus.
CE3# is a NAND chip enable output signal.
GPIO3 is a general purpose I/O signal.
49
PD4 or FD[12]
CE4# or GPIO4
I/O/Z
I (PD4) Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and EPxFIFOCFG.0 (wordwide) bits.
FD[12] is the bidirectional FIFO/GPIF data bus.
CE4# is a NAND chip enable output signal.
GPIO4 is a general purpose I/O signal.
50
PD5 or FD[13]
CE5# or GPIO5
I/O/Z
I (PD5) Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and EPxFIFOCFG.0 (wordwide) bits.
FD[13] is the bidirectional FIFO/GPIF data bus.
CE5# is a NAND chip enable output signal.
GPIO5 is a general purpose I/O signal.
51
PD6 or FD[14]
CE6# or GPIO6
I/O/Z
I (PD6) Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and EPxFIFOCFG.0 (wordwide) bits.
FD[14] is the bidirectional FIFO/GPIF data bus.
CE6# is a NAND chip enable output signal.
GPIO6 is a general purpose I/O signal.
52
PD7 or FD[15]
CE7# or GPIO7
I/O/Z
I (PD7) Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and EPxFIFOCFG.0 (wordwide) bits.
FD[15] is the bidirectional FIFO/GPIF data bus.
CE7# is a NAND chip enable output signal.
GPIO7 is a general purpose I/O signal.
Power and Ground
3, 7
AVCC
N/A
Power
N/A
Analog VCC. Connect this pin to 3.3 V power source. This signal
provides power to the analog section of the chip.
6, 10
AGND
N/A
Ground
N/A
Analog Ground. Connect to ground with as short a path as
possible.
11, 17, VCC
27, 32,
43, 55
N/A
Power
N/A
VCC. Connect to 3.3 V power source.
12, 26, GND
28, 41,
53, 56
N/A
Ground
N/A
Ground.
Document Number: 001-04247 Rev. *N
Page 20 of 40
CY7C68033
CY7C68034
Register Summary
NX2LP-Flex register bit definitions are described in the EZ-USB TRM in greater detail. Some registers that are listed here and in the
TRM do not apply to the NX2LP-Flex. They are kept here for consistency reasons only. Registers that do not apply to the NX2LP-Flex
should be left at their default power up values.
Table 9. NX2LP-Flex Register Summary
Hex Size
E400 128
E480 128
E50D
E600 1
E601 1
E602 1
E603 1
E604 1
E605
E606
E607
E608
1
1
1
1
E609 1
E60A 1
E60B 1
E60C 1
3
E610 1
E611 1
E612
E613
E614
E615
1
1
1
1
2
E618 1
E619 1
E61A 1
E61B 1
E61C 4
E620 1
E621 1
E622 1
E623 1
E624 1
E625 1
E626 1
E627 1
E628 1
Name
Description
b7
GPIF Waveform Memories
WAVEDATA
GPIF Waveform
D7
Descriptor 0, 1, 2, 3 data
reserved
GENERAL CONFIGURATION
GPCR2
General Purpose
reserved
Configuration Register 2
CPUCS
CPU Control & Status
0
IFCONFIG
Interface Configuration
1
(Ports, GPIF, slave FIFOs)
[7]
PINFLAGSAB
Slave FIFO FLAGA and FLAGB3
FLAGB Pin Configuration
[7]
PINFLAGSCD
Slave FIFO FLAGC and FLAGD3
FLAGD Pin Configuration
FIFORESET [7]
Restore FIFOS to default NAKALL
state
BREAKPT
Breakpoint Control
0
BPADDRH
Breakpoint Address H
A15
BPADDRL
Breakpoint Address L
A7
UART230
230 Kbaud internally
0
generated ref. clock
FIFOPINPOLAR [7]
Slave FIFO Interface pins 0
polarity
REVID
Chip Revision
rv7
[7]
REVCTL
Chip Revision Control
UDMA
GPIFHOLDAMOUNT MSTB Hold Time (for
UDMA)
reserved
ENDPOINT CONFIGURATION
EP1OUTCFG
Endpoint 1-OUT
Configuration
EP1INCFG
Endpoint 1-IN
Configuration
EP2CFG
Endpoint 2 Configuration
EP4CFG
Endpoint 4 Configuration
EP6CFG
Endpoint 6 Configuration
EP8CFG
Endpoint 8 Configuration
reserved
EP2FIFOCFG [7]
Endpoint 2/slave FIFO
configuration
EP4FIFOCFG [7]
Endpoint 4/slave FIFO
configuration
[7]
EP6FIFOCFG
Endpoint 6/slave FIFO
configuration
[7]
EP8FIFOCFG
Endpoint 8/slave FIFO
configuration
reserved
EP2AUTOINLENH [7] Endpoint 2 AUTOIN
Packet Length H
EP2AUTOINLENL [7] Endpoint 2 AUTOIN
Packet Length L
EP4AUTOINLENH [7] Endpoint 4 AUTOIN
Packet Length H
EP4AUTOINLENL [7] Endpoint 4 AUTOIN
Packet Length L
EP6AUTOINLENH [7] Endpoint 6 AUTOIN
Packet Length H
EP6AUTOINLEN L [7] Endpoint 6 AUTOIN
Packet Length L
EP8AUTOINLENH [7] Endpoint 8 AUTOIN
Packet Length H
EP8AUTOINLENL [7] Endpoint 8 AUTOIN
Packet Length L
ECCCFG
ECC Configuration
b6
b5
D6
D5
reserved
reserved
b4
D4
b3
D3
b2
b1
b0
Default
Access
D2
D1
D0
xxxxxxxx
RW
reserved
reserved
reserved
00000000
R
0
3048 MHz
FULL_SPEE reserved
D_ONLY
PORTCSTB CLKSPD1 CLKSPD0
0
IFCLKPOL ASYNC
CLKINV
GSTATE
CLKOE
IFCFG1
8051RES
IFCFG0
00000010
10000000
rrbbbbbr
RW
FLAGB2
FLAGB1
FLAGB0
FLAGA3
FLAGA2
FLAGA1
FLAGA0
00000000
RW
FLAGD2
FLAGD1
FLAGD0
FLAGC3
FLAGC2
FLAGC1
FLAGC0
00000000
RW
0
0
0
EP3
EP2
EP1
EP0
xxxxxxxx
W
0
A14
A6
0
0
A13
A5
0
0
A12
A4
0
BREAK
A11
A3
0
BPPULSE
A10
A2
0
BPEN
A9
A1
230UART1
0
A8
A0
230UART0
00000000
xxxxxxxx
xxxxxxxx
00000000
rrrrbbbr
RW
RW
rrrrrrbb
0
PKTEND
SLOE
SLRD
SLWR
EF
FF
00000000
rrbbbbbb
rv6
rv5
rv4
rv3
rv2
rv1
rv0
R
0
0
0
0
0
0
dyn_out
enh_pkt
RevA
00000001
00000000
0
0
0
0
0
0
HOLDTIME1 HOLDTIME0 00000000
rrrrrrbb
VALID
0
TYPE1
TYPE0
0
0
0
0
10100000
brbbrrrr
VALID
0
TYPE1
TYPE0
0
0
0
0
10100000
brbbrrrr
VALID
VALID
VALID
VALID
DIR
DIR
DIR
DIR
TYPE1
TYPE1
TYPE1
TYPE1
TYPE0
TYPE0
TYPE0
TYPE0
SIZE
0
SIZE
0
0
0
0
0
BUF1
0
BUF1
0
BUF0
0
BUF0
0
10100010
10100000
11100010
11100000
bbbbbrbb
bbbbrrrr
bbbbbrbb
bbbbrrrr
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN 0
WORDWIDE 00000101
rbbbbbrb
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN 0
WORDWIDE 00000101
rbbbbbrb
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN 0
WORDWIDE 00000101
rbbbbbrb
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN 0
WORDWIDE 00000101
rbbbbbrb
0
0
0
0
0
PL10
PL9
PL8
00000010
rrrrrbbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000
RW
0
0
0
0
0
0
PL9
PL8
00000010
rrrrrrbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000
RW
0
0
0
0
0
PL10
PL9
PL8
00000010
rrrrrbbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000
RW
0
0
0
0
0
0
PL9
PL8
00000010
rrrrrrbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000
RW
0
0
0
0
0
0
0
ECCM
00000000
rrrrrrrb
rrrrrrbb
Note
7. The register can only be reset, it cannot be set.
Document Number: 001-04247 Rev. *N
Page 21 of 40
CY7C68033
CY7C68034
Table 9. NX2LP-Flex Register Summary (continued)
Hex Size
E629
E62A
E62B
E62C
E62D
E62E
E62F
E630
H.S.
E630
F.S.
E631
H.S.
E631
F.S
E632
H.S.
E632
F.S
E633
H.S.
E633
F.S
E634
H.S.
E634
F.S
E635
H.S.
E635
F.S
E636
H.S.
E636
F.S
E637
H.S.
E637
F.S
Name
1
1
1
1
1
1
1
1
ECCRESET
ECC1B0
ECC1B1
ECC1B2
ECC2B0
ECC2B1
ECC2B2
EP2FIFOPFH [8]
1
EP2FIFOPFH [8]
1
EP2FIFOPFL
[8]
1
EP2FIFOPFL
[8]
1
EP4FIFOPFH [8]
1
EP4FIFOPFH
[8]
1
EP4FIFOPFL
[8]
1
EP4FIFOPFL [8]
1
EP6FIFOPFH
[8]
1
EP6FIFOPFH
[8]
1
EP6FIFOPFL [8]
1
EP6FIFOPFL [8]
1
EP8FIFOPFH
[8]
1
EP8FIFOPFH
[8]
1
EP8FIFOPFL [8]
1
[8]
EP8FIFOPFL
8
E640 1
reserved
EP2ISOINPKTS
E641 1
EP4ISOINPKTS
E642 1
EP6ISOINPKTS
E643 1
EP8ISOINPKTS
E644 4
E648 1
E649 7
E650 1
reserved
INPKTEND [8]
OUTPKTEND [8]
INTERRUPTS
EP2FIFOIE [8]
E651 1
EP2FIFOIRQ [8, 9]
E652 1
EP4FIFOIE
[8]
[8, 9]
E653 1
EP4FIFOIRQ
E654 1
EP6FIFOIE [8]
E655 1
EP6FIFOIRQ
[8, 9]
[8]
E656 1
EP8FIFOIE
E657 1
EP8FIFOIRQ [8, 9]
E658 1
IBNIE
E659 1
IBNIRQ
E65A 1
NAKIE
[8]
Description
b7
b6
b2
b1
Default
Access
x
LINE12
LINE4
COL2
LINE12
LINE4
COL2
IN:PKTS[1]
OUT:PFC11
OUT:PFC11
x
x
LINE11
LINE10
LINE3
LINE2
COL1
COL0
LINE11
LINE10
LINE3
LINE2
COL1
COL0
IN:PKTS[0] 0
OUT:PFC10
OUT:PFC10 0
x
LINE9
LINE1
LINE17
LINE9
LINE1
0
PFC9
x
LINE8
LINE0
LINE16
LINE8
LINE0
0
PFC8
00000000
00000000
00000000
00000000
00000000
00000000
00000000
10001000
W
R
R
R
R
R
R
bbbbbrbb
PKTSTAT
x
LINE13
LINE5
COL3
LINE13
LINE5
COL3
IN:PKTS[2]
OUT:PFC12
OUT:PFC12
PFC9
10001000
bbbbbrbb
PFC7
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
IN:PKTS[2]
OUT:PFC8
PFC0
00000000
RW
IN:PKTS[1]
OUT:PFC7
DECIS
IN:PKTS[0]
OUT:PFC6
PKTSTAT
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000
RW
0
0
PFC8
10001000
bbrbbrrb
DECIS
PKTSTAT
0
IN: PKTS[1] IN: PKTS[0] 0
OUT:PFC10 OUT:PFC9
OUT:PFC10 OUT:PFC9 0
0
PFC8
10001000
bbrbbrrb
PFC7
PFC6
PFC5
ECC Reset
ECC1 Byte 0 Address
ECC1 Byte 1 Address
ECC1 Byte 2 Address
ECC2 Byte 0 Address
ECC2 Byte 1 Address
ECC2 Byte 2 Address
Endpoint 2/slave FIFO
Programmable Flag H
Endpoint 2/slave FIFO
Programmable Flag H
Endpoint 2/slave FIFO
Programmable Flag L
Endpoint 2/slave FIFO
Programmable Flag L
Endpoint 4/slave FIFO
Programmable Flag H
Endpoint 4/slave FIFO
Programmable Flag H
Endpoint 4/slave FIFO
Programmable Flag L
Endpoint 4/slave FIFO
Programmable Flag L
Endpoint 6/slave FIFO
Programmable Flag H
Endpoint 6/slave FIFO
Programmable Flag H
Endpoint 6/slave FIFO
Programmable Flag L
Endpoint 6/slave FIFO
Programmable Flag L
Endpoint 8/slave FIFO
Programmable Flag H
Endpoint 8/slave FIFO
Programmable Flag H
Endpoint 8/slave FIFO
Programmable Flag L
Endpoint 8/slave FIFO
Programmable Flag L
x
LINE15
LINE7
COL5
LINE15
LINE7
COL5
DECIS
x
LINE14
LINE6
COL4
LINE14
LINE6
COL4
PKTSTAT
DECIS
b5
b4
b3
b0
PFC4
PFC3
PFC2
PFC1
PFC0
00000000
RW
IN: PKTS[1] IN: PKTS[0] PFC5
OUT:PFC7 OUT:PFC6
DECIS
PKTSTAT
IN:PKTS[2]
OUT:PFC12
DECIS
PKTSTAT
OUT:PFC12
PFC4
PFC3
PFC2
PFC1
PFC0
00000000
RW
IN:PKTS[1] IN:PKTS[0] 0
OUT:PFC11 OUT:PFC10
OUT:PFC11 OUT:PFC10 0
PFC9
PFC8
00001000
bbbbbrbb
PFC9
bbbbbrbb
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
IN:PKTS[2]
OUT:PFC8
PFC0
00001000
PFC7
00000000
RW
IN:PKTS[1]
OUT:PFC7
DECIS
IN:PKTS[0]
OUT:PFC6
PKTSTAT
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000
RW
0
0
PFC8
00001000
bbrbbrrb
DECIS
PKTSTAT
0
IN: PKTS[1] IN: PKTS[0] 0
OUT:PFC10 OUT:PFC9
OUT:PFC10 OUT:PFC9 0
0
PFC8
00001000
bbrbbrrb
PFC7
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000
RW
IN: PKTS[1] IN: PKTS[0] PFC5
OUT:PFC7 OUT:PFC6
PFC4
PFC3
PFC2
PFC1
PFC0
00000000
RW
EP2 (if ISO) IN Packets
per frame (1–3)
EP4 (if ISO) IN Packets
per frame (1–3)
EP6 (if ISO) IN Packets
per frame (1–3)
EP8 (if ISO) IN Packets
per frame (1–3)
AADJ
0
0
0
0
0
INPPF1
INPPF0
00000001
brrrrrbb
AADJ
0
0
0
0
0
INPPF1
INPPF0
00000001
brrrrrrr
AADJ
0
0
0
0
0
INPPF1
INPPF0
00000001
brrrrrbb
AADJ
0
0
0
0
0
INPPF1
INPPF0
00000001
brrrrrrr
Force IN Packet End
Force OUT Packet End
Skip
Skip
0
0
0
0
0
0
EP3
EP3
EP2
EP2
EP1
EP1
EP0
EP0
xxxxxxxx
xxxxxxxx
W
W
Endpoint 2 slave FIFO
Flag Interrupt Enable
Endpoint 2 slave FIFO
Flag Interrupt Request
Endpoint 4 slave FIFO
Flag Interrupt Enable
Endpoint 4 slave FIFO
Flag Interrupt Request
Endpoint 6 slave FIFO
Flag Interrupt Enable
Endpoint 6 slave FIFO
Flag Interrupt Request
Endpoint 8 slave FIFO
Flag Interrupt Enable
Endpoint 8 slave FIFO
Flag Interrupt Request
IN-BULK-NAK Interrupt
Enable
IN-BULK-NAK interrupt
Request
Endpoint Ping-NAK/IBN
Interrupt Enable
0
0
0
0
EDGEPF
PF
EF
FF
00000000
RW
0
0
0
0
0
PF
EF
FF
00000000
rrrrrbbb
0
0
0
0
EDGEPF
PF
EF
FF
00000000
RW
0
0
0
0
0
PF
EF
FF
00000000
rrrrrbbb
0
0
0
0
EDGEPF
PF
EF
FF
00000000
RW
0
0
0
0
0
PF
EF
FF
00000000
rrrrrbbb
0
0
0
0
EDGEPF
PF
EF
FF
00000000
RW
0
0
0
0
0
PF
EF
FF
00000000
rrrrrbbb
0
0
EP8
EP6
EP4
EP2
EP1
EP0
00000000
RW
0
0
EP8
EP6
EP4
EP2
EP1
EP0
00xxxxxx
rrbbbbbb
EP8
EP6
EP4
EP2
EP1
EP0
0
IBN
00000000
RW
Notes
8. The register can only be reset, it cannot be set.
9. SFRs not part of the standard 8051 architecture.
Document Number: 001-04247 Rev. *N
Page 22 of 40
CY7C68033
CY7C68034
Table 9. NX2LP-Flex Register Summary (continued)
Hex Size
Name
E65B 1
NAKIRQ [10]
E65C 1
E65D 1
E65E 1
USBIE
USBIRQ [10]
EPIE
E65F 1
EPIRQ [10]
E660 1
E661 1
E662 1
[10]
GPIFIE
GPIFIRQ [10]
USBERRIE
E663 1
USBERRIRQ [10]
E664 1
ERRCNTLIM
E665 1
E666 1
CLRERRCNT
INT2IVEC
E667 1
INT4IVEC
E668 1
E669 7
E670 1
INTSET-UP
reserved
INPUT/OUTPUT
PORTACFG
E671 1
PORTCCFG
E672 1
PORTECFG
E673
E677
E678
E679
E67A
E67B
4
1
1
1
1
1
XTALINSRC
reserved
I2CS
I2DAT
I2CTL
XAUTODAT1
E67C 1
XAUTODAT2
E680
E681
E682
E683
E684
E685
E686
E687
E688
1
1
1
1
1
1
1
1
2
E68A
E68B
E68C
E68D
1
1
1
1
UDMA CRC
UDMACRCH [10]
UDMACRCL [10]
UDMACRCQUALIFIER
USB CONTROL
USBCS
SUSPEND
WAKEUPCS
TOGCTL
USBFRAMEH
USBFRAMEL
MICROFRAME
FNADDR
reserved
ENDPOINTS
EP0BCH [10]
EP0BCL [10]
reserved
EP1OUTBC
E68E
E68F
E690
E691
E692
E694
E695
E696
E698
E699
1
1
1
1
2
1
1
2
1
1
reserved
EP1INBC
EP2BCH [10]
EP2BCL [10]
reserved
EP4BCH [10]
EP4BCL [10]
reserved
EP6BCH [10]
EP6BCL [10]
E67D 1
E67E 1
E67F 1
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default
Access
Endpoint Ping-NAK/IBN EP8
Interrupt Request
USB Int Enables
0
USB Interrupt Requests 0
Endpoint Interrupt
EP8
Enables
Endpoint Interrupt
EP8
Requests
GPIF Interrupt Enable
0
GPIF Interrupt Request 0
USB Error Interrupt
ISOEP8
Enables
USB Error Interrupt
ISOEP8
Requests
USB Error counter and
EC3
limit
Clear Error Counter EC3:0 x
Interrupt 2 (USB)
0
Autovector
Interrupt 4 (slave FIFO & 1
GPIF) Autovector
Interrupt 2&4 setup
0
EP6
EP4
EP2
EP1
EP0
0
IBN
xxxxxx0x
bbbbbbrb
EP0ACK
EP0ACK
EP6
HSGRANT
HSGRANT
EP4
URES
URES
EP2
SUSP
SUSP
EP1OUT
SUTOK
SUTOK
EP1IN
SOF
SOF
EP0OUT
SUDAV
SUDAV
EP0IN
00000000
0xxxxxxx
00000000
RW
rbbbbbbb
RW
EP6
EP4
EP2
EP1OUT
EP1IN
EP0OUT
EP0IN
0
RW
0
0
ISOEP6
0
0
ISOEP4
0
0
ISOEP2
0
0
0
0
0
0
GPIFWF
GPIFWF
0
GPIFDONE 00000000
GPIFDONE 000000xx
ERRLIMIT 00000000
RW
RW
RW
ISOEP6
ISOEP4
ISOEP2
0
0
0
ERRLIMIT
0000000x
bbbbrrrb
EC2
EC1
EC0
LIMIT3
LIMIT2
LIMIT1
LIMIT0
xxxx0100
rrrrbbbb
x
I2V4
x
I2V3
x
I2V2
x
I2V1
x
I2V0
x
0
x
0
xxxxxxxx
00000000
W
R
0
I4V3
I4V2
I4V1
I4V0
0
0
10000000
R
0
0
0
AV2EN
0
INT4SRC
AV4EN
00000000
RW
I/O PORTA Alternate
Configuration
I/O PORTC Alternate
Configuration
I/O PORTE Alternate
Configuration
XTALIN Clock Source
FLAGD
SLCS
0
0
0
0
INT1
INT0
00000000
RW
GPIFA7
GPIFA6
GPIFA5
GPIFA4
GPIFA3
GPIFA2
GPIFA1
GPIFA0
00000000
RW
GPIFA8
T2EX
INT6
RXD1OUT
RXD0OUT T2OUT
T1OUT
T0OUT
00000000
RW
0
0
0
0
0
0
0
EXTCLK
00000000
rrrrrrrb
I2C Bus Control & Status
I2C Bus Data
I2C Bus Control
Autoptr1 MOVX access,
when APTREN=1
Autoptr2 MOVX access,
when APTREN=1
START
d7
0
D7
STOP
d6
0
D6
LASTRD
d5
0
D5
ID1
d4
0
D4
ID0
d3
0
D3
BERR
d2
0
D2
ACK
d1
STOPIE
D1
DONE
d0
400kHz
D0
000xx000
xxxxxxxx
00000000
xxxxxxxx
bbbrrrrr
RW
RW
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
UDMA CRC MSB
UDMA CRC LSB
UDMA CRC Qualifier
CRC15
CRC7
QENABLE
CRC14
CRC6
0
CRC13
CRC5
0
CRC12
CRC4
0
CRC11
CRC3
QSTATE
CRC10
CRC2
QSIGNAL2
CRC9
CRC1
QSIGNAL1
CRC8
CRC0
QSIGNAL0
01001010
10111010
00000000
RW
RW
brrrbbbb
USB Control & Status
Put chip into suspend
Wakeup Control & Status
Toggle Control
USB Frame count H
USB Frame count L
Microframe count, 0–7
USB Function address
HSM
x
WU2
Q
0
FC7
0
0
0
x
WU
S
0
FC6
0
FA6
0
x
WU2POL
R
0
FC5
0
FA5
0
x
WUPOL
I/O
0
FC4
0
FA4
DISCON
x
0
EP3
0
FC3
0
FA3
NOSYNSOF
x
DPEN
EP2
FC10
FC2
MF2
FA2
RENUM
x
WU2EN
EP1
FC9
FC1
MF1
FA1
SIGRSUME
x
WUEN
EP0
FC8
FC0
MF0
FA0
x0000000
xxxxxxxx
xx000101
x0000000
00000xxx
xxxxxxxx
00000xxx
0xxxxxxx
rrrrbbbb
W
bbbbrbbb
rrrbbbbb
R
R
R
R
Endpoint 0 Byte Count H (BC15)
Endpoint 0 Byte Count L (BC7)
(BC14)
BC6
(BC13)
BC5
(BC12)
BC4
(BC11)
BC3
(BC10)
BC2
(BC9)
BC1
(BC8)
BC0
xxxxxxxx
xxxxxxxx
RW
RW
Endpoint 1 OUT Byte
Count
BC6
BC5
BC4
BC3
BC2
BC1
BC0
0xxxxxxx
RW
Endpoint 1 IN Byte Count 0
Endpoint 2 Byte Count H 0
Endpoint 2 Byte Count L BC7/SKIP
BC6
0
BC6
BC5
0
BC5
BC4
0
BC4
BC3
0
BC3
BC2
BC10
BC2
BC1
BC9
BC1
BC0
BC8
BC0
0xxxxxxx
00000xxx
xxxxxxxx
RW
RW
RW
Endpoint 4 Byte Count H 0
Endpoint 4 Byte Count L BC7/SKIP
0
BC6
0
BC5
0
BC4
0
BC3
0
BC2
BC9
BC1
BC8
BC0
000000xx
xxxxxxxx
RW
RW
Endpoint 6 Byte Count H 0
Endpoint 6 Byte Count L BC7/SKIP
0
BC6
0
BC5
0
BC4
0
BC3
BC10
BC2
BC9
BC1
BC8
BC0
00000xxx
xxxxxxxx
RW
RW
0
Note
10. The register can only be reset, it cannot be set.
Document Number: 001-04247 Rev. *N
Page 23 of 40
CY7C68033
CY7C68034
Table 9. NX2LP-Flex Register Summary (continued)
Hex Size
E69A
E69C
E69D
E69E
E6A0
Name
2
1
1
2
1
reserved
EP8BCH [11]
EP8BCL [11]
reserved
EP0CS
E6A1 1
EP1OUTCS
E6A2 1
EP1INCS
E6A3 1
EP2CS
E6A4 1
EP4CS
E6A5 1
EP6CS
E6A6 1
EP8CS
E6A7 1
EP2FIFOFLGS
E6A8 1
EP4FIFOFLGS
E6A9 1
EP6FIFOFLGS
E6AA 1
EP8FIFOFLGS
E6AB 1
EP2FIFOBCH
E6AC 1
EP2FIFOBCL
E6AD 1
EP4FIFOBCH
E6AE 1
EP4FIFOBCL
E6AF 1
EP6FIFOBCH
E6B0 1
EP6FIFOBCL
E6B1 1
EP8FIFOBCH
E6B2 1
EP8FIFOBCL
E6B3 1
SUDPTRH
E6B4 1
SUDPTRL
E6B5 1
SUDPTRCTL
2
E6B8 8
reserved
SET-UPDAT
E6C0 1
E6C1 1
GPIF
GPIFWFSELECT
GPIFIDLECS
E6C2
E6C3
E6C4
E6C5
1
1
1
1
E6C6 1
GPIFIDLECTL
GPIFCTLCFG
GPIFADRH [11]
GPIFADRL [11]
FLOWSTATE
FLOWSTATE
E6C7 1
FLOWLOGIC
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default
Access
Endpoint 8 Byte Count H 0
Endpoint 8 Byte Count L BC7/SKIP
0
BC6
0
BC5
0
BC4
0
BC3
0
BC2
BC9
BC1
BC8
BC0
000000xx
xxxxxxxx
RW
RW
Endpoint 0 Control and
Status
Endpoint 1 OUT Control
and Status
Endpoint 1 IN Control and
Status
Endpoint 2 Control and
Status
Endpoint 4 Control and
Status
Endpoint 6 Control and
Status
Endpoint 8 Control and
Status
Endpoint 2 slave FIFO
Flags
Endpoint 4 slave FIFO
Flags
Endpoint 6 slave FIFO
Flags
Endpoint 8 slave FIFO
Flags
Endpoint 2 slave FIFO
total byte count H
Endpoint 2 slave FIFO
total byte count L
Endpoint 4 slave FIFO
total byte count H
Endpoint 4 slave FIFO
total byte count L
Endpoint 6 slave FIFO
total byte count H
Endpoint 6 slave FIFO
total byte count L
Endpoint 8 slave FIFO
total byte count H
Endpoint 8 slave FIFO
total byte count L
Setup Data Pointer high
address byte
Setup Data Pointer low
address byte
Setup Data Pointer Auto
Mode
HSNAK
0
0
0
0
0
BUSY
STALL
10000000
bbbbbbrb
0
0
0
0
0
0
BUSY
STALL
00000000
bbbbbbrb
0
0
0
0
0
0
BUSY
STALL
00000000
bbbbbbrb
0
NPAK2
NPAK1
NPAK0
FULL
EMPTY
0
STALL
00101000
rrrrrrrb
0
0
NPAK1
NPAK0
FULL
EMPTY
0
STALL
00101000
rrrrrrrb
0
NPAK2
NPAK1
NPAK0
FULL
EMPTY
0
STALL
00000100
rrrrrrrb
0
0
NPAK1
NPAK0
FULL
EMPTY
0
STALL
00000100
rrrrrrrb
0
0
0
0
0
PF
EF
FF
00000010
R
0
0
0
0
0
PF
EF
FF
00000010
R
0
0
0
0
0
PF
EF
FF
00000110
R
0
0
0
0
0
PF
EF
FF
00000110
R
0
0
0
BC12
BC11
BC10
BC9
BC8
00000000
R
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
00000000
R
0
0
0
0
0
BC10
BC9
BC8
00000000
R
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
00000000
R
0
0
0
0
BC11
BC10
BC9
BC8
00000000
R
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
00000000
R
0
0
0
0
0
BC10
BC9
BC8
00000000
R
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
00000000
R
A15
A14
A13
A12
A11
A10
A9
A8
xxxxxxxx
RW
A7
A6
A5
A4
A3
A2
A1
0
xxxxxxx0
bbbbbbbr
0
0
0
0
0
0
0
SDPAUTO
00000001
RW
8 bytes of setup data
SET-UPDAT[0] =
bmRequestType
SET-UPDAT[1] =
bmRequest
SET-UPDAT[2:3] =
wValue
SET-UPDAT[4:5] =
wIndex
SET-UPDAT[6:7] =
wLength
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
R
Waveform Selector
GPIF Done, GPIF IDLE
drive mode
Inactive Bus, CTL states
CTL Drive Type
GPIF Address H
GPIF Address L
SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1
DONE
0
0
0
0
FIFOWR0
0
FIFORD1
0
FIFORD0
IDLEDRV
11100100
10000000
RW
RW
0
TRICTL
0
GPIFA7
0
0
0
GPIFA6
CTL5
CTL5
0
GPIFA5
CTL4
CTL4
0
GPIFA4
CTL3
CTL3
0
GPIFA3
CTL2
CTL2
0
GPIFA2
CTL1
CTL1
0
GPIFA1
CTL0
CTL0
GPIFA8
GPIFA0
11111111
00000000
00000000
00000000
RW
RW
RW
RW
Flowstate Enable and
Selector
Flowstate Logic
FSE
0
0
0
0
FS2
FS1
FS0
00000000
brrrrbbb
LFUNC1
LFUNC0
TERMA2
TERMA1
TERMA0
TERMB2
TERMB1
TERMB0
00000000
RW
Note
11. The register can only be reset, it cannot be set.
Document Number: 001-04247 Rev. *N
Page 24 of 40
CY7C68033
CY7C68034
Table 9. NX2LP-Flex Register Summary (continued)
Hex Size
Name
E6C8 1
FLOWEQ0CTL
E6C9 1
FLOWEQ1CTL
E6CA 1
FLOWHOLDOFF
E6CB 1
FLOWSTB
E6CC 1
FLOWSTBEDGE
E6CD 1
E6CE 1
FLOWSTBPERIOD
GPIFTCB3 [12]
E6CF 1
GPIFTCB2 [12]
E6D0 1
GPIFTCB1 [12]
E6D1 1
[12]
GPIFTCB0
Description
CTL-Pin States in
Flowstate (when
Logic = 0)
CTL-Pin States in
Flowstate (when
Logic = 1)
Holdoff Configuration
b7
b6
CTL0E3
CTL0E2
CTL0E1 /
CTL5
CTL0E0 /
CTL4
CTL3
CTL2
CTL1
CTL0
00000000
RW
CTL0E3
CTL0E2
CTL0E1 /
CTL5
CTL0E0 /
CTL4
CTL3
CTL2
CTL1
CTL0
00000000
RW
b4
b3
HOCTL2
HOCTL1
HOCTL0
00010010
RW
MSTB2
MSTB1
MSTB0
00100000
RW
HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD HOSTATE
0
SLAVE
RDYASYNC CTLTOGL
SUSTAIN
0
Flowstate Strobe
Configuration
Flowstate Rising/Falling 0
Edge Configuration
Master-Strobe Half-Period D7
GPIF Transaction Count TC31
Byte 3
GPIF Transaction Count TC23
Byte 2
GPIF Transaction Count TC15
Byte 1
GPIF Transaction Count TC7
Byte 0
b2
b1
b0
E6D3
E6D4
E6DA
E6DB
E6DC
E6E2
E6E3
E6E4
E6EA
E6EB
E6EC
E6F0
E6F1
E6F2
E6F3
E6F4
E6F5
E6F6
E740
E780
E7C0
Default
Access
0
0
0
0
0
FALLING
RISING
00000001
rrrrrrbb
D6
TC30
D5
TC29
D4
TC28
D3
TC27
D2
TC26
D1
TC25
D0
TC24
00000010
00000000
RW
RW
TC22
TC21
TC20
TC19
TC18
TC17
TC16
00000000
RW
TC14
TC13
TC12
TC11
TC10
TC9
TC8
00000000
RW
TC6
TC5
TC4
TC3
TC2
TC1
TC0
00000001
RW
00000000
RW
2
E6D2
reserved
reserved
reserved
1
EP2GPIFFLGSEL [12] Endpoint 2 GPIF Flag
select
1
EP2GPIFPFSTOP
Endpoint 2 GPIF stop
transaction on prog. flag
[12]
1
EP2GPIFTRIG
Endpoint 2 GPIF Trigger
3
reserved
reserved
reserved
1
EP4GPIFFLGSEL [12] Endpoint 4 GPIF Flag
select
1
EP4GPIFPFSTOP
Endpoint 4 GPIF stop
transaction on GPIF Flag
[12]
1
EP4GPIFTRIG
Endpoint 4 GPIF Trigger
3
reserved
reserved
reserved
1
EP6GPIFFLGSEL [12] Endpoint 6 GPIF Flag
select
1
EP6GPIFPFSTOP
Endpoint 6 GPIF stop
transaction on prog. flag
[12]
1
EP6GPIFTRIG
Endpoint 6 GPIF Trigger
3
reserved
reserved
reserved
1
EP8GPIFFLGSEL [12] Endpoint 8 GPIF Flag
select
1
EP8GPIFPFSTOP
Endpoint 8 GPIF stop
transaction on prog. flag
1
EP8GPIFTRIG [12]
Endpoint 8 GPIF Trigger
3
reserved
1
XGPIFSGLDATH
GPIF Data H
(16-bit mode only)
1
XGPIFSGLDATLX
Read/Write GPIF Data L &
trigger transaction
1
XGPIFSGLDATLNOX Read GPIF Data L, no
transaction trigger
1
GPIFREADYCFG
Internal RDY, Sync/Async,
RDY pin states
1
GPIFREADYSTAT
GPIF Ready Status
1
GPIFABORT
Abort GPIF Waveforms
2
reserved
ENDPOINT BUFFERS
64
EP0BUF
EP0-IN/-OUT buffer
64
EP10UTBUF
EP1-OUT buffer
64
EP1INBUF
EP1-IN buffer
2048 reserved
b5
0
0
1
0
0
0
0
FS1
FS0
00000000
RW
0
0
0
0
0
0
0
FIFO2FLAG 00000000
RW
x
x
x
x
x
x
x
x
xxxxxxxx
W
0
0
0
0
0
0
FS1
FS0
00000000
RW
0
0
0
0
0
0
0
FIFO4FLAG 00000000
RW
x
x
x
x
x
x
x
x
xxxxxxxx
W
0
0
0
0
0
0
FS1
FS0
00000000
RW
0
0
0
0
0
0
0
FIFO6FLAG 00000000
RW
x
x
x
x
x
x
x
x
xxxxxxxx
W
0
0
0
0
0
0
FS1
FS0
00000000
RW
0
0
0
0
0
0
0
FIFO8FLAG 00000000
RW
x
x
x
x
x
x
x
x
xxxxxxxx
W
D15
D14
D13
D12
D11
D10
D9
D8
xxxxxxxx
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
R
INTRDY
SAS
TCXRDY5
0
0
0
0
0
00000000
bbbrrrrr
0
x
0
x
RDY5
x
RDY4
x
RDY3
x
RDY2
x
RDY1
x
RDY0
x
00xxxxxx
xxxxxxxx
R
W
D7
D7
D7
D6
D6
D6
D5
D5
D5
D4
D4
D4
D3
D3
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0
xxxxxxxx
xxxxxxxx
xxxxxxxx
RW
RW
RW
RW
Note
12. The register can only be reset, it cannot be set.
Document Number: 001-04247 Rev. *N
Page 25 of 40
CY7C68033
CY7C68034
Table 9. NX2LP-Flex Register Summary (continued)
Hex Size
Name
F000 1024 EP2FIFOBUF
F400 512
EP4FIFOBUF
F600 512
reserved
F800 1024 EP6FIFOBUF
Description
8A
8B
8C
8D
8E
8F
90
91
92
1
1
1
1
1
1
1
1
1
93
98
5
1
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A8
1
1
1
1
1
1
1
1
1
1
5
1
A9
AA
1
1
AB
1
AC
1
AD
AF
B0
B1
2
1
1
1
B2
B3
B4
B5
B6
B7
1
1
1
1
1
1
b3
b2
b1
b0
Default
Access
D3
D2
D1
D0
xxxxxxxx
RW
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
512/1024-byte EP 6/slave D7
FIFO buffer (IN or OUT)
512 byte EP 8/slave FIFO D7
buffer (IN or OUT)
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
RW
0
DISCON
0
0
0
0
0
400 kHz
xxxxxxxx[14] n/a
D7
D7
A7
A15
A7
A15
0
SMOD0
TF1
D6
D6
A6
A14
A6
A14
0
x
TR1
D5
D5
A5
A13
A5
A13
0
1
TF0
D4
D4
A4
A12
A4
A12
0
1
TR0
D3
D3
A3
A11
A3
A11
0
x
IE1
D2
D2
A2
A10
A2
A10
0
x
IT1
D1
D1
A1
A9
A1
A9
0
x
IE0
D0
D0
A0
A8
A0
A8
SEL
IDLE
IT0
xxxxxxxx
00000111
00000000
00000000
00000000
00000000
00000000
00110000
00000000
RW
RW
RW
RW
RW
RW
RW
RW
RW
GATE
CT
M1
M0
GATE
CT
M1
M0
00000000
RW
D7
D7
D15
D15
x
D6
D6
D14
D14
x
D5
D5
D13
D13
T2M
D4
D4
D12
D12
T1M
D3
D3
D11
D11
T0M
D2
D2
D10
D10
MD2
D1
D1
D9
D9
MD1
D0
D0
D8
D8
MD0
00000000
00000000
00000000
00000000
00000001
RW
RW
RW
RW
RW
D7
IE5
A15
D6
IE4
A14
D5
I²CINT
A13
D4
USBNT
A12
D3
1
A11
D2
0
A10
D1
0
A9
D0
0
A8
xxxxxxxx
00001000
00000000
RW
RW
RW
SM0_0
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
00000000
RW
D7
A15
A7
D6
A14
A6
D5
A13
A5
D4
A12
A4
D3
A11
A3
D2
A10
A2
D1
A9
A1
D0
A8
A0
00000000
00000000
00000000
RW
RW
RW
A15
A7
A14
A6
A13
A5
A12
A4
A11
A3
A10
A2
A9
A1
A8
A0
00000000
00000000
RW
RW
D7
x
x
D6
x
x
D5
x
x
D4
x
x
D3
x
x
D2
x
x
D1
x
x
D0
x
x
xxxxxxxx
xxxxxxxx
xxxxxxxx
RW
W
W
EA
ES1
ET2
ES0
ET1
EX1
ET0
EX0
00000000
RW
EP8F
EP8E
EP6F
EP6E
EP4F
EP4E
EP2F
EP2E
01011010
R
0
EP4PF
EP4EF
EP4FF
0
EP2PF
EP2EF
EP2FF
00100010
R
0
EP8PF
EP8EF
EP8FF
0
EP6PF
EP6EF
EP6FF
01100110
R
0
D7
D7
0
D6
D6
0
D5
D5
0
D4
D4
0
D3
D3
APTR2INC
D2
D2
APTR1INC
D1
D1
APTREN
D0
D0
00000110
xxxxxxxx
xxxxxxxx
RW
RW
RW
D7
D7
D7
D7
D7
D6
D6
D6
D6
D6
D5
D5
D5
D5
D5
D4
D4
D4
D4
D4
D3
D3
D3
D3
D3
D2
D2
D2
D2
D2
D1
D1
D1
D1
D1
D0
D0
D0
D0
D0
00000000
00000000
00000000
00000000
00000000
RW
RW
RW
RW
RW
reserved
I²C Configuration Byte
Special Function Registers (SFRs)
IOA [13]
Port A (bit addressable)
SP
Stack Pointer
DPL0
Data Pointer 0 L
DPH0
Data Pointer 0 H
DPL1 [13]
Data Pointer 1 L
DPH1 [13]
Data Pointer 1 H
DPS [13]
Data Pointer 0/1 select
PCON
Power Control
TCON
Timer/Counter Control (bit
addressable)
TMOD
Timer/Counter Mode
Control
TL0
Timer 0 reload L
TL1
Timer 1 reload L
TH0
Timer 0 reload H
TH1
Timer 1 reload H
CKCON [13]
Clock Control
reserved
IOB [13]
Port B (bit addressable)
EXIF [13]
External Interrupt Flag(s)
MPAGE [13]
Upper Addr Byte of MOVX
using @[email protected]
reserved
SCON0
Serial Port 0 Control (bit
addressable)
SBUF0
Serial Port 0 Data Buffer
[13]
AUTOPTRH1
Autopointer 1 Address H
AUTOPTRL1 [13]
Autopointer 1 Address L
reserved
AUTOPTRH2 [13]
Autopointer 2 Address H
AUTOPTRL2 [13]
Autopointer 2 Address L
reserved
IOC [13]
Port C (bit addressable)
INT2CLR [13]
Interrupt 2 clear
INT4CLR [13]
Interrupt 4 clear
reserved
IE
Interrupt Enable (bit
addressable)
reserved
[13]
EP2468STAT
Endpoint 2,4,6,8 status
flags
[13]
EP24FIFOFLGS
Endpoint 2,4 slave FIFO
status flags
EP68FIFOFLGS [13] Endpoint 6,8 slave FIFO
status flags
reserved
AUTOPTRSET-UP [13] Autopointer 1&2 setup
IOD [13]
Port D (bit addressable)
IOE [13]
Port E (NOT bit
addressable)
OEA [13]
Port A Output Enable
OEB [13]
Port B Output Enable
OEC [13]
Port C Output Enable
[13]
OED
Port D Output Enable
OEE [13]
Port E Output Enable
reserved
1
b4
D4
FE00 512
xxxx
89
b5
D5
EP8FIFOBUF
1
1
1
1
1
1
1
1
1
b6
D6
FC00 512
80
81
82
83
84
85
86
87
88
b7
512/1024-byte EP 2/slave D7
FIFO buffer (IN or OUT)
512 byte EP 4/slave FIFO D7
buffer (IN or OUT)
Notes
13. SFRs not part of the standard 8051 architecture.
14. If no NAND is detected by the SIE then the default is 00000000.
Document Number: 001-04247 Rev. *N
Page 26 of 40
CY7C68033
CY7C68034
Table 9. NX2LP-Flex Register Summary (continued)
Hex Size
Name
B8
1
IP
B9
BA
1
1
reserved
EP01STAT [15]
[15, 16]
BB
1
GPIFTRIG
BC
BD
1
1
reserved
GPIFSGLDATH [15]
BE
BF
1
1
C0
1
GPIFSGLDATLX [15]
GPIFSGLDAT
LNOX [15]
SCON1 [15]
[15]
C1
C2
C8
1
6
1
SBUF1
reserved
T2CON
C9
CA
1
1
reserved
RCAP2L
CB
1
RCAP2H
CC
CD
CE
D0
1
1
2
1
TL2
TH2
reserved
PSW
D1
D8
D9
E0
7
1
7
1
reserved
EICON [15]
reserved
ACC
E1
E8
7
1
reserved
EIE [15]
E9
F0
F1
F8
7
1
7
1
reserved
B
reserved
EIP [15]
F9
7
reserved
Description
b7
b6
b5
b4
b3
b2
b1
Interrupt Priority (bit
addressable)
1
PS1
PT2
PS0
PT1
PX1
PT0
Endpoint 0&1 Status
0
0
0
0
0
EP1INBSY
Endpoint 2,4,6,8 GPIF
slave FIFO Trigger
DONE
0
0
0
0
GPIF Data H (16-bit mode D15
only)
GPIF Data L w/Trigger
D7
GPIF Data L w/No Trigger D7
D14
D13
D12
D6
D6
D5
D5
D4
D4
Serial Port 1 Control (bit SM0_1
addressable)
Serial Port 1 Data Buffer D7
SM1_1
SM2_1
D6
Timer/Counter 2 Control
(bit addressable)
TF2
Capture for Timer 2,
auto-reload, up-counter
Capture for Timer 2,
auto-reload, up-counter
Timer 2 reload L
Timer 2 reload H
b0
Default
Access
10000000
RW
00000000
R
RW
EP1OUTBS EP0BSY
Y
EP1
EP0
10000xxx
brrrrbbb
D11
D10
D9
D8
xxxxxxxx
RW
D3
D3
D2
D2
D1
D1
D0
D0
xxxxxxxx
xxxxxxxx
RW
R
REN_1
TB8_1
RB8_1
TI_1
RI_1
00000000
RW
D5
D4
D3
D2
D1
D0
00000000
RW
EXF2
RCLK
TCLK
EXEN2
TR2
CT2
CPRL2
00000000
RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
D7
D15
D6
D14
D5
D13
D4
D12
D3
D11
D2
D10
D1
D9
D0
D8
00000000
00000000
RW
RW
Program Status Word (bit CY
addressable)
AC
F0
RS1
RS0
OV
F1
P
00000000
RW
External Interrupt Control SMOD1
1
ERESI
RESI
INT6
0
0
0
01000000
RW
Accumulator (bit
addressable)
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
External Interrupt
Enable(s)
1
1
1
EX6
EX5
EX4
EI²C
EUSB
11100000
RW
B (bit addressable)
D7
D6
D5
D4
D3
D2
D1
D0
00000000
RW
1
1
PX6
PX5
PX4
PI²C
PUSB
11100000
RW
External Interrupt Priority 1
Control
PX0
R = all bits read-only
W = all bits write-only
r = read-only bit
w = write-only bit
b = both read/write bit
Notes
15. SFRs not part of the standard 8051 architecture.
16. If no NAND is detected by the SIE then the default is 00000000.
Document Number: 001-04247 Rev. *N
Page 27 of 40
CY7C68033
CY7C68034
Absolute Maximum Ratings
Static Discharge Voltage ......................................... > 2000 V
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Max Output Current, per I/O port ................................ 10 mA
Operating Conditions
TA (Ambient Temperature Under Bias)
Commercial ................................................... 0 °C to +70 °C
Ambient Temperature
with Power Supplied (Commercial) ............... 0 °C to +70 °C
TA (Ambient Temperature Under Bias)
Industrial .................................................. –40 °C to +105 °C
Ambient Temperature
with Power Supplied (Industrial) .............. –40 °C to +105 °C
Supply Voltage .........................................+3.00 V to +3.60 V
Supply Voltage to Ground Potential .............–0.5 V to +4.0 V
Ground Voltage ................................................................ 0 V
DC Input Voltage to any Input Pin ....................... +5.25 V[17]
FOSC (Oscillator or Crystal
Frequency) ............. 24 MHz ± 100 ppm (Parallel Resonant)
DC Voltage Applied to
Outputs in High Z State ...................... –0.5 V to VCC + 0.5 V
Power Dissipation .................................................... 300 mW
DC Electrical Characteristics
Parameter
Min
Typ
Max
Unit
Supply voltage
3.00
3.3
3.60
V
VCC ramp up
0 to 3.3 V
200
–
–
s
VIH
Input HIGH voltage
2
–
5.25
V
VIL
Input LOW voltage
–0.5
–
0.8
V
VIH_X
Crystal input HIGH voltage
2
–
5.25
V
VIL_X
Crystal input LOW voltage
–0.5
–
0.8
V
II
Input leakage current
0< VIN < VCC
–
–
±10
A
VOH
Output voltage HIGH
IOUT = 4 mA
2.4
–
–
V
VOL
Output LOW voltage
IOUT = –4 mA
–
–
0.4
V
IOH
Output current HIGH
–
–
4
mA
IOL
Output current LOW
–
–
4
mA
CIN
Input pin capacitance
VCC
ISUSP
ICC
Description
Conditions
Except D+/D–
–
–
10
pF
D+/D–
–
–
15
pF
Suspend current
Connected
–
300
380 [18]
A
CY7C68034
Disconnected
–
100
150 [18]
A
[18]
mA
Suspend current
Connected
–
0.5
1.2
CY7C68033
Disconnected
–
0.3
1.0 [18]
mA
8051 running, connected to USB HS
–
43
–
mA
8051 running, connected to USB FS
–
35
–
mA
Supply current
IUNCONFIG
Unconfigured current
Before bMaxPower granted by host
TRESET
Reset time after valid power
VCC min = 3.0 V
Pin reset after powered on
–
43
–
mA
5.0
–
–
ms
200
–
–
s
USB Transceiver
USB 2.0-compliant in full and high speed modes.
Notes
17. Applying power to I/O pins when the chip is not powered is not recommended.
18. .Measured at Max VCC, 25 °C.
Document Number: 001-04247 Rev. *N
Page 28 of 40
CY7C68033
CY7C68034
AC Electrical Characteristics
USB Transceiver
USB 2.0-compliant in full and high speed modes.
Slave FIFO Asynchronous Read
Figure 11. Slave FIFO Asynchronous Read Timing Diagram [19]
tRDpwh
SLRD
tRDpwl
FLAGS
tXFD
tXFLG
DATA
N+1
N
tOEon
tOEoff
SLOE
Table 10. Slave FIFO Asynchronous Read Parameters [20]
Parameter
Description
Min
Max
Unit
tRDpwl
SLRD pulse width LOW
50
–
ns
tRDpwh
SLRD pulse width HIGH
50
–
ns
tXFLG
SLRD to FLAGS output propagation delay
–
70
ns
tXFD
SLRD to FIFO data output propagation delay
–
15
ns
tOEon
SLOE turn on to FIFO data valid
–
10.5
ns
tOEoff
SLOE turn off to FIFO data hold
–
10.5
ns
Slave FIFO Asynchronous Write
Figure 12. Slave FIFO Asynchronous Write Timing Diagram [19]
tWRpwh
SLWR/SLCS#
tWRpwl
tSFD
tFDH
DATA
tXFD
FLAGS
Table 11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK [21]
Min
Max
Unit
tWRpwl
Parameter
SLWR pulse LOW
Description
50
–
ns
tWRpwh
SLWR pulse HIGH
70
–
ns
tSFD
SLWR to FIFO DATA setup time
10
–
ns
tFDH
FIFO DATA to SLWR hold time
10
–
ns
tXFD
SLWR to FLAGS output propagation delay
–
70
ns
Notes
19. Dashed lines denote signals with programmable polarity.
20. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
21. GPIF asynchronous RDYx signals have a minimum setup time of 50 ns when using internal 48 MHz IFCLK.
Document Number: 001-04247 Rev. *N
Page 29 of 40
CY7C68033
CY7C68034
Slave FIFO Asynchronous Packet End Strobe
Figure 13. Slave FIFO Asynchronous Packet End Strobe Timing Diagram [22]
tPEpwh
PKTEND
tPEpwl
FLAGS
tXFLG
Table 12. Slave FIFO Asynchronous Packet End Strobe Parameters [23]
Parameter
Description
Min
Max
Unit
tPEpwl
PKTEND pulse width LOW
50
–
ns
tPWpwh
PKTEND pulse width HIGH
50
–
ns
tXFLG
PKTEND to FLAGS output propagation delay
–
115
ns
Slave FIFO Output Enable
Figure 14. Slave FIFO Output Enable Timing Diagram [24]
SLOE
tOEon
DATA
tOEoff
Table 13. Slave FIFO Output Enable Parameters
Min
Max
Unit
tOEon
Parameter
SLOE assert to FIFO DATA output
Description
–
10.5
ns
tOEoff
SLOE deassert to FIFO DATA hold
–
10.5
ns
Notes
22. SFRs not part of the standard 8051 architecture.
23. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
24. Dashed lines denote signals with programmable polarity.
Document Number: 001-04247 Rev. *N
Page 30 of 40
CY7C68033
CY7C68034
Slave FIFO Address to Flags/Data
Figure 15. Slave FIFO Address to Flags/Data Timing Diagram [25]
FIFOADR [1.0]
tXFLG
FLAGS
tXFD
DATA
N
N+1
Table 14. Slave FIFO Address to Flags/Data Parameters
Parameter
Description
Min
Max
Unit
tXFLG
FIFOADR[1:0] to FLAGS output propagation delay
–
10.7
ns
tXFD
FIFOADR[1:0] to FIFODATA output propagation delay
–
14.3
ns
Min
Max
Unit
Slave FIFO Asynchronous Address
Figure 16. Slave FIFO Asynchronous Address Timing Diagram [25]
SLCS/FIFOADR [1:0]
tSFA
tFAH
SLRD/SLWR/PKTEND
Table 15. Slave FIFO Asynchronous Address Parameters [26]
Parameter
Description
tSFA
FIFOADR[1:0] to SLRD/SLWR/PKTEND Setup Time
10
–
ns
tFAH
RD/WR/PKTEND to FIFOADR[1:0] Hold Time
10
–
ns
Notes
25. Dashed lines denote signals with programmable polarity.
26. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Document Number: 001-04247 Rev. *N
Page 31 of 40
CY7C68033
CY7C68034
Sequence Diagram
Sequence Diagram of a Single and Burst Asynchronous Read
Figure 17. Slave FIFO Asynchronous Read Sequence and Timing Diagram [27]
tSFA
tFAH
tSFA
tFAH
FIFOADR
t=0
tRDpwl
tRDpwh
tRDpwl
T=0
tRDpwl
tRDpwh
tRDpwl
tRDpwh
tRDpwh
SLRD
t=2
t=3
T=3
T=2
T=4
T=5
T=6
SLCS
tXFLG
tXFLG
FLAGS
tXFD
Data (X)
Driven
DATA
tXFD
tXFD
N
N
N+3
N+2
tOEon
tOEoff
tOEon
tXFD
N+1
tOEoff
SLOE
t=4
t=1
T=7
T=1
Figure 18. Slave FIFO Asynchronous Read Sequence of Events Diagram
SLOE
FIFO POINTER
N
FIFO DATA BUS Not Driven
SLRD
SLRD
SLOE
SLOE
SLRD
SLRD
SLRD
SLRD
SLOE
N
N
N+1
N+1
N+1
N+1
N+2
N+2
N+3
N+3
Driven: X
N
N
Not Driven
N
N+1
N+1
N+2
N+2
Not Driven
Figure 17 shows the timing relationship of the SLAVE FIFO
signals during an asynchronous FIFO read. It shows a single
read followed by a burst read.
■
The data that is driven, after asserting SLRD, is the updated
data from the FIFO. This data is valid after a propagation delay
of tXFD from the activating edge of SLRD. In Figure 17, data N
is the first valid data read from the FIFO. For data to appear on
the data bus during the read cycle (that is SLRD is asserted),
SLOE MUST be in an asserted state. SLRD and SLOE can
also be tied together.
■
At t = 0 the FIFO address is stable and the SLCS signal is
asserted.
■
At t = 1, SLOE is asserted. This results in the data bus being
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
The same sequence of events is also shown for a burst read
marked with T = 0 through 5.
At t = 2, SLRD is asserted. The SLRD must meet the minimum
active pulse of tRDpwl and minimum deactive pulse width of
tRDpwh. If SLCS is used then, SLCS must be in asserted with
SLRD or before SLRD is asserted (that is the SLCS and SLRD
signals must both be asserted to start a valid read condition).
Note In burst read mode, during SLOE is assertion, the data bus
is in a driven state and outputs the previous data. After SLRD is
asserted, the data from the FIFO is driven on the data bus (SLOE
must also be asserted) and then the FIFO pointer is
incremented.
■
Note
27. Dashed lines denote signals with programmable polarity.
Document Number: 001-04247 Rev. *N
Page 32 of 40
CY7C68033
CY7C68034
Sequence Diagram of a Single and Burst Asynchronous Write
Figure 19. Slave FIFO Asynchronous Write Sequence and Timing Diagram [28]
tSFA
tFAH
tSFA
tFAH
FIFOADR
t=0
tWRpwl
tWRpwh
T=0
tWRpwl
tWRpwl
tWRpwh
tWRpwl
tWRpwh
tWRpwh
SLWR
t=3
t =1
T=1
T=3
T=4
T=6
T=7
T=9
SLCS
tXFLG
tXFLG
FLAGS
tSFD tFDH
tSFD tFDH
tSFD tFDH
tSFD tFDH
N+1
N+2
N+3
N
DATA
t=2
T=2
T=5
T=8
tPEpwl
tPEpwh
PKTEND
Figure 19 shows the timing relationship of the SLAVE FIFO write
in an asynchronous mode. The diagram shows a single write
followed by a burst write of three bytes and committing the
4-byte-short packet using PKTEND.
The FIFO flag is also updated after tXFLG from the deasserting
edge of SLWR.
■
At t = 0 the FIFO address is applied, insuring that it meets the
setup time of tSFA. If SLCS is used, it must also be asserted
(SLCS may be tied low in some applications).
■
At t = 1 SLWR is asserted. SLWR must meet the minimum
active pulse of tWRpwl and minimum de-active pulse width of
tWRpwh. If the SLCS is used, it must be in asserted with SLWR
or before SLWR is asserted.
Note In the burst write mode, after SLWR is deasserted, the data
is written to the FIFO and then the FIFO pointer is incremented
to the next byte in the FIFO. The FIFO pointer is post
incremented.
■
At t = 2, data must be present on the bus tSFD before the
deasserting edge of SLWR.
At t = 3, deasserting SLWR causes the data to be written from
the data bus to the FIFO and then increments the FIFO pointer.
The same sequence of events are shown for a burst write and is
indicated by the timing marks of T = 0 through 5.
As shown in Figure 19 after the four bytes are written to the FIFO
and SLWR is deasserted, the short 4-byte packet can be
committed to the host using the PKTEND. The external device
should be designed to not assert SLWR and the PKTEND signal
at the same time. It should be designed to assert the PKTEND
after SLWR is deasserted and met the minimum de-asserted
pulse width. The FIFOADDR lines are to be held constant during
the PKTEND assertion.
Note
28. Dashed lines denote signals with programmable polarity.
Document Number: 001-04247 Rev. *N
Page 33 of 40
CY7C68033
CY7C68034
Ordering Information
Ordering Code
Description
Silicon for battery-powered applications
CY7C68034-56LTXC
8 × 8 mm, 56-pin QFN (Sawn)
CY7C68034-56LTXI
8 × 8 mm, 56-pin QFN (Sawn)
Silicon for non-battery-powered applications
CY7C68033-56LTXC
8 × 8 mm, 56-pin QFN (Sawn)
Development Kit
CY3686
EZ-USB NX2LP-Flex Development Kit
Ordering Code Definitions
CY 7
C
68
03X - 56 LT
X X
X
X = T or blank
T = Tape and Reel; blank = Tube
Temperature Range: X = C or I
C = Commercial; I = Industrial
X = Pb-free (RoHS Compliant)
Package Type:
LT = QFN package
No. of pins in package: 56-pin
Part Number: 03X = 034 or 033
Family Code: 68 = USB
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-04247 Rev. *N
Page 34 of 40
CY7C68033
CY7C68034
Package Diagrams
Figure 20. 56-pin QFN (8 × 8 × 1.0 mm) LT56B 4.5 × 5.2 EPAD (Sawn) Package Outline, 001-53450
001-53450 *D
Document Number: 001-04247 Rev. *N
Page 35 of 40
CY7C68033
CY7C68034
PCB Layout Recommendations
Follow these recommendations [29] to ensure reliable high
performance operation:
■
At least a four-layer impedance controlled boards is
recommended to maintain signal quality.
■
Specify impedance targets (ask your board vendor what they
can achieve) to meet USB specifications.
■
To control impedance, maintain trace widths and trace spacing.
■
Minimize any stubs to avoid reflected signals.
■
Connections between the USB connector shell and signal
ground must be done near the USB connector.
■
Bypass/flyback
recommended.
■
DPLUS and DMINUS trace lengths should be kept to within
2 mm of each other in length, with preferred length of
20–30 mm.
■
Maintain a solid ground plane under the DPLUS and DMINUS
traces. Do not allow the plane to be split under these traces.
■
No vias should be placed on the DPLUS or DMINUS trace
routing unless absolutely necessary.
■
Isolate the DPLUS and DMINUS traces from all other signal
traces as much as possible.
caps
on
VBUS,
near
connector,
are
Quad Flat Package No Leads (QFN) Package
Design Notes
Electrical contact of the part to the printed circuit board (PCB) is
made by soldering the leads on the bottom surface of the
package to the PCB. Therefore, special attention is required to
the heat transfer area below the package to provide a good
thermal bond to the circuit board. Design a copper (Cu) fill into
the PCB as a thermal pad under the package. Heat is transferred
from the NX2LP-Flex to the PCB through the device’s metal
paddle on the bottom side of the package. It is then conducted
from the PCB’s thermal pad to the inner ground plane by a
5 × 5 array of vias. A via is a plated through hole in the PCB with
a finished diameter of 13 mil. The QFN’s metal die paddle must
be soldered to the PCB’s thermal pad. Solder mask is placed on
the board top side over each via to resist solder flow into the via.
The mask on the top side also minimizes outgassing during the
solder reflow process.
For further information on this package design, refer to the
application note Application Note for Surface Mount Assembly of
Amkor’s Eutectic and Lead-Free CSPnl™ Wafer Level Chip
Scale Packages. This application note provides detailed
information on board mounting guidelines, soldering flow, rework
process, and so on.
Note
29. Source for recommendations: EZ-USB FX2™PCB Design Recommendations and High Speed USB Platform Design Guidelines.
Document Number: 001-04247 Rev. *N
Page 36 of 40
CY7C68033
CY7C68034
Figure 21 displays a cross-sectional area underneath the package. The cross section is of only one via. The solder paste template
needs to be designed to enable at least 50% solder coverage. The thickness of the solder paste template should be 5 mil. It is
recommended that ‘No Clean’ type 3 solder paste is used for mounting the part. Nitrogen purge is recommended during reflow.
Figure 22 is a plot of the solder mask pattern and Figure 23 displays an X-Ray image of the assembly (darker areas indicate solder).
Figure 21. Cross-section of the Area Underneath the QFN Package.
0.017” dia
Solder Mask
Cu Fill
Cu Fill
PCB Material
Via hole for thermally connecting the
QFN to the circuit board ground plane.
0.013” dia
PCB Material
This figure only shows the top three layers of the
circuit board: Top Solder, PCB Dielectric, and the Ground Plane.
Figure 22. Plot of the Solder Mask (White Area)
Figure 23. X-ray Image of the Assembly
Document Number: 001-04247 Rev. *N
Page 37 of 40
CY7C68033
CY7C68034
Acronyms
Acronym
Document Conventions
Description
Units of Measure
ASIC
application specific integrated circuit
CPU
central processing unit
°C
Symbol
degree Celsius
Unit of Measure
DSP
digital signal processor
kHz
kilohertz
ECC
error correcting codes
MHz
megahertz
EEPROM
electrically erasable programmable read only
memory
µA
microampere
µs
microsecond
FIFO
first in first out
GPIF
general programmable interface
µW
microwatt
GPIO
general purpose input/output
mA
milliampere
I/O
input/output
mm
millimeter
LAN
local area network
ms
millisecond
LSB
least-significant bit
mV
millivolt
MSB
most-significant bit
mW
milliwatt
PLL
phase locked loop
ns
nanosecond
PCB
printed circuit board

ohms
PSoC
programmable system-on-chip
%
percent
QFN
quad flat no leads
pF
picofarad
RAM
random access memory
ROM
read only memory
SCL
serial clock
SDA
serial data line
SIE
serial interface engine
USB
universal serial bus
Document Number: 001-04247 Rev. *N
ppm
parts per million
V
volt
Page 38 of 40
CY7C68033
CY7C68034
Document History Page
Document Title: CY7C68033/CY7C68034, EZ-USB® NX2LP-Flex™ Flexible USB NAND Flash Controller
Document Number: 001-04247
Rev.
ECN No.
Submission
Date
Orig. of
Change
**
388499
See ECN
GIR
Preliminary draft
*A
394699
See ECN
XUT
Minor Change: Upload data sheet to external website. Publicly announcing the
parts. No physical changes to document were made
*B
400518
See ECN
GIR
Took ‘Preliminary’ off the top of all pages. Corrected the first bulleted item.
Corrected Figure 3-2 caption. Added new logo
*C
433952
See ECN
RGL
Added I2C functionality
*D
498295
See ECN
KKU
Updated Data sheet format
Changed In/Output reference from I/O to I/O
Changed set-up to setup
Changed IFCLK and CLKOUT pins to GPIO8 and GPIO9. Removed external
IFCLK
*E
2717536
06/11/2009
DPT
Added 56 QFN (8 X 8 mm) package diagram and added CY7C68033-56LTXC
and CY7C68034-56LTXC part information in the Ordering Information table
Description of Change
*F
2728424
07/02/2009
GNKK
*G
2896281
03/19/2010
ODC
*H
2933818
05/18/2010
SHAH /
AESA
*I
3349690
08/25/2011
ODC
Updated Package Diagrams (Removed Package Drawing 51-85144).
Added Units of Measure.
Updated to new template.
*J
3668026
07/06/2012
GAYA
Updated Ordering Information (with part number CY7C68034-56LTXI).
*K
3711000
08/13/2012
GAYA
Updated Absolute Maximum Ratings.
Updated Operating Conditions.
*L
4505623
09/23/2014
GAYA
Updated ECC NAND Flash correction feature details.
Updated Package Diagrams
*M
4612073
01/12/2015
GAYA
Updated Pin Assignments:
Updated Figure 9.
Updated Table 8:
Updated details in “Default Pin Name” column corresponding to 56-pin QFN
Pin Number 54 and 13.
Updated to new template.
*N
4928521
09/21/2015
GAYA
No technical updates.
Completing Sunset Review.
Document Number: 001-04247 Rev. *N
Updated revision in the footer
Removed inactive parts.Updated package diagram. Added table of
contents.Updated links in Sales, Solutions and Legal Information.
Added Contents and Acronyms
Updated Default NAND Firmware Features
Formatted table footnotes.
Page 39 of 40
CY7C68033
CY7C68034
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
cypress.com/go/memory
cypress.com/go/psoc
cypress.com/go/touch
Technical Support
cypress.com/go/support
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2005-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-04247 Rev. *N
Revised September 21, 2015
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 40 of 40
Similar pages