CYUSB330x, CYUSB331x, CYUSB332x, CYUSB230x HX3 USB 3.0 Hub Datasheet.pdf

CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
HX3 USB 3.0 Hub
General Description
HX3 is a family of USB 3.0 hub controllers compliant with the USB 3.0 specification revision 1.0. HX3 supports SuperSpeed (SS),
Hi-Speed (HS), Full-Speed (FS), and Low-Speed (LS) on all the ports. It has integrated termination, pull-up, and pull-down resistors,
and supports configuration options through pin-straps to reduce the overall BOM of the system.
HX3 includes the following Cypress-proprietary features:
Shared Link™: Enables extra downstream (DS) ports for on-board connections in embedded applications
Ghost Charge™: Enables charging of devices connected to the DS ports when no host is connected on the upstream (US) port
HX3 USB 3.0 Hub
Features
■
USB 3.0-Certified Hub, TID# 330000060
■
Supports up to Four USB 3.0-Compliant DS ports
❐ All ports support SS (5 Gbps), and are backward-compatible
with HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps)
❐ SS and USB 2.0 Link Power Management (LPM)
❐ Dedicated Hi-Speed Transaction Translators (Multi-TT)
❐ LED status indicators – suspend, SS, and USB 2.0 operation
■
Shared Link™ for Embedded Applications
❐ Each DS port can simultaneously connect to an embedded
SS device and a removable USB 2.0 device
❐ Enables up to eight device connections
■
Enhanced Battery Charging
❐ Each DS port complies with the USB Battery Charging v1.2
(BC v1.2) specification
❐ Ghost Charge™: Each DS port can emulate a Dedicated
Charging Port (DCP) when the host is not connected to the
US port
❐ Accessory Charger Adapter Dock (ACA-Dock): Enables
charging and simultaneous data transfer for a smart phone
or a tablet acting as a host compliant to BC v1.2
❐ Apple charging supported on all DS ports
■
■
■
Extensive Configuration Support
❐ Pin-strap configuration for the following functions:
• Vendor ID (VID)
• Charging support for each DS port
• Number of active ports
• Number of non-removable devices
• Ganged or individual power switch enables for DS ports
• Power switch polarity selection
2
❐ Custom configuration modes supported with eFuse, I C
EEPROM, or I2C slave
• SS and USB 2.0 PHY parameters
• Product ID (PID)/VID, manufacturer, and product string
descriptors
• Swap DP/DM signals for flexible PCB routing
■
Software Features
❐ Microsoft WHQL-certified for Windows XP/Vista/7/8/8.1
❐ Compatible with Mac OS 10.9 and Linux kernel version 3.11
❐ Customize configuration parameters with the easy-to-use
Cypress’s “Blaster Plus” software tool
■
Flexible Packaging Options
❐ 68-pin QFN (8 × 8 × 1.0 mm)
❐ 88-pin QFN (10 × 10 × 1.0 mm)
❐ 100-ball BGA (6 × 6 × 1.0 mm)
❐ Industrial temperature range (–40 °C to +85 °C)
ARM® Cortex™-M0
Integrated
CPU
❐ 16 KB RAM, 32 KB ROM
❐ Configure GPIOs for overcurrent protection, power enable,
and LEDs
2
❐ Upgrade firmware using (a) I C EEPROM or (b) an external
2
I C master
Vendor-Command Support to Implement a USB-to-I2C Bridge
❐ Firmware upgrade of an external ASSP connected to HX3
through USB
❐ In-System Programming (ISP) of the EEPROM connected to
HX3 through USB
Cypress Semiconductor Corporation
Document Number: 001-73643 Rev. *O
•
198 Champion Court
•
San Jose, CA 95134-1709
• +1-408-943-2600
Revised November 25, 2015
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Block Diagram
SS
PHY
VBUS
SSRxP/M
DP
DM
USB 2.0 PHY
SSTxP/M
US Port
USB 2.0
SS
ARM
Cortex-M0
VBUS
Detect
RAM
USB 2.0 Controller
SS Controller
PHY Interface
US Port Control Routing
Hub Controller
Hub Controller
Repeater
Four Transaction
Translators
ROM
I2C
1.2 V
US Buffers
DS Buffers
DS Port 1
Document Number: 001-73643 Rev. *O
DS Port 2
DS Port 3
Port
Control
PWR
OVR
LED
SSTxP/M
SS
PHY
SSRxP/M
USB 2.0
PHY
DP
DM
Port
Control
PWR
OVR
LED
SS
PHY
SSTxP/M
USB 2.0
PHY
SSRxP/M
Port
Control
PWR
OVR
LED
SSTxP/M
SS
PHY
SSRxP/M
USB 2.0
PHY
DP
DM
PWR
OVR
LED
SSTxP/M
SSRxP/M
DP
DM
Port
Control
26 MHz
Buffer and Routing Logic
DP
DM
Routing Logic
SS
PHY
I2C_CLK
3.3 V
PLL
USB 2.0
PHY
I2C_DATA
DS Port 4
Page 2 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Contents
Architecture Overview ..................................................... 4
SS Hub Controller ....................................................... 4
USB 2.0 Hub Controller............................................... 4
CPU............................................................................. 4
I2C Interface................................................................ 4
Port Controller ............................................................. 4
Applications ...................................................................... 4
HX3 Product Options ....................................................... 5
Product Features .............................................................. 6
Shared Link ................................................................. 6
Ghost Charge .............................................................. 6
Vendor-Command Support ......................................... 7
ACA-Dock Support ...................................................... 7
Pin Information ................................................................. 8
System Interfaces........................................................... 24
Upstream Port (US)................................................... 24
Downstream Ports (DS1, 2, 3, 4) .............................. 24
Communication Interfaces (I2C)................................ 24
Oscillator ................................................................... 24
GPIOs........................................................................ 24
Power Control............................................................ 24
Reset ......................................................................... 24
Configuration Mode Select ........................................ 24
Configuration Options................................................ 24
Document Number: 001-73643 Rev. *O
EMI ................................................................................... 31
ESD .................................................................................. 31
Absolute Maximum Ratings .......................................... 32
Electrical Specifications ................................................ 32
DC Electrical Characteristics..................................... 32
Power Consumption .................................................. 33
Ordering Information...................................................... 34
Ordering Code Definitions ......................................... 35
Packaging........................................................................ 36
Package Diagrams.......................................................... 37
Acronyms ........................................................................ 39
Reference Documents.................................................... 39
Document Conventions ................................................. 39
Units of Measure ....................................................... 39
Silicon Revision History ................................................ 40
Method of Identification ............................................. 40
Document History........................................................... 41
Sales, Solutions, and Legal Information ...................... 42
Worldwide Sales and Design Support....................... 42
Products .................................................................... 42
PSoC® Solutions ...................................................... 42
Cypress Developer Community................................. 42
Technical Support ..................................................... 42
Page 3 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Architecture Overview
The Block Diagram on page 2 shows the HX3 architecture. HX3
consists of two independent hub controllers (SS and USB 2.0),
the Cortex-M0 CPU subsystem, an I2C interface, and port
controller blocks.
SS Hub Controller
This block supports the SS hub functionality based on the
USB 3.0 specification. The SS hub controller supports the
following:
■
SS link power management (U0, U1, U2, U3 states)
■
Full-duplex data transmission
USB 2.0 Hub Controller
This block supports the LS, FS, and HS hub functionalities. It
includes the repeater, frame timer, and four transaction translators.
The USB 2.0 hub controller block supports the following:
I2C Interface
The I2C interface in HX3 supports the following:
■
■
I2C Slave, Master, and Multi-master configurations
2
2
❐ Configure HX3 by an external I C master in I C slave mode
2
❐ Configure HX3 from an I C EEPROM
2
❐ Multi-master mode to share EEPROM with other I C masters
In-System Programming of the I2C EEPROM from HX3’s
US port
Port Controller
The port controller block controls DS port power to comply with
the BC v1.2 and USB 3.0 specifications. This block also controls
the US port power in the ACA-Dock mode. Control signals for
external power switches are implemented within the chip. HX3
controls the external power switches at power-on to reduce
in-rush current.
The port controller block supports the following:
■
Overcurrent detection
■
USB 2.0 link power management (L0, L1, L2, L3 states)
■
SS and USB 2.0 port indicators for each DS port
■
Suspend, resume, and remote wake-up signaling
■
Ganged and individual power control modes
■
Multi-TT (one TT for each DS port)
■
Automatic port numbering based on active ports
CPU
Applications
The ARM Cortex-M0 CPU subsystem is used for the following
functions:
■
Standalone hubs
■
PC and tablet motherboards
■
Docking station
■
Hand-held cradles
■
Monitors
■
Digital TVs
■
Set-top boxes
■
Printers
■
System configuration and initialization
■
Battery charging control
■
Vendor-specific commands for the USB-to-I2C bridge
■
String-descriptor support
■
Suspend status indicator
■
Shared Link support in embedded systems
Document Number: 001-73643 Rev. *O
Page 4 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
HX3 Product Options
Table 1. HX3 Product Options
CYUSB3302
CYUSB3304
CYUSB3312
CYUSB3314
CYUSB3324
CYUSB3326
CYUSB3328
CYUSB230268LTXI
CYUSB230468LTXI
2 (USB 3.0)
4 (USB 3.0)
2 (USB 3.0)
4 (USB 3.0)
4 (USB 3.0)
6 (2 USB 3.0,
2 SS,
2 USB 2.0)
8 (4 SS,
4 USB 2.0)
2 (USB 2.0)
4 (USB 2.0)
0
0
0
0
0
2[1]
4
0
0
BC v1.2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ACA-Dock
No
No
No
No
Yes
No
Yes
No
No
Ganged
Ganged
Individual and
Ganged
Individual
and Ganged
Individual
and Ganged
Individual
Individual
Ganged
Ganged
Pin-Strap
support
No
No
Yes
Yes
Yes
Yes
Yes
No
No
I2C
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Vendor
command
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Features
Number of DS
ports
Number of
Shared Link
ports
External Power
Switch Control
Port indicators
No
No
Yes
Yes
Yes
No
No
No
No
Packages[2]
68-QFN,
100-ball BGA
68-QFN,
100-ball BGA
88-QFN,
100-ball BGA
88-QFN,
100-ball BGA
88-QFN,
100-ball BGA
88-QFN,
100-ball BGA
88-QFN,
100-ball BGA
68-QFN,
100-ball BGA
68-QFN,
100-ball BGA
Temperature
range
Industrial and
Commercial
Industrial and
Commercial
Industrial and
Commercial
Industrial and
Commercial
Industrial and
Commercial
Industrial and
Commercial
Industrial
(88-QFN only)
and Commercial
Industrial and
Commercial
Industrial and
Commercial
Notes
1. DS1 and DS2 are Shared link Ports.
2. BGA Industrial Grade packages are limited to 1 W of active power. For power calculations refer to Table 10 on page 33.
Document Number: 001-73643 Rev. *O
Page 5 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Product Features
Shared Link
Figure 1. Application of Shared Link in a Notebook
Example: Shared Link Provides Six USB Ports in a Notebook
USB 2.0
2
USB 3.0
6
DS4
6
HX3
Internal
SS Port
USB 3.0
2
USB 2.0
HX3
USB
3.0 Port
USB 3.0
Card Reader
Shared Link is a Cypress-proprietary feature that enables a
USB 3.0 port to be split into an embedded SS port and a
standard USB 2.0 port. Shared Link enables a maximum of eight
DS ports from a four-port USB 3.0 hub.
For example, if one of the DS ports is connected to an embedded
SS device, such as a USB 3.0 camera, HX3 enables the system
designer to reuse the USB 2.0 signals of that specific port to
connect to a standard USB 2.0 port. Figure 1 shows how Shared
Link can be used in an application.
Figure 2. DS Port VBUS Control in Shared Link
HX3
USB 3.0 DS Port
Embedded
SuperSpeed
Device
DSx_PWREN is another output signal generated by HX3 and
controls VBUS for the removable USB 2.0 device. For example,
when an overcurrent condition occurs, DSx_PWREN turns off
the port power.
Ghost Charge
Ghost Charge is a Cypress-proprietary feature for charging USB
devices on the DS port when the US port is not connected to a
host. For example, in a docking station with HX3 as shown in
Figure 3, when the laptop is undocked, HX3 will emulate a
dedicated charging port (DCP) to provide charge to a phone
connected on a DS port.
Figure 3. Ghost Charge
Power to Smartphone
(HX3’s Downstream Port)
DSx_PWREN
DM
USB 2.0
PHY
DP
SSTXP/M
SSRXP/M
VBUS
DSx_VBUSEN_SL
SuperSpeed
PHY
D+
D-
4
USB 3.0
SSTX+
SSTX-
6
SS
(internal)
6
SSRX+
USB 3.0
6
SSRX-
DS3
Standard
USB 2.0 Port
DS1
4
US
PC
Chipset
USB 3.0 Host
SS
(internal)
USB 3.0 Port Split Into SS Port and Standard USB 2.0 Port
USB 2.0
WiFi Module
USB 3.0
Camera
DS2
Notebook PC
Motherboard
VBUS
Removable
USB 2.0
Device
The Shared Link mode requires a separate VBUS control for the
removable USB 2.0 device and the embedded SS device.
Figure 2 shows the VBUS control implementation.
USB Cable
HX3
Notebook PC
Undocked
Charge a smartphone without docking the notebook
To ensure that the embedded SS device does not fall back to
USB 2.0 operation, an external power switch is required. This
switch is controlled by HX3, which generates an output signal
called DSx_VBUSEN_SL. This signal controls the VBUS for the
embedded device.
Document Number: 001-73643 Rev. *O
Page 6 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
When the US port is disconnected from the host, HX3 detects if
any of the DS ports are connected to a device requesting
charging. It determines the charging method and then switches
to the appropriate signaling based on the detected charging
specification as shown in Figure 4. The hub either emulates a
USB-compliant dedicated charging port by connecting DP and
DM (see the BC v1.2 specification) or other supported
proprietary charging schemes.
Figure 4. Ghost Charge Implementation in HX3
HX3 DS PORT
Other
Charging
Scheme
BC v1.2
Scheme
ACA-Dock Support
In traditional USB topologies, the host provides VBUS to enable
and charge the connected devices. For OTG hosts, however, an
ACA-Dock provides VBUS and a method to charge the host.
HX3 supports the ACA-Dock standard (see BC v1.2 specification) by integrating the functions of the adapter controller.
Figure 5 shows the ACA-Dock system. If the ACA-Dock feature
is enabled, HX3 turns on the external power switch to drive
VBUS on the US port. To inform the OTG host that it is connected
to an ACA-Dock, the ID pin is tied to ground using a resistor
RID_A,3 as shown in Figure 5. The ACA-Dock feature can be
disabled using the Configuration Options on page 24.
For example, a BC v1.2 compliant phone such as a Sony Xperia
(neo V) can be docked to a HX3-based ACA-Dock system. The
phone acts as an OTG host and the ACA-Dock charges the
phone connected to the US port while also powering the four DS
ports.
Charging
Scheme
Detector
Power
Switch
VBUS
DSx_OVRCURR
DSx_PWREN
DM
DP
Figure 5. ACA-Dock Support
5V
VBUS
Power
Source
5V
Wall Charger
Detector
Battery
Charger
Power
Switch
US_PWREN
HX3
USB Battery-Powered Device
Ghost Charge is enabled by default and can be disabled through
configuration. Refer to Configuration Options on page 24.
Vendor-Command Support
VBUS
To US OTG
Enabled Device
ID
RID_A
VBUS
Micro A Plug
PCB
HX3 supports vendor-specific requests and can also enumerate
as a vendor-specific device. The vendor-specific request can be
used to (a) bridge USB and I2C and (b) configure HX3. This
feature can be used for the following applications:
■
Firmware upgrade of an external ASSP connected to HX3
through USB
■
In-System programming (ISP) of an EEPROM connected to
HX3 through USB
Note
3. 124 k is the recommended RID_A value as per BC v1.2 specification, but some portable devices use custom RID_A values.
Document Number: 001-73643 Rev. *O
Page 7 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Pin Information
57
56 55 54
AVDD12
60 59 58
AVDD12
XTL_OUT
62 61
XTL_IN
63
AVDD33
DS2_DM
DS2_DP
64
US_DP
NC
65
US_DM
NC
66
DS1_DM
AVDD33
67
DS1_DP
NC
68
AVDD33
NC
Figure 6. HX3 68-Pin QFN 2-Port Pinout
53 52
DVDD12
1
51 DS1_RXP
RREF_USB2
2
50 DS1_RXM
DVDD12
3
49 DVDD12
AVDD33
4
48 DS1_TXM
US_TXM
5
47 DS1_TXP
US_TXP
6
46 AVDD12
DVDD12
7
45 DS2_RXP
US_RXM
8
44 DS2_RXM
US_RXP
9
AVDD12
10
42 DS2_TXM
NC
11
41 DS2_TXP
NC
12
40 GND
DVDD12
13
39 NC
NC
14
38 NC
NC
15
37 DVDD12
AVDD12
16
36 NC
VBUS_US
17
35 NC
43 DVDD12
21
22
23
24
25
26
27
28
29
30
31
32
33
34
RESERVED2
MODE_SEL[0]
MODE_SEL[1]
NC
RREF_SS
DVDD12
VDD_IO
PWR_EN
OVRCURR
RESETN
I2C_CLK
I2C_DATA
AVDD12
VDD_EFUSE
Document Number: 001-73643 Rev. *O
20
SUSPEND
19
RESERVED1
18
VBUS_DS
68-Pin QFN
Page 8 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
57
56 55 54
AVDD12
60 59 58
AVDD12
XTL_OUT
62 61
XTL_IN
DS2_DP
63
AVDD33
DS2_DM
64
US_DP
DS3_DM
65
US_DM
DS3_DP
66
DS1_DM
AVDD33
67
DS1_DP
DS4_DP
68
AVDD33
DS4_DM
Figure 7. HX3 68-Pin QFN 4-Port Pinout
53 52
DVDD12
1
51 DS1_RXP
RREF_USB2
2
50 DS1_RXM
DVDD12
3
49 DVDD12
AVDD33
4
48 DS1_TXM
US_TXM
5
47 DS1_TXP
US_TXP
6
46 AVDD12
DVDD12
7
45 DS2_RXP
US_RXM
8
44 DS2_RXM
US_RXP
9
AVDD12
10
42 DS2_TXM
DS4_TXP
11
41 DS2_TXP
DS4_TXM
12
40 GND
DVDD12
13
39 DS3_TXM
DS4_RXM
14
38 DS3_TXP
DS4_RXP
15
37 DVDD12
AVDD12
16
36 DS3_RXM
VBUS_US
17
35 DS3_RXP
43 DVDD12
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
VBUS_DS
VDD_EFUSE
SUSPEND
RESERVED1
RESERVED2
MODE_SEL[0]
MODE_SEL[1]
NC
RREF_SS
DVDD12
VDD_IO
PWR_EN
OVRCURR
RESETN
I2C_CLK
I2C_DATA
AVDD12
68-Pin QFN
Document Number: 001-73643 Rev. *O
Page 9 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Figure 8. HX3 100-Ball BGA Pinout for CYUSB3302
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
NC
NC
NC
AVDD33
DS2_DM
DS2_DP
AVDD33
US_DM
US_DP
AVDD12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
NC
NC
NC
VDD_IO
VSS
AVDD33
NC
NC
NC
DVDD12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
US_TXM
NC
NC
NC
NC
VSS
DS1_DP
DS1_DM
AVDD12
DS1_RXM
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
US_TXP
NC
NC
DVDD12
VSS
DVDD12
VSS
DVDD12
VSS
DS1_RXP
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
DVDD12
RREF_US
B2
NC
NC
XTL_IN
XTL_OUT
VDD_IO
DS1_TXM
VSS
DVDD12
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
DVDD12
OVRCUR
R
RESETN
DS1_TXP
AVDD12
DS2_RXP
G5
G6
G7
G8
G9
G10
VDD_IO
PWR_EN
I2C_DATA
VSS
DS2_RXM
US_RXM
VSS
AVDD33
MODE_SE
L[1]
G1
G2
G3
G4
US_RXP
VBUS_DS
SUSPEND
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
AVDD12
VBUS_US
VDD_EFU
SE
RESERVE
D2
RREF_SS
VSS
DS2_TXM
DS2_TXP
NC
AVDD12
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
VSS
AVDD12
VSS
GPIO
NC
I2C_CLK
NC
NC
VSS
NC
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
NC
NC
DVDD12
NC
NC
NC
NC
NC
DVDD12
NC
Document Number: 001-73643 Rev. *O
RESERVE MODE_SE
D1
L[0]
Page 10 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Figure 9. HX3 100-Ball BGA Pinout for CYUSB3304
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
NC
DS4_DM
DS4_DP
AVDD33
DS2_DM
DS2_DP
AVDD33
US_DM
US_DP
AVDD12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
NC
NC
NC
VDD_IO
VSS
AVDD33
NC
NC
NC
DVDD12
C1
C2
C3
C4
C5
C6
C7
C8
C9
10
US_TXM
NC
NC
DS3_DP
DS3_DM
VSS
DS1_DP
DS1_DM
AVDD12
DS1_RXM
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
US_TXP
NC
NC
DVDD12
VSS
DVDD12
VSS
DVDD12
VSS
DS1_RXP
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
DVDD12
RREF_US
B2
NC
NC
XTL_IN
XTL_OUT
VDD_IO
DS1_TXM
VSS
DVDD12
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
DVDD12
OVRCUR
R
RESETN
DS1_TXP
AVDD12
DS2_RXP
G5
G6
G7
G8
G9
G10
VDD_IO
PWR_EN
I2C_DATA
VSS
DS2_RXM
US_RXM
VSS
AVDD33
MODE_SE
L[1]
G1
G2
G3
G4
US_RXP
VBUS_DS
SUSPEND
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
AVDD12
VBUS_US
VDD_EFU
SE
RESERVE
D2
RREF_SS
VSS
DS2_TXM
DS2_TXP
NC
AVDD12
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
VSS
AVDD12
VSS
GPIO
NC
I2C_CLK
NC
NC
VSS
DS3_RXM
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
DS4_TXP
DS4_TXM
DVDD12
DS4_RXP
DS4_RXM
NC
DS3_TXP
DS3_TXM
DVDD12
DS3_RXP
Document Number: 001-73643 Rev. *O
RESERVE MODE_SE
D1
L[0]
Page 11 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Table 2. 68-Pin QFN, 100-Ball BGA Pinout for CYUSB3302 and CYUSB3304
Pin Name
Type
68-QFN Pin#
100-BGA
Ball #
US_RXP
I
9
G1
SuperSpeed receive plus
US_RXM
I
8
F1
SuperSpeed receive minus
US_TXP
O
6
D1
SuperSpeed transmit plus
CYUSB3302 CYUSB3304
Description
US Port
US_TXM
O
5
C1
SuperSpeed transmit minus
US_DP
I/O
57
A9
USB 2.0 data plus
US_DM
I/O
58
A8
USB 2.0 data minus
DS1 Port
DS1_RXP
I
51
D10
SuperSpeed receive plus
DS1_RXM
I
50
C10
SuperSpeed receive minus
DS1_TXP
O
47
F8
SuperSpeed transmit plus
DS1_TXM
O
48
E8
SuperSpeed transmit minus
DS1_DP
I/O
60
C7
USB 2.0 data plus
DS1_DM
I/O
59
C8
USB 2.0 data minus
DS2 Port
DS2_RXP
I
45
F10
SuperSpeed receive plus
DS2_RXM
I
44
G10
SuperSpeed receive minus
DS2_TXP
O
41
H8
SuperSpeed transmit plus
DS2_TXM
O
42
H7
SuperSpeed transmit minus
DS2_DP
I/O
62
A6
USB 2.0 data plus
DS2_DM
I/O
63
A5
USB 2.0 data minus
DS3 Port
NC
DS3_RXP
I
35
K10
SuperSpeed receive plus
NC
DS3_RXM
I
36
J10
SuperSpeed receive minus
NC
DS3_TXP
O
38
K7
SuperSpeed transmit plus
NC
DS3_TXM
O
39
K8
SuperSpeed transmit minus
NC
DS3_DP
I/O
65
C4
USB 2.0 data plus
NC
DS3_DM
I/O
64
C5
USB 2.0 data minus
DS4 Port
NC
DS4_RXP
I
15
K4
SuperSpeed receive plus
NC
DS4_RXM
I
14
K5
SuperSpeed receive minus
NC
DS4_TXP
O
11
K1
SuperSpeed transmit plus
NC
DS4_TXM
O
12
K2
SuperSpeed transmit minus
NC
DS4_DP
I/O
67
A3
USB 2.0 data plus
NC
DS4_DM
I/O
68
A2
USB 2.0 data minus
OVRCURR
I
30
F6
Ganged overcurrent input
PWR_EN
I/O
29
G7
Ganged power enable output
NC
I/O
25
NA
NC
Document Number: 001-73643 Rev. *O
Page 12 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Table 2. 68-Pin QFN, 100-Ball BGA Pinout for CYUSB3302 and CYUSB3304 (continued)
Pin Name
Type
68-QFN Pin#
100-BGA
Ball #
RESERVED1
I/O
21
G4
This pin must be pulled HIGH using a 10 k to VDD_IO.
RESERVED2
I
22
H4
This pin must be pulled HIGH using a 10 k to VDD_IO.
CYUSB3302 CYUSB3304
Description
Mode Select, Clock, and Reset
MODE_SEL[0]
I
23
G5
Device operation mode select bit 0; refer to Table 5 on page 24
MODE_SEL[1]
I
24
F4
Device operation mode select bit 1; refer to Table 5 on page 24
XTL_OUT
A
54
E6
Crystal out
XTL_IN
A
55
E5
Crystal in
RESETN
I
31
F7
Active LOW reset input
I2C_CLK
I/O
32
J6
I2C clock
I2C_DATA
I/O
33
G8
I2C data
SUSPEND
I/O
20
G3
Hub suspend status indicator. This pin is asserted if both the
SS and USB 2.0 hubs are in the suspend state and is
de-asserted when either of the hubs comes out of the suspend
state.
Power and Ground
H3
1.2 V normal operation, 2.5 V for programming. Customers
should connect to 1.2 V.
VDD_EFUSE
PWR
19
AVDD12
PWR
10, 16, 34, 46,
52, 53
GND
PWR
40
DVDD12
PWR
1, 3, 7, 13, 27,
37, 43, 49,
VBUS _US
PWR
17
H2
This pin must be connected to VBUS from US port
VBUS_DS
PWR
18
G2
This pin is used to power the Apple-charging circuit in HX3.
For BC v1.2 compliance testing, connect pin to GND. For
normal operation, connect pin to local 5 V supply.
AVDD33
PWR
4, 56, 61, 66
VDD_IO
PWR
28
A10, C9, F9,
1.2 V analog supply
H1, H10, J2
B5, C6, D5, D7,
D9, E9, F2, G9, GND pin
H6, J1, J3, J9
B10, D4, D6,
D8, E1, E10, 1.2 V core supply
F5, K3, K9
A4, A7, B6, F3 3.3 V analog supply
B4, E7, G6
3.3 V I/O supply
USB Precision Resistors
RREF_USB2
A
2
E2
Connect pin to a precision resistor (6.04 k±1%) to generate
a current reference for USB 2.0 PHY.
RREF_SS
A
26
H5
Connect pin to a precision resistor (200  ±1%) for SS PHY
termination impedance calibration.
Note
4. These pins are Do Not Use (DNU); they must be left floating.
Document Number: 001-73643 Rev. *O
Page 13 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Table 3. 68-Pin QFN, 100-Ball BGA Pinout for CYUSB2302 and CYUSB2304
Pin Name
Type
68-QFN Pin#
100-BGA
Ball #
NC
I
9
G1
SuperSpeed receive plus
NC
I
8
F1
SuperSpeed receive minus
NC
O
6
D1
SuperSpeed transmit plus
CYUSB2302 CYUSB2304
Description
US Port
NC
O
5
C1
SuperSpeed transmit minus
US_DP
I/O
57
A9
USB 2.0 data plus
US_DM
I/O
58
A8
USB 2.0 data minus
DS1 Port
NC
I
51
D10
SuperSpeed receive plus
NC
I
50
C10
SuperSpeed receive minus
NC
O
47
F8
SuperSpeed transmit plus
NC
O
48
E8
SuperSpeed transmit minus
DS1_DP
I/O
60
C7
USB 2.0 data plus
DS1_DM
I/O
59
C8
USB 2.0 data minus
DS2 Port
NC
I
45
F10
SuperSpeed receive plus
NC
I
44
G10
SuperSpeed receive minus
NC
O
41
H8
SuperSpeed transmit plus
NC
O
42
H7
SuperSpeed transmit minus
DS2_DP
I/O
62
A6
USB 2.0 data plus
DS2_DM
I/O
63
A5
USB 2.0 data minus
DS3 Port
NC
NC
I
35
K10
SuperSpeed receive plus
NC
NC
I
36
J10
SuperSpeed receive minus
NC
NC
O
38
K7
SuperSpeed transmit plus
NC
NC
O
39
K8
SuperSpeed transmit minus
NC
DS3_DP
I/O
65
C4
USB 2.0 data plus
NC
DS3_DM
I/O
64
C5
USB 2.0 data minus
DS4 Port
NC
NC
I
15
K4
SuperSpeed receive plus
NC
NC
I
14
K5
SuperSpeed receive minus
NC
NC
O
11
K1
SuperSpeed transmit plus
NC
NC
O
12
K2
SuperSpeed transmit minus
NC
DS4_DP
I/O
67
A3
USB 2.0 data plus
NC
DS4_DM
I/O
68
A2
USB 2.0 data minus
OVRCURR
I
30
F6
Ganged overcurrent input
PWR_EN
I/O
29
G7
Ganged power enable output
NC
I/O
25
NA
NC
Document Number: 001-73643 Rev. *O
Page 14 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Table 3. 68-Pin QFN, 100-Ball BGA Pinout for CYUSB2302 and CYUSB2304 (continued)
Pin Name
Type
68-QFN Pin#
100-BGA
Ball #
RESERVED1
I/O
21
G4
This pin must be pulled HIGH using a 10 k to VDD_IO.
RESERVED2
I
22
H4
This pin must be pulled HIGH using a 10 k to VDD_IO.
CYUSB2302 CYUSB2304
Description
Mode Select, Clock, and Reset
MODE_SEL[0]
I
23
G5
Device operation mode select bit 0; refer to Table 5 on page 24
MODE_SEL[1]
I
24
F4
Device operation mode select bit 1; refer to Table 5 on page 24
XTL_OUT
A
54
E6
Crystal out
XTL_IN
A
55
E5
Crystal in
RESETN
I
31
F7
Active LOW reset input
I2C_CLK
I/O
32
J6
I2C clock
I2C_DATA
I/O
33
G8
I2C data
SUSPEND
I/O
20
G3
Hub suspend status indicator. This pin is asserted if both the
SS and USB 2.0 hubs are in the suspend state and is
de-asserted when either of the hubs comes out of the suspend
state.
Power and Ground
H3
1.2 V normal operation, 2.5 V for programming. Customers
should connect to 1.2 V.
VDD_EFUSE
PWR
19
AVDD12
PWR
10, 16, 34, 46,
52, 53
GND
PWR
40
DVDD12
PWR
1, 3, 7, 13, 27,
37, 43, 49,
VBUS _US
PWR
17
H2
This pin must be connected to VBUS from US port
VBUS_DS
PWR
18
G2
This pin is used to power the Apple-charging circuit in HX3.
For BC v1.2 compliance testing, connect pin to GND. For
normal operation, connect pin to local 5 V supply.
AVDD33
PWR
4, 56, 61, 66
VDD_IO
PWR
28
A10, C9, F9,
1.2 V analog supply
H1, H10, J2
B5, C6, D5, D7,
D9, E9, F2, G9, GND pin
H6, J1, J3, J9
B10, D4, D6,
D8, E1, E10, 1.2 V core supply
F5, K3, K9
A4, A7, B6, F3 3.3 V analog supply
B4, E7, G6
3.3 V I/O supply
USB Precision Resistors
RREF_USB2
A
2
E2
Connect pin to a precision resistor (6.04 k±1%) to generate
a current reference for USB 2.0 PHY.
RREF_SS
A
26
H5
Connect pin to a precision resistor (200  ±1%) for SS PHY
termination impedance calibration.
Document Number: 001-73643 Rev. *O
Page 15 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
VDD_IO
DS3_PWREN
DS2_PWREN
DS3_AMBER
DS2_LED_SS
DVDD12
NC
NC
AVDD33
NC
NC
DS2_DM
DS2_DP
AVDD33
DS1_DP
DS1_DM
US_DM
US_DP
AVDD33
XTL_IN
XTL_OUT
AVDD12
Figure 10. HX3 88-Pin QFN 2-Port Pinout
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
DS2_OVRCURR
1
66
VDD_IO
DS1_AMBER
2
65
DS3_OVRCURR
DS1_GREEN
3
64
DS3_GREEN
DS1_LED_SS
4
63
DS3_LED_SS
DS2_AMBER
5
62
AVDD12
DS2_GREEN
6
61 DS1_RXP
RREF_USB2
7
60 DS1_RXM
DVDD12
8
59 DVDD12
AVDD33
9
58 DS1_TXM
US_TXM
10
57 DS1_TXP
US_TXP
11
DVDD12
12
US_RXM
13
54
US_RXP
14
53 DVDD12
AVDD12
15
52
DS2_TXM
NC
16
51
DS2_TXP
NC
17
50
GND
DVDD12
18
49
NC
NC
19
48 NC
NC
20
47
DVDD12
AVDD12
21
46
NC
VBUS_US
22
45
NC
56
88-Pin QFN
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
VBUS_DS
VDD_EFUSE
SUSPEND
DS4_LED_SS
RESERVED1
MODE_SEL[0]
MODE_SEL[1]
DS4_AMBER
US_PWREN
RREF_SS
DVDD12
VDD_IO
DS4_PWREN/PWR_EN4
DS4_OVRCURR
RESETN
DS1_PWREN
US_OVRCURR
I2C_CLK
I2C_DATA
DS1_OVRCURR
DS4_GREEN
AVDD12
55 DS2_RXP
23
Document Number: 001-73643 Rev. *O
AVDD12
DS2_RXM
Page 16 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
VDD_IO
DS3_PWREN
DS2_PWREN
DS3_AMBER
DS2_LED_SS
DVDD12
DS4_DM
DS4_DP
AVDD33
DS3_DP
DS3_DM
DS2_DM
DS2_DP
AVDD33
DS1_DP
DS1_DM
US_DM
US_DP
AVDD33
XTL_IN
XTL_OUT
AVDD12
Figure 11. HX3 88-Pin QFN 4-Port Pinout
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
DS2_OVRCURR
1
66
VDD_IO
DS1_AMBER
2
65
DS3_OVRCURR
DS1_GREEN
3
64
DS3_GREEN
DS1_LED_SS
4
63
DS3_LED_SS
DS2_AMBER
5
62
AVDD12
DS2_GREEN
6
61 DS1_RXP
RREF_USB2
7
60 DS1_RXM
DVDD12
8
59 DVDD12
AVDD33
9
58 DS1_TXM
US_TXM
10
57 DS1_TXP
US_TXP
11
DVDD12
12
US_RXM
13
54
US_RXP
14
53 DVDD12
AVDD12
15
52
DS2_TXM
DS4_TXP
16
51
DS2_TXP
DS4_TXM
17
50
GND
DVDD12
18
49
DS3_TXM
DS4_RXM
19
48 DS3_TXP
DS4_RXP
20
47
DVDD12
AVDD12
21
46
DS3_RXM
VBUS_US
22
45
DS3_RXP
56
88-Pin QFN
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
VBUS_DS
VDD_EFUSE
SUSPEND
DS4_LED_SS
RESERVED1
MODE_SEL[0]
MODE_SEL[1]
DS4_AMBER
US_PWREN
RREF_SS
DVDD12
VDD_IO
DS4_PWREN/PWR_EN4
DS4_OVRCURR
RESETN
DS1_PWREN
US_OVRCURR
I2C_CLK
I2C_DATA
DS1_OVRCURR
DS4_GREEN
AVDD12
55 DS2_RXP
23
Document Number: 001-73643 Rev. *O
AVDD12
DS2_RXM
Page 17 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Figure 12. HX3 100-Ball BGA Pinout for CYUSB3312
A1
A2
DS3_PWR
NC
EN
B1
B2
DS2_OVR DS2_PWR
CURR
EN
C1
C2
DS1_AMBE
US_TXM
R
D1
D2
DS1_LED_
US_TXP
SS
E1
E2
RREF_USB
DVDD12
2
F1
F2
US_RXM
G1
US_RXP
H1
AVDD12
J1
VSS
K1
NC
A3
A4
A5
A6
A7
A8
A9
A10
NC
AVDD33
DS2_DM
DS2_DP
AVDD33
US_DM
US_DP
AVDD12
B3
B4
B5
B6
B7
B8
B9
DS3_AMBE
DS3_OVR DS3_GREE DS3_LED_
VDD_IO
VSS
AVDD33
R
CURR
N
SS
C3
C4
C5
C6
C7
C8
C9
DS2_LED_
NC
NC
VSS
DS1_DP
DS1_DM
AVDD12
SS
D3
D4
D5
D6
D7
D8
D9
DS1_GREE
DVDD12
VSS
DVDD12
VSS
DVDD12
VSS
N
E3
E4
E5
E6
E7
E8
E9
DS2_GREE DS2_AMBE
XTL_IN
XTL_OUT
VDD_IO
DS1_TXM
VSS
N
R
F3
F4
F5
F6
F7
F8
F9
MODE_SE
DS4_OVR
VSS
AVDD33
DVDD12
RESETN
DS1_TXP
AVDD12
L[1]
CURR
G2
G3
G4
G5
G6
G7
G8
G9
RESERVE MODE_SE
DS4_PWR
VBUS_DS SUSPEND
VDD_IO
I2C_DATA
VSS
D1
L[0]
EN
H2
H3
H4
H5
H6
H7
H8
H9
VDD_EFUS DS4_LED_
DS4_GREE
VBUS_US
RREF_SS
VSS
DS2_TXM DS2_TXP
E
SS
N
J2
J3
J4
J5
J6
J7
J8
J9
DS4_AMBE US_PWRE
DS1_PWR DS1_OVR
AVDD12
VSS
I2C_CLK
VSS
R
N
EN
CURR
K2
K3
K4
K5
K6
K7
K8
K9
US_OVRC
NC
DVDD12
NC
NC
NC
NC
DVDD12
URR
Document Number: 001-73643 Rev. *O
B10
DVDD12
C10
DS1_RXM
D10
DS1_RXP
E10
DVDD12
F10
DS2_RXP
G10
DS2_RXM
H10
AVDD12
J10
NC
K10
NC
Page 18 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Figure 13. HX3 100-Ball BGA Pinout for CYUSB3314, CYUSB332x
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
DS3_PWR
EN
DS4_DM
DS4_DP
AVDD33
DS2_DM
DS2_DP
AVDD33
US_DM
US_DP
AVDD12
B4
B5
B6
B7
B8
B9
B10
DS3_GRE
EN
DS3_LED
_SS
DVDD12
B1
B2
B3
DS2_OVR
CURR
DS2_PWR
EN
DS3_AMB
ER
VDD_IO
VSS
AVDD33
DS3_OVR
CURR
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
US_TXM
DS1_AMB
ER
DS2_LED
_SS
DS3_DP
DS3_DM
VSS
DS1_DP
DS1_DM
AVDD12
DS1_RXM
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
US_TXP
DS1_LED
_SS
DS1_GRE
EN
DVDD12
VSS
DVDD12
VSS
DVDD12
VSS
DS1_RXP
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
DVDD12
RREF_US
B2
DS2_GRE
EN
DS2_AMB
ER
XTL_IN
XTL_OUT
VDD_IO
DS1_TXM
VSS
DVDD12
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
DVDD12
DS4_OVR
CURR
RESETN
DS1_TXP
AVDD12
DS2_RXP
G5
G6
G7
G8
G9
G10
VDD_IO
DS4_PWR
EN
I2C_DATA
VSS
DS2_RXM
H6
H7
H8
H9
H10
AVDD12
US_RXM
VSS
AVDD33
MODE_SE
L[1]
G1
G2
G3
G4
US_RXP
VBUS_DS
SUSPEND
H1
H2
H3
H4
AVDD12
VBUS_US
VDD_EFU
SE
DS4_LED
_SS
RREF_SS
VSS
DS2_TXM
DS2_TXP
DS4_GRE
EN
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
VSS
AVDD12
VSS
DS4_AMB
ER
US_PWR
EN
I2C_CLK
DS1_PWR
EN
DS1_OVR
CURR
VSS
DS3_RXM
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
DS4_RXM
US_OVRC
URR
DS3_TXP
DS3_TXM
DVDD12
DS3_RXP
DS4_TXP
DS4_TXM
DVDD12
Document Number: 001-73643 Rev. *O
RESERVE MODE_SE
D1
L[0]
DS4_RXP
H5
Page 19 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Table 4. 88-Pin QFN, 100-Ball BGA Pinout for CYUSB331X and CYUSB332X
Pin Name
CYUSB3314
CYUSB3324
Type
Pin#
Ball#
US_RXP
I
14
G1
SuperSpeed receive plus
US_RXM
I
13
F1
SuperSpeed receive minus
US_TXP
O
11
D1
SuperSpeed transmit plus
CYUSB3312
Description
CYUSB3326
CYUSB3328
US Port
US_TXM
O
10
C1
SuperSpeed transmit minus
US_DP
I/O
71
A9
USB 2.0 data plus
US_DM
I/O
72
A8
USB 2.0 data minus
US_OVRCURR
US_PWREN[5]
I
39
K6
I/O
31
J5
PWR_SW_POL[6]
CYUSB3324/3328: Overcurrent detect input for US port in ACA-Dock
mode. If ACA-Dock mode is disabled using Configuration Options on
page 24, this pin must be pulled HIGH using a 10 k to VDD_IO.
Other part numbers: This pin must be pulled HIGH using a 10 k to
VDD_IO.
CYUSB3324/3328: VBUS power enable output for US port in ACA-Dock
mode. If ACA-Dock mode is disabled using Configuration Options on
page 24, this pin can be left floating if Pin-Strap is not enabled.
Other part numbers: This pin can be left floating if Pin-Strap (Pin# 63) is
not enabled.
This pin is called PWR_SW_POL in pin-strap configuration mode.
DS1 Port
DS1_RXP
I
61
D10
SuperSpeed receive plus
DS1_RXM
I
60
C10
SuperSpeed receive minus
DS1_TXP
O
57
F8
SuperSpeed transmit plus
DS1_TXM
O
58
E8
SuperSpeed transmit minus
DS1_DP
I/O
74
C7
USB 2.0 data plus
DS1_DM
I/O
73
C8
USB 2.0 data minus
DS1_OVRCURR
I
42
J8
Overcurrent detect input for DS1 port
DS1_PWREN[5]
I/O
38
J7
DS1_CDP_EN[6]
DS1_AMBER[5]
ACA_DOCK[6]
This pin is called DS1_CDP_EN in pin-strap configuration mode.
I/O
2
C2
DS1_GREEN[5]
DS1_VBUSEN_SL[5]
LED_AMBER output for DS1 port
This pin is called ACA-DOCK in pin-strap configuration mode.
CYUSB3312/3314/3324: LED_GREEN output for DS1 port
I/O
3
D3
PORT_DISABLE[0][6]
CYUSB3326/3328: VBUS power enable output for SS port 1
This pin is called PORT_DISABLE[0] in pin-strap configuration mode.
DS1_LED_SS[5]
PORT_DISABLE[1][6]
VBUS power enable output for DS1 port. When the port is disabled, this
pin is in tristate.
LED_SS output for DS1 port
I/O
4
D2
This pin is called PORT_DISABLE[1] in pin-strap configuration mode.
Notes
5. This pin can be configured as a GPIO using custom firmware. For information contact www.cypress.com/support.
6. For pin-strap configuration details, refer to Table 6 on page 25.
Document Number: 001-73643 Rev. *O
Page 20 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Table 4. 88-Pin QFN, 100-Ball BGA Pinout for CYUSB331X and CYUSB332X (continued)
Pin Name
CYUSB3314
CYUSB3312
CYUSB3324
Type
Pin#
Ball#
Description
CYUSB3326
CYUSB3328
DS2 Port
DS2_RXP
I
55
F10
SuperSpeed receive plus
DS2_RXM
I
54
G10
SuperSpeed receive minus
DS2_TXP
O
51
H8
SuperSpeed transmit plus
DS2_TXM
O
52
H7
SuperSpeed transmit minus
DS2_DP
I/O
76
A6
USB 2.0 data plus
DS2_DM
I/O
77
A5
USB 2.0 data minus
DS2_OVRCURR
I
1
B1
Overcurrent detect input for DS2 port
DS2_PWREN[7]
I/O
86
B2
DS2_CDP_EN[8]
This pin is called DS2_CDP_EN in the pin-strap configuration mode.
DS2_AMBER[7]
LED_AMBER output for DS2 port
NON_REMOVABLE[0][8]
I/O
5
E4
DS2_GREEN[7]
DS2_VBUSEN_SL
VBUS power enable output for DS2 port. When the port is disabled, this
pin is in tristate.
This pin is called NON_REMOVABLE[0] in the pin-strap configuration
mode.
CYUSB3312/3314/3324: LED_GREEN output for DS2 port
[7]
I/O
6
E3
I/O
84
C3
NON_REMOVABLE[1][8]
DS2_LED_SS[7]
PWR_EN_SEL[8]
CYUSB3326/3328: VBUS power enable output for SS port 2
This pin is called NON_REMOVABLE[1] in the pin-strap configuration
mode.
LED_SS output for DS2 port
This pin is called PWR_EN_SEL in the pin-strap configuration mode.
DS3 Port
NC
DS3_RXP
I
45
K10
SuperSpeed receive plus
NC
DS3_RXM
I
46
J10
SuperSpeed receive minus
NC
DS3_TXP
O
48
K7
SuperSpeed transmit plus
NC
DS3_TXM
O
49
K8
SuperSpeed transmit minus
NC
DS3_DP
I/O
79
C4
USB 2.0 data plus
NC
DS3_DM
I/O
78
C5
USB 2.0 data minus
I
65
B7
CYUSB3314/3324/3326/3328: Overcurrent detect input for DS3 port
CYUSB3312: This pin must be pulled HIGH using a 10 k to VDD_IO.
I/O
87
A1
DS3_OVRCURR
DS3_PWREN[7]
DS3_CDP_EN[8]
DS3_AMBER[7]
VID_SEL[2][8]
VBUS power enable output for DS3 port. When the port is disabled, this
pin is in tristate.
This pin is called DS3_CDP_EN in the pin-strap configuration mode.
I/O
85
B3
LED_AMBER output for DS3 port
This pin is called VID_SEL[2] in the pin-strap configuration mode.
Notes
7. This pin can be configured as a GPIO using custom firmware. For information contact www.cypress.com/support.
8. For pin-strap configuration details, refer to Table 6 on page 25.
Document Number: 001-73643 Rev. *O
Page 21 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Table 4. 88-Pin QFN, 100-Ball BGA Pinout for CYUSB331X and CYUSB332X (continued)
Pin Name
CYUSB3314
CYUSB3312
CYUSB3324
Type
Pin#
Ball#
Description
CYUSB3326
CYUSB3328
DS3_GREEN[9]
DS3_VBUSEN_SL[9]
CYUSB3312/3314/3324: LED_GREEN output for DS3 port
I/O
64
B8
VID_SEL[1][10]
DS3_LED_SS[9]
PIN_STRAP[10]
CYUSB3328: VBUS power enable output for SS port 3
This pin is called VID_SEL[1] in the pin-strap configuration mode. For
pin-strap configuration details, refer to Table 6 on page 25.
LED_SS output for DS3 port
I/O
63
B9
This pin is called PIN_STRAP in pin-strap configuration mode. When
connected to VDD_IO through a 10-k resistor, this pin enables
pin-strap configuration mode for HX3.
DS4 Port
NC
DS4_RXP
I
20
K4
SuperSpeed receive plus
NC
DS4_RXM
I
19
K5
SuperSpeed receive minus
NC
DS4_TXP
O
16
K1
SuperSpeed transmit plus
NC
DS4_TXM
O
17
K2
SuperSpeed transmit minus
NC
DS4_DP
I/O
81
A3
USB 2.0 data plus
NC
DS4_DM
I/O
82
A2
USB 2.0 data minus
I
36
F6
CYUSB3314/3324/3326/3328: Overcurrent detect input for DS4 port.
CYUSB3312: This pin must be pulled HIGH using a 10 k to VDD_IO.
DS4_OVRCURR
DS4_PWREN/PWR_EN4
I/O
35
G7
DS4_CDP_EN[10]
DS4_AMBER[9]
I2C_DEV_ID[10]
This pin is called DS4_CDP_EN in the pin-strap configuration mode.
I/O
30
J4
DS4_GREEN[9]
DS4_VBUSEN_SL
VBUS power enable output for DS4 port. This pin is also used as power
enable output when configured in ganged power mode using the Blaster
Plus tool. When the port is disabled, this pin is in tristate.
LED_AMBER output for DS4 port
This pin is called I2C_DEV_ID in the pin-strap configuration mode.
CYUSB3312/3314/3324: LED_GREEN output for DS4 port
I/O
43
H9
VID_SEL[0][10]
CYUSB3328: VBUS power enable output for SS port 4
This pin is called VID_SEL[0] in the pin-strap configuration mode.
DS4_LED_SS
I/O
26
H4
LED_SS output for DS4 port. The LED must be connected to GND as
shown in Figure 16 on page 25. If LED is not used, this pin must be pulled
HIGH using a 10 k to VDD_IO.
RESERVED1
I
27
G4
This pin must be pulled HIGH using a 10 k to VDD_IO.
Mode Select, Clock, and Reset
MODE_SEL[0]
I
28
G5
Device operation mode select bit 0; refer to Table 5 on page 24
MODE_SEL[1]
I
29
F4
Device operation mode select bit 1; refer to Table 5 on page 24
XTL_OUT
A
68
E6
Crystal out
XTL_IN
A
69
E5
Crystal in
RESETN
I
37
F7
Active LOW reset input
I2C_CLK
I/O
40
J6
I2C clock
I2C_DATA
I/O
41
G8
I2C data
Notes
9. This pin can be configured as a GPIO using custom firmware. For information contact www.cypress.com/support.
10. For pin-strap configuration details, refer to Table 6 on page 25.
Document Number: 001-73643 Rev. *O
Page 22 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Table 4. 88-Pin QFN, 100-Ball BGA Pinout for CYUSB331X and CYUSB332X (continued)
Pin Name
CYUSB3314
CYUSB3312
CYUSB3324
Type
Pin#
Ball#
Description
I/O
25
G3
Hub suspend status indicator. This pin is asserted if both the SS and
USB 2.0 hubs are in the suspend state and is de-asserted when either
of the hubs comes out of the suspend state.
CYUSB3326
CYUSB3328
SUSPEND
Power and Ground
VDD_EFUSE
PWR
24
AVDD12
PWR
15, 21,
44, 56,
62, 67
GND
PWR
50
DVDD12
PWR
8, 12,
18, 33,
47, 53,
59, 83
VBUS _US
PWR
22
VBUS_DS
PWR
23
AVDD33
PWR
VDD_IO
PWR
9, 70,
75, 80
34, 66,
88
H3
1.2 V normal operation, 2.5 V for programming. Customers should
connect to 1.2 V
A10, C9,
F9, H1, 1.2 V analog supply
H10, J2
B5, C6,
D5, D7,
D9, E9,
GND pin
F2, G9,
H6, J1,
J3, J9
B10, D4,
D6, D8,
E1, E10, 1.2 V core supply
F5, K3,
K9
CYUSB3324/3328: Connect the VBUS_US pin to the local 5 V supply.
If ACA-Dock mode is disabled using Configuration Options on page 24,
H2
this pin must be connected to VBUS from US port.
Other part numbers: This pin must be connected to VBUS from US port.
This pin is used to power the Apple-charging circuit in HX3.
G2
For BC v1.2 compliance testing, connect pin to GND. For normal
operation, connect pin to local 5 V supply.
A4, A7,
3.3 V analog supply
B6, F3
B4, E7,
3.3 V I/O supply
G6
USB Precision Resistors
RREF_USB2
A
7
E2
RREF_SS
A
32
H5
Document Number: 001-73643 Rev. *O
Connect pin to a precision resistor (6.04 k ±1%) to generate a current
reference for USB 2.0 PHY.
Connect pin to a precision resistor (200  ±1%) for SS PHY termination
impedance calibration.
Page 23 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
System Interfaces
Upstream Port (US)
This port is compliant with the USB 3.0 specification and includes
an integrated 1.5 k pull-up and termination resistors. It also
supports ACA-Dock to enable charging an OTG host connected
on the US port.
Downstream Ports (DS1, 2, 3, 4)
DS ports are compliant with the USB 3.0 specification and
integrate 15 k pull-down and termination resistors. Ports can
be disabled or enabled, and can be set to removable or
non-removable options. BC v1.2 charging is enabled by default
and can be disabled on each DS port using the configuration
options (see Configuration Options).
The RESETN pin can be tied to VDD_IO through an external
resistor and to ground (GND) through an external capacitor
(minimum 5 ms time constant), as shown in Figure 15. This
creates a clean reset signal for power-on reset (POR).
HX3 does not support internal brown-out detection. If the system
requires this feature, an external reset should be provided on the
RESETN pin when supplies are below their valid operating
ranges.
Figure 15. Reset Connection
VDD_IO
10 k
RESETN
Communication Interfaces (I2C)
The interface follows the Inter-IC Bus specification, version 3.0,
with support for the standard mode (100 kHz) and the fast mode
(400 kHz) frequencies. HX3 supports I2C in the slave and master
modes. The I2C interface supports the multi-master mode of
operation. Both the SCL and SDA signals require external
pull-up resistors based on the specification. VDD_IO for HX3 is
3.3 V and it is expected that the I2C pull-up resistors will be
connected to the same supply.
Oscillator
HX3 requires an external crystal with a frequency of 26 MHz and
an accuracy of ±150 ppm in parallel resonant, fundamental
mode. The crystal drive circuit is capable of a low-power drive
level (<200 µW). The crystal connection to the XTL_OUT and
XTL_IN pins is shown in Figure 14.
1.5 µF
Configuration Mode Select
Configuration options are selected through the MODE_SEL pins
and the pin-strap enable pin (PIN_STRAP). After power-up,
these pins are sampled by an on-chip bootloader to determine
the configuration options (see Table 5).
Table 5. HX3 Boot Sequence
Figure 14. Crystal Connection
26 MHz
XTL_IN
10 pF
XTL_OUT
10 pF
*
MODE
SEL[1]
MODE
SEL[0]
0
0
Reserved. Do not use this mode.
1
1
Internal ROM configuration
0
1
I2C Master, read configuration from I2C
EEPROM*
1
0
I2C Slave, configure from an external I2C
Master*
HX3 Configuration Modes
Download Cypress-provided firmware from www.cypress.com/hx3.
Configuration Options
GPIOs
HX3 can be configured by using one of the following:
HX3 GPIOs are used for overcurrent sensing, controlling
external power switches, and driving LEDs. These pins can sink
up to 4 mA current each. GPIOs also enable pin-straps for input
configuration. Refer to Table 6 for more details.
■
eFuse (one-time programmable memory)
■
Pin-Strap (read configuration from dedicated pins at power on)
■
External I2C slave such as an EEPROM
Power Control
■
External I2C master
The PWR_EN[1-4] and OV_CURR[1-4] pins interface HX3 to
external power switches. These pins are used to control power
switches for DS port power and monitor overcurrent conditions.
The power switch polarity and the power control mode (individual
and ganged) can be changed using the configuration options.
The I2C master/slave configuration overrides the pin-strap
configuration. Pin-straps override the eFuse configuration, and
the eFuse configuration overrides the internal ROM
configuration.
Reset
HX3 contains eFuses, which are OTP elements on the chip that
can be electrically blown. The eFuses are read by the bootloader
to determine the customer-specific configurations. eFuse
programming is supported only at factory and distributor
locations where programming conditions can be controlled.
eFuse programming is supported under the following conditions:
HX3 operates with two external power supplies, 3.3 V and 1.2 V.
There is no power sequencing requirement between these two
supplies. However, the RESETN pin should be held LOW until
both these supplies become stable.
Document Number: 001-73643 Rev. *O
eFuse Configuration
Page 24 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Temperature range of 25 °C–70 °C and programming voltage of
2.5 V–2.7 V.
Figure 16. Pin-Strap With LED or LED-Only Connection
To GPIO
VDD_IO
Pin-Strap Configuration
Pin-straps are supported for select product options (see Table 1
on page 5) to provide reconfigurability without an additional
EEPROM. The pin-strap configuration is enabled by pulling the
Pin #63 of 88-pin QFN HIGH. Table 6 on page 25 shows the
configuration options supported through pin-straps and the
GPIOs used for this purpose. Figure 16 and Figure 17 show how
the GPIOs need to be connected if pin-strap and LED connection
are required or only pin-strap is required.
HX3 samples pin-strap GPIOs at power-up. Floating straps are
considered as invalid and the default configuration is used. If
PIN_STRAP (Pin #63 of 88-pin QFN) is floating, all strap inputs
are considered invalid. A GPIO is considered strapped “1” or “0”
when connected with a weak pull-up (10 k) or pull-down
(10 k) respectively. After the initial sampling at power-up and
reset, the GPIOs are used in their normal functions.
10 k
800  –
1 k
800  –
1 k
10 k
VSS
To GPIO
Pin-Strap HIGH
with LED
Pin-Strap LOW
with LED
Figure 17. Pin-Strap Connection
VDD_IO
10 k
To GPIO
Pin-Strap HIGH
To GPIO
10 k
VSS
Pin-Strap LOW
Table 6. Pin-Strap Configuration
88-QFN
Pin #
30
31
2
84
63
4
3
6
5
85
64
43
38
86
87
35
Pin-Strap Name
Strapped ‘0’[11]
Strapped ‘1’[11]
ID 0: HX3 I2C slave address (7 bits) is 0x60.
This is also the default I2C slave address for ID 1: HX3 I2C slave address (7 bits) is 0x58
the 68-pin QFN package.
Power enable and overcurrent will be active Power enable and overcurrent will be active
PWR_SW_POL
LOW
HIGH
ACA_DOCK
Disabled
Enabled
PWR_EN_SEL
Individual
Gang
PIN_STRAP[13]
No pin-strapping
Pin-strapping configuration enabled
PORT_DISABLE[1]
PORT_DISABLE[1:0] =
b’00: DS1, DS2, DS3, DS4 active
b’01: DS1, DS2, DS3 active
b’10: DS1, DS2 active
PORT_DISABLE[0]
b’11: DS1 active
Pin-straps cannot enable ports disabled by factory setting.
NON_REMOVABLE[1][14] NON_REMOVABLE[1:0] =
b’00: DS1, DS2, DS3, DS4 removable
b’01: DS1, DS2, DS3 removable
NON_REMOVABLE[0][14] b’10: DS1, DS2 removable
b’11: DS1 removable
VID[2]
VID[1]
Reserved. If PIN_STRAP is enabled and CY VID is required, strap VID[2:0] to ‘1’.
VID[0]
strapped ‘0’
strapped ‘1’
strapped ‘0’
strapped ‘1’
DS1_CDP_EN[15]
DS1 CDP enabled
DS1 CDP disabled
DS1 CDP disabled
DS1 CDP enabled
DS2_CDP_EN[15]
DS2 CDP enabled
DS2 CDP disabled
DS2 CDP disabled
DS2 CDP enabled
DS3_CDP_EN[15]
DS3 CDP enabled
DS3 CDP disabled
DS3 CDP disabled
DS3 CDP enabled
DS4_CDP_EN[15]
DS4 CDP enabled
DS4 CDP disabled
DS4 CDP disabled
DS4 CDP enabled
I2C_DEV_ID[12]
Notes
11. See Figure 16 and Figure 17.
12. I2C_DEV_ID is valid only when HX3 is in I2C slave mode.
13. VID, PORT_DISABLE, NON_REMOVABLE are group straps. If one of the pins in a group strap is floating (INVALID), that group input will be INVALID and the default
will not be overwritten.
14. These DS ports are exposed ports and the connected devices can be removed.
15. DSx_CDP_EN will be active LOW input when PWR_SW_POL is set to active LOW; similarly DSx_CDP_EN will be active HIGH input when PWR_SW_POL is set to
active HIGH.
Document Number: 001-73643 Rev. *O
Page 25 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
I2C Configuration
I2C
When enabled for
configuration through the MODE_SEL
pins (See Table 5 on page 24), HX3 can be configured as an I2C
master or as an I2C slave. HX3’s configuration data is a
maximum of 197 bytes and HX3’s firmware is 10 KB. Note that
HX3’s firmware also includes configuration settings.
HX3 as I2C Master
HX3 reads configurations from an external I2C EEPROM with
sizes ranging from 16 to 64 KB. An example of a supported
EEPROM is 24LC128. Based on the contents of the bSignature
and bImageType fields in Table 7 on page 26, HX3 performs one
of the following actions:
■
Loads custom configuration settings from the EEPROM when
bSignature is “CY” and bImageType is 0xD4.
■
Loads the Cypress-provided firmware from the EEPROM when
bSignature is “CY” and bImageType is 0xB0. This firmware also
includes configuration settings.
■
If bSignature  “CY”, HX3 enumerates in the vendor-specific
mode.
The contents of the EEPROM can be updated with the
easy-to-use Cypress Blaster Plus tool. Blaster Plus is a
GUI-based tool to configure HX3. This tool allows to do the
following:
■
Download the Cypress-provided firmware from a PC via HX3's
US port and store it on an EEPROM connected to HX3’s I2C
port.
■
Read the configuration settings from the EEPROM. These
settings are displayed in the Blaster Plus GUI. Modify settings
as required.
■
Write back the updated settings on to the EEPROM. In addition,
an image file can be created for external use.
The Blaster Plus tool, user guide, and the Cypress-provided
firmware are available at www.cypress.com/hx3.
HX3 as I2C Slave
An external I2C master can program the configuration settings
into HX3 according to the EEPROM map in Table 7 on page 26.
Alternatively, the HX3 firmware (<10 KB), which includes configuration settings, can also be programmed. It is recommended to
use the Blaster Plus tool to create the HX3 firmware or configuration image file. HX3’s I2C slave address needs to be provided
while creating the image file. Refer to Table 6 for HX3’s I2C slave
address.
Table 7. EEPROM Map
I2C Offset Bits
Name
0
7:0 bSignature LSB (“C”)
1
7:0 bSignature MSB (“Y”)
2
7:6 bImageCTL
5:4 I2C Speed
3:1 bImageCTL
0 bImageCTL
3
7:0 bImageType
4
7:0 bD4Length
5
6
7
8
7:0
7:0
7:0
7:0
VID [7:0]
VID [15:8]
PID [7:0]
PID [15:8]
Document Number: 001-73643 Rev. *O
Default
Description
0x43 The first byte of the 2-byte signature initialized with “CY” ASCII
text.
When the signature is not valid, the hub enumerates as a
vendor-specific device.
0x59 The second byte of the 2-byte signature initialized with “CY”
ASCII text. When the signature is not valid, the hub enumerates
as a vendor-specific device.
b’00
Reserved
b’11
b’01: 400 kHz
b’11: 100 kHz
b’000 Reserved
0
0: Execution binary file
1: Data file
0xD4 0xD4: Load only configuration
0xB0: Load firmware boot image
All other bImageType will return an error code.
40
bD4Length is defined in bytes as the length from offset 5.
I2C offset bytes 0–4 are the header bytes.
bD4Length = 6: Only update VID, PID, and DID
bD4Length = 18: Configuration options (no PHY trim)
bD4Length = 40: Configuration options with PHY trim options
bD4Length > 40: User must provide valid string descriptors
bD4Length > 192: Error
0xB4 Custom Vendor ID - LSB
0x04 Custom Vendor ID - MSB
0x04 Custom Product ID (PID)
0x65 Default: 0x6504
If separate PID is used for USB 2.0, the USB 2.0 PID will be read
from offset 35 and 36.
Else, USB 2.0 PID = PID+2; Default: 0x6506
Page 26 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Table 7. EEPROM Map (continued)
I2C Offset Bits
9
7:0 DID [7:0]
10
11
12
Name
7:0 DID [15:8]
7:0 Reserved
7:4 SHARED_LINK_EN
Default
00 88-pin
QFN,
10 68-pin
QFN
50
0
b’0000
3:0 SHC_ACTIVE_PORTS [3:0]
b’1111
13
7:0 POWER_ON_TIME
14
7:4 REMOVABLE_PORTS [3:0]
b’1111
3:0 UHC_ACTIVE_PORTS [3:0]
b’1111
15
0x32
7
SS_LED_PIN_CONTROL
0
6
GREEN_LED_PIN_CONTROL
0
5
AMBER_LED_PIN_CONTROL
0
4
PORT_INDICATORS
1
3
COMPOUND_HUB
0
2:1 Reserved
0 GANG
Document Number: 001-73643 Rev. *O
0
0
Description
Custom Device ID - revision - LSB
Custom Device ID - revision - MSB
Reserved
Enable Shared Link on DS port
bit[7:4]=DS4, DS3, DS2, DS1
0: Shared Link not enabled
1: Shared Link enabled
Indicates if a SuperSpeed port is active.
bit[3:0] = DS4, DS3, DS2, DS1
0: Not active
1: Active
Time (in 2-ms intervals) from the time the power-on sequence
begins on a port until power is good on that port
(bPwron2PwrGood)
Indicates if the port is removable.
bit[7:4]=DS4, DS3, DS2, DS1
0: Non-removable
1: Removable
Indicates if a USB 2.0 port is active.
bit[3:0]=DS4, DS3, DS2, DS1
0: Not active
1: Active
Port 1–4: SS LED disable
0: DS[1:4]_LED_SS are LEDs. The LED glows when the SS port
is active and not in disabled state.
1: DS[1:4]_LED_SS are not LEDs
Port 1–4: USB 2.0 Green LED disable
0: DS[1:4]_GREEN are LEDs
1: DS[1:4]_GREEN are not LEDs
Port 1–4: USB 2.0 Amber LED disable
0: DS[1:4]_AMBER are LEDs
1: DS[1:4]_AMBER are not LEDs
Port indicators supported
0: Port indicators are not supported on its DS-facing ports and
the USB 2.0 PORT_INDICATOR request has no effect.
1: Port indicators are supported on its DS-facing ports and the
USB 2.0 PORT_INDICATOR request controls the indicators.
Identifies a compound device.
0: Hub is not part of a compound device.
1: Hub is part of a compound device.
Reserved
1: Ganged power switch enable for all DS ports
0: Individual port power switch enable for each DS port
Page 27 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Table 7. EEPROM Map (continued)
I2C Offset Bits
Name
16
7 SUSPEND_INDICATOR_DISABLE
6
5
4:0
17
7:5
4
3
2
1
0
18
7:4
3:0
19
7
6
5
4
3:0
20
21
22
7:0
7:4
3
2:0
7:0
Default
Description
0
0: Suspend indicator enabled
1: Suspend indicator disabled
SS_US_DISABLE
0
Hub mode of operation (USB 3.0 or USB 2.0)
0: USB 3.0 hub and USB 2.0 hub enabled
1: USB 3.0 hub disabled and USB 2.0 hub enabled
PWR_EN_POLARITY
0
Power switch control output polarity
0: Active LOW
1: Active HIGH
PORT_POLARITY
b’00000 USB 2.0 DP and DM swapped
bit[4:0]=DS4, DS3, DS2, DS1, US
1: Port polarity swapped
0: Port polarity not swapped
Reserved
0
Reserved
BC_ENABLE
1
0: BC v1.2 disabled
1: BC v1.2 enabled
ACA_DOCK
0
If this bit is set, enable ACA-Dock on the US port
APPLE_XA
0
0: Max limit for Apple charging 2.1 A
1: Max limit for Apple charging 1 A
Reserved
0
Reserved
GHOST_CHARGE_EN
1
0: Ghost Charging disabled
1: Ghost Charging enabled
CDP_EN[3:0]
b’1111 Per-port charging setting
bit[7:4]=DS4, DS3, DS2, DS1
0: CDP disabled
1: CDP enabled
DCP_EN[3:0]
b’0000 Per-port charging setting
bit[3:0]=DS4, DS3, DS2, DS1
0: DCP disabled
1: DCP enabled
EMBEDDED_HUB
0
If this bit is set, the US is as an embedded port and VBUS
connected to VBUS_US pin is ignored.
ILLEGAL_DESCRIPTOR
1
If this bit is set, the USB 2.0 hub controller will accept both 0x00
and 0x29 as valid descriptor types. If '0', only 0x29 will be
accepted as a valid descriptor type.
Reserved
1
Reserved
OC_POLARITY
0
Overcurrent input polarity
0: Active LOW
1: Active HIGH
OC_TIMER
b’1000 Time in milliseconds for which the overcurrent inputs will be
filtered
Reserved
0
Reserved
Reserved
0
Reserved
STRING_DESCRIPTOR_ENABLE[16]
0
0: String descriptor support is disabled
1: String descriptor support is enabled
When string descriptors are not supported, the hub controller
returns a non-zero index (compile-time programmable) for each
string which is supported, and 0x00 for each string not
supported, as indicated by this field.
Reserved
0
Reserved
Reserved
0
Reserved
Note
16. When the string descriptor supports LangID, Manufacturer, Product and Serial Number, the serial number must be unique for each device.
Document Number: 001-73643 Rev. *O
Page 28 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Table 7. EEPROM Map (continued)
I2C Offset Bits
Name
23
7:6 HS_AMPLITUDE_DS4
5:4 HS_AMPLITUDE_DS3
3:2 HS_AMPLITUDE_DS2
1:0 HS_AMPLITUDE_DS2
24
7:6 HS_AMPLITUDE_US
5:2 HS_SLOPE
1:0 HS_TX_VREF
25
7:3 HS_PREEMP_EN[4:0]
26
2
1
0
7
6
5
4:1
HS_PREEMP_DEPTH_DS4[17]
HS_PREEMP_DEPTH_DS3[17]
HS_PREEMP_DEPTH_DS2[17]
HS_PREEMP_DEPTH_DS1[17]
HS_PREEMP_DEPTH_US[17]
Reserved
PCS_TX_DEEMPH_DS4
0
7:4
3:0
7:4
3:0
7
6
5:0
Reserved
PCS_TX_DEEMPH_DS3
PCS_TX_DEEMPH_DS2
PCS_TX_DEEMPH_DS1
PCS_TX_DEEMPH_US
Reserved
Reserved
PCS_TX_SWING_FULL_DS4
27
28
29
30
7:6 Reserved
5:0 PCS_TX_SWING_FULL_DS3
Default
b’00
b’00
b’00
b’00
b’00
b'0100
Description
HS driver amplitude control; HS driver current: +0% to +7.5%
b’00: Default
b’01: +2.5%
b’10: +5%
b’11: +7.5%
HS driver slope control for all ports
b’0000: +15%
b’0001: +5%
b’0100: Default
b’0101: -5%
b’1111: -7.5%
b’10
Reference voltage for HS squelch (transmission envelope
detector) for all ports
b’00: 96 mV
b’01: 108 mV
b’10: 120 mV
b’11: 132 mV
b’00000 HS driver pre-emphasis enable – for ports DS4, DS3, DS2, DS1,
and US
0: pre-emphasis is disabled
1: pre-emphasis is enabled
0
HS driver pre-emphasis depth
0: +10%
0
1: +20%
0
0
0
1
Reserved
0x6
USB 3.0 Tx driver de-emphasis value
0x3: -2.75 dB
0x6: -3.4 dB (Default)
0x9: -4.0 dB
0
Reserved
0x6
USB 3.0 Tx driver de-emphasis value
0x3: -2.75 dB
0x6
0x6: -3.4 dB (Default)
0x6
0x9: -4.0 dB
0x6
0
Reserved
1
Reserved
0x29 Adjust launch amplitude of the transmitter
0x1F – 0.9 V
0x29 – 1.0 V (Default)
0x35 – 1.1 V
0x3F – 1.2 V
0
Reserved
0x29 Adjust launch amplitude of the transmitter
0x1F – 0.9 V
0x29 – 1.0 V (Default)
0x35 – 1.1 V
0x3F – 1.2 V
Note
17. HS_PREEMP_DEPTH is valid only when corresponding HS_PREEMP_EN is set for that port.
Document Number: 001-73643 Rev. *O
Page 29 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Table 7. EEPROM Map (continued)
I2C Offset Bits
Name
31
7:6 Reserved
5:0 PCS_TX_SWING_FULL_DS2
32
7:6 Reserved
5:0 PCS_TX_SWING_FULL_DS1
33
7:6 Reserved
5:0 PCS_TX_SWING_FULL_US
34
35
36
37–44
45
46
47
48
49
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
Reserved
UHC_PID [7:0]_LSB
UHC_PID [15:8]_MSB
Reserved
bLength: LangID
DescType
LangID - MSB
LangID - LSB
bLength: Manufacturer (X)
50
51
7:0 DescType
7:0 bString: Manufacturer
49 + X
7:0 bLength: Product (Y)
50 + X
7:0 DescType
Document Number: 001-73643 Rev. *O
Default
Description
0
Reserved
0x29 Adjust launch amplitude of the transmitter
0x1F – 0.9 V
0x29 – 1.0 V (Default)
0x35 – 1.1 V
0x3F – 1.2 V
0
Reserved
0x29 Adjust launch amplitude of the transmitter
0x1F – 0.9 V
0x29 – 1.0 V (Default)
0x35 – 1.1 V
0x3F – 1.2 V
0
Reserved
0x29 Adjust launch amplitude of the transmitter
0x1F – 0.9 V
0x29 – 1.0 V (Default)
0x35 – 1.1 V
0x3F – 1.2 V
0
Reserved
0x06 USB 2.0 PID. If bD4Length  40, USB 2.0 PID will be read from
0x65 this location.
0
Eight bytes reserved for future expansion
4
Size of LangID (defined by spec as N+2)
3
String descriptor type (constant value)
9
String language ID - MSB of wLangID
4
String language ID - MSB of wLangID
54
Manufacturer string length (“bLength: LangID + bLength:
Manufacturer + bLength: Product + bLength: Serial Number”
should be less than or equal to 152 bytes). X ≤ 66.
3
String descriptor type (constant value)
‘2’, 0, ‘0’, Manufacturer string: UNICODE UTF-16LE per USB 2.0 specifi0, ‘1’, 0, cation: “2014 Cypress Semiconductor”
‘4’, 0, ‘ ‘,
0, ‘C’, 0,
‘y’, 0, ‘p’,
0, ‘r’, 0,
‘e’, 0, ‘s’,
0, ‘s’, 0,
‘ ‘, 0, ‘S’,
0, ‘e’, 0,
‘m’, 0, ‘i’,
0, ‘c’, 0,
‘o’, 0, ‘n’,
0, ‘d’, 0,
‘u’, 0, ‘c’,
0, ‘t’, 0,
‘o’, 0, ‘r’,
0
22
Product string length (“bLength: LangID + bLength: Manufacturer + bLength: Product + bLength: Serial Number” should be
less than or equal to 152 bytes). Y ≤ 66.
3
String descriptor type (constant value)
Page 30 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Table 7. EEPROM Map (continued)
I2C Offset Bits
Name
51 + X
7:0 bString: Product
49 + X + Y 7:0 bLength: Serial Number (Z)
50 + X + Y 7:0 DescType
51 + X + Y 7:0 bString: Serial Number
Default
Description
‘C’, 0, Product string: UNICODE UTF-16LE per USB 2.0 specification:
‘Y’, 0, ‘-’, “CY-HX3 HUB”
0, ‘H’, 0,
‘X’, 0, ‘3’,
0, ‘ ‘, 0,
‘H’, 0,
‘U’, 0,
‘B’, 0
22
Serial number string length (“bLength: LangID + bLength:
Manufacturer + bLength: Product + bLength: Serial Number”
should be less than or equal to 152 bytes). Z ≤ 66.
3
String descriptor type (constant value)
‘1’, 0, ‘2’, Serial number string: UNICODE UTF-16LE per USB 2.0 speci0, ‘3’, 0, fication: “123456789A”
‘4’, 0, ‘5’,
0, ‘6’, 0,
‘7’, 0, ‘8’,
0, ‘9’, 0,
‘A’, 0
EMI
ESD
HX3 meets the EMI requirements outlined by FCC 15B (USA)
and EN55022 (Europe) for consumer electronics. HX3 tolerates
EMI conducted by aggressors outlined by the above specifications and continues to function as expected.
HX3 has a built-in ESD protection on all pins. The ESD protection
level provided on these ports is 2.2 kV Human Body Model
(HBM) based on the JESD22-A114 specification.
Document Number: 001-73643 Rev. *O
Page 31 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Electrostatic discharge voltage ................................. 2200 V
Storage temperature................................... –65 °C to +150 °C
I/O voltage supply ...............................................3 V to 3.6 V
Operating temperature .............................. –40 °C to +85 °C
Oscillator or crystal frequency ................. 26 MHz ±150 ppm
Maximum input sink current per I/O .............................. 4 mA
Electrical Specifications
HX3 meets all USB-IF Electrical Compliance specifications.
DC Electrical Characteristics
Table 8. DC Electrical Characteristics
Parameter
DVDD12
Description
1.2 V core supply
VDD_EFUSE
eFuse supply
AVDD12
VDD_IO
AVDD33
VIH
VIL
VOH
VOL
IOS
1.2 V analog supply
3.3 V I/O supply
3.3 V analog supply
Input HIGH voltage
Input LOW voltage
Output HIGH voltage
Output LOW voltage
Input sink current
IIX
Input leakage current
IOZ
ICC
Output HI-Z leakage current
1.2 V supplies combined
operating current
3.3 V supplies combined
operating current
VRAMP
Voltage ramp rate on core and I/O
Voltage ramp must be monotonic
supplies
ICC
VN
VN_USB
Noise level permitted on core and
I/O supplies
Noise level permitted on AVDD12
and AVDD33 supply
Document Number: 001-73643 Rev. *O
Conditions
Min
–
1.14
Normal operation
1.14
Programming
2.5
–
1.14
–
3
–
3
–
0.7 × VDD_IO
–
0
Output HIGH voltage at IOH  +4 mA
2.4
Output LOW voltage at IOL –4 mA
–
LED GPIO usage
–
All I/O signals held at VDD_IO or
GND
–
Typ
1.2
1.2
2.6
1.2
3.3
3.3
–
–
–
–
–
Max
Units
1.26
V
1.26
V
2.7
V
1.26
V
3.6
V
3.6
V
VDD_IO
V
0.3 × VDD_IO V
–
V
0.4
V
4
mA
–1
–
1
µA
–
–
10
µA
–
–
410
526
mA
–
–
260
286
mA
0.2
–
50
V/ms
–
–
100
mV
–
–
20
mV
Max p-p noise level permitted on all
supplies except AVDD
Max p-p noise level permitted USB
supply
Page 32 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Power Consumption
Table 9 provides the power consumption estimates for HX3 under different conditions. Table 10 summarizes the power consumption
for various combinations of devices connected to DS ports.
For example, to calculate the HX3 power consumption for three SS devices connected to DS ports (and no device connected to one
DS port), and a US port connected to a USB 3.0 host:
Power consumption = [a] + 2*[g] = 492.5 + 2*76 = 644 mW
[a] is the active power consumption for the US port connected to a USB 3.0 host and the SS device connected to the DS port.
[g] is the incremental power consumption for an additional SS device connected to the DS port.
Table 9. Power Consumption Estimates for Various Usage Scenarios
Typical Consumption
Number and Speed of
DS Ports Connected
Device Condition
Supply Current (mA)
Power (mW)
Comments
1.2 V
3.3 V
NA
12.0
7.1
37.8
1 SS
204.1
75.0
492.5
[a]
1 HS
Active power with USB 3.0 host [19]
1 FS
51.2
45.2
210.7
[b]
Suspend [18]
51.2
34.0
173.7
[c]
218.0
103.4
602.9
[d]
51.2
45.2
210.7
[e]
51.2
34.0
173.7
[f]
SS
39.4
8.7
76.0
[g]
HS
7.0
19.8
73.7
[h]
FS
7.0
14.2
55.2
[i]
10.6
9.6
44.4
[j]
1 SS + 1 HS
Active power with USB 2.0 host [19, 1 HS
20]
1 FS
Incremental active power for
additional DS port
–
Active power saving per disabled DS
port[21]
–
Table 10. Power Consumption Under Various Configurations
Configuration
Number of DS Devices
Connected With Data
Transfer
Typical Consumption
Supply Current (mA)
Comments
Power (mW)
1.2 V
3.3 V
322
101
720
[a] + 3*[g]
297
121
755
[d] + 2*[g]
283
92
644
[a] + 2*[g]
USB 3.0
4-Port Hub
(USB 3.0 host)
4 SS devices
3 SS + 1 HS devices
3 SS devices
USB 3.0
4-Port Hub with one port disabled
(USB 3.0 host)
Shared Link with eight DS ports
USB 2.0
4-Port Hub
(USB 2.0 host)
3 SS devices
272
83
600
[a] + 2*[g] - [j]
2 SS + 1 HS devices
247
103
634
[d] + [g] - [j]
4 SS + 4 HS devices
4 HS devices
357
72
189
105
1052
432
[d] + 3*([g] + [h])
[e] + 3*[h]
3 HS + 1 FS devices
72
99
413
[e] + 2*[h] + [i]
Notes
18. US port in low-power state (SS in U3 and USB 2.0 in L2).
19. All four DS ports are enabled.
20. US SS disabled using configuration options. Refer to Table 7 on page 26 for I2C configuration options.
21. Power saving applicable only with a USB 3.0 host. DS ports can be disabled through configuration options. Refer to Table 6 on page 25 for pin-strapping and
Table 7 on page 26 for I2C configuration options.
Document Number: 001-73643 Rev. *O
Page 33 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Ordering Information
Table 11 lists HX3’s ordering information. The table contains only the part numbers that are currently available for order. Additional
part numbers for industrial temperature range can be made available on request. For more information, visit the Cypress website or
contact the local sales representative.
Table 11. Ordering Information
Ordering
Part Number
Number of
DS Ports
Number of
Shared Link
Ports
Ghost
Charge
ACADock
Temperature
Package
1.
CYUSB3302-68LTXC
2 (USB 3.0)
0
Yes
No
0-70 °C
68-QFN
2.
CYUSB3302-68LTXI
2 (USB 3.0)
0
Yes
No
–40-85 °C
68-QFN
3.
CYUSB3304-68LTXC
4 (USB 3.0)
0
Yes
No
0-70 °C
68-QFN
4.
CYUSB3304-68LTXI
4 (USB 3.0)
0
Yes
No
–40-85 °C
68-QFN
5.
CYUSB3312-88LTXC
2 (USB 3.0)
0
Yes
No
0-70 °C
88-QFN
6.
CYUSB3312-88LTXI
2 (USB 3.0)
0
Yes
No
–40-85 °C
88-QFN
7.
CYUSB3314-88LTXC
4 (USB 3.0)
0
Yes
No
0-70 °C
88-QFN
8.
CYUSB3314-88LTXI
4 (USB 3.0)
0
Yes
No
–40-85 °C
88-QFN
9.
CYUSB3324-88LTXC
4 (USB 3.0)
0
Yes
Yes
0-70 °C
88-QFN
10.
CYUSB3324-88LTXI
4 (USB 3.0)
0
Yes
Yes
–40-85 °C
88-QFN
11.
CYUSB3326-88LTXC
6 (2 USB 3.0, 2 SS, 2 USB 2.0)
2
Yes
No
0-70 °C
88-QFN
12.
CYUSB3326-88LTXI
6 (2 USB 3.0, 2 SS, 2 USB 2.0)
2
Yes
No
–40-85 °C
88-QFN
13.
CYUSB3328-88LTXC
8 (4 SS, 4 USB 2.0)
4
Yes
Yes
0-70 °C
88-QFN
14.
CYUSB3328-88LTXI
8 (4 SS, 4 USB 2.0)
4
Yes
Yes
–40-85 °C
88-QFN
15.
CYUSB3302-BVXC
2 (USB 3.0)
0
Yes
No
0-70 °C
100-BGA
16.
CYUSB3302-BVXI
2 (USB 3.0)
0
Yes
No
–40-85 °C
100-BGA
17.
CYUSB3304-BVXC
4 (USB 3.0)
0
Yes
No
0-70 °C
100-BGA
18.
CYUSB3304-BVXI
4 (USB 3.0)
0
Yes
No
–40-85 °C
100-BGA
19.
CYUSB3312-BVXC
2 (USB 3.0)
0
Yes
No
0-70 °C
100-BGA
20.
CYUSB3312-BVXI
2 (USB 3.0)
0
Yes
No
–40-85 °C
100-BGA
21.
CYUSB3314-BVXC
4 (USB 3.0)
0
Yes
No
0-70 °C
100-BGA
22.
CYUSB3314-BVXI
4 (USB 3.0)
0
Yes
No
–40-85 °C
100-BGA
23.
CYUSB3324-BVXC
4 (USB 3.0)
0
Yes
Yes
0-70 °C
100-BGA
24.
CYUSB3324-BVXI
4 (USB 3.0)
0
Yes
Yes
–40-85 °C
100-BGA
25.
CYUSB3326-BVXC
6 (2 USB 3.0, 2 SS, 2 USB 2.0)
2
Yes
No
0-70 °C
100-BGA
26.
CYUSB3326-BVXI
6 (2 USB 3.0, 2 SS, 2 USB 2.0)
2
Yes
No
–40-85 °C
100-BGA
27.
CYUSB3328-BVXC
8 (4 SS, 4 USB 2.0)
4
Yes
Yes
0-70 °C
100-BGA
28.
CYUSB2302-68LTXI
2 (USB 2.0)
0
Yes
No
–40-85 °C
68-QFN
29.
CYUSB2304-68LTXI
4 (USB 2.0)
0
Yes
No
–40-85 °C
68-QFN
Serial
No.
Document Number: 001-73643 Rev. *O
Page 34 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Ordering Code Definitions
CY USB X
3
X
X -XXXX X
X
Temperature Range: C= Commercial; I= Industrial
Pb-free
Package Type: 68LT = 68-pin QFN
88LT = 88-pin QFN
BV = 100-ball BGA
Number of Ports
Feature list: 0 = Basic, 1 = Intermediate, 2 = Advanced
Hub Family
USB speed: 3=USB 3.0; 2= USB 2.0
Marketing Code: USB
Company ID: CY = Cypress
Document Number: 001-73643 Rev. *O
Page 35 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Packaging
Table 12. Package Characteristics
Parameter
Description
Min
Typ
Max
Units
TA
Operating ambient temperature
–40
–
85
°C
TJ
Operating junction temperature
–40
–
125
°C
TJA
Package JA (68-pin QFN)
–
16.2
–
°C/W
TJA
Package JA (88-pin QFN)
–
15.7
–
°C/W
TJA
Package JA (100-ball BGA)
–
35
–
°C/W
TJC
Package JC (68-pin QFN)
–
23.8
–
°C/W
TJC
Package JC (88-pin QFN)
–
18.9
–
°C/W
TJC
Package JC (100-ball BGA)
–
12
–
°C/W
Table 13. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Maximum Time at Peak Temperature
68-pin QFN
260 °C
30 seconds
88-pin QFN
260 °C
30 seconds
100-ball BGA
260 °C
30 seconds
Table 14. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
68-pin QFN
MSL 3
88-pin QFN
MSL 3
100-ball BGA
MSL 3
Document Number: 001-73643 Rev. *O
Page 36 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Package Diagrams
Figure 18. 68-pin QFN (8 × 8 × 1.0 mm) LT68B 5.1 × 5.1 mm EPAD (Sawn) Package Outline
NOTES:
1.
HATCH AREA IS SOLDERABLE EXPOSED PAD
2. REFERENCE JEDEC#: MO-220
001-78925 *B
3. ALL DIMENSIONS ARE IN MILLIMETERS
Figure 19. 88-pin QFN (10 × 10 × 1.0 mm) LT88B 5.3 × 5.3 EPAD (Sawn) Package Outline
001-76569 *B
Document Number: 001-73643 Rev. *O
Page 37 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Figure 20. 100-Ball BGA (6.0 × 6.0 × 1.0 mm) BZ100 Package Outline
51-85209 *E
Document Number: 001-73643 Rev. *O
Page 38 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Acronyms
Reference Documents
Table 15. Acronyms Used in this Document
USB 2.0 Specification
Acronym
Description
USB 3.0 Specification
ACA
Accessory Charging Adapter
Battery Charging Specification
ASSP
Application-Specific Standard Product
Document Conventions
BC
Battery Charging
CDP
Charging Downstream Port
DS
DownStream
DCP
Dedicated Charging Port
DNU
Do Not Use
DWG
Device Working Group
EEPROM
Electrically Erasable Programmable Read-Only
Memory
Units of Measure
Table 16. Units of Measure
Symbol
Unit of Measure
°C
degree celsius

ohm
Gbps
gigabit per second
KB
kilobyte
kilohertz
FS
Full-Speed
kHz
FW
FirmWare
k
kiloohm
GND
GrouND
Mbps
megabit per second
GPIO
General-Purpose Input/Output
MHz
megahertz
HS
Hi-Speed
µA
microampere
ISP
In-System Programming
mA
milliampere
I/O
Input/Output
ms
millisecond
LS
Low-Speed
mW
milliwatt
NC
No Connect
ns
nanosecond
OTG
On-The-Go
ppm
parts per million
PID
Product ID
V
volt
POR
Power-On Reset
ROM
Read-Only Memory
SCL
Serial CLock
SDA
Serial DAta
SS
SuperSpeed
TT
Transaction Translator
US
UpStream
VID
Vendor ID
Document Number: 001-73643 Rev. *O
Page 39 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Silicon Revision History
This datasheet is applicable for the USB-IF certified (TID# 330000060) HX3 Rev. *D and Rev. *C Silicon.
Rev. *D: This Silicon revision improves the yield of HX3, and is drop-in compatible for all the part numbers. There is no need to change
the board design or layout to use the HX3 Rev. *D Silicon. Products are completely compatible with the HX3 Rev. *C Silicon.
Rev. *C: This Silicon revision fixes the errata applicable to the Rev. *A Silicon.
The following table defines the changes between Rev. *A, Rev. *C, and Rev. *D Silicon.
No.
Items
Part Numbers
Rev. *A
Rev. *C
Rev. *D
1
USB-IF Compliance
All
Requires firmware on
external EEPROM
No external EEPROM
required
No external EEPROM
required
2
FS-only hub or host connected to
HX3 Upstream Port
All
Not supported
Supported
Supported
3
Suspend Power
All
90 mW
37.8 mW
37.8 mW
Method of Identification
Markings on row 3 of the HX3 package differentiate Rev. *D Silicon from Rev. *C Silicon and Rev. *A Silicon as indicated in the
example below. Cypress maintains traceability of product to wafer level, including wafer fabrication location, through the lot number
marked on the package.
HX3 REV *A SILICON
Document Number: 001-73643 Rev. *O
HX3 REV *C SILICON
HX3 REV *D SILICON
Page 40 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Document History
Document Title: CYUSB330x, CYUSB331x, CYUSB332x, CYUSB230x HX3 USB 3.0 Hub
Document Number: 001-73643
Revision
ECN
Orig. of
Change
Submission
Date
*E
4271496
MURT
02/21/2014
Updated all sections of the datasheet
Updated datasheet for new part numbers
*F
4291210
MURT
02/25/2014
Post to web.
*G
4308926
MURT
03/14/2014
Updated Table 7.
Description of Change
4463533
MURT
08/01/2014
Updated Features:
Updated TID#.
Updated Electrical Specifications:
Updated Power Consumption:
Updated Table 9:
Updated details corresponding to suspend power.
Removed Errata.
*I
4483117
RAJM
08/22/2014
Added Silicon Revision History.
*J
4499514
RAJM
09/15/2014
Added BGA package information.
11/28/2014
Updated HX3 Product Options:
Updated Table 1.
Updated Pin Information:
Updated Table 4.
*H
*K
4582512
PRJI
*L
4632890
HBM
01/20/2015
Updated Pin Information:
Updated Figure 12.
Updated Figure 13.
Updated Table 4.
Added Packaging.
Updated Package Diagrams:
spec 51-85209 – Changed revision from *D to *E.
*M
4669639
HBM
02/24/2015
No content update.
*N
4764583
HBM
05/13/2015
Updated Figure 19 (spec 001-76569 *A to *B) in Package Diagrams.
Updated Silicon Revision History and Method of Identification.
*O
4941772
HBM
11/25/2015
Updated Table 1 and Table 11 with the new part numbers CYUSB2302-68LTXI and CYUSB2304-68LTXI.
Document Number: 001-73643 Rev. *O
Page 41 of 42
CYUSB330x, CYUSB331x
CYUSB332x, CYUSB230x
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
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cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/memory
cypress.com/go/psoc
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psoc.cypress.com/solutions
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Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2011-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-73643 Rev. *O
Revised November 25, 2015
Page 42 of 42
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