AN203277 FM 32-bit Microcontroller Family Hardware Design Considerations.pdf

AN203277
FM 32-bit Microcontroller Family Hardware Design Considerations
Author: James Williams
Associated Project: No
Associated Part Family: All FM0+, FM3 and FM4 parts
Software Version: None
Related Application Notes: For a complete list, click here.
To get the latest version of this application note, please visit:
http://www.cypress.com/AN203277.
AN203277 reviews several topics for designing a hardware system around FM0+, FM3, and FM4 family MCUs.
Subjects include power system, reset, crystal, and other pin connections, and programming and debugging
interfaces.
Contents
FM 32-bit Microcontroller Family Hardware Design
Considerations ..................................................................1
Contents ............................................................................1
Introduction .......................................................................2
Package Selection.............................................................2
Power System ...................................................................4
Digital Power Connections ...........................................4
Analog Power Consumption Considerations ................7
Analog Noise Consideration .........................................8
Analog Inputs and Related External Circuits ................9
Analog Input Leakage Current Consideration............. 10
Total Chip Power Considerations ............................... 11
Thermal Considerations ............................................. 13
Power Ramp-up Considerations................................. 13
GPIO and Non-Power Pins ............................................. 14
C Pin Decoupling........................................................ 15
Quartz Crystal Placement and Signal Routing ........... 16
Device Reset .............................................................. 17
I/O Pins and Device Reset ......................................... 17
Port Input / Unused Pins / Latch-up................................. 18
www.cypress.com
EMC, ESD Protection, Latch-up Consideration ............... 19
Programming and Debug ................................................ 23
JTAG/SWD Connections ............................................ 24
Traceport Connections ............................................... 25
Minimum System............................................................. 26
Schematic (Serial Programming) ............................... 26
Serial Interface ........................................................... 26
Schematic (USB Programming) ................................. 27
USB Interface .................................................................. 28
Summary ......................................................................... 28
Related Documents......................................................... 28
About the Author ............................................................. 28
Appendix A – PCB Layout Tips and I/O Pin Selection .... 29
Appendix B – Schematic Checklist.................................. 31
Document History............................................................ 32
Worldwide Sales and Design Support ............................. 33
Products .......................................................................... 33
®
PSoC Solutions ............................................................. 33
Cypress Developer Community....................................... 33
Document No. 002-03277 Rev. **
1
FM 32-bit Microcontroller Family Hardware Design Considerations
Introduction
The FM0+, FM3, and FM4 families of MCUs provide power and flexibility for complex applications, beyond what traditional
MCUs offer. However, this power and flexibility raises new considerations when designing an FM device into a printed circuit
board (PCB) design.
These considerations include proper connections for device power, reset, crystal, programming, and other pins.
Good board layout techniques are also important, especially for precision analog applications.
This application note provides information on each of these topics so that you can successfully design FM devices into your
PCB and hardware environment.
This application note is for hardware design engineers and PCB layout engineers who have some previous experience with
32-bit MCU circuit board design, but may not have direct knowledge of the FM family design requirements.
It is assumed that the reader has a basic understanding of PCB layout tools and how to use them to implement the design
suggestions given here.
This document does not go into specific PCB design tools or how tool design rules are configured.
Package Selection
One of the first decisions you must make for your design is which package to use. Several considerations drive this decision,
including number of I/O pins required, PCB and product size, PCB design rules, and thermal and mechanical stresses.
The FM device families have a very large selection of devices to help match your exact needs in any situation with an efficient
and cost-effective solution. Packaging solutions range from the ultra-small Wafer Scale Packages to high pin count Ball Grid
Array packages. Easier to layout on lower layer counts and lower cost PCBs are the Leaded Quad Flat Pack (LQFP). LQFP
packaging options range from 48 pin devices to 216 pin devices.
Following are some package selection criteria:
LQFP



Easier to route signals due to large pitch and the open area below the part
Less mechanical rigidity for more protection against vibration and mechanical stress
Disadvantages are larger package and lower thermal conduction (θJA).
48-QFN and 64-QFN



QFN packages are smaller
Better thermal conduction due to center thermal pad
Disadvantages are:


More difficult to route signals due to the center pad
Possibility of mechanical stress on the device inducing electrical / mechanical performance changes. Center pad
solder paste and solder mask must be designed taking these factors into account.
For more information, see AN72845, Design Guidelines for QFN Packaged Devices.
www.cypress.com
Document No. 002-03277 Rev. **
2
FM 32-bit Microcontroller Family Hardware Design Considerations
BGA and PBGA

Small-scale packages offering high pin counts in larger lead pitches, which significantly reduce the manufacturing
complexities for high I/O devices. BGA packages are used in applications requiring:



Faster circuitry speed because the terminations are much shorter and therefore less inductive and resistive

Robust reflow processing, due to higher pitch (1.27 mm , 0.050”, typical), better lead rigidity, and self-alignment
characteristics. Self-alignment during reflow is very beneficial and opens the process window considerably.

Disadvantage: X-ray needed for solder joint inspection
Better heat dissipation
Conventional surface mount technology (SMT) production technologies such as stencil printing and component mounting
can be used
CSP and WLCSP

Are true die-scale packages and offer the smallest footprint for each I/O pin count of any standard package. They are
used in applications with:



Very small PCB size
Flexible printed circuits (FPC)
However, the manufacturing process is more complex and requires specialized knowledge. For more information see:


AN69061, Design, Manufacturing, and Handling Guidelines for Cypress Wafer Level Chip Scale Packages.
AN89611, PSoC 3 and PSoC 5LP Getting Started with Chip Scale Packages
www.cypress.com
Document No. 002-03277 Rev. **
3
FM 32-bit Microcontroller Family Hardware Design Considerations
Power System
The FM power system is based on separate supplies and returns for analog, digital, backup, USB, and Ethernet, as Table 1
shows.
Table 1. Power Domains
Power
Domain
Associated Power and Return Pins
Analog
AVCC, AVRH, AVRL, AVSS
Digital
VCC , VSS
Backup Battery
VBAT, VSS
USB
USBVCC, VSS
Ethernet
ETHVCC, VSS
Digital Power Connections
The power supply must be from 2.7 V to 5.5 V for normal usage, depending on the selected FM series. Refer to the datasheet
for maximum and minimum power supply voltages. For USB functionality, provide 3.3 V to USBVCC.
If the USB data pins (USDMn, USDPn) are used only as digital I/O ports. USBVCC must be connected to VCC, Failure to
connect USBVCC to VCC causes the GPIO function of the USB pins to operate incorrectly.
Note that if VCC is routed to several pins; these pins must be connected together on the PCB. The PCB trace between the VCC
pins should be as short as possible; ideally, it should be run underneath the device directly between the pins. For QFN
packages with center pads, the trace can be run through vias to another PCB layer. Figure 1 shows this.
Figure 1. PCB Trace Between VCC Pins
Cypress FM MCU and PSoC development kit schematics and board Gerber files provide good examples of how to incorporate
FM MCUs into board schematics. For more information, see Related Documents.
To reduce power supply noise throughout the device, each VCC pin should be connected to a ceramic decoupling capacitor.
The PCB trace between the pin and the capacitor should be as short and wide as possible – for more information see
Appendix A. One or more 10 μF bulk decoupling capacitors should also be placed on each board assembly.
Note It is good practice to check the datasheets for your bypass capacitors, specifically the working voltage and the DC bias
specifications. With some capacitors, the actual capacitance can decrease considerably when the DC bias is a significant
percentage of the rated working voltage.
www.cypress.com
Document No. 002-03277 Rev. **
4
FM 32-bit Microcontroller Family Hardware Design Considerations
Decoupling capacitors (DeCaps) for power supply must be placed within the “current flow”. Otherwise inductance and resistive
effects negate having the capacitors. Figure 2 shows this.
Figure 2. Examples of DeCap Placement
If possible, all decoupling capacitors should be placed on the same mounting side as the MCU. Cypress recommends 10 nF
(~100 MHz resonance) to 100 nF (~10 MHz resonance) depending on the application.
Figure 3 shows the recommended routing and placement for single-sided metal layer. (Note, that in all following illustrations
the mounting metal layer is drawn in black and the back side metal layer in gray).
Figure 3. Routing and Placement for Single-Sided Metal Layer
www.cypress.com
Document No. 002-03277 Rev. **
5
FM 32-bit Microcontroller Family Hardware Design Considerations
Figure 4 shows the recommended routing and placement for double sided metal layers. Note that despite the capacitor being
placed on the opposite side from the MCU, this solution is preferred as the via to the ground plane and the via connectin g to
the VCC pin minimize inductance over other solutions.
Figure 4. Routing and Placement for Double-Sided Metal Layer
Figure 5 shows the recommended placement and routing if mounting on both sides is not possible.
Figure 5. Placement and Routing if Mounting on Only One Side
www.cypress.com
Document No. 002-03277 Rev. **
6
FM 32-bit Microcontroller Family Hardware Design Considerations
Analog Power Connections
The analog system voltage, applied to AVCC relative to AVSS, can be up to 5.5 V (absolute maximum), and must be greater
than or equal to all other applied power voltages. That is, the voltage applied to the other VCC power pins, relative to VSS, must
be ≤ AVCC.
Analog Power Consumption Considerations
The power consumption (IR, IA) of the ADC increases when a conversion is in progress. While the ADC is halted, only leakage
current (IRH, IAH) flows. Figure 6 shows this behavior.
Figure 6. Analog Power Consumption Considerations
ADSR_SCS/ADSR_PCS
Bit Value
1
ADSR_SCS = 1
ADSR_PCS = 1
0
t
Reference Voltage Current
(AVRH, AVRL)
IR
IH
t
Power Supply Current
(AVCC)
IA
t
IAH
Refer to the MCU’s datasheet for the actual currents.
www.cypress.com
Document No. 002-03277 Rev. **
7
FM 32-bit Microcontroller Family Hardware Design Considerations
Analog Noise Consideration
Cypress FM microcontrollers have an embedded 12-bit successive approximation register ADC. Due to the high resolution, the
digital bit stream from the ADC output is sensitive to environment noise. For example, 1 LSB corresponds to only 1.221 mV for
VREF = 5 V. Hence, the noise introduced from external circuits must be considered and should be reduced to the minimum
possible.
The reference voltage VREF, which is equal to AVRH - AVVL, is connected to the weighted capacitor array and the resistor array
of the ADC. The noise coupled to AVRH is not rejected by the ADC. This noise is added to VREF directly, introducing an error
with a ratio of VNoise/VREF. For example, to keep the error caused by this kind of noise below 0.1 LSB, the noise level of VREF
must be kept within 0.122 mV.
To minimize noise error, connect the AVRH and AVRL pins with low impedance routing. In practice often a simple low-pass RC
filter is used for noise reduction. In this case the reference voltage supply current (see datasheet) must be taken into account
when calculating the filter resistor, to minimize the voltage drop while converting. Normally two capacitors in parallel are
recommended: one filtering low frequency noise, the other one filtering high frequency noise ((10 nF – 1 μF) || (10 pF – 100
pF)). In most cases, this configuration suppresses the noise efficiently. If very high frequency noise appears in the
environment, an additional noise filter such as a dedicated π mode RC filter might be useful.
The analog power path AVCC supplies the internal voltage comparator and the analog switches of the ADC, while the VCC path
supplies all the digital parts in the microcontroller. Internal parasitic capacitors may couple noise from AVCC to the internal
voltage comparator of the ADC. AVCC should not be connected directly to VCC - a filter should be used. For more efficient noise
filtering, the same configuration as for AVRH is recommended.
Figure 7. Analog Noise Consideration
www.cypress.com
Document No. 002-03277 Rev. **
8
FM 32-bit Microcontroller Family Hardware Design Considerations
Analog Inputs and Related External Circuits
Figure 8. Analog Inputs and Related External Circuits
To protect the analog pins from suffering from an over-voltage, a “clamping resistor” is usually added to the input pins. The
minimum value of the resistor can be chosen as
Rclamp= Uovervoltage/Iclamp,
Where, Iclamp is the specified maximum clamp current in the data sheet.
For some applications, a large clamp resistor is sometimes unacceptable. As a compromise, external clamping diodes with low
leakage current may be added between the input pin and the AVCC pin and the AVSS pin. These clamping diodes should be
rated to clamp the voltage at currents greater than the internal ESD diodes.
In some cases, the analog input voltage is biased with a voltage supply higher than the maximum allowed voltage for the
microcontroller. For example, in automotive applications, sensors may be biased with the car battery, which exhibits a voltage
of 12 V/24 V. A resistor divider is commonly used to reduce the sensor voltage signal seen on the pin down to a value that is
equal to or smaller than AVCC and VCC.
The ratio between R1 and R2 should satisfy the following constraint:
R1 U Signal
≥
−1
R2 AVCC
Another factor that influences the values of R1, R2, and Rclamp is related to current consumption budget and input signal noise
suppression. The second factor is discussed here in more detail. The signal from the sensors may be noisy. The noise, which
has a time constant smaller than the sampling time Tsampling, is transparent to the ADC, resulting in distorted output. In this
case, an additional dedicated bypass capacitor together with the clamping resistor and resistor divider, works as a low pass
filter. A larger capacitor lowers the AC impedance and is more effective at shunting away the noise signal. Generally, the time
constant of this low pass filter (Rclamp + R1 || R2) x Cnoise should be chosen to be considerably larger than the sampling time (5
to 10 times larger as a rule of thumb).
However, this time constant should be also considerably smaller than the time constant of the analog input signal. Then, the
analog pin is able to follow the dynamic changes of the input voltage, which the ADC is being used to track. These, along with
the values of R1/R2 or Rclamp, must be considered when choosing the capacitor value to avoid rolling off any high frequency
signal components of interest.
www.cypress.com
Document No. 002-03277 Rev. **
9
FM 32-bit Microcontroller Family Hardware Design Considerations
Analog Input Leakage Current Consideration
All analog input pins by design have a small leakage current, whose value ranges from 3 υA to 1 υA, depending on
temperature. The leakage current, which flows through the external resistor, introduces an undesired voltage drop. This error
voltage is a function of the external resistor and the leakage current itself. The following example shows a value of the resistor
with this factor taken into consideration. For the case of using a resistor divider to reduce the error due to leakage current, the
size of R1 || R2 + Rclamp should not be too large and should be according to the following equation:
R1 || R2 + Rclamp ≤
U LSB
I leakage
Note:
ULSB = UREF / 4096
To keep the error smaller than one LSB for a leakage of 3 µA, the size of R1 || R2 + Rclamp should be smaller than 400 Ω. As
the leakage current drops down to 1 µA, the value of R1 || R2 + Rclamp can be chosen as large as 1.2 kΩ. This is considering
VREF of 5 V.
The leakage current consists of two parts: one is due to the leakage current of the input ESD structure. Another leakage
current appears only as the multiplexer is switched on during sampling time; its contribution is usually considerably larger than
the one created from the ESD structure. The second leakage current can be regarded as a noise during the sampling time by
the bypass capacitor, which is commonly used to filter the noise from the sensor input. If this capacitor is large enough, it can
absorb most of the second leakage current during the sampling time, eliminating its contribution to the error voltage.
Figure 9. Sources of Analog Leakage Offset Currents
www.cypress.com
Document No. 002-03277 Rev. **
10
FM 32-bit Microcontroller Family Hardware Design Considerations
Figure 10. Error Voltage in the Sampling Phase
Leakage Current
Ileakage1
+
Ileakage1
Ileakage1
t
Error voltage due to leakage
current without bypass
capacitor
Voltage
Error voltage due to leakage
current with bypass capacitor
t
No active
phase
Sampling
phase
Comparison
phase
To show the effect of the bypass capacitor on reducing the leakage current error, we take a sampling time of 5 µs and a
leakage current of 3 µA as an example. If we want to keep the voltage drop due to the second leakage current smaller than
0.5 LSB, the minimum size of the bypass capacitor should be chosen as:
C=
3µA × 5µs
≈ 6nF
4.99mV / 2
Total Chip Power Considerations
Each IO pin driver has a drive capability based mainly on the functionality assigned to the given port. For most pins/ports this
is a fixed value; for some it is programmable. The maximum value of the drive current is 4 mA, 8 mA, 10 mA, 12 mA, or 20
mA. The current depends on the major function associated with each pin group. See GPIO and Non-Power Pins for more
detail of individual pin currents.
It is important to know that the total combined drive of all pins cannot exceed 100 mA average over a 100 ms period. Peak
currents of up to 200 mA total are permissible as long the duration is less than 100 ms.
www.cypress.com
Document No. 002-03277 Rev. **
11
FM 32-bit Microcontroller Family Hardware Design Considerations
In addition to the power sourced from and sunk into the pins, the operating current of the peripherals internal to the device
must be considered. Many of the high performance FM4 devices with a large number of internal peripherals can consume
more than 250 mA of internal peripheral current. Data for each peripheral is listed in the datasheet. A good estimate of the
total operating current can be calculated from adding these peripheral currents. Figure 11 shows the total power of an MCU
implementation (Pd). It is based on the sum of the currents of all the internal peripherals (from data sheets) ICC (INT) and the
sum of all I/O currents ICC (IO) calculated from circuit design components driven by the I/O pins.
Figure 11. Sources of MCU Total Power.
www.cypress.com
Document No. 002-03277 Rev. **
12
FM 32-bit Microcontroller Family Hardware Design Considerations
Thermal Considerations
Once an indication of the MCU total power requirement is known, it is very important to understand if the system design can
properly dissipate this power into the ambient air efficiently enough to require no further action or if significant heat sinking and
PCB design choices might be required. The Cypress FM family MCUs cover a wide range of products from devices capable of
very low power to MCUs with very fast complex logic requiring higher power needs. Under certain conditions, MCUs may
dissipate more than 1 Watt of power including the core, peripheral, and I/O currents. With a lot of power in a device, you must
consider steps necessary to keep it from overheating. Before a design is finalized, a complete thermal review should be done.
Items such as the amount of airflow through the system, nearby heat sources, and PCB construction should be reviewed. The
examples given below are first steps to determine whether your preliminary design objectives can be met.
For a first order approximation, first check the datasheet for the thermal resistance from junction to ambient (θJA), for the
package that you intend to use. θJA is expressed in units of °C/watt. For example, the θJA for an LQFP 120-pin FM4 is
38°C/watt. For the same device in an LQFP 120-pin package with an exposed pad on the bottom side correctly mounted, the
θJA is reduced to18°C/watt, allowing a much higher total device power usage or a higher ambient operating temperature.
The maximum temperature difference between the device junction and the ambient air surrounding the device is θJA times the
maximum power, or as in the first case above 38°C/watt x 1.0 watt = 38°C. Because the specified maximum operating junction
temperature of the device is 125°C, the maximum allowable ambient air temperature is 125 – 38 = 87°C. If you use the
exposed pad version of package, which has a lower thermal resistance θJA of 18°C/watt if implemented with proper PCB to
pad design, then the maximum allowable ambient air temperature is 125 – 18 = 107°C. This allows a 20°C increase in ambient
operating temperature or the possibility to drive more power from the device I/O or core.
Each datasheet for a device series contains a table showing package thermal resistance and maximum permissible power.
This allows you to quickly see the amount of power that can practically be consumed by a device in a given package. The
table also gives recommended minimal PCB construction. Most FM MCUs can be mounted to simple single or double layer
printed circuited boards. For other devices, the table recommends at least a four layer construction, where the inner plane
layers help dissipate heat.
Note The datasheet specifications for θJA are typical. You should design your product such that the ambient air temperature is
much less than the allowable maximum.
Note With the above calculation, if the θJA or the power dissipated is high, the maximum allowable ambient air temperature
could theoretically approach the 125°C junction temperature limit. However, the product's commercial-range ambient air
temperature limit of 85°C or the industrial-range ambient air temperature limit of 105°C still applies. In the examples above, the
first example would be unacceptable for operating a consumer grade (85°C) device. In the second example, a consumer grade
or industrial grade device would be well suited depending on the choice of operating conditions of the final product.
Many FM MCU devices are offered in PBGA and QFN packages. Due to the small size reducing the available surface area for
thermal conduction, these packages must be thoroughly reviewed for power applications. For more information and examples
of higher order thermal review, see AN72845, Design Guidelines for QFN Packaged Devices.
Power Ramp-up Considerations
Turn power on/off in the sequence shown below or at the same time. If not using the A/D converter and D/A converter, connect
AVCC= VCC and AVSS= VSS.
Turning on:
VBAT → VCC → USBVCC
VBAT →VCC →ETHVCC
VCC → AVCC → AVRH
Turning off:
USBVCC → VCC → VBAT
ETHVCC → VCC → VBAT
AVRH → AVCC → VCC
The voltages at the VCC pins must be less than or equal to that on AVCC.
www.cypress.com
Document No. 002-03277 Rev. **
13
FM 32-bit Microcontroller Family Hardware Design Considerations
When powering up the device, the maximum ramp rate for any VCC pin is 0.1 V/μs.
GPIO and Non-Power Pins
The I/O pins of the FM MCU family are made of I/O pin drivers of different types. The type of pin driver and a reference
schematic of the driver and the current capability of each are all described in the datasheet in “I/O Circuit Type” for a particular
device. These circuit types can then be related to the actual device pins in “Pin Descriptions” in the datasheet.
While almost any pin can be used as a general-purpose I/O, note that the current drive for pins is allocated per the major
peripheral function of the pin. For example, the current drive on the NAND flash interface is 3x greater than the standard I/O
drive. If a system had a very long run CSIO (SPI) link and no need of the NAND interface, you could use the multifunction
serial (MFS) block associated with the pins of the NAND flash interface for the CSIO. See Table 2.
Table 2. Pin Function and Associated Pin Current
Pin Function
Associated Pin Current
GPIO
4 mA
SD Card
8 mA
UART
8 mA
2
Hi Current MFS I C/SPI
8 mA
Remaining MFS modules
4 mA
USB
~20 mA
NAND
12 mA
Ethernet
8 mA
Quad SPI
4 mA / 10 mA selectable.
External Bus Ctln / Clk
8 mA
For more information on all pin types, see the datasheet for your device.
Table 3 shows the remaining MCU critical pins and gives short information about how to connect them.
Table 3. Remaining MCU Critical Pins and their Connections
Pin Name
VCC
VSS
C
AVCC
AVSS
AVVRH
USBVCC
ETHVCC
X0, X0A
X1, X1A
www.cypress.com
Function
Main supply for I/O buffer and MCU core.
Main supply for I/O buffer and MCU core.
External 4uF to 10 µF ceramic capacitor (dielectric X7R) as smoothing capacitor
for internal 1.2 V regulator output, used for supply of the MCU core. Refer to the
datasheet for selection of capacitance value.
Power supply for the A/D converter.
Power supply for the A/D converter.
Reference voltage input for the A/D converter.
Power supply for internal USB host/function. Use voltage according to datasheet
and purpose of supplied pins (USB or GPIO).
Power supply for internal Ethernet MAC. Use voltage according datasheet and
purpose of supplied pins (Ethernet or GPIO).
Oscillator input. If not used, it shall be connected with pull-up or pull-down resistor
or set to digital output (see the datasheet).
Oscillator output. The crystal and bypass capacitor must be connected via shortest
distance with X1/X1A pin. If not used, it shall be open.
Document No. 002-03277 Rev. **
14
FM 32-bit Microcontroller Family Hardware Design Considerations
C Pin Decoupling
The C pin is connected to the internal 1.2 V supply for the MCU core. Proper filtering and decoupling of this pin is critical for a
working design. The decoupling capacitor must be placed very near to the C pin.
Figure 12 shows the recommended routing and placement for single sided metal layer. (Note, that in all following illustrations
the mounting metal layer is drawn in black and the back side metal layer in gray).
Figure 12. C Pin Routing and Placement for Single Sided Metal Layer Circuit Board
Figure 13 shows the recommended routing and placement for double sided metal layer. Note that despite the capacitor being
placed on the opposite side from the MCU, this solution is preferred as the via to the ground plane and the via connecting to
the C pin minimize inductance over other solutions.
Figure 13. C Pin Routing and Placement for Double Sided Metal Layer Circuit Board
www.cypress.com
Document No. 002-03277 Rev. **
15
FM 32-bit Microcontroller Family Hardware Design Considerations
Quartz Crystal Placement and Signal Routing
The crystal must be placed as near as possible to the MCU. Therefore the oscillator capacitors must be placed “behind” the
crystal.
Figure 14 shows the recommended placement and signal routing for a single metal layer circuit board.
Figure 14. Quartz Crystal Placement and Signal Routing for Single Metal Layer Circuit Board
Figure 15 shows the quartz recommended placement and signal routing for a double sided metal layer layout.
Figure 15. Quartz Crystal Placement and Signal Routing for Double Metal Layer Circuit Board
www.cypress.com
Document No. 002-03277 Rev. **
16
FM 32-bit Microcontroller Family Hardware Design Considerations
Device Reset
To reset the FM MCU, apply a low level pulse to the INITX pin. This can be via a switch or external reset controller. A
capacitor must be connected between Vss and the INITX pin for debouncing the switch and for EMI protection. Use a
capacitor of not more than 1 nF. This capacity covers the most common frequency protection in a wide range. Higher
capacities and the high input impedance of the INITX pin may cause latch-up effects with high currents being released from
the capacitor through the INITX pin by the Reset SW. If a high value must be used limit any current rush with a series resistor.
Note that reset is not a low power condition. The MCU must be released from reset and commanded into low power modes.
Reset should not be used as a method of power gating the device. While the I/O pins are generally in high impedance mode,
the internal peripherals may be actively clocked and waiting for the rising edge of INITX to initialize.
I/O Pins and Device Reset
The I/O pins are always in one of three states relative to device reset:
1.
While reset is active, all I/O pins are in the high-impedance analog state.
2.
When the MCU comes out of reset, the state for each I/O port is set to high-impedance analog (the default), pull-up, or
pull-down.
3.
The final state for each I/O pin is determined by user software. Care in software coding should be taken to ensure there
are no floating inputs or contending outputs in any condition.
www.cypress.com
Document No. 002-03277 Rev. **
17
FM 32-bit Microcontroller Family Hardware Design Considerations
Port Input / Unused Pins / Latch-up
Do not leave digital I/O pins unconnected while they are switched to input. If they are unconnected while being switched to
input, those pins can enter a so-called floating state. This can cause a high ICC current, which is adverse to low power modes.
Also, damage to the MCU can occur. Use the internal pull-up resistors in this case. If not, use external pull-up or pull-down
resistors to define the input-level. Figure 16 shows every possible way to connect I/O to a MCU GPIO pin. While you are
designing match your GPIO case to this figure and verify that it is a proper connection.
Never connect a resistor divider with similar resistance values as shown in the second example of the figure below. Be very
careful in connecting the output of an external device to the MCU (see example below with dotted cross) make absolutely sure
that you understand the power up, reset and, run conditions that this MCU pin may exhibit. For good design practice, you
should consider using the next example over and adding a small series resistor to protect the system if the MCU and the
external device ever have their outputs driven at the same time.
Figure 16. Connecting Digital I/O Pins
Be careful connecting input pins to other devices that can go into High-Z states. Always use internal pull-up or external pull-up
or pull-down resistors in this situation.
Outputs from external digital circuits should always be connected via a serial resistor to an MCU input pin to prevent latch-up
effects caused by under- or overshoots.
Choose debouncing and decoupling capacitors that are as physically small as practical. This reduces the inductance of the
capacitor and the interconnect.
www.cypress.com
Document No. 002-03277 Rev. **
18
FM 32-bit Microcontroller Family Hardware Design Considerations
All pins are set to input after their power-on default if they do not share an analog port. Analog ports have the digital I/O
functionality disabled after reset. They may be left open, but for ESD protection they should be terminated with a pull-up or
pull-down resistor if not used.
Note:
−
Do not connect any input ports directly to VCC or VSS (GND) if PCB routing and power supply can carry noise.
Use pull-up or pull-down resistors (2 kΩ … 4 kΩ).
EMC, ESD Protection, Latch-up Consideration
Be careful with external switches to VCC or ground together with debouncing capacitors connected to port pins.
A typical configuration is shown in Figure 17.
Figure 17. External Switch Configuration
RPD is a pull-down resistor and CBD is a debouncing capacitor. If the switch SW is open, a “0” is read from the port pin Pxy. If
the switch is closed, the input changes to “1”.
From the physical aspect, you must consider that the switch is often placed some distance from the MCU by cable, wire, or
circuit path. The longer the circuit path is, the higher is its inductivity LX (and capacity CX).
An equivalent circuit diagram is shown in Figure 18.
Figure 18. Equivalent Circuit Diagram
www.cypress.com
Document No. 002-03277 Rev. **
19
FM 32-bit Microcontroller Family Hardware Design Considerations
By closing the switch SW at time t0, the voltage can be measured at point (A) in the above circuit as shown in Figure 19.
Figure 19. Measuring Voltage at Point (A)
But at the port pin Pxy on point (B) in the above circuit the voltage can be measured as shown in Figure 20.
Figure 20. Measuring Voltage at Point (B)
www.cypress.com
Document No. 002-03277 Rev. **
20
FM 32-bit Microcontroller Family Hardware Design Considerations
By closing the switch SW, (as in figure below) the circuit becomes a parallel oscillator with the wire-inductivity LX, the
debouncing capacity CX, and the damping RPD of the pull-down resistor. Assume the power supply to be ideal; that is, it has no
internal resistance.
Figure 21. Circuit after Closing Switch SW
www.cypress.com
Document No. 002-03277 Rev. **
21
FM 32-bit Microcontroller Family Hardware Design Considerations
Because RPD is often chosen high (> 50 kOhms), its damping effect is weak.
This (weakly) attenuated oscillator causes voltage overshoots on the port pin, drawn in red in Figure 22.
Figure 22. Voltage Overshoots on the Port Pin
These overshoots may cause an internal latch-up on the port pin, because the internal clamping diode connected to VCC
becomes conductive. Opening the switch causes a similar result. In this case there are undershoots on the port pin.
The frequency of the oscillation can be calculated by:
f OSC =
1
2π L X C DB
.
The inductivity LX is the unknown value and depends on the PCB, its routing, and the wire lengths.
There are two countermeasures to prevent latch-up.
One solution is to decrease the capacity of the debouncing capacitor. This increases the oscillation frequency, and the overall
energy of the overshoots is smaller. See Figure 23
Figure 23. Decreasing the Capacity of the Debouncing Capacitor
“big” capacity
“small” capacity
This solution has two disadvantages: First the debouncing effect decreases and second, there is no guarantee that the latchup condition is eliminated.
www.cypress.com
Document No. 002-03277 Rev. **
22
FM 32-bit Microcontroller Family Hardware Design Considerations
A better solution is to use a series resistor at the port pin, as Figure 24 shows.
Figure 24. Using a Resistor at the Port Pin
The series resistor RS reduces the amplitude of the oscillation and decreases the voltage offset at first. The resistor must not
be chosen too high, so that the port pin input voltage VP is within the positive CMOS level. See Figure 25.
Figure 25. Effect of the Series Resistor RS
Good design practice is to protect I/O pins, and consequently the device itself, from electrostatic discharge (ESD) by putting on
the PCB a 50 Ω to 100 Ω resistor in series with any I/O pin that is routed off the PCB – for example to a button or a connector.
For more information on electromagnetic compatibility (EMC) and ESD considerations, see AN80994, PSoC EMC Best
Practices, and Appendix A.
Programming and Debug
All of the FM families of MCUs support both the Joint Test Action Group (JTAG) and serial wire debug (SWD) interfaces for
device flash programming and debugging. In addition, the FM3 and FM4 family of devices supports an extended Traceport
capability available to enhance the debugger capability by adding trace capability.
www.cypress.com
Document No. 002-03277 Rev. **
23
FM 32-bit Microcontroller Family Hardware Design Considerations
JTAG/SWD Connections
The FM MCU family supports JTAG debugging for full JTAG and SWD. Figure 26 shows the connection for the MB9BF50xN
as an example. Refer to the corresponding datasheet for different FM derivatives and their JTAG/SWD pin locations. If
supported by your debugging system, the external debugger can optionally supply power to the system in test from the
Debugger Power output on pin 19 of the JTAG connector.
Figure 26. JTAG/SWD Connection
*1 Only needed if SWD connector should also provide JTAG lines
www.cypress.com
Document No. 002-03277 Rev. **
24
FM 32-bit Microcontroller Family Hardware Design Considerations
Traceport Connections
Besides the JTAG/SWD ports, the FM3/FM4 MCU families also support debug via Traceport. Figure 27 shows the connections
for the MB9BF50xN as an example. Refer to the corresponding datasheet for different FM derivatives and their Traceport pin
locations.
Figure 27. FM3/FM4 Debug Trace Port Connection
Unlike the event trace provided by the SWD and JTAG, the Traceport lets you know what your application was doing before it
received an interrupt, what it is doing while the ISR is executing, and what happens after it leaves the interrupt. It tells you
where the application has been and exactly how it got there. In short, it gives you full insight to your application’s behavior in
real-time without being intrusive.
www.cypress.com
Document No. 002-03277 Rev. **
25
FM 32-bit Microcontroller Family Hardware Design Considerations
Minimum System
There are components required to guarantee that an FM MCU device always is recoverable in a user system. There are
conditions under which the part is NOT reprogrammable via debug mode. Setting the flash security bit, poor software
programming, wrong PLL settings, or other factors might keep an MCU from booting into user operating mode and make it
incapable of off chip programming.
To help you avoid locking up a system so that it is no longer usable, Cypress provides a small boot ROM on every FM device.
This ROM is activated by pulling the MD0 pin to a high state. Port 6 bit 0 (P60) is used to select between serial and USB
recovery mode.
Figure 28 and Figure 29 show the configuration of these two methods of recovery and the components required to implement
each method. Components shown in the two figures below are coded as Black = required and Gray = optional but suggested.
The choice of implementation is completely up to you. You might not need an RS-232 interface; in this case you could remove
the RS-232 driver device and implement a 5 volt serial-to-USB cable to connect and recover the system.
If needed, this mode of operation can also be used for production programming of the device. Be aware that proprietary
software is needed to recover and program the device. The “MCU Flash programmer” software and “USB Direct Programmer”
software are available on our website.
Schematic (Serial Programming)
Figure 28 is a schematic of a minimum hardware system that uses the UART asynchronous channel for flash programming.
Note that for other MCU families, a different interconnects to the serial driver is required. Please see device data sheet.
Figure 28. RS232 Programming
Serial Interface
The PC connection section is needed only if there are no 3...5 V external serial data lines for programming. The MAX3232 is a
standard level shifter, which converts the 3...5 V levels of the MCU to ±12 V RS232V24 levels, and vice versa.
www.cypress.com
Document No. 002-03277 Rev. **
26
FM 32-bit Microcontroller Family Hardware Design Considerations
Consider that the internal charge pumps of the level shifter can produce noise on the +3…5 V line, which can influence the
ADC, if AVCC and AVRH are directly (unfiltered) connected to it.
Consider that the logic level at port P60 determines UART or USB programming. If the port is not used in your application and
USB programming is not needed, it can also be connected directly to GND (considering good EMI routing). Do not switch this
port to output mode in this case.
Schematic (USB Programming)
Figure 29 is a schematic of a minimum hardware system that uses the USB function for flash programming (if USB is available
on the MCU). Note that for other MCU families, a different interconnect to the serial driver is required. Please see device data
sheet.
Figure 29. USB Programming
www.cypress.com
Document No. 002-03277 Rev. **
27
FM 32-bit Microcontroller Family Hardware Design Considerations
USB Interface
The MCU can be supplied either by external power or by VBUS connection to the USB host. In any case, for USBVCC +3.3 V is
needed. Use a 3.3 V regulator for USBVCC, if VBUS is used for powering the MCU.
Consider that the internal charge pumps of the level shifter can produce noise on the +3…5 V line, which can influence the
ADC, if AVCC and AVRH are directly (unfiltered) connected to it.
Note Cypress kit schematics provide good examples of how to incorporate MCUs into board schematics. For more
information, see Related Documents.
Summary
Many of the hardware considerations given in this application note are similar to those for other MCU devices. However, the
power and flexibility of FM families raise additional topics, such as selecting the best pins for the application and using
opportunities to simplify and optimize PCB routing.
This application note has provided information on each of these topics, so that you can successfully design Cypress MCU
devices into a PCB and hardware environment.
Use the Schematic Checklist in Appendix B to check your hardware design.
Related Documents
The following application notes are a good source for more detailed information:





AN57821 – PSoC 3 and PSoC 5LP Mixed Signal Circuit Board Layout Considerations
AN72845 – Design Guidelines for QFN Packaged Devices
AN89611 – PSoC 3 and PSoC 5LP Getting Started with Chip Scale Packages
AN69061 – Design, Manufacturing, and Handling Guidelines for Cypress Wafer Level Chip Scale Packages
AN88619 – PSoC 4 Hardware Design Considerations
Cypress development kit schematics are good examples of how to incorporate MCUs into board schematics. It may be helpful
to review the following Cypress kit schematics:


FM0-64L-S6E1C3 FM0+ S1E1C –Series Starter Kit.
FM4-176L-S6E2GM FM4 S6E2GM Pioneer Kit.
About the Author
Name:
James Williams
Title:
Applications Engineer Principal
Background:
15 yrs. in MCU Applications Engineering.
www.cypress.com
Document No. 002-03277 Rev. **
28
FM 32-bit Microcontroller Family Hardware Design Considerations
Appendix A – PCB Layout Tips and I/O Pin Selection
When you create a schematic with an FM Family device, you should select which pins go to which functions in the following
order:
1.
Power pins: How many different or separate voltages are required for digital, analog, and USB power? The analog
converter supply pins (AVCC, AVSS, AVRH) should be connected even if the ADC of the MCU is not used to avoid latch-up
conditions on the analog pins even if they are switched to digital input. See Power System for details.
2.
Crystal and clock generation: You must plan for these high impedance (crystal) and or high frequency clock traces at
the very beginning of your design. Your layout needs to accommodate keepouts and keepaway for these signals.
3.
C pin: A 1..10 µF ceramic capacitor (dielectric X7R, for example 4.7 µF) must be connected near the C pin of the MCU.
Otherwise, the MCU may not operate correctly or may be damaged in worst case.
4.
Mode Pins: The mode pins signal the MCU operation mode after reset. They should be pulled-up with 2 kΩ resistors. If
the PCB routing protects against ESD and EMI influence, the mode pins can be connected directly to VCC and VSS (GND)
depending on needed logic level – see Programming and Debug for details.
5.
Fixed pins: Will you need the following features:


Device reset? All FM devices require the INITX pin to at a minimum have an RC filter on the pin See Device Reset.

MHz or 32 kHz crystal oscillator? If not, the pins can generally be used as GPIOs – see GPIO and Non-Power Pins for
details.

Analog features, ADC inputs, DAC outputs, external voltage reference? If not, the pins can be used as GPIOs – see
Analog Noise Consideration for details.

USB? If not, the USBIO pins can be used as limited GPIOs – see USB Interface. They can also be used for flash
programming and debug – see Programming and Debug for details.

Wake from low power modes, reduced power, sleep, deep sleep? Use of special wakeup pins may be required to
support exiting from some modes.

External bus interface? External bus interfaces often operate at high speeds and require impedance matched traces to
function at full speed reliably. Short, direct routes are required. Connections should all be equal in length.

High speed or Quad CSIO (SPI) interface? These interfaces are both fast and have drive control selection capability.
These require impedance matched traces to function at full speed reliably. Short direct routes are required.
Connections should all be equal in length.

Ethernet? The Mii or RMii Ethernet interface should be as short and direct to the magnetics and connector as possible.
Connections should all be equal in length. Physical isolation of this part of the circuitry helps reduce interface to and
from this section.
Flash programming or debug, using JTAG or SWD? If not, some of the pins can be used as GPIOs – see
Programming and Debug for details. Remember to always allow for boot mode recovery of a device in the system.
6.
GPIO pins and digital function pins: All remaining pins can be used for digital I/O functions, and can be assigned to
simplify or optimize your PCB layout.
7.
NC or unused pins: Do not leave input pins open. If not possible, switch pin to output. See I/O Pins and Device Reset.for
how to proceed with unused (not connected) pins.
8.
(DNU) pins: Any device pin marked “do not use” (DNU) must be left unconnected and floating.
Note Cypress FM Family and PSoC Family kit schematics provide good examples of how to incorporate PSoC into board
schematics. For more information, see Related Documents.
www.cypress.com
Document No. 002-03277 Rev. **
29
FM 32-bit Microcontroller Family Hardware Design Considerations
There are many classic techniques for designing PCBs for low noise and electromagnetic compatibility (EMC). Some of these
techniques include:

Multiple layers: Although they are more expensive, it is best to use a multi-layer PCB with separate layers dedicated to
the VCC and VSS supplies. This gives good decoupling and shielding effects. Provide separate fills on these layers for
AVCC, VCC, AVSS, and VSS.
To reduce cost, a 2-layer or even a single-layer PCB can be used. In that case, you must have a good layout for all VSS
and VDD.

Ground and Power Supply: There should be a single point for gathering all ground returns. Avoid ground loops, or
minimize their surface area. All component-free surfaces of the PCB should be filled with additional grounding to create a
shield, especially when using 2-layer or single-layer PCBs.
The power supply should be near to the ground line to minimize the area of the supply loop. The supply loop can act as an
antenna and can be a major emitter or receiver of electromagnetic interference (EMI).

Decoupling: The standard decoupler for external power is a 100 µF capacitor. Supplementary 0.1 μF capacitors should
be placed as close as possible to the VSS and VDD pins of the device, to reduce high frequency power supply ripple.
Generally, you should decouple all sensitive or noisy signals to improve EMC performance. Decoupling can be both
capacitive and inductive.

Component Position: You should separate the different circuits on the PCB according to their EMI contribution. This
helps reduce cross-coupling on the PCB. For example, separate noisy high current circuits, low voltage circuits, and digital
components.

Signal Routing: Check the routing of the following signal types to improve EMC performance:



Noisy signals, for example signals with fast edge times
Sensitive and high impedance signals
Signals that capture events, such as interrupts and strobe signals
To increase EMC performance, keep the trace lengths as short as possible, and isolate the traces with VSS traces. To
avoid crosstalk, do not route traces near or parallel to other noisy and sensitive traces.
For more information, several references are available:


The Circuit Designer's Companion, Second Edition, (EDN Series for Design Engineers) by Tim Williams





Printed Circuits Handbook (McGraw Hill Handbooks), by Darwin Edwards, Clyde F. Coombs, Jr.,
PCB Design for Real-World EMI Control (The Springer International Series in Engineering and Computer Science), by
Bruce R. Archambeault and James Drewniak
EMC and the Printed Circuit Board: Design, Theory, and Layout Made Simple, by Mark I. Montrose
Signal Integrity Issues and Printed Circuit Board Design, by Douglas Brooks
Cypress AN80994, PSoC 3, PSoC 4, and PSoC 5LP EMC Best Practices
Application Note: Board Level Assembly and Reliability Considerations for QFN Type Packages – Amkor Technology,
September 2008 http://www.amkor.com/go/packaging/all-packages/microleadframeandreg
www.cypress.com
Document No. 002-03277 Rev. **
30
FM 32-bit Microcontroller Family Hardware Design Considerations
Appendix B – Schematic Checklist
Each item in the following checklist should be confirmed (C) or noted as not applicable (NA). For example, if you choose a
single power domain for your system , you can mark all the items related to multiple power domains as NA
Catalog
Power
Item
C / NA
Remark
Is the voltage at the AVCC pin always greater than or equal to the voltage at any of the
VCC pins?
If there are multiple power domains on the PCB, have the VCC pins been assigned
accordingly?
Are the correct capacitors connected to each AVCC and VCC pin? Do the capacitors
have appropriate working voltage and DC bias specifications?
Are the power voltage ramp-up speeds limited?
Are the total I/O currents less than the current limit?
Does your package selection have the correct thermal resistance for your anticipated
total chip power?
I/O Pins
Have your pin selections been optimized for your PCB / application? See I/O Pins and
Device Reset.
Are all device pins marked “do not use” (DNU) left unconnected and floating?
Are all unused I/O pins left floating and software programmed to outputs driving a low
signal?
Have series resistors been added to all pins being routed off the PCB, for ESD
protection?
Reset
Is the reset pin (INITX) connection in accordance with Device Reset?
Programming
and Debugging
Are the JTAG or SWD pin connections in accordance with Programming and Debug?
Oscillators
Are the crystals and external components connected correctly?
Analog
Connections
Are bypass capacitors connected to the correct pins?
Are analog power connections isolated from digital power?
Is a single point used for gathering all analog ground returns?
PCB
www.cypress.com
Does your PCB layout implement the techniques suggested in Appendix A – PCB
Layout Tips and I/O Pin Selection?
Document No. 002-03277 Rev. **
31
FM 32-bit Microcontroller Family Hardware Design Considerations
Document History
Document Title: AN203277 - FM 32-bit Microcontroller Family Hardware Design Considerations
Document Number: 002-03277
Revision
**
ECN
5057349
www.cypress.com
Orig. of
Change
JPWI
Submission
Date
2/9/2016
Description of Change
New Application Note
Document No. 002-03277 Rev. **
32
FM 32-bit Microcontroller Family Hardware Design Considerations
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find
the office closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
cypress.com/go/automotive
psoc.cypress.com/solutions
Clocks & Buffers
cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Interface
cypress.com/go/interface
Lighting & Power Control
cypress.com/go/powerpsoc
cypress.com/go/plc
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Memory
cypress.com/go/memory
Technical Support
PSoC
cypress.com/go/psoc
cypress.com/go/support
Touch Sensing
cypress.com/go/touch
USB Controllers
cypress.com/go/usb
Wireless/RF
cypress.com/go/wireless
PSoC is a registered trademark and PSoC Creator is a trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks
referenced herein are the property of their respective owners.
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone
Fax
Website
: 408-943-2600
: 408-943-4730
: www.cypress.com
© Cypress Semiconductor Corporation, 2016. The information contained herein is subject to change without notice. Cypress Semiconductor
Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any
license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or
safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The
inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies
Cypress against all charges.
This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide
patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a
personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative
works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source
Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the
right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or
use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a
malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
www.cypress.com
Document No. 002-03277 Rev. **
33
Similar pages