REVISIONS LTR DESCRIPTION A Update boilerplate paragraphs to current requirements. - PHN DATE APPROVED 12-01-19 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Phu H. Nguyen Original date of drawing YY MM DD CHECKED BY 06-08-09 Phu H. Nguyen APPROVED BY Thomas M. Hess SIZE A REV AMSC N/A . CODE IDENT. NO. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO TITLE MICROCIRCUIT, DIGITAL-LINEAR, 2.7 V TO 5.5 V 12 BIT 3 μs QUADRUPLE DIGITAL TO ANALOG CONVERTER WITH POWER DOWN, MONOLITHIC SILICON DWG NO. V62/06602 16236 A PAGE 1 OF 12 5962-V025-12 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 2.7 V to 5.5 V 12 bit 3 μs quadruple digital to analog converter with power down microcircuit, with an operating temperature range of -55°C to +125°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/06602 - Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type 01 Generic Circuit function TLV5614-EP 2.7 V to 5.5 V 12 bit 3 μs quadruple digital to analog converter with power down 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins X 16 JEDEC PUB 95 Package style MO-153 Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator A B C D E Z Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other 1.3 Absolute maximum ratings. 1/ Supply voltage ( DVDD, AVDD to GND)................................................................................... Supply voltage difference (AVDD to DVDD) ............................................................................ Digital input voltage range ................................................................................................... Reference input voltage range ............................................................................................. Operating free-air temperature range ( TA ).......................................................................... 7.0 V -2.8 V to 2.8 V -0.3 V to DVDD + 0.3 V -0.3 V to AVDD + 0.3 V -55°C to +125°C Storage temperature range (TSTG) ....................................................................................... -65°C to 150°C Lead temperature 1.6 mm (1/16 in) from case for 10 s ........................................................ 260°C _________ 1/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/06602 REV A PAGE 2 1.4 Recommended operating conditions. Supply voltage range (AVDD, DVDD): 5 V supply ..................................................................................................................... 3 V supply ..................................................................................................................... Minimum high level digital input voltage(VIH): DVDD = 2.7 V ................................................................................................................. DVDD = 5.5 V ................................................................................................................. Maximum low level digital input voltage(VIL): DVDD = 2.7 V ................................................................................................................. DVDD = 5.5 V ................................................................................................................. Reference voltage, Vref to REFINAB, REFINCD terminal: 5 V supply 2/ ............................................................................................................... 3 V supply 2/ ............................................................................................................... Minimum load resistance, (RL) ............................................................................................. Maximum load capacitance, (CL) ......................................................................................... Maximum serial clock rate, (SCLK) ...................................................................................... Operating free-air temperature range ( TA ).......................................................................... Typical package thermal resistance, junction to ambient (θJA) ............................................ 4.5 V to 5.5 V 2.7 V to 3.3 V 2.0 V 2.4 V 0.6 V 1.0 V 0.0 V to VDD – 1.5 V 0.0 V to VDD – 1.5 V 2 kΩ 100 pF 20 MHz -55°C to +125°C 108°C/W 2. APPLICABLE DOCUMENTS JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 JEDEC STD 51-7 – – Registered and Standard Outlines for Semiconductor Devices High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103 North 10th Street, Suite 240–S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 2/ Voltages greater than AVDD/2 cause output saturation for large DAC codes. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/06602 REV A PAGE 3 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Functional block diagram. The functional block diagram shall be as shown in figure 3. 3.5.4 Operating life derating chart. The operating life derating chart shall be as shown in figure 4. 3.5.5 Power down supply current . The power down supply current shall be as shown in figure 5. 3.5.6 Timing diagram. The timing diagram shall be as shown in figure 6. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/06602 REV A PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Resolution Integral nonlinarity (INL), end point adjusted Differential nonlinearity (DNL) Zero scale error (offset error at zero scale) Zero scale error temperature coefficient Gain error Gain error temperature coefficient Zero scale Power supply rejection ratio Full scale Individual DAC output specifications Voltage output range Output load regulation accuracy Reference inputs (REFINAB, REFINCD) Input voltage range Input resistance Input capacitance Reference feed through Symbol Conditions -55°C ≤ TA ≤ 125°C Vref = 2.048 V for AVDD = DVDD = 5.0 V Vref = 1.024 V for AVDD = DVDD = 3.0 V unless otherwise specified Limits Min Unit Max 12 EZS 2/ 3/ 4/ 5/ 6/ 7/ 8/ ±4 ±1 ±12 10 Typ ±0.7 10 Typ -80 Typ -80 Typ 9/ VO RL = 10 kΩ RL = 2 kΩ vs 10 kΩ 0 AVDD – 0.4 0.25 VI RI CI 10/ 0 AVDD – 1.5 10 Typ 5 Typ -75 Typ 0.5 Typ 1 Typ REFIN = 1 VPP at 1 kHz + 1.024 Vdc 11/ REFIN = 0.2 VPP + 1.024 Vdc Slow large signal Fast Reference input bandwidth bits LSB mV ppm/°C % of FS voltage ppm/°C dB V % of FS voltage V MΩ pF dB MHz Digital inputs (DIN, CS , LDAC , PD ) High level digital input current Low level digital input current Input capacitance Power supply IIH IIL CI Power supply current IDD VI = VDD VI = 0 V 3 Typ 5-V supply, No load, Clock running, All inputs 0 V or VDD 3-V supply, No load, Clock running, All inputs 0 V or VDD Power down supply current μA ±1 ±1 Slow Fast Slow Fast pF 2.4 5.6 1.8 4.8 See figure 5 mA 10 Typ nA See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/06602 REV A PAGE 5 TABLE I. Electrical performance characteristics – Continued. Test Conditions -55°C ≤ TA ≤ 125°C Vref = 2.048 V for AVDD = DVDD = 5.0 V Vref = 1.024 V for AVDD = DVDD = 3.0 V unless otherwise specified Symbol Limits Min Unit Max Analog output dynamic performance Glitch energy Signal to noise ratio Signal to noise + distortion Total harmonic distortion Spurious free dynamic range Digital input timing requirements SNR S/(N+D) THD SFDR CL = 100 pF, VO = 10% to 90% Slow RL = 10 kΩ, Vref = 2.048 V, 1.024 V Fast To ±0.5 LSB, CL = 100 pF, Slow RL = 10 kΩ, 12/ Fast To ±0.5 LSB, CL = 100 pF, Slow RL = 10 kΩ, 13/ Fast Code transition from 7FF to 800 Sine wave generated by DAC, Reference voltage = 1.024 at 3 V and 2.048 at 5 V, fs = 400 KSPS, fOUT = 1.1 kHz sine wave, CL = 100 pF, RL = 10 kΩ, BW = 20 kHz Setup time, CS low before FS↓ tsu(CS-FS) See figure 6. Setup time, FS low before first negative SCLK edge Setup time, sixteenth negative SCLK edge after FS low on which bit D0 is sampled before rising edge of FS Setup time. The first positive SCLK tsu(FS-CK) 8 tsu(C16-FS) 10 tsu(C16-CS) 10 twH twL tsu(D) 25 25 8 th(D) 5 Output slew rate Output setting time Output setting time, code to code SR tS tS(C) 5 Typ 1 Typ 3 Typ 9 Typ 1 Typ 2 Typ 10 Typ 74 Typ 66 Typ -68 Typ 70 Typ V/μs μs nV-s dB 10 ns edge after D0 is sampled before CS rising edge. If FS is used instead of the SCLK positive edge to update DAC, then the setup time is between the FS rising edge and CS rising edge. Pulse duration, SCLK high Pulse duration, SCLK low Setup time, data ready before SCLK falling edge. Hold time, data held valid after SCLK falling edge. Pulse duration, FS high twH(FS) 60 Typ See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/06602 REV A PAGE 6 TABLE I. Electrical performance characteristics – Continued. 1/ 2/ 3/ 4/ 5/ 6/ 7/ 8/ 9/ 10/ 11/ 12/ 13/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full scale errors. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1-LSB amplitude change of any two adjacent codes. Monotonis means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. Zero scale error is th deviation from zero voltage output when the digital input code is zero. 6 Zero error scale error temperature coefficient is given by: EZS TC = [EZS(Tmax) – EZS(Tmin)]/Vref x 10 /(Tmax - Tmin). Gain error is the deviation from the ideal output (2Vref – 1 LSB) with an output load of 10 kΩ, excluding the effects of the zero error. 6 Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG(Tmin)]/Vref x 10 /(Tmax - Tmin). Zero scale error rejection ratio (EZS-RR) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.3 V dc, and measuring the proportion of this signal imposed on the zero code output voltage. Full scale rejection ratio (EG-RR) ) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.3 V dc, and measuring the proportion of this signal imposed on the full scale output voltage after subtracting the zero scale change. Reference input voltages greater than VDD/2 cause output saturation for large DAC codes. Reference feed through is measured at the DAC output, with an input code = 000 hex and a Vref (REFINAB or REFINCD) input = 1.024 Vdc + 1 VPP at 1 kHz. Setting time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of FFF hex to 080 hex for 080 hex to FFF hex. Setting time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of one count. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/06602 REV A PAGE 7 Case X Symbol A A1 b c D Dimension Millimeters Symbol Min Max 1.45 E 0.00 0.15 E1 0.30 0.50 e 0.08 0.22 L 2.75 3.05 Millimeters Min Max 1.45 1.75 2.60 3.00 0.95 NOM 0.30 0.55 NOTES: 1. This drawing is subject to change without notice. 2. Body dimensions do not include mold flash or protrusion not to exceed 0.15 mm (0.006 inches). 3. Falls within JEDEC MO-153. FIGURE 1. Case outline. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/06602 REV A PAGE 8 Case X Terminal number 1 2 Terminal symbol DVDD PD Terminal number 9 10 Terminal symbol AGND REFINCD 3 LDAC 11 OUTD 4 5 6 DIN SCLK CS 12 13 14 OUTC OUTB OUTA 7 8 FS DGND 15 16 REFINAB AVDD FIGURE 2. Terminal connections. FIGURE 3. Functional block diagram DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/06602 REV A PAGE 9 FIGURE 4. Operating life derating chart. FIGURE 5. Power down supply current. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/06602 REV A PAGE 10 FIGURE 6. Timing diagram. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE CODE IDENT NO. DWG NO. A 16236 V62/06602 REV A PAGE 11 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. 1/ Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number V62/06602-01XE 01295 TLV5614MPWREP The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code 01295 DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE CODE IDENT NO. DWG NO. A 16236 V62/06602 REV A PAGE 12