PRELIMINARY
EZ-PD™ CCG4
USB Type-C Port Controller
General Description
EZ-PD™ CCG4 is a dual USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG4 provides
a complete dual USB Type-C and USB-Power Delivery port control solution for notebooks, power adapters and docking stations. It
can also be used in dual role and downstream facing port applications. EZ-PD CCG4 uses Cypress’s proprietary M0S8 technology
with a 32-bit, 48-MHz ARM® Cortex®-M0 processor with 128 KB flash and integrates two complete Type-C Transceivers including the
Type-C termination resistors RP and RD.
Applications
Low-Power Operation
■
Notebooks
■ Power adapters
■ Docking stations
■
■
■
2.7-V to 5.5-V operation
Integrated VCONN FETs to power EMCA cables
Independent supply voltage pin for GPIO that allows 1.71-V to
5.5-V signaling on the I/Os
Reset: 1.0 µA, Deep Sleep: 2.5 µA, Sleep: 2.5 mA
Features
■
32-bit MCU Subsystem
System-Level ESD on CC Pins
48-MHz ARM Cortex-M0 CPU
■ 128-KB Flash
■ 8-KB SRAM
■ In-system reprogrammable
■
■
± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based
on IEC61000-4-2 level 4C
Hot Swappable IOs
■
Integrated Digital Blocks
Four integrated timers or counters to meet response times
required by the USB-PD protocol
■ Four run-time serial communication blocks (SCBs) with
reconfigurable I2C, SPI, or UART functionality
■
Port 1 I2C pins and CC1, CC2 pins are hot-swappable
Packages
■
■
6.0 mm 6.0 mm, 0.6 mm, 40-pin QFN
Supports industrial temperature range (–40 °C to +85 °C)
Clocks and Oscillators
■
Integrated oscillator eliminating the need for external clock
Type-C Support
Two integrated transceivers (baseband PHY)
Integrated UFP (RD) and current sources for DFP (RP) on both
Type-C ports
■ Integrated dead battery termination for DRP applications
■ Supports two USB Type-C ports
■
■
Cypress Semiconductor Corporation
Document Number: 001-98440 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 2, 2016
PRELIMINARY
EZ-PD™ CCG4
Logic Block Diagram
CCG4: Single-Chip Type-C Controller
MCU Subsystem
Integrated Digital Blocks
I/O Subsystem
CC_PORT1 5
CORTEX-M0
4 x SCB2
SPI, UART)
48 MHz
Flash
(128KB)
SRAM
(8KB)
Advanced High-Performance Bus (AHB)
(I2 C,
Profiles and
Configurations
2 x Baseband MAC
2 x Baseband PHY
Programmable I/O Matrix
4 x TCPWM 1
CC_PORT2 5
2x V CONN
FETs
(PORT1)
2x V CONN
FETs
(PORT2)
GPIOs6
Integrated Rd3 and Rp4
4 x 8-bit SAR ADC
Serial Wire Debug
1. Timer, counter, pulse width modulation block
2. Serial communication block configurable as UART, SPI, or I2C
3. Termination resistor denoting a UFP
4. Current Sources to indicate a DFP
5. Configuration Channel
6. General purpose input/output
Document Number: 001-98440 Rev. *C
Page 2 of 29
PRELIMINARY
EZ-PD™ CCG4
Contents
Functional Overview ........................................................ 5
CPU and Memory Subsystem ..................................... 5
USB-PD Subsystem (SS) ............................................ 5
System Resources ...................................................... 6
Peripherals .................................................................. 6
GPIO ........................................................................... 7
Pinouts .............................................................................. 8
Power ............................................................................... 13
Application Diagrams ..................................................... 14
Electrical Specifications ................................................ 16
Absolute Maximum Ratings ....................................... 16
Device-Level Specifications ...................................... 16
Digital Peripherals ..................................................... 19
Memory ..................................................................... 20
Document Number: 001-98440 Rev. *C
System Resources .................................................... 20
Ordering Information ...................................................... 23
Ordering Code Definitions ......................................... 23
Packaging ........................................................................ 24
Acronyms ........................................................................ 26
Document Conventions ................................................. 27
Units of Measure ....................................................... 27
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC® Solutions ...................................................... 29
Cypress Developer Community ................................. 29
Technical Support ..................................................... 29
Page 3 of 29
PRELIMINARY
EZ-PD™ CCG4
Figure 1. EZ-PD CCG4 Block Diagram
CPU Subsystem
FLASH
128 KB
SRAM
8 KB
ROM
8 KB
FAST MUL
NVIC, IRQMX
Read Accelerator
SRAM Controller
ROM Controller
System Resources
Lite
System Interconnect (Single Layer AHB)
Peripherals
Peripheral Interconnect (MMIO)
PCLK
Clock
Clock Control
WDT
IMO
ILO
Power Modes
Active/Sleep
Deep Sleep
4 x TCPWM
Test
DFT Logic
DFT Analog
IOSS GPIO (5 x ports)
Reset
Reset Control
XRES
2 x USB-PD
High Speed I/O Matrix
2 X VCONN FET
Power
Sleep Control
WIC
POR
REF
PWRSYS
2 x SAR ADC
AHB-Lite
SPCIF
CC BB PHY
32-bit
SWD/TC
Cortex
M0
48 MHz
4 x SCB
CCG4
Pads, ESD
28 x GPIOs, 2 OVTs
IO Subsystem
Document Number: 001-98440 Rev. *C
Page 4 of 29
PRELIMINARY
EZ-PD™ CCG4
Functional Overview
CPU and Memory Subsystem
USB-PD Subsystem (SS)
CPU
EZ-PD CCG4 has a USB-PD subsystem consisting of two USB
Type-C baseband transceivers and physical-layer logic. These
transceivers perform the BMC and the 4b/5b encoding and
decoding functions as well as the 1.2-V analog front end. This
subsystem integrates the required termination resistors to
identify the role of the EZ-PD CCG4 solution. RD is used to
identify EZ-PD CCG4 as a UFP in a DRP application. When
configured as a DFP, integrated current sources perform the role
of RP or pull-up resistors. These current sources can be
programmed to indicate the complete range of current capacity
on VBUS defined in the USB Type-C spec. EZ-PD CCG4
responds to all USB-PD communication.
The Cortex-M0 CPU in EZ-PD CCG4 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to higher
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and also includes a wakeup
interrupt controller (WIC). The WIC can wake the processor up
from the Deep Sleep mode, allowing power to be switched off to
the main processor when the chip is in the Deep Sleep mode.
The Cortex-M0 CPU provides a nonmaskable interrupt (NMI)
input, which is made available to the user when it is not in use
for system functions requested by the user.
The CPU also includes a serial wire debug (SWD) interface,
which is a 2-wire form of JTAG. The debug configuration used for
EZ-PD CCG4 has four break-point (address) comparators and
two watchpoint (data) comparators.
Flash
The EZ-PD CCG4 device has a flash module with a flash
accelerator, tightly coupled to the CPU to improve average
access times from the flash block. The flash block is designed to
deliver two wait-states (WS) access time at 48 MHz and with
0-WS access time at 16 MHz. The flash accelerator delivers 85%
of single-cycle SRAM access performance on average. Part of
the flash module can be used to emulate EEPROM operation if
required.
The USB-PD sub-system contains two 8-bit SAR (successive
approximation register) ADC per port for analog to digital
conversions. The ADC includes a 8-bit DAC and a comparator.
The DAC output forms the positive input of the comparator. The
negative input of the comparator is from a 4-input multiplexer.
The four inputs of the multiplexer are a pair of global analog
multiplex busses an internal bandgap voltage and an internal
voltage proportional to the absolute temperature. All GPIO inputs
can be connected to the global analog multiplex busses through
a switch at each GPIO that can enable that GPIO to be
connected to the mux bus for ADC use. The CC1 and CC2 pins
of both Type-C ports are not available to connect to the mux
busses.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
Document Number: 001-98440 Rev. *C
Page 5 of 29
PRELIMINARY
EZ-PD™ CCG4
Figure 2. USB-PD Subsystem
To/From System Resources
vref
iref
To/ from AHB
2 x 8-bit ADC
per Type-C port
From AMUX
VCONN FET Enable
V5V
TxRx Enable
VCONN
FETs
2 x Digital Baseband PHY
Tx_data
from AHB
Enable Logic
Tx
SRAM
4b5b
Encoder
SOP
Insert
BMC
Encoder
Rx_data
to AHB
Rp
TX
CRC
CC1
RD1
RX
Rx
SRAM
4b5b
Decoder
SOP
Detect
BMC
Decoder
CC2
Comp
CC control
CC detect
Deep Sleep Reference Enable
Ref
Active
Rd
DB
Rd
2 x Analog Baseband PHY
Deep Sleep
Vref & Iref Gen
Functional, Wakeup Interrupts
vref, iref
RD2
8kV IEC ESD
RD1 shorted to CC1 and RD2 shorted to CC2 for DRP applications using
bondwire. For DFP applications, RD1 and RD2 not shorted to CC1 and CC2.
Dead Battery (DB) Rd termination removed after MCU boots up
System Resources
Peripherals
Power System
Serial Communication Blocks (SCB)
The power system is described in detail in the section “Power”
on page 13. It provides the assurance that voltage levels are as
required for each respective mode and either delay mode entry
(on power-on reset (POR), for example) until voltage levels are
as required for proper function or generate resets (brown-out
detect (BOD)) or interrupts (low voltage detect (LVD)). EZ-PD
CCG4 can operate from three different power sources over the
range of 2.7 to 5.5 V and has three different power modes,
transitions between which are managed by the power system.
EZ-PD CCG4 provides Sleep and Deep Sleep low-power
modes.
EZ-PD CCG4 has four SCBs, which can be configured to
implement an I2C, SPI, or UART interface. The hardware I2C
blocks implement full multi-master and slave interfaces capable
of multimaster arbitration. In the SPI mode, the SCB blocks can
be configured to act as a master or a slave.
Clock System
The clock system for EZ-PD CCG4 consists of the internal main
oscillator (IMO) and the internal low-power oscillator (ILO).
In the I2C mode, the SCB blocks are capable of operating at
speeds up to 1 Mbps (Fast Mode Plus) and have flexible
buffering options to reduce interrupt overhead and latency for the
CPU. These blocks also support I2C that creates a mailbox
address range in the memory of EZ-PD CCG4 and effectively
reduce I2C communication to reading from and writing to an
array in memory. In addition, the blocks support 8-deep FIFOs
for receive and transmit which, by increasing the time given for
the CPU to read data, greatly reduce the need for clock
stretching caused by the CPU not having read data on time.
The I2C peripherals are compatible with the I2C Standard-mode,
Fast-mode, and Fast-mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus
I/Os are implemented with GPIO in open-drain modes.
Document Number: 001-98440 Rev. *C
Page 6 of 29
PRELIMINARY
The I2C port on SCB 2, SCB 3 and SCB 4 blocks of EZ-PD CCG4
are not completely compliant with the I2C spec in the following:
2
■
The GPIO cells for SCB 2 to SCB 4 I C port are not
overvoltage-tolerant and, therefore, cannot be hot-swapped or
powered up independently of the rest of the I2C system.
■
Fast-mode Plus has an IOL specification of 20 mA at a VOL of
0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a
VOL maximum of 0.6 V.
■
Fast-mode and Fast-mode Plus specify minimum Fall times,
which are not met with the GPIO cell; Slow strong mode can
help meet this spec depending on the bus load.
GPIO
EZ-PD CCG4 has 30 GPIOs that includes the I2C and SWD pins,
which can also be used as GPIOs. The I2C pins from only
SCB 1 are overvoltage-tolerant. The number of available GPIOs
vary with the part numbers. The GPIO block implements the
following:
■
Seven drive strength modes:
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
■
Input threshold select (CMOS or LVTTL)
■
Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes
■
Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode)
■
Selectable slew rates for dV/dt related noise control to improve
EMI
Timer/Counter/PWM Block (TCPWM)
EZ-PD CCG4 has four TCPWM blocks. Each implements a
16-bit timer, counter, pulse-width modulator (PWM), and
quadrature decoder functionality. The block can be used to
measure the period and pulse width of an input signal (timer),
find the number of times a particular event occurs (counter),
generate PWM signals, or decode quadrature signals.
EZ-PD™ CCG4
During power-on and reset, the I/O pins are forced to the disable
state so as not to crowbar any inputs and/or cause excess
turn-on current. A multiplexing network known as a high-speed
I/O matrix is used to multiplex between various signals that may
connect to an I/O pin.
Document Number: 001-98440 Rev. *C
Page 7 of 29
PRELIMINARY
EZ-PD™ CCG4
Pinouts
Table 1. Pinout for CYPD4225-40LQXIT and CYPD4235-40LQXIT
Group
USB Type-C Port 1
USB Type-C Port 2
VBUS Control
VCONN Control
Overvoltage
Protection (OVP)
GPIOs and Serial
Interfaces
Pin Name
Pin Number
Description
CC1_P1
9
USB PD connector detect/Configuration Channel 1
CC2_P1
7
USB PD connector detect/Configuration Channel 2
CC1_P2
22
USB PD connector detect/Configuration Channel 1
CC2_P2
24
USB PD connector detect/Configuration Channel 2
VBUS_P_CTRL_P1
11
Full rail control I/O for enabling/disabling Provider load FET of USB
Type-C port 1
VBUS_C_CTRL_P1
12
Full rail control I/O for enabling/disabling Consumer load FET of USB
Type-C port 1/SCB1 (see Table 3 through Table 6 on page 11)
VBUS_P_CTRL_P2
39
Full rail control I/O for enabling/disabling Provider load FET of USB
Type-C port 2
VBUS_C_CTRL_P2
38
Full rail control I/O for enabling/disabling Consumer load FET of USB
Type-C port 2
VBUS_DISCHARGE_P1
20
I/O used for discharging VBUS line during voltage change
VBUS_DISCHARGE_P2
40
I/O used for discharging VBUS line during voltage change
VCONN_MON_P1/GPIO
19
VCONN_MON_P1 (Monitor VCONN for UVP condition on port 1)/GPIO
SCL_3/VCONN_MON_P2
25
SCB3 (see Table 3 through Table 6) or VCONN_MON_P2(Monitor
VCONN for UVP condition on port 2)
OVP_TRIP_P1
14
VBUS overvoltage output indicator for port 1 (active LOW)
OVP_TRIP_P2
21
VBUS overvoltage output indicator for port 2 (active LOW)
VBUS_MON_P1/GPIO
13
VBUS_MON_P1 (VBUS overvoltage protection monitoring
signal)/GPIO
HPD_P1/GPIO
18
HPD_P1 (Hot Plug Detect I/O for port 1)/GPIO
HPD_P2/GPIO
30
HPD_P2 (Hot Plug Detect I/O for port 2)/GPIO
MUX_CTRL_3_P2/OCP_DET_P2
34
MUX_CTRL_3_P2 (Mux control for port 2) or VBUS Overcurrent
Protection Input for port 2 (active LOW)
GPIO/MUX_CTRL_2_P2
35
MUX_CTRL_2_P2 (Mux control for port 2)/SCB4 (see Table 3 through
Table 6)
GPIO/MUX_CTRL_1_P2
36
MUX_CTRL_1_P2 (Mux control for port 2)/SCB4 (see Table 3 through
Table 6)
VBUS_MON_P2
37
VBUS_MON_P2(VBUS overvoltage protection monitoring signal)
VSEL_2_P2/GPIO
27
VSEL_2_P2(Voltage selection control for VBUS on port 2)/GPIO
I2C_SCL_SCB1_EC
17
SCB1/SCB4 (see Table 3 through Table 6)
I2C_SDA_SCB1_EC
16
SCB1/SCB3 (see Table 3 through Table 6)
I2C_INT_EC
15
I2C Interrupt line
I2C_SCL_SCB2_AR/VSEL_1_P2
4
SCB2 (see Table 3 through Table 6) or VSEL_1_P2 (Voltage selection
control for VBUS on port 2)
I2C_SDA_SCB2_AR/VSEL_1_P1
3
SCB1/SCB2 (see Table 3 through Table 6) or VSEL_1_P1 (Voltage
selection control for VBUS on port 1)
I2C_INT_AR_P1/OCP_DET_P1
5
I2C interrupt line or VBUS Overcurrent Protection Input for port 1 (active
LOW)
I2C_INT_AR_P2
6
I2C interrupt line/SCB1/SCB2 (see Table 3 through Table 6)
SDA_3/MUX_CTRL_3_P1/VSEL_2_P1
26
SCL_4/MUX_CTRL_1_P1
29
SCB3 (see Table 3 through Table 6) or MUX_CTRL_3_P1 (Mux control
for port 1) or VSEL_2_P1 (Voltage selection control for VBUS on port 1)
SCB4 (see Table 3 through Table 6)/MUX_CTRL_1_P1 (Mux control for
port 1)
Document Number: 001-98440 Rev. *C
Page 8 of 29
PRELIMINARY
EZ-PD™ CCG4
Table 1. Pinout for CYPD4225-40LQXIT and CYPD4235-40LQXIT (continued)
Group
GPIOs and Serial
Interfaces
Reset
Power
Pin Name
Pin Number
Description
SDA_4/MUX_CTRL_2_P1
28
SCB4 (see Table 3 through Table 6)/MUX_CTRL_2_P1 (Mux control for
port 1)
SWD_IO/AR_RST#
1
SWD_IO (serial wire debug I/O)/SCB1. See Table 3 through Table 6.
SWD_CLK/I2C_CFG_EC
2
SWD Clock/I2C_CFG_EC
XRES[1]
10
Reset input (active LOW)
V5V_P1
8
2.7-V to 5.5-V supply for VCONN FET of Type-C port 1
V5V_P2
23
2.7-V to 5.5-V supply for VCONN FET of Type-C port 2
VDDIO
32
1.71-V to 5.5-V supply for I/Os
VCCD
33
1.8-V regulator output for filter capacitor. This pin cannot drive external
load.
VDDD
31
VDDD supply input/output (2.7 V to 5.5 V)
VSS
EPAD
Ground supply
Note
1. This is firmware configurable GPIO. By default, this pin is floating. Firmware can add pull-up/pull-down and enable/disable IO buffers.
VDDIO
VDDD
MUX_CTRL_2_P2/GPIO
35
34
31
VBUS_MON_P2/GPIO
MUX_CTRL_1_P2/GPIO
33
32
VBUS_C_CTRL_P2
37
36
VBUS_DISCHARGE_P2
VBUS_P_CTRL_P2
39
38
40
MUX_CTRL_3_P2/OCP_DET_P2
VCCD
Figure 3. 40-Pin QFN Pin Map (Top View) for CYPD4225-40LQXIT and CYPD4235-40LQXIT
SWD_CLK/I2C_CFG_EC
I2C_SDA_SCB2_AR/VSEL_1_P1
1
2
3
I2C_SCL_SCB2_AR/VSEL_1_P2
I2C_INT_AR_P1/OCP_DET_P1
I2C_INT_AR_P2
4
5
6
CC2_P1
V5V_P1
CC1_P1
XRES
7
8
24
23
9
22
21
Document Number: 001-98440 Rev. *C
HPD_P2/GPIO
29
28
27
26
SCL_4/MUX_CTRL_1_P1
SDA_4/MUX_CTRL_2_P1
VSEL_2_P2/GPIO
SDA_3/MUX_CTRL_3_P1/VSEL_2_P1
25
SCL_3/VCONN_MON_P2
CC2_P2
V5V_P2
CC1_P2
OVP_TRIP_P2
VBUS_DISCHARGE_P1
VCONN_MON_P1/GPIO
OVP_TRIP_P1
I2C_INT_EC
HPD_P1/GPIO
13
14
15
16
VBUS_C_CTRL_P1
VBUS_MON_P1/GPIO
30
17
18
19
20
12
I2C_SDA_SCB1_EC
I2C_SCL_SCB1_EC
11
10
VBUS_P_CTRL_P1
SWD_IO/AR_RST#
Page 9 of 29
PRELIMINARY
EZ-PD™ CCG4
Table 2. Pinout for CYPD4125-40LQXIT and CYPD4135-40LQXIT
Group
USB Type-C Port 1
VBUS Control
Pin Name
Pin Number
Description
CC1_P1
9
USB PD connector detect/Configuration Channel 1
CC2_P1
7
USB PD connector detect/Configuration Channel 2
VBUS_P_CTRL_P1
11
Full rail control I/O for enabling/disabling. Provider load FET of USB
Type-C port 1.
VBUS_C_CTRL_P1
12
Full rail control I/O for enabling/disabling. Consumer load FET of USB
Type-C port 1/SCB1 (see Table 3 through Table 6 on page 11).
VBUS_DISCHARGE_P1
20
I/O used for discharging VBUS line during voltage change
VCONN Control
VCONN_MON_P1/GPIO
19
VCONN_MON_P1 (Monitor VCONN for OVP condition on port 1)/GPIO
Overvoltage
Protection (OVP)
OVP_TRIP_P1
14
VBUS overvoltage output indicator for port 1 (active LOW)
GPIO
27
SCB3 (see Table 3 through Table 6)/GPIO
VBUS_MON_P1/GPIO
13
VBUS_MON_P1 (VBUS overvoltage protection monitoring
signal)/GPIO
HPD_P1/GPIO
18
HPD_P1 (Hot Plug Detect I/O for port 1)/GPIO
GPIO
21
GPIO
30
GPIO
34
GPIO
35
GPIO
36
GPIO
37
GPIO
38
GPIO
39
GPIOs and Serial
Interfaces
Reset
GPIO
40
I2C_SCL_SCB1_EC
17
GPIO
GPIO/SCB4 (see Table 3 through Table 6)
GPIO
SCB1/SCB4 (see Table 3 through Table 6)
I2C_SDA_SCB1_EC
16
SCB1/SCB3 (see Table 3 through Table 6)
I2C_INT_EC
15
I2C interrupt line
I2C_SCL_SCB2_AR
4
SCB2 (see Table 3 through Table 6)
I2C_SDA_SCB2_AR/VSEL_1_P1
3
SCB1 or SCB2 (see Table 3 through Table 6) or voltage selection control
for VBUS on port 2
I2C_INT_AR_P1/OCP_DET_P1
5
I2C interrupt line or VBUS Overcurrent Protection Input for port 1 (Active
LOW)
GPIO
6
GPIO/SCB1/SCB2 (see Table 3 through Table 6)
SCL_3/GPIO
25
GPIO/SCB3 (see Table 3 through Table 6)
SDA_3/MUX_CTRL_3_P1/VSEL_2_P1
26
SCB3 (see Table 3 through Table 6) or MUX_CTRL_3_P1 (Mux control
for port 1), or Voltage selection control for VBUS on port 1
SCL_4/MUX_CTRL_1_P1
29
SCB3 (see Table 3 through Table 6) or MUX_CTRL_1_P1 (Mux control
for port 1)
SDA_4/MUX_CTRL_2_P1
28
SCB4 (see Table 3 through Table 6) or MUX_CTRL_2_P1 (Mux control
for port 1)
SWD_IO/AR_RST#
1
Serial wire debug I/O (SWD IO)/SCB1. See Table 3 through Table 6 or
Alpine Ridge Reset.
SWD_CLK/I2C_CFG_EC
2
SWD Clock/I2C_CFG_EC
XRES[2]
10
Reset input (active LOW)
Note
2. This is firmware configurable GPIO. By default, this pin is floating. Firmware can add pull-up/pull-down and enable/disable IO buffers.
Document Number: 001-98440 Rev. *C
Page 10 of 29
PRELIMINARY
EZ-PD™ CCG4
Table 2. Pinout for CYPD4125-40LQXIT and CYPD4135-40LQXIT (continued)
Group
Power
Pin Name
Pin Number
8
2.7-V to 5.5-V supply for VCONN FET of Type-C port 1
VDDIO
32
1.71-V to 5.5-V supply for I/Os
VCCD
33
1.8-V regulator output for filter capacitor. This pin cannot drive external
load.
VDDD
No Connect
Description
V5V_P1
31
VSS
EPAD
NC
22
NC
23
NC
24
VDDD supply I/O (2.7 V to 5.5 V)
Ground supply
These pins are not bonded
Note
2. This is firmware configurable GPIO. By default, this pin is floating. Firmware can add pull-up/pull-down and enable/disable IO buffers.
Table 3. Serial Communication Block (SCB1) Configuration
Pin
12
14
UART
UART_TX_SCB1
SPI Master
SPI_MOSI_SCB1
SPI Slave
I2C Master
I2C Slave
SPI_MOSI_SCB1
VBUS_C_CTRL_P1
VBUS_C_CTRL_P1
SPI_CLK_SCB1
VSEL_2_P1/
VCONN_MON_P1
VSEL_2_P1/
VCONN_MON_P1
UART_RX_SCB1
SPI_CLK_SCB1
17
UART_RTS_SCB1
SPI_MISO_SCB1
SPI_MISO_SCB1
I2C_SDA_SCB1
I2C_SDA_SCB1
16
UART_CTS_SCB1
SPI_SEL_SCB1
SPI_SEL_SCB1
I2C_SCL_SCB1
I2C_SCL_SCB1
Table 4. Serial Communication Block (SCB2) Configuration
Pin
UART
SPI Master
SPI Slave
I2C Master
I2C Slave
4
UART_TX_SCB2
SPI_CLK_SCB2
SPI_CLK_SCB2
I2C_SCL_SCB2
I2C_SCL_SCB2
3
UART_RX_SCB2
SPI_MISO_SCB2
SPI_MISO_SCB2
I2C_SDA_SCB2
I2C_SDA_SCB2
6
UART_RTS_SCB2
SPI_SEL_SCB2
SPI_SEL_SCB2
GPIO
GPIO
1
UART_CTS_SCB2
SPI_MOSI_SCB2
SPI_MOSI_SCB2
SWD_IO
SWD_IO
Table 5. Serial Communication Block (SCB3) Configuration
Pin
UART
SPI Master
SPI Slave
I2C Master
I2C Slave
26
UART_TX_SCB3
SPI_MISO_SCB3
SPI_MISO_SCB2
I2C_SDA_SCB3
I2C_SDA_SCB3
25
UART_RX_SCB3
SPI_MOSI_SCB3
SPI_MOSI_SCB3
I2C_SCL_SCB3
I2C_SCL_SCB3
16
UART_RTS_SCB3
SPI_SEL_SCB3
SPI_SEL_SCB3
I2C_SCL_SCB1
I2C_SCL_SCB1
21
UART_CTS_SCB3
SPI_CLK_SCB3
SPI_CLK_SCB3
AR_RST#
AR_RST#
Table 6. Serial Communication Block (SCB4) Configuration
Pin
UART
SPI Master
SPI Slave
I2C Master
I2C Slave
28
UART_TX_SCB4
SPI_MOSI_SCB4
SPI_MOSI_SCB4
I2C_SDA_SCB4
I2C_SDA_SCB4
29
UART_RX_SCB4
SPI_MISO_SCB4
SPI_MISO_SCB4
I2C_SCL_SCB4
I2C_SCL_SCB4
36
UART_RTS_SCB4
SPI_SEL_SCB4
SPI_SEL_SCB4
GPIO
GPIO
35
UART_CTS_SCB4
SPI_CLK_SCB4
SPI_CLK_SCB4
GPIO
GPIO
Document Number: 001-98440 Rev. *C
Page 11 of 29
PRELIMINARY
EZ-PD™ CCG4
Document Number: 001-98440 Rev. *C
VDDIO
VDDD
32
31
OCP_DET_P2/GPIO
VCCD
GPIO
35
34
33
GPIO
GPIO
36
GPIO
22
NC
NC
10
21
GPIO
VCONN_MON_P1/GPIO
VBUS_DISCHARGE_P1
HPD_P1/GPIO
I2C_SDA_SCB1_EC
I2C_SCL_SCB1_EC
17
18
19
20
NC
OVP_TRIP_P1
I2C_INT_EC
SCL_3
24
23
13
25
7
8
9
14
15
16
26
VBUS_C_CTRL_P1
5
6
SCL_4/MUX_CTRL_1_P1
SDA_4/MUX_CTRL_2_P1
GPIO
SDA_3/MUX_CTRL_3_P1/VSEL_2_P1
VBUS_MON_P1/GPIO
GPIO
29
28
27
12
CC2_P1
V5V_P1
CC1_P1
XRES
30
2
3
4
11
I2C_SCL_SCB2_AR
I2C_INT_AR_P1/OCP_DET_P1
GPIO
1
VBUS_P_CTRL_P1
SWD_IO/AR_RST#
SWD_CLK/I2C_CFG_EC
I2C_SDA_SCB2_AR/VSEL_1_P1
39
38
37
40
GPIO
GPIO
Figure 4. 40-Pin QFN Pin Map (Top View) for CYPD4125-40LQXIT and CYPD4135-40LQXIT
Page 12 of 29
PRELIMINARY
EZ-PD™ CCG4
Power
The following power system diagram shows the set of power
supply pins as implemented in EZ-PD CCG4.
CCG4 shall be able to operate from three possible external
supply sources: V5V_P1 for first Type-C port, V5V_P2 for
second Type- C port and VDDD.
CCG4 has the power supply input V5V_P1 and V5V_P2 pins for
providing power to EMCA cables through integrated VCONN
FETs. There are two VCONN FETs in CCG4 per Type-C port to
power either CC1 or CC2 pin. These FETs are capable of
providing a minimum of 1W on the CC1 and CC2 pins for the
EMCA cables. In USB-PD applications, the valid levels on
V5V_P1 and V5V_P2 supplies can range from 4.85 V to 5.5 V.
The chip’s internal operating power supply is derived from
VDDD. In UFP mode, CCG4 operates in 2.7 V – 5.5V. In DFP
and DRP modes, it operates in the 3.0 V – 5.5 V range.
A separate I/O supply pin, VDDIO, allows the GPIOs to operate
at levels from 1.71 V to 5.5 V. The VDDIO pin can be equal to or
less than the voltages connected to the V5V_P1 or V5V_P2 and
VDDD pins. The VDDIO supply should be less than or equal to
VDDD supply.
The VCCD output of EZ-PD CCG4 must be bypassed to ground
via an external capacitor (in the range of 80 to 120 nF; X5R
ceramic or better).
Bypass capacitors must be used from VDDD and V5V_P1 or
V5V_P2 pins to ground; typical practice for systems in this
frequency range is to use a 0.1-µF capacitor on VDDD, V5V_P1
and V5V_P2. Note that these are simply rules of thumb and that
for critical applications, the PCB layout, lead inductance, and the
bypass capacitor parasitic should be simulated to design and
obtain optimal bypassing.
Figure 5 shows an example of the power supply bypass
capacitors.
Figure 5. EZ-PD CCG4 Power and Bypass Scheme Example
[4]
CC1_P2
CC2_P2
[5]
[3]
V5V_P2
CC1_P1
CC2_P1
V5V_P1
VDDD
Core Regulator
(SRSS-Lite)
VDDIO
VCCD
GPIOs
Core
2 x CC
Tx/Rx
VSS
Note
3. V5V_P1 denoted power supply input for Type-C port 1
V5V_P2 denoted power supply input for Type-C port 2
4. CC1_1:USB PD connector detect/Configuration Channel 1 for Type-C port 1
CC1_2:USB PD connector detect/Configuration Channel 1 for Type-C port 2
5. CC2_1:USB PD connector detect/Configuration Channel 2 for Type-C port 1
CC2_2:USB PD connector detect/Configuration Channel 2 for Type-C port 2
Document Number: 001-98440 Rev. *C
Page 13 of 29
PRELIMINARY
EZ-PD™ CCG4
Application Diagrams
Figure 6. CCG4 in a Dual Port Notebook Application using CYPD4225-40LQXIT
USB 3.0
HOST
HS
2
SSTX/RX
4
DISPLAY PORT
CONTROLLER 1
ML_LANE_[0:3]N
4
ML_LANE_[0:3]P
4
AUX P/N
2
MUX
TX
4
RX
4
SBU
2
HPD_P1
I2C_SCL
I2C_SDA
VBUS_SINK
4.7 uF
49.9KO
100 KO
4.7 uF
2
100 KO
10 O
VBUS_C_CTRL_P1
100 KO
2
OPTIONAL VDDIO SUPPLY. CAN SHORT
TO VDDD IN SINGLE SUPPLY SYSTEMS.
49.9KO
100 KO
4.7 uF
VDDIO
100 KO
TO DISPLAY_PORT
CONTROLLER 1
TO DISPLAY PORT
CONTROLLER 2
VSEL_2_P1
VSEL_1_P1
VSEL_2_P2
VSEL_1_P2
HPD_P2
18
30
33
32
100 KO
0.1µF
VCCD
31
VDDD
VDDIO
V5V_P1
8
1µF
200 O
VBUS_MON_P1/GPIO
14
13 VBUS_MON_P1
VSEL_2_P2 27
VDDIO
CC2_P1
VSEL_2_P2/GPIO
CC1_P1
VDDIO
VBUS_P_CTRL_P1
100 KO
10
0.1µF
2.2 KO
2.2 KO
EMBEDDED
CONTROLLER
21
2.2 KO
15
0.1µF
10 KO
OVP_TRIP_P1
TYPE-C
RECEPTACLE 1
100 KO
100 KO
HPD_P2/GPIO
10 O
VBUS_DISCHARGE_P1
VBUS
HPD_P1/GPIO
19 VCONN_MON_P1/GPIO
DC/DC
OR
AC-DC
SECONDARY
(5-20V)
CHARGER
HPD_P1
SWD_IO/AR_RST#
SWD_CLK/I2C_CFG_EC
1µF
V5V_P2
1
2
23
VBUS_P_CTRL_P1
1µF
10 O
7
CC2
9
CC1
11 VBUS_P_CTRL_P1
330pF
330pF
VBUS_DISCHARGE_P1
VBUS_DISCHARGE_P1 20
XRES
OVP_TRIP_P2
I2C_INT_EC
VBUS_C_CTRL_P1
CCG4
(CYPD4225-40LQXIT)
40-QFN MUX_CTRL_3_P2/GPIO
GND
12 VBUS_C_CTRL_P1
34
GND
17 I2C_SCL_SCB1_EC
16
VSEL_1_P2
4
VSEL_1_P1
3
5
6
VDDIO
2.2 KO
2.2 KO
I2C MASTER
FOR ALT
MODE MUX
CONTROL
CONNECTED
TO TYPE-C
PORT1 or
PORT2
25
VSEL_2_P1 26
I2C_SCL 29
I2C_SDA 28
EPAD
MUX_CTRL_2_P2/GPIO
I2C_SDA_SCB1_EC
I2C_SCL_SCB2_AR/VSEL_1_P2
MUX_CTRL_1_P2/GPIO
I2C_SDA_SCB2_AR/VSEL_1_P1
VBUS_C_CTRL_P2/
35
36
38 VBUS_C_CTRL_P2
I2C_INT_AR_P1
VBUS_P_CTRL_P2
VBUS_P_CTRL_P2 39
I2C_INT_AR_P2
VBUS_DISCHARGE_P2
VBUS_DISCHARGE_P2 40
SCL_3/VCONN_MON_P2/GPIO
CC2_P2
SDA_3/MUX_CTRL_3_P1/VSEL_2_P1
CC1_P2
SCL_4/MUX_CTRL_1_P1/GPIO
24
CC2
22
SDA_4/MUX_CTRL_2_P1/GPIO
330pF
100 KO
VBUS_MON_P2
VSS
CC1
VBUS
330pF
37 VBUS_MON_P2
TYPE-C
RECEPTACLE 2
0.1µF
10 KO
VBUS_SINK
VBUS
4.7 uF
DP/DM
DP/DM
3.3V
SSTX/RX
5.0V
SBU
5.0V
DP/DM
DP/DM
VBUS
SSTX/RX
SBU
VBUS_SOURCE
49.9KO
100 KO
2
100 KO
VBUS (5-20V)
VBUS_SOURCE
4.7 uF
49.9KO
100 KO
VBUS_P_CTRL_P2
10 O
100 KO
200 O
VBUS_DISCHARGE_P2
10 O
100 KO
USB 3.0
HOST
HS
2
SSTX/RX
4
DISPLAY PORT
CONTROLLER 2
ML_LANE_[0:3]N
4
ML_LANE_[0:3]P
4
AUX P/N
2
TX
4
RX
4
SBU
2
MUX
HPD_P2
I2C_SCL
Document Number: 001-98440 Rev. *C
2
4.7 uF
10 O
VBUS_P_CTRL_P2
I2C_SDA
Page 14 of 29
PRELIMINARY
EZ-PD™ CCG4
Figure 7. CCG4 in a Single Port Notebook Application using CYPD4125-40LQXIT
USB 3.0
HOST
HS
2
SSTX/RX
4
DISPLAY PORT
CONTROLLER 1
ML_LANE_[0:3]N
4
ML_LANE_[0:3]P
4
AUX P/N
2
MUX
TX
4
RX
4
SBU
2
HPD_P1
VBUS_SINK
I2C_SCL
CHARGER
I2C_SDA
4.7 uF
49.9KO
100 KO
2
100 KO
VBUS_C_CTRL_P1
10 O
100 KO
VBUS
OPTIONAL VDDIO SUPPLY. CAN SHORT
TO VDDD IN SINGLE SUPPLY SYSTEMS.
5.0V
5.0V
3.3V
4.7 uF
49.9KO
100 KO
TO DISPLAY_PORT
CONTROLLER 1
HPD_P1
18
10 O
33
32
100 KO
0.1µF
200O
VCCD
31
VDDD
VDDIO
8
1µF
V5V_P1
23
SWD_IO/AR_RST#
SWD_CLK/I2C_CFG_EC
V5V_P2
1
2
1µF
4.7 uF
100 KO
VDDIO
VBUS_P_CTRL_P1
1µF
VBUS_DISCHARGE_P1 10 O
100 KO
TYPE-C
RECEPTACLE 1
VBUS
HPD_P1/GPIO
100 KO
VBUS_MON_P1/GPIO
13 VBUS_MON_P1
19 VCONN_MON__P1/GPIO
14
10 KO
CC2_P1
OVP_TRIP_P1
CC1_P1
VDDIO
VDDIO
VBUS_P_CTRL_P1
100 KO
10
0.1µF
2.2 KO
2.2 KO
EMBEDDED
CONTROLLER
21
2.2 KO
15
17
16
4
VSEL_1_P1
3
5
VDDIO
6
25
2.2 KO
2.2 KO
I2C MASTER FOR ALT MODE
MUX CONTROL CONNECTED TO
TYPE-C PORT1
VSEL_2_P1
26
I2C_SCL
29
I2C_SDA
28
EPAD
Document Number: 001-98440 Rev. *C
I2C_INT_EC
0.1µF
7
VBUS_C_CTRL_P1
CCG4
(CYPD4125-40LQXIT)
40-QFN
GPIO
CC2
9
11 VBUS_P_CTRL_P1
VBUS_DISCHARGE_P1
VBUS_DISCHARGE_P1 20
XRES
GPIO
CC1
330pF
330pF
GND
12 VBUS_C_CTRL_P1
27
I2C_SCL_SCB1_EC
I2C_SDA_SCB1_EC
GPIO
30
34
I2C_SCL_SCB2_AR
GPIO
I2C_SDA_SCB2_AR/VSEL_1_P1
GPIO
I2C_INT_AR_P1
GPIO 36
GPIO
GPIO 37
SCL_3
GPIO
SDA_3/MUX_CTRL_3_P1/VSEL_2_P1
GPIO
SCL_4/MUX_CTRL_1_P1
SDA_4/MUX_CTRL_2_P1
VSS
DP/DM
DP/DM
VSEL_1_P1
2
VBUS (5-20V)
VBUS_SOURCE
SSTX/RX
SBU
VSEL_2_P1
DC/DC
OR
AC-DC
SECONDARY
(5-20V)
GPIO
NC
NC
35
38
39
40
24
22
Page 15 of 29
PRELIMINARY
EZ-PD™ CCG4
Electrical Specifications
Absolute Maximum Ratings
Table 7. Absolute Maximum Ratings[6]
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
VDDD_MAX
Digital supply relative to VSS
–0.5
–
6
V
Absolute max
V5V_P1
Max supply voltage relative to VSS
–
–
6
V
Absolute max
V5V_P2
Max supply voltage relative to VSS
–
–
6
V
Absolute max
VDDIO_MAX
Max supply voltage relative to VSS
–
–
6
V
Absolute Max
VGPIO_ABS
GPIO voltage
–0.5
–
VDDIO + 0.5
V
Absolute max
IGPIO_ABS
Maximum current per GPIO
–25
–
25
mA
Absolute max
IGPIO_injection
GPIO injection current, Max for VIH
> VDDD, and Min for VIL < VSS
–0.5
–
0.5
mA
Absolute max, current
injected per pin
ESD_HBM
Electrostatic discharge human
body model
2200
–
–
V
–
ESD_CDM
Electrostatic discharge charged
device model
500
–
–
V
–
LU
Pin current for latch-up
–200
–
200
mA
ESD_IEC_CON
Electrostatic discharge
IEC61000-4-2
8000
–
–
V
Contact discharge on
CC1, CC2 pins
ESD_IEC_AIR
Electrostatic discharge
IEC61000-4-2
15000
–
–
V
Air discharge for pins
CC1, CC2
–
Device-Level Specifications
All specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 3.0 V to 5.5 V,
except where noted.
Table 8. DC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
VDDD
Power supply input voltage
2.7
–
5.5
V
UFP applications
SID.PWR#1_A
VDDD
Power supply input voltage
3.0
–
5.5
V
DFP/DRP applications
SID.PWR#26
V5V_P1,
V5V_P2
Power supply input voltage
4.85
–
5.5
V
–
SID.PWR#1
PWR#13
VDDIO
GPIO power supply
1.71
–
5.5
V
–
SID.PWR#24
VCCD
Output voltage (for core logic)
–
1.8
–
V
–
SID.PWR#15
CEFC
External regulator voltage bypass
on VCCD
80
100
120
nF
X5R ceramic or better
SID.PWR#16
CEXC
Power supply decoupling capacitor
on VDDD
0.8
1
–
µF
X5R ceramic or better
SID.PWR#27
CEXV
Power supply decoupling capacitor
on V5V_P1 and V5V_P2
–
0.1
–
µF
X5R ceramic or better
mA
V5V_P1 and V5V_P2 = 5 V,
TA = 25 °C,
CC I/O IN Transmit or Receive,
no I/O sourcing current, CPU at
24 MHz, two PD ports active
Active Mode, VDDD = 2.7 to 5.5 V. Typical values measured at VDD = 3.3 V.
SID.PWR#4
IDD12
Supply current
–
10
–
Note
6. Usage above the absolute maximum conditions listed in Table 7 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 001-98440 Rev. *C
Page 16 of 29
PRELIMINARY
EZ-PD™ CCG4
Table 8. DC Specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
–
2.5
4.0
mA
VDDD = 3.3 V, TA = 25 °C, all
blocks except CPU are ON, CC
I/O ON, no I/O sourcing current
Sleep Mode, VDDD = 2.7 to 5.5 V
SID25A
IDD20A
I2C wakeup
WDT ON
IMO at 48 MHz
Deep Sleep Mode, VDDD = 2.7 to 3.6 V (Regulator on)
SID34
IDD29
VDDD = 2.7 to 3.6 V
I2C wakeup and WDT ON
–
60
–
µA
VDDD = 3.3 V, TA = 25 °C
SID_DS
IDD_DS
VDDD = 2.7 to 3.6 V
CC wakeup ON
–
2.5
–
µA
Power source = VDDD, Type-C
not attached, CC enabled for
wakeup, RP disabled
SID_DS1
IDD_DS1
VDDD = 2.7 to 3.6 V
CC wakeup ON
–
100
–
µA
Power source = VDDD, Type-C
not attached, CC enabled for
wakeup, RP and RD connected
at 70 ms intervals by CPU. RP,
RD connection should be
enabled for both PD ports.
IDD_XR
Supply current while XRES
asserted
–
1
10
µA
–
XRES Current
SID307
Table 9. AC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
DC
–
48
MHz
–
0
–
µs
Guaranteed by
characterization
TDEEPSLEEP Wakeup from Deep Sleep mode
–
–
35
µs
24-MHz IMO. Guaranteed by
characterization.
SID.XRES#5
TXRES
External reset pulse width
5
–
–
µs
Guaranteed by
characterization
SYS.FES#1
T_PWR_RDY
Power-up to “Ready to accept
I2C / CC command”
–
5
25
ms
Guaranteed by
characterization
SID.CLK#4
FCPU
CPU frequency
SID.PWR#20
TSLEEP
Wakeup from sleep mode
SID.PWR#21
Details/Conditions
3.0 V VDDD 5.5 V
I/O
Table 10. I/O DC Specifications
Spec ID
Typ
Max
Units
VIH[7]
Input voltage HIGH threshold 0.7 × VDDIO
–
–
V
CMOS input
SID.GIO#38
VIL
Input voltage LOW threshold
–
–
0.3 × VDDIO
V
CMOS input
SID.GIO#39
VIH[7]
LVTTL input, VDDIO < 2.7 V
0.7× VDDIO
–
–
V
–
SID.GIO#37
Parameter
Description
Min
Details/Conditions
SID.GIO#40
VIL
LVTTL input, VDDIO < 2.7 V
–
–
0.3 × VDDIO
V
–
SID.GIO#41
VIH[7]
LVTTL input, VDDIO 2.7 V
2.0
–
–
V
–
SID.GIO#42
VIL
LVTTL input, VDDIO 2.7 V
–
–
0.8
V
SID.GIO#33
VOH
Output voltage HIGH level
VDDIO –0.6
–
–
V
SID.GIO#34
VOH
Output voltage HIGH level
VDDIO –0.5
–
–
V
IOH = 1 mA at 1.8-V VDDIO
SID.GIO#35
VOL
Output voltage LOW level
–
–
0.6
V
IOL = 4 mA at 1.8-V VDDIO
SID.GIO#36
VOL
Output voltage LOW level
–
–
0.6
V
IOL = 8 mA at 3 V VDDIO
–
IOH = 4 mA at 3-V VDDIO
Note
7. VIH must not exceed VDDIO + 0.2 V.
Document Number: 001-98440 Rev. *C
Page 17 of 29
PRELIMINARY
EZ-PD™ CCG4
Table 10. I/O DC Specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID.GIO#5
RPULLUP
Pull-up resistor
3.5
5.6
8.5
kΩ
–
SID.GIO#6
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
kΩ
–
SID.GIO#16
IIL
Input leakage current
(absolute value)
–
–
2
nA
SID.GIO#17
CIN
Input capacitance
–
–
7
pF
–
25 °C, VDDIO = 3.0 V
SID.GIO#43
VHYSTTL
Input hysteresis LVTTL
25
40
–
mV
VDDIO 2.7 V. Guaranteed
by characterization.
SID.GPIO#44
VHYSCMOS
Input hysteresis CMOS
0.05 × VDDIO
–
–
mV
Guaranteed by
characterization
SID69
IDIODE
Current through protection
diode to VDDIO/Vss
–
–
100
µA
Guaranteed by
characterization
SID.GIO#45
ITOT_GPIO
Maximum total source or sink
chip current
–
–
200
mA
Guaranteed by
characterization
Table 11. I/O AC Specifications
(Guaranteed by Characterization)
Spec ID
SID70
Parameter
TRISEF
Rise time
Description
Min
2
Typ
–
Max
12
SID71
TFALLF
Fall time
2
–
12
Units
Details/Conditions
ns 3.3-V VDDIO, Cload = 25 pF
ns 3.3-V VDDIO, Cload = 25 pF
XRES
Table 12. XRES DC Specifications
Spec ID
SID.XRES#1
Parameter
VIH
Description
Input voltage HIGH threshold
Min
Typ
0.7 × VDDIO –
Max
–
Units
Details/Conditions
V
CMOS input
SID.XRES#2
VIL
Input voltage LOW threshold
–
–
0.3 × VDDIO
V
CMOS input
SID.XRES#3
CIN
Input capacitance
–
–
7
pF
SID.XRES#4
VHYSXRES
Input voltage hysteresis
–
–
0.05 × VDDIO
mV
–
Guaranteed by
characterization
Document Number: 001-98440 Rev. *C
Page 18 of 29
PRELIMINARY
EZ-PD™ CCG4
Digital Peripherals
The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.
Pulse Width Modulation (PWM) for GPIO Pins
Table 13. PWM AC Specifications
(Guaranteed by Characterization)
Spec ID
SID.TCPWM.3
Parameter
Description
TCPWMFREQ Operating frequency
Min
–
Typ
Fc
SID.TCPWM.4
Max Units
Details/Conditions
–
MHz Fc max = CLK_SYS. Maximum = 48 MHz
TPWMENEXT Input trigger pulse width
–
2/Fc
–
ns
SID.TCPWM.5
TPWMEXT
Output trigger pulse width
–
2/Fc
–
ns
SID.TCPWM.5A
TCRES
Resolution of counter
–
1/Fc
–
ns
SID.TCPWM.5B
PWMRES
PWM resolution
–
1/Fc
–
ns
SID.TCPWM.5C
QRES
Quadrature inputs resolution
–
1/Fc
–
ns
For all trigger events
Minimum possible width of Overflow,
Underflow, and CC (Counter equals
Compare value) outputs
Minimum time between successive
counts
Minimum pulse width of PWM output
Minimum pulse width between
quadrature-phase inputs
I2C
Table 14. Fixed I2C AC Specifications
(Guaranteed by Characterization)
Spec ID
SID153
Parameter
FI2C1
Description
Min
–
Bit rate
Typ
–
Max
1
Units
Mbps
Details/Conditions
–
Table 15. Fixed UART AC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID162
FUART
Bit rate
–
–
1
Mbps
–
Table 16. Fixed SPI AC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID166
FSPI
SPI operating frequency
(Master; 6X oversampling)
–
–
8
MHz
–
Min
Typ
Max
Units
Details / Conditions
–
Table 17. Fixed SPI Master Mode AC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
SID167
TDMO
MOSI valid after SClock
driving edge
–
–
15
ns
SID168
TDSI
MISO valid before SClock
capturing edge
20
–
–
ns
Full clock, late MISO
sampling
SID169
THMO
Previous MOSI data hold
time
0
–
–
ns
Referred to Slave capturing
edge
Min
Typ
Max
Units
Details / Conditions
40
–
–
ns
–
Table 18. Fixed SPI Slave Mode AC Specifications
(Guaranteed by Characterization)
Spec ID
SID170
Parameter
TDMI
Description
MOSI valid before Sclock
capturing edge
Document Number: 001-98440 Rev. *C
Page 19 of 29
PRELIMINARY
EZ-PD™ CCG4
Table 18. Fixed SPI Slave Mode AC Specifications
(Guaranteed by Characterization) (continued)
SID171
TDSO
SID171A
TDSO_EXT
SID172
THSO
SID172A
TSSELSCK
MISO valid after Sclock
driving edge
–
–
48 + 3 * TSCB
ns
MISO valid after Sclock
driving edge in Ext Clk mode
–
–
48
ns
–
Previous MISO data hold
time
0
–
–
ns
–
100
–
–
ns
–
SSEL valid to first SCK valid
edge
TSCB = TCPU = 1/24 MHz
Memory
Table 19. Flash AC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID.MEM#4
TROWWRITE[8]
Row (block) write time (erase and
program)
–
–
20
ms
–
SID.MEM#3
TROWERASE[8]
Row erase time
–
–
13
ms
–
SID.MEM#8
Row program time after erase
–
–
7
ms
–
SID178
TROWPROGRAM[8]
TBULKERASE[8]
Bulk erase time (128 KB)
–
–
35
ms
–
SID180
TDEVPROG[8]
Total device program time
–
–
25
seconds
Guaranteed by
characterization
SID.MEM#6
FEND
Flash endurance
100 K
–
–
cycles
Guaranteed by
characterization
SID182
FRET1
Flash retention. TA 55 °C, 100 K
P/E cycles
20
–
–
years
Guaranteed by
characterization
SID182A
FRET2
Flash retention. TA 85 °C, 10 K
P/E cycles
10
–
–
years
Guaranteed by
characterization
Min
Typ
System Resources
Power-on-Reset (POR) with Brown Out
Table 20. Imprecise Power On Reset (PRES)
Spec ID
Parameter
Description
Max
Units
Details/Conditions
SID185
VRISEIPOR
Rising trip voltage
0.80
–
1.50
V
Guaranteed by
characterization
SID186
VFALLIPOR
Falling trip voltage
0.75
–
1.4
V
Guaranteed by
characterization
Min
Typ
Max
Table 21. Precise Power On Reset (POR)
Spec ID
Parameter
Description
SID190
VFALLPPOR
BOD trip voltage in active and
sleep modes
SID192
VFALLDPSLP
BOD trip voltage in Deep Sleep
Units
Details/Conditions
1.48
–
1.62
V
Guaranteed by
characterization
1.1
–
1.5
V
Guaranteed by
characterization
Note
8. It can take as much as 20 milliseconds to write to flash. During this time the device should not be reset, or flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
Document Number: 001-98440 Rev. *C
Page 20 of 29
PRELIMINARY
EZ-PD™ CCG4
SWD Interface
Table 22. SWD Interface Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID.SWD#1 F_SWDCLK1
3.3 V VDDIO 5.5 V
–
–
14
MHz
SWDCLK ≤ 1/3 CPU clock frequency
SID.SWD#2 F_SWDCLK2
1.8 V VDDIO 3.3 V
–
–
7
MHz
SWDCLK ≤ 1/3 CPU clock frequency
SID.SWD#3 T_SWDI_SETUP
T = 1/f SWDCLK
0.25 * T
–
–
ns
Guaranteed by characterization
SID.SWD#4 T_SWDI_HOLD
T = 1/f SWDCLK
0.25 * T
–
–
ns
Guaranteed by characterization
SID.SWD#5 T_SWDO_VALID
T = 1/f SWDCLK
–
–
0.5*T
ns
Guaranteed by characterization
SID.SWD#6 T_SWDO_HOLD
T = 1/f SWDCLK
1
–
–
ns
Guaranteed by characterization
Internal Main Oscillator
Table 23. IMO AC Specifications
Spec ID
Parameter
Min
Typ
Max
Units
Details/Conditions
SID.CLK#13 FIMOTOL
Frequency variation at 24, 36,
and 48 MHz (trimmed)
–
–
±2
%
–
SID226
TSTARTIMO
IMO startup time
–
–
7
µs
–
SID229
TJITRMSIMO
RMS jitter at 48 MHz
–
145
–
ps
–
IMO frequency
24
–
48
MHz
–
Min
Typ
Max
FIMO
–
Description
Internal Low-Speed Oscillator
Table 24. ILO AC Specifications
Spec ID
Parameter
Description
Units
Details/Conditions
SID234
TSTARTILO
ILO startup time
–
–
2
ms
Guaranteed by
characterization
SID236
TILODUTY
ILO duty cycle
40
50
60
%
Guaranteed by
characterization
SID.CLK#5
FILO
ILO Frequency
20
40
80
kHz
Document Number: 001-98440 Rev. *C
–
Page 21 of 29
PRELIMINARY
EZ-PD™ CCG4
Power Down
Table 25. PD DC Specifications
Spec ID
Parameter
Description
Min
Typ
Max Units
Details/Conditions
SID.PD.1
Rp_std
DFP CC termination for default USB
Power
64
80
96
µA
–
SID.PD.2
Rp_1.5A
DFP CC termination for 1.5A power
166
180
194
µA
–
SID.PD.3
Rp_3.0A
DFP CC termination for 3.0A power
304
330
356
µA
–
SID.PD.4
Rd
UFP CC termination
4.59
5.1
5.61
kΩ
–
4.08
5.1
6.12
kΩ
All supplies forced to 0 V and 1.0 V
applied at CC1 or CC2. Applicable
for DRP applications only.
Voltage drop from V5V_P1 and
V5V_P2 pins to CC1 pin while
sourcing 215 mA.
SID.PD.15 Vdrop_V5V_CC1 CC1 and CC2 pins of Port1 and Port2
are not short circuit protected.
Max allowed sourcing current is
500 mA.
–
–
100
mV
–
Voltage drop from V5V_P1 and
V5V_P2 pins to CC2 pin while
sourcing 215 mA
SID.PD.16 Vdrop_V5V_CC2 CC1 and CC2 pins of Port1 and Port2
are not short circuit protected.
Max allowed sourcing current is
500 mA.
–
–
100
mV
–
SID.PD.5
UFP Dead Battery CC termination on
CC1 and CC2
Rd_DB
Analog to Digital Converter
Table 26. ADC DC Specifications
Spec ID
Parameter
SID.ADC.1 Resolution
Description
ADC resolution
Min
Typ
Max
Units
Details/Conditions
–
8
–
bits
–
SID.ADC.2 INL
Integral nonlinearity
–1.5
–
1.5
LSB
–
SID.ADC.3 DNL
Differential nonlinearity
–2.5
–
2.5
LSB
–
SID.ADC.4 Gain Error
Gain error
–1.0
–
1.0
LSB
–
Min
Typ
Max
Units
Details/Conditions
–
–
3
V/ms
–
Table 27. ADC AC Specifications
Spec ID
Parameter
SID.ADC.5 SLEW_Max
Description
Rate of change of sampled voltage
signal
Document Number: 001-98440 Rev. *C
Page 22 of 29
PRELIMINARY
EZ-PD™ CCG4
Ordering Information
The EZ-PD CCG4 part numbers and features are listed in Table 28.
Table 28. EZ-PD CCG4 Ordering Information
Part Number
Battery
Type-C Ports Dead
Termination
Application
CYPD4225-40LQXIT Notebooks, docking stations
2
Termination
Resistor
Rp[10], RD[9]
DRP
40-pin QFN
No
DFP
40-Pin QFN
DRP
40-pin QFN
DFP
40-Pin QFN
CYPD4125-40LQXIT Notebooks, docking stations
1
Yes
CYPD4135-40LQXIT Power adapters
1
No
RP[10]
2
Package
Yes
RP[10]
[10]
CYPD4235-40LQXIT Power adapters
Role
Rp
, RD
[9]
Ordering Code Definitions
CY PD
4 1/2 0
X
-
XX XX
X
I
T
T = Tape and Reel
Temperature Grade:
I = Industrial
Pb-free
Package Type: XX = FN, LH or LQ
FN = CSP; LH = DFN; LQ = QFN
Number of pins in the package: XX = 14, 20, or 40
Device Role: Unique combination of role and termination:
X = 2 or 3 or 4 or 5
Feature: Unique Applications
Number of Type-C Ports: 1 = 1 Port, 2 = 2 Ports
Product Type: 4 = Fourth-generation product family, CCG4
Marketing Code: PD = Power Delivery product family
Company ID: CY = Cypress
Notes
9. Termination resistor denoting an accessory or upstream facing port.
10. Termination resistor denoting a downstream facing port.
Document Number: 001-98440 Rev. *C
Page 23 of 29
PRELIMINARY
EZ-PD™ CCG4
Packaging
Table 29. Package Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Units
TA
Operating ambient temperature
–
–40
25
85
°C
TJ
Operating junction temperature
–
–40
–
100
°C
TJA
Package JA (40-pin QFN)
–
–
31
–
°C/W
TJC
Package JC (40-pin QFN)
–
–
29
–
°C/W
Table 30. Solder Reflow Peak Temperature
Package
40-pin QFN
Maximum Peak Temperature
Maximum Time within 5 °C of Peak Temperature
260 °C
30 seconds
Table 31. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
40-pin QFN
Document Number: 001-98440 Rev. *C
MSL
MSL 3
Page 24 of 29
PRELIMINARY
EZ-PD™ CCG4
Figure 8. 40-Pin QFN (6 × 6 × 0.6 mm), LR40A/LQ40A 4.6 × 4.6 E-PAD (Sawn) Package Outline, 001-80659
001-80659 *A
Document Number: 001-98440 Rev. *C
Page 25 of 29
PRELIMINARY
Acronyms
Table 32. Acronyms Used in this Document (continued)
Table 32. Acronyms Used in this Document
Acronym
EZ-PD™ CCG4
Description
Acronym
Description
opamp
operational amplifier
OCP
overcurrent protection
OVP
overvoltage protection
PCB
printed circuit board
PD
power delivery
PGA
programmable gain amplifier
PHY
physical layer
ADC
analog-to-digital converter
API
application programming interface
ARM®
advanced RISC machine, a CPU architecture
CC
configuration channel
CPU
central processing unit
CRC
cyclic redundancy check, an error-checking
protocol
POR
power-on reset
CS
current sense
PRES
precise power-on reset
DFP
downstream facing port
PSoC®
Programmable System-on-Chip™
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
PWM
pulse-width modulator
DRP
dual role port
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
electrically erasable programmable read-only
EEPROM
memory
EMCA
a USB cable that includes an IC that reports cable
characteristics (e.g., current rating) to the Type-C
ports
RX
receive
SAR
successive approximation register
SCL
I2C serial clock
SDA
I2C serial data
EMI
electromagnetic interference
ESD
electrostatic discharge
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output
IC
integrated circuit
SRAM
static random access memory
IDE
integrated development environment
SWD
serial wire debug, a test protocol
TX
transmit
Type-C
a new standard with a slimmer USB connector and
a reversible cable, capable of sourcing up to 100 W
of power
UART
Universal Asynchronous Transmitter Receiver, a
communications protocol
USB
Universal Serial Bus
USBIO
USB input/output, CCG4 pins used to connect to a
USB port
XRES
external reset I/O pin
I2C, or IIC Inter-Integrated Circuit, a communications protocol
ILO
internal low-speed oscillator, see also IMO
IMO
internal main oscillator, see also ILO
I/O
input/output, see also GPIO
LVD
low-voltage detect
LVTTL
low-voltage transistor-transistor logic
MCU
microcontroller unit
NC
no connect
NMI
nonmaskable interrupt
NVIC
nested vectored interrupt controller
Document Number: 001-98440 Rev. *C
S/H
sample and hold
SPI
Serial Peripheral Interface, a communications
protocol
Page 26 of 29
PRELIMINARY
EZ-PD™ CCG4
Document Conventions
Units of Measure
Table 33. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
Hz
hertz
KB
1024 bytes
kHz
kilohertz
k
kilo ohm
Mbps
megabits per second
MHz
megahertz
M
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
V
volt
Document Number: 001-98440 Rev. *C
Page 27 of 29
PRELIMINARY
EZ-PD™ CCG4
Document History Page
Document Title: EZ-PD™ CCG4 USB Type-C Port Controller
Document Number: 001-98440
Revision
ECN
Orig. of
Change
Submission
Date
**
4921014
MURT
09/24/2015
New datasheet
*A
4999504
MURT
11/03/2015
Updated Table 1, Table 2, Table 7, Table 8, Table 18 and Table 23.
Updated Figure 3 through Figure 6 and Figure 7.
*B
5049109
MURT
12/14/2015
Updated Table 8 and Table 26.
03/02/2016
Removed “Fixed UART DC Specifications”, “Fixed I2C DC Specifications”, “Fixed SPI DC
Specifications”, “IMO DC SPecifications” and “ILO DC Specifications” table.
Updated application schematic for both single port and dual port notebook applications
Updated copyright information
Updated Sleep Current in General Description from 2 mA to 2.5 mA
Updated description for pin#34, pin#5, and pin#10 row in table 1
Updated description for pin#5 and pin#10 row in table 2
*C
5141544
MVTA
Document Number: 001-98440 Rev. *C
Description of Change
Page 28 of 29
PRELIMINARY
EZ-PD™ CCG4
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC
cypress.com/psoc
Touch Sensing
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/touch
USB Controllers
Wireless/RF
psoc.cypress.com/solutions
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation 2015-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify
and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right
to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software
is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any
component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole
or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify
and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-98440 Rev. *C
Revised March 2, 2016
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 29 of 29