PRELIMINARY
EZ-PD™ CCG3
USB Type-C Port Controller
General Description
EZ-PD™ CCG3 is a highly integrated USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD
CCG3 provides a complete USB Type-C and USB-Power Delivery port control solution for notebooks, dongles, monitors, docking
stations and power adapters. CCG3 uses Cypress’s proprietary M0S8 technology with a 32-bit, 48-MHz ARM® Cortex® -M0 processor
with 128-KB flash, 8-KB SRAM, 20 GPIOs, full-speed USB device controller, a Crypto engine for authentication, a 20V-tolerant
regulator, and a pair of FETs to switch a 5V (VCONN) supply, which powers cables. CCG3 also integrates two pairs of gate drivers to
control external VBUS FETs and system level ESD protection. CCG3 is available in 40-QFN and 42-WLCSP packages.
Features
■
Type-C and USB-PD Support
■
Integrated USB Power Delivery 3.0 support
■ Integrated USB-PD BMC transceiver
■ Integrated VCONN FETs
■ Configurable resistors RA, RP and RD
■ Dead Battery Detection support
■ Integrated fast role swap and extended data messaging
■ Supports one USB Type-C port
■ Integrated Hardware based overcurrent protection (OCP) and
overvoltage protection (OVP)
■
Integrated timers and counters to meet response times
required by the USB-PD protocol
Four run-time reconfigurable serial communication blocks
(SCBs) with reconfigurable I2C, SPI, or UART functionality
Clocks and Oscillators
■
Integrated oscillator eliminating the need for external clock
Power
■
2.7 V to 21.5 V operation
■
2x Integrated dual-output gate drivers for external VBUS FET
switch control
■
Independent supply voltage pin for GPIO that allows 1.71 V to
5.5 V signaling on the I/Os
■
48-MHz ARM Cortex-M0 CPU
128-KB Flash
■ 8-KB SRAM
■
Reset: 30 µA, Deep Sleep: 30 µA, Sleep: 3.5 mA
■
System-Level ESD Protection
Integrated Digital Blocks
■
Hardware Crypto block enables Authentication
■ Full-Speed USB Device Controller supporting Billboard Device
Class
Packages
32-bit MCU Subsystem
■
■
■
■
Cypress Semiconductor Corporation
Document Number: 002-03288 Rev. *E
•
198 Champion Court
On CC, SBU, DPLUS, DMINUS and VBUS pins
± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based
on IEC61000-4-2 level 4C
40-pin QFN and 42-ball CSP for Notebooks/Accessories
Supports industrial temperature range (–40 °C to +105 °C)
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 28, 2016
PRELIMINARY
EZ-PD™ CCG3
Logic Block Diagram
Document Number: 002-03288 Rev. *E
Page 2 of 33
PRELIMINARY
EZ-PD™ CCG3
Contents
EZ-PD CCG3 Block Diagram ............................................ 4
Functional Overview ........................................................ 5
CPU and Memory Subsystem ..................................... 5
Crypto Block ................................................................ 5
Integrated Billboard Device ......................................... 5
USB-PD Subsystem (SS) ............................................ 5
Full-Speed USB Subsystem ........................................ 6
Peripherals .................................................................. 6
GPIO ........................................................................... 7
Power Systems Overview ................................................ 8
Pinouts .............................................................................. 9
Applications .................................................................... 12
Electrical Specifications ................................................ 15
Absolute Maximum Ratings ....................................... 15
Device-Level Specifications ...................................... 15
Digital Peripherals ..................................................... 18
Document Number: 002-03288 Rev. *E
System Resources .................................................... 20
Ordering Information ...................................................... 25
Ordering Code Definitions ......................................... 25
Package Diagrams .......................................................... 26
Acronyms ........................................................................ 27
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 33
Worldwide Sales and Design Support ....................... 33
Products .................................................................... 33
PSoC® Solutions ...................................................... 33
Cypress Developer Community ................................. 33
Technical Support ..................................................... 33
Page 3 of 33
PRELIMINARY
EZ-PD™ CCG3
EZ-PD CCG3 Block Diagram
Figure 1. EZ-PD CCG3 Block Diagram[1]
CPU Subsystem
FLASH
2x64 KB
SRAM
8 KB
ROM
8 KB
FAST MUL
NVIC, IRQMX
Read Accelerator
SRAM Controller
ROM Controller
System Resources
Lite
Power Modes
Active/Sleep
Deep Sleep
High Speed I/O Matrix
ADC / ACA
CHG DET
Pads, ESD
USB-FS
CC BB PHY
2 X VCONN FET
OCP
2 X GATE DRIVER
USB-PD SS
2 x 2 ANALOG XBAR
Test
DFT Logic
DFT Analog
Peripheral Interconnect (MMIO)
PCLK
OVP
Reset
Reset Control
XRES
Peripherals
4 x TCPWM
Clock
Clock Control
WDT
IMO
ILO
System Interconnect (Single Layer AHB)
IOSS GPIO (3 x ports)
Power
Sleep Control
WIC
POR
REF
PWRSYS
HV REG
AHB-Lite
SPCIF
CRYPTO
32-bit
SWD/TC
Cortex
M0
48 MHz
4 x SCB
CCG3
FS-PHY
22 x GPIOs, 2 x OVTs
IO Subsystem
Note
1. See Acronyms section for more details.
Document Number: 002-03288 Rev. *E
Page 4 of 33
PRELIMINARY
EZ-PD™ CCG3
Functional Overview
USB-PD Subsystem (SS)
CPU and Memory Subsystem
The USB-PD sub-system contains all of the blocks related to
USB Type-C and Power Delivery. The sub-system is comprised
of the following:
CPU
The Cortex-M0 CPU in EZ-PD CCG3 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to higher
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and also includes a Wakeup
Interrupt Controller (WIC). The WIC can wake the processor up
from the Deep Sleep mode, allowing power to be switched off to
the main processor when the chip is in the Deep Sleep mode.
The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI)
input, which is made available to the user when it is not in use
for system functions requested by the user.
The CPU also includes a serial wire debug (SWD) interface,
which is a two-wire form of JTAG. The debug configuration used
for EZ-PD CCG3 has four break-point (address) comparators
and two watchpoint (data) comparators.
Flash
The EZ-PD CCG3 device has a flash module with two banks of
64 KB flash, a flash accelerator, tightly coupled to the CPU to
improve average access times from the flash block. The flash
block is designed to deliver 1 wait-state (WS) access time at
48 MHz and with 0-WS access time at 24 MHz. The flash
accelerator delivers 85% of single-cycle SRAM access
performance on average. Part of the flash module can be used
to emulate EEPROM operation if required.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
Crypto Block
CCG3 integrates a crypto block for hardware assisted
authentication of firmware images. It also supports filed
upgradeability of firmware in a trusted ecosystem. The CCG3
Crypto block provides cryptography functionality. It includes
hardware acceleration blocks for AES (Advanced Encryption
Standard) block cipher, SHA-1 (Secure Hash Algorithm) and
SHA-2 hash, Cyclic Redundancy Check (CRC) and pseudo
random number generation.
Integrated Billboard Device
CCG3 includes a complete full speed USB 2.0 device controller
capable of functioning as a Billboard class device. The USB 2.0
device controller can also support other device classes.
Document Number: 002-03288 Rev. *E
■
BMC PHY: USB-PD Transceiver with Fast Role Swap (FRS)
transmit and detect
■
VCONN power FETs for the CC lines
■
VCONN Ra Termination and Leakers
■
Analog Cross-Bar to switch between the SBU1/SBU2 and
AUX_P/AUX_N pins
■
Programmable Pull-up and Pull-down termination on the
AUX_P/AUX_N pins
■
HPD Processor
■
VBUS_C Regulator (20V LDO)
■
Power Switch between VSYS supply and VBUS_C Regulator
output
■
VBUS_C Over-Voltage
Detectors
■
Current Sense Amplifier (CSA) for over current detection
■
Gate Drivers for VBUS_P and VBUS_C external Power FETs
■
VBUS_C discharge switch
■
USB2.0 Full-Speed (FS) PHY with integrated 5.0V to 3.3V
regulator
■
Charger Detection / Emulation for USB BC1.2 and other
proprietary protocols
■
2 instances of 8-bit SAR ADCs
■
8kV IEC ESD Protection on the following pins: VBUS_C, CC1,
CC2, SBU1, SBU2, DP, DM
(OV)
and
Under-Voltage
(UV)
The EZ-PD™ CCG3 USB-PD subsystem interfaces to the pins
of a USB Type-C connector. It includes a USB Type-C baseband
transceiver and physical-layer logic. This transceiver performs
the BMC and the 4b/5b encoding and decoding functions as well
as integrating the 1.2V analog front end. This subsystem
integrates the required terminations to identify the role of the
CCG3 device, including Rp and Rd for UFP/DFP roles and Ra
for EMCA/VCONN powered accessories. The programmable
VCONN leakers are included in order to discharge VCONN
capacitance during a disconnect event. It also integrates power
FETs for supplying VCONN power to the CC1/CC2 pins from the
V5V pin. The Analog Cross-Bar allows for connecting either of
the SBU1/SBU2 pins to either of the AUX_P/AUX_N pins to
support DisplayPort sideband signaling. The integrated HPD
processor can be used to control or monitor the HPD signal of a
DisplayPort source or sink.
The OV/UV (Over-Voltage/Under-Voltage) block monitors the
VBUS_C supply for programmable over-voltage and
under-voltage conditions. The CSA amplifies the voltage across
an external sense resistor, which is proportional to the current
being drawn from the external DC-DC VBUS supply converter.
The CSA output can either be measured with an ADC or
configured to detect an over-current condition. The VBUS_P and
VBUS_C gate drivers control the gates of external power FETs
Page 5 of 33
PRELIMINARY
for the VBUS_C and VBUS_P supplies. The gate drivers can be
configured to support both P and N type external power FETs.
The gate drivers are configured by default for nFET devices. In
applications using pFETs, the gate drivers must be appropriately
configured. The OV/UV and CSA blocks can generate interrupts
to automatically turn off the power FETs for the programmed
over-voltage and over-current conditions. The VBUS_C
discharge switch allows for discharging the VBUS_C line
through an external resistor.
The USB-PD sub-system also contains two 8-bit Successive
Approximation Register (SAR) ADCs for analog to digital
EZ-PD™ CCG3
conversions. Each ADC includes an 8-bit DAC and a
comparator. The DAC output forms the positive input of the
comparator. The negative input of the comparator is from a
4-input multiplexer. The four inputs of the multiplexer are a pair
of global analog multiplex busses, an internal bandgap voltage
and an internal voltage proportional to the absolute temperature.
Each GPIO pin can be connected to the global Analog Multiplex
Busses through a switch, which allows either ADC to sample the
pin voltage. When sensing the GPIO pin voltage with an ADC,
the pin voltage cannot exceed the VDDD or VDDIO supply
values.
Figure 2. USB-PD Subsystem
CONSUMER N/PFETs
charger
PRODUCER N/PFETs
dc-dc
VBUS_P
OC
VBUS_P_CTRL
Gate
Driver
CSA
VBUS_C_CTRL
Gate
Driver
VBUS_DISCHARGE
VDDD
VSYS
POWER
SWITCH
RA
VBUS_C
OV/UV
VCONN
SWITCH
Leaker
CC1
V5V
CC2
PROGRAMMABLE
PULL-UP, PULL-DOWN
BMC
PHY w/ FRS
AUX_P
SBU1
ANALOG
CROSS-BAR
AUX_N
HPD
SBU2
USB Type-C Port
VCONN
LDO
DP
HPD
2x
ADCs
USB 2.0
FS PHY
CHARGER
DETECT
DM
USB PD SubSystem
Full-Speed USB Subsystem
The FSUSB subsystem contains a full speed USB device
controller.
Peripherals
Serial Communication Blocks (SCB)
EZ-PD CCG3 has four SCBs, which can be configured to
implement an I2C, SPI, or UART interface. The hardware I2C
blocks implement full multi-master and slave interfaces capable
of multimaster arbitration. In the SPI mode, the SCB blocks can
be configured to act as master or slave.
I2C
In the
mode, the SCB blocks are capable of operating at
speeds of up to 1 Mbps (Fast Mode Plus) and have flexible
Document Number: 002-03288 Rev. *E
buffering options to reduce interrupt overhead and latency for the
CPU. These blocks also support I2C that creates a mailbox
address range in the memory of EZ-PD CCG3 and effectively
reduce I2C communication to reading from and writing to an
array in memory. In addition, the blocks support 8-deep FIFOs
for receive and transmit which, by increasing the time given for
the CPU to read data, greatly reduce the need for clock
stretching caused by the CPU not having read data on time.
The I2C peripherals are compatible with the I2C Standard-mode,
Fast-mode, and Fast-mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204).
The I2C bus I/Os are implemented with GPIO in open-drain
modes.
Page 6 of 33
PRELIMINARY
The I2C port on SCB 1-3 blocks of EZ-PD CCG3 are not
completely compliant with the I2C spec in the following aspects:
2
■
The GPIO cells for SCB 1's I C port are not overvoltage-tolerant
and, therefore, cannot be hot-swapped or powered up
independently of the rest of the I2C system.
■
Fast-mode Plus has an IOL specification of 20 mA at a VOL of
0.4V. The GPIO cells can sink a maximum of 8-mA IOL with a
VOL maximum of 0.6V.
■
Fast-mode and Fast-mode Plus specify minimum Fall times,
which are not met with the GPIO cell; Slow strong mode can
help meet this spec depending on the bus load.
GPIO
EZ-PD CCG3 has up to 20 GPIOs (GPIOs can be configured for
GPIOs, SCB, SBU and Aux signals) and SWD pins, which can
also be used as GPIOs. The I2C pins from SCB 0 are
overvoltage-tolerant.
The GPIO block implements the following:
■
Seven drive strength modes:
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
■
Input threshold select (CMOS or LVTTL)
■
Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes
■
Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode)
■
Selectable slew rates for dV/dt related noise control to improve
EMI
Timer/Counter/PWM Block (TCPWM)
EZ-PD CCG3 has four TCPWM blocks. Each implements a
16-bit timer, counter, pulse-width modulator (PWM), and
quadrature decoder functionality. The block can be used to
measure the period and pulse width of an input signal (timer),
find the number of times a particular event occurs (counter),
generate PWM signals, or decode quadrature signals.
EZ-PD™ CCG3
During power-on and reset, the I/O pins are forced to the disable
state so as not to crowbar any inputs and/or cause excess
turn-on current. A multiplexing network known as a high-speed
I/O matrix is used to multiplex between various signals that may
connect to an I/O pin.
Document Number: 002-03288 Rev. *E
Page 7 of 33
PRELIMINARY
Power Systems Overview
Figure 3 shows an overview of the power system requirement for
CCG3. CCG3 shall be able to operate from two possible external
supply sources VBUS (4.0 V–21.5 V) or VSYS (2.7 V–5.5 V). The
VBUS supply is regulated inside the chip with a low-dropout
regulator (LDO) down to 3.3 V level. The chip’s internal VDDD rail
is intelligently switched between the output of the VBUS regulator
and unregulated VSYS. The switched supply, VDDD is either used
directly inside some analog blocks or further regulated down to
VCCD which powers majority of the core using regulators.
EZ-PD™ CCG3
Besides Reset mode, CCG3 has three different power modes:
Active, Sleep and Deep Sleep, transitions between which are
managed by the Power System. A separate power domain VDDIO
is provided for the GPIOs. The VDDD and VCCD pins, both the
output of regulators are brought out for connecting a 1-µF
capacitor for the regulator stability only. These pins are not
supported as power supplies. When CCG3 is powered from
VSYS that is greater than 3.3 V, the dedicated USB regulator
allows USB operation.
Figure 3. EZ-PD CCG3 Power System Block Diagram
VSYS
1uF
Switch
VBUS
LDO
VBUS_P
OC
VBUS_P_CTRL
VCONN
VBUS_DISCHARGE
OVP
OCP
RA
VDDIO
VSS
VBUS_C_CTRL
USB Regulator
Regulator
GPIO
Gate Driver
VDDD
Gate Driver
VCCD
1uF
1uF
Core
FS-USB
TX/RX
CC
Tx/Rx
1uF
DP, DM
CC1, CC2
VSS
CCG3
Table 1. CCG3 Power Modes
Mode
Description
RESET
Power is Valid and XRES is not asserted. An internal reset source is asserted or SleepController
is sequencing the system out of reset.
ACTIVE
Power is Valid and CPU is executing instructions.
SLEEP
Power is Valid and CPU is not executing instructions. All logic that is not operating is clock gated
to save power.
DEEP SLEEP
Main regulator and most hard-IP are shut off. DeepSleep regulator powers logic, but only
low-frequency clock is available.
Document Number: 002-03288 Rev. *E
Page 8 of 33
PRELIMINARY
EZ-PD™ CCG3
Pinouts
Table 2. CCG3 Pin Description for 42-CSP and 40-QFN Devices
Pin Map 42-CSP Pin Map 40-QFN
A5
Name
Description
1
VBUS_P_CTRL1
VBUS Gate Driver Control 1 for Producer Switch
A6
2
VBUS_P_CTRL0
B6
3
CC2
USB PD connector detect/Configuration Channel 2
C5
N/A
CC2
USB PD connector detect/Configuration Channel 2
D4
4
V5V
5.0V – 5.5V supply for VCONN FETs
C6
5
CC1
USB PD connector detect/Configuration Channel 1
D6
N/A
CC1
USB PD connector detect/Configuration Channel 1
E6
6
VCONN
F6
7
P1.0
VBUS Gate Driver Control 0 for Producer Switch
VCONN Input - provides Ra termination for cable applications
GPIO/UART_2_TX / SPI_2_MISO
D5
8
P1.1
GPIO/UART_2_RX / SPI_2_SEL
E5
9
P1.2
GPIO/UART_0_RX/ UART_3_CTS/ SPI_3_MOSI/ I2C_3_SCL / HPD
G6
10
P1.3
GPIO/UART_0_TX/ UART_3_RTS/ SPI_3_CLK/ I2C_3_SDA
E4
11
AUX_P / P1.6
DisplayPort AUX_P signal / GPIO / UART_1_TX / SPI_1_MISO
F5
12
SBU1 / P1.4
USB Type-C SBU1 signal / GPIO / UART_3_TX/ SPI_3_MISO/
SWD_1_CLK
G5
13
SBU2 / P1.5
USB Type-C SBU2 signal / GPIO / UART_3_RX/ SPI_3_SEL/
SWD_1_DAT
G4
14
AUX_N / P1.7
DisplayPort AUX_N signal / GPIO / UART_1_RX / SPI_1_SEL
F4
15
P2.0
GPIO / UART_1_CTS / SPI_1_CLK/ I2C_1_SCL / SWD_0_DAT
GPIO / UART_1_RTS / SPI_1_MOSI/ I2C_1_SDA / SWD_0_CLK
G3
16
P2.1
G2
17
VDDD
VDDD Supply Input / Output (2.7 V–5.5 V)
F3
18
VDDIO
1.71 V–5.5 V supply for I/Os. This supply also powers the global analog
multiplex buses.
F2
19
VCCD
1.8V regulator output for filter capacitor
G1
20
VSYS
System Power Supply (2.7 V–5.5 V)
F1
21
DPLUS
USB 2.0 DP
E1
22
DMINUS
USB 2.0 DM
E2
23
P2.4
GPIO
D3
24
P2.5
GPIO / UART_0_TX/ SPI_0_MOSI
D2
25
P2.6
GPIO / UART_0_RX/ SPI_0_CLK
D1
26
XRES
C3
27
P0.0
I2C_0_SDA / GPIO_OVT / UART_0_CTS / SPI_0_SEL
C2
28
P0.1
I2C_0_SCL / GPIO_OVT / UART_0_RTS / SPI_0_MISO
C1
29
VBUS_C_CTRL1
C4
30
VBUS_C_CTRL0
B1
31
VBUS
A1
32
E3
33
VSS
EPAD
VSS
External Reset Input. Internally pulled-up to VDDIO.
VBUS Gate Driver Control 1 for Consumer Switch
VBUS Gate Driver Control 0 for Consumer Switch
VBUS Input (4 V–21.5 V)
VBUS_DISCHARGE VBUS Discharge Control output
Document Number: 002-03288 Rev. *E
Ground Supply (GND)
Page 9 of 33
PRELIMINARY
EZ-PD™ CCG3
Table 2. CCG3 Pin Description for 42-CSP and 40-QFN Devices (continued)
Pin Map 42-CSP Pin Map 40-QFN
Name
Description
A2
34
P3.2
B2
35
P3.3
GPIO
B3
36
P3.4
GPIO / UART_2_CTS / SPI_2_MOSI/ I2C_2_SDA
A3
37
P3.5
GPIO / UART_2_RTS / SPI_2_CLK/ I2C_2_SCL
B4
38
P3.6
GPIO
A4
39
OC
Over-current Sensor Input
B5
40
VBUS_P
VBUS Producer Input (4.0 V–21.5 V)
VBUS_P
OC
GPIO
GPIO
GPIO
GPIO
GPIO
GND
VBUS_DISCHARGE
VBUS
40
39
38
37
36
35
34
33
32
31
Figure 4. Pinout of 40-QFN Package (Top View)
VBUS_P_CTRL1
1
30
VBUS_C_CTRL0
VBUS_P_CTRL0
29
28
VBUS_C_CTRL1
CC2
2
3
V5V
CC1
4
5
27
26
GPIO_OVT
XRES
VCONN
GPIO
6
GPIO
GPIO
GPIO
8
25
24
23
GPIO
9
10
22
DMINUS
21
DPLUS
Document Number: 002-03288 Rev. *E
11
12
13
14
15
16
17
18
19
20
SBU1
SBU2
AUX_N
GPIO
GPIO
VDDD
VDDIO
VCCD
VSYS
7
AUX_P
GPIO
EPAD
GPIO_OVT
GPIO
Page 10 of 33
PRELIMINARY
EZ-PD™ CCG3
Figure 5. Pinout of 42-WLCSP Bottom (Balls Up) View
6
5
VBUS_P_CT VBUS_P_CT
RL0
RL1
4
3
2
1
OC
GPIO
P3.5
GPIO
P3.2
VBUS_DISC
HARGE
A
CC2
VBUS_P
GPIO
P3.6
GPIO
P3.4
GPIO
P3.3
VBUS
B
CC1
CC2
VBUS_C_CT
RL0
GPIO_OVT
P0.0
GPIO_OVT
P0.1
VBUS_C_CT
RL1
C
CC1
GPIO
P1.1
V5V
GPIO
P2.5
GPIO
P2.6
XRES
D
VCONN
GPIO
P1.2
AUX_P
VSS
GPIO
P2.4
DMINUS
E
GPIO
P1.0
SBU1
GPIO
P2.0
VDDIO
VCCD
DPLUS
F
GPIO
P1.3
SBU2
AUX_N
GPIO
P2.1
VDDD
VSYS
G
Document Number: 002-03288 Rev. *E
Page 11 of 33
PRELIMINARY
EZ-PD™ CCG3
Applications
Figure 6. Thunderbolt Cable Application Diagram
5V, 2A Load Switch
Default Load Switch is open
5V, 2A Load Switch
Default Load Switch is open
Type-C Plug
Type-C Plug
Switch & Diode
can be replaced by
an Ideal Diode
(5V, 500mA
capable)
1uF
10V
X7R
Regulator
A6
A5
P3.6 VBUS_P_CTRL1
D4
B1
B5
E6
CC2
C6
CC1
F5
SBU1
G5
SBU2
1uF
10V
X7R
1M
G2
F3
1uF
10V
X7R
F4
G3
VBUS_P_CTRL0
3.3V
LSTX
F6
D5
LSRX
LSRX
D5
CDR_GPIO_1
CDR_GPIO_1
C2
I2C_SCL/ P0.1
A2
P3.2
CDR_GPIO_2
CDR_GPIO_3
CDR_GPIO_2
CDR_GPIO_3
I2C_SDA/ P0.0
VCONN
CC1
VBUS_C_CTRL0
SBU1
VBUS_DISCHARGE
SBU2
CYPD3105-42FNXIT
42CSP
VDDD
LSTX
F6
C4
A1
A1
MUX_I2C_SCL
MUX_I2C_SDA
DMINUS
GPIO
GND
VCCD
1.3uF
10V
X7R
AUX_P
F2
E4
E1
CDR
CDR
1uF
10V
X7R
E3
1uF
10V
X7R
VCONN
CC1
SBU1
VBUS_DISCHARGE
CYPD3105-42FNXIT
42CSP
SBU2
VDDD
VDDIO
A4
OC
F1
DPLUS
MUX_I2C_SCL
E1
MUX_I2C_SDA
D1
D1
V5V
VBUS
VBUS_P
VBUS_C_CTRL0
B6 CC2
A4
OC
F1
DPLUS
VBUS_P_CTRL1 P3.6
UART_2_TX/P1,0
D6 CC1
C5 CC2
CC1 D6
B4
A5
VBUS_P_CTRL0
VBUS_C_CTRL1
UART_2_RX/P1.1
C3
I2C_SDA/ P0.0
C2
I2C_SCL/ P0.1
A2
P3.2
C4
CC2 C5
CC2 B6
VDDIO
A6
VSYS
C1
C1
C3
UART_2_TX/P1,0
UART_2_RX/P1.1
VBUS_P
G1
VSYS
VBUS_C_CTRL1
V5V
VBUS
Switch & Diode
can be replaced by
an Ideal Diode
(5V, 500mA
capable)
VCONN_S
W_CTRL
G1
XRES
A3, B2, B3, D2,
D3, E2, E5, G6
Regulator
3.3V
B4
1uF
10V
X7R
VCONN
VCONN
VCONN_S
W_CTRL
E3
DMINUS
D4
B1
B5
E6
CC2
C6
CC1
F5
SBU1
G5
G2
SBU2
1uF
10V
X7R
1M
F3
F4
1uF
10V
X7R
G3
XRES
GPIO
GND
AUX_N
AUX_N
G4
G4
AUX_P
E4
A3, B2, B3, D2,
D3, E2, E5, G6
VCCD
F2
1.3uF
10V
X7R
SSTX,
SSRX
SSTX,
SSRX
GND
GND
Figure 7. Power Adapter Application Diagram (40-QFN Device)
DC/DC
OR
AC-DC Secondary
(5-20V)
VBUS_OC
VBUS_IN
DMN3018SSD-13
D
10 m 1%
VBUS_OUT
DMN3018SSD-13
S
S
VBUS
D
G
G
10M
10uF
50V
10M
VSEL1 VSEL2
100
2
39
28
27
40
31
1uF
50V
X7R
33
X
20
17
18
1uF
10V
X7R
X
X
X
11
14
6
OC
VSEL2/P0.0
VBUS_P_CTRL0
VBUS_P_CTRL1
VSEL1/P0.1
VBUS_DISCHARGE
CC2 3
VBUS_P
CC1
VBUS
VBUS_C_CTRL1
GND
VSYS
VDDD
CYPD3135-40LQXIT
40QFN VBUS_C_CTRL0
V5V
VDDIO
P2.5
AUX_P
DPLUS
AUX_N
DMINUS
VCONN
GPIO
XRES
VCCD
26
19
1.3uF
10V
X7R
0.1uF
Document Number: 002-03288 Rev. *E
1
32
SBU1 SBU2
12
X
CC2
5
CC1
29
X
30 X
4
5V
VBUS_OUT
390pF
5%
X7R
390pF
5%
X7R
Type-C
Receptacle
100K
24
21
10K
DPLUS
22
DMINUS
7, 8, 9, 10, 15, 16, 23,
25, 34, 35, 36, 37, 38
13
X
GND
Page 12 of 33
PRELIMINARY
EZ-PD™ CCG3
Figure 8. Power Bank Application Diagram (40-QFN Device)
Consumer Path
D
10M
DMN3018SSD-13
D
1uF
35V
X7R
D
VBATT
7, 8, 15, 16, 23,
24, 25, 27, 28, 38
17
0.1uF
10V
0.1uF
10V
1uF
10V
18
2
10M
1
VBUS_C_CTRL1
VBUS
VBUS_C_CTRL0
GPIO
VBUS_DISCHARGE
VDDD
VDDIO
CYPD3121-40LQXIT
40QFN
CC1
DPLUS
13
GPIO/SBU2
X
36
32
DMINUS
CC2
5
6
CC1
X
11
X
I2C_SDA/GPIO
AUX_N/GPIO
14
X
XRES
VCCD
19
35
I2C_
I2C_
SCL/GPIO SDA/GPIO
10
9
GND
X
26
33
0.1uF
10V
X7R
1uF
10V
X7R
Document Number: 002-03288 Rev. *E
Discrete Ckts
to support
Legacy Charge
Source
SS
DP
DN
GND
From Power
Subsystem
CCG3
GPIO
Type-C
Receptacle
390pF
5%
X7R
22
AUX_P/GPIO
GPIO
390pF
5%
X7R
21
I2C_SCL/GPIO
GPIO
100
30
CC2 3
VCONN
34
29
VSYS
12
GPIO/SBU1
X
37
10uF
50V
G
VBUS_P_CTRL0 VBUS_P_CTRL1
4
V5V
X
31
VBUS
40
VBUS_P
20
1uF
10V
10M
D
10M
39
VBUS
G
DMN3018SSD-13
S
S
G
OC
0.1uF
10V
S
VBUS
Provider Path
10 m 1%
0.1uF
10V
S
G
Power
Subsystem
+
Battery
CCG3 gate driver control configuration
needs to be appropriately set, based
on the VBUS FET type (nFET/pFET).
DMN3018SSD-13
DMN3018SSD-13
VBUS
Type-A
Receptacle
DP
DN
GND
Page 13 of 33
PRELIMINARY
EZ-PD™ CCG3
Figure 9. DRP Application Diagram
VINT20
DMN3018SSD-13
DMN3018SSD-13
Charger
D
S
S
D
G
10M
G
10M
VBUS
VBUS_SUPPLY
DMN3018SSD-13
DC/DC
1uF
35V
X7R
10 m 1%
V3P3 and V5P0 are 3.3V and 5V
supplies coming from the motherboard.
CCG3 gate driver control configuration
needs to be appropriately set, based
on the VBUS FET type (nFET/pFET).
VBUS
4
31
40
V3P3
20
0.1uF
10V
0.1uF
10V
1uF
10V
7, 8, 15, 16, 23,
24, 25, 27, 28, 38
VDDD
0.1uF
10V
0.1uF
10V
17
18
1uF
10V
X
2.2K
2.2K
X
12
13
37
36
Embedded
Controller
USB
Chipset
DisplayPort
Chipset
D
34
D+/HPD
SS
10uF
50V
G
10M
10M
1
OC
VBUS_P_CTRL0 VBUS_P_CTRL1
V5V
VBUS_C_CTRL1
29
VBUS
VBUS_P
VBUS
VSYS
VBUS_C_CTRL0
GPIO
VBUS_DISCHARGE
VDDD
VDDIO
CYPD3125-40LQXIT
40QFN
SBU1
CC1
DPLUS
SBU2
DMINUS
I2C_SCL / P3.5
AUX_P
I2C_SDA / P3.4
AUX_N
I2C_INT / P3.2
XRES
HOTPLUG_
MUX_I2C_ MUX_I2C_ GND
DET / P3.3 VCCD SCL/P1.2 SDA/P1.3
19
35
10
9
1uF
10V
X7R
HPD
SCL
SDA
100
30
32
CC2 3
VCONN
VDDD
2.2K
S
S
G
2
39
V5P0
D
DMN3018SSD-13
CC2
5
6
CC1
390pF
5%
X7R
X
21
390pF
5%
X7R
Type-C
Receptacle
22
11
14
X
X
26
33
SS
0.1uF
10V
X7R
D+/-
DP/DN
GND
HS/SS/
DP/SBU
Lines
SS
DP0/1/2/3
AUX+/-
Document Number: 002-03288 Rev. *E
Data Mux
Page 14 of 33
PRELIMINARY
EZ-PD™ CCG3
Electrical Specifications
Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings
Parameter
Description
VSYS_MAX
Digital supply relative to VSS
Min
Typ
Max
Units
Details/Conditions
–0.5
–
6
V
Absolute max
V5V
Max supply voltage relative to VSS
–
–
6
V
Absolute max
VBUS_MAX
Max supply voltage relative to VSS
–
–
24
V
Absolute max
VDDIO_MAX
Max supply voltage relative to VSS
–
–
6
V
Absolute Max
VGPIO_ABS
GPIO voltage
–0.5
–
VDDIO + 0.5
V
Absolute max
IGPIO_ABS
Maximum current per GPIO
–25
–
25
mA
Absolute max
IGPIO_injection
GPIO injection current, Max for VIH >
VDDD, and Min for VIL < VSS
–0.5
–
0.5
mA
Absolute max, current injected
per pin
ESD_HBM
Electrostatic discharge human body
model
2200
–
–
V
–
ESD_CDM
Electrostatic discharge charged
device model
500
–
–
V
–
LU
Pin current for latch-up
–200
–
200
mA
–
ESD_IEC_CON Electrostatic discharge IEC61000-4-2
8000
–
–
V
Contact discharge on CC1, CC2,
VBUS, DPLUS, DMINUS, SBU1
and SBU2 pins
ESD_IEC_AIR
15000
–
–
V
Air discharge for CC1, CC2,
VBUS, DPLUS, DMINUS, SBU1
and SBU2 pins
Electrostatic discharge IEC61000-4-2
Device-Level Specifications
All specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted.
Table 4. DC Specifications
Description
Min
Typ
Max
Units
SID.PWR#1
Spec ID
VSYS
–
2.7
–
5.5
V
–40 °C to +85 °C TA. UFP Mode.
SID.PWR#1_A
VSYS
–
3
–
5.5
V
–40 °C to +85 °C TA.
DFP/DRP or Gate Driver Modes
SID.PWR#23
VCONN
Power Supply Input Voltage
2.7
–
5.5
V
–40 °C to +85 °C TA
SID.PWR#13
VDDIO
IO Supply Voltage
1.71
–
5.5[2]
V
–40 °C to +85 °C TA,
2.7V < VDDD < 5.5V
SID.PWR#13_A VDDIO
IO Supply Voltage for ADC
operation
2.7
–
5.5
V
–40 °C to +85 °C TA,
2.7V < VDDD < 5.5V
SID.PWR24
VCCD
Output Voltage for core Logic
–
1.8
–
V
SID.PWR#24_B VDDD
Output Voltage for VDDD Rail
2.7
–
5.5
V
SID.PWR#4
Parameter
IDD
Supply current
–
25
–
mA
Details/Conditions
–
All values of VSYS and VBUS
FROM VSYS or VBUS
VBUS = 5V,
TA = 25 °C / VSYS = 5V, TA = 25 °C
FS USB, CC IO in Tx or Rx, no I/O
sourcing current, 2 SCBs at 1 Mbps,
CPU at 12 MHz
Note
2. If VDDIO > VDDD, GPIO P2.4 cannot be used. It must be left unconnected. See Tables 2 and 3 for pin numbers.
Document Number: 002-03288 Rev. *E
Page 15 of 33
PRELIMINARY
EZ-PD™ CCG3
Table 4. DC Specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID.PWR#1_B
VSYS
Power supply for USB operation
4.5
–
5.5
V
USB configured, USB Regulator
enabled
SID.PWR#1_C
VSYS
Power supply for USB operation
3.15
–
3.45
V
USB configured, USB Regulator
disabled
SID.PWR#1_D
VSYS
Power supply for charger
detect/emulation operation
3.15
–
5.5
V
–40 °C to +85 °C TA
SID.PWR#27
VBUS
Power Supply Input Voltage
4
–
21.5
V
–40 °C to +85 °C TA
SID.PwR#28
VBUS
Power Supply Input Voltage for
USB operation
4.5
–
21.5
V
USB configured, USB Regulator
disabled
SID.PWR#30
VBUS_P
Power Supply Input Voltage
4.00
–
21.5
V
–40 °C to +85 °C TA
SID.PWR#15
Cefc
External Regulator voltage
bypass for VCCD
1
1.3
1.6
µF
X5R ceramic or better
SID.PWR#16
Cexc
Power supply decoupling
capacitor for VSYS
0.8
1
–
µF
X5R ceramic or better
Sleep Mode. VSYS = 2.7 V to 5.5 V. Typical values measured at VDD = 3.3 V and TA = 25 °C.
SID25A
CC, I2C, WDT Wakeup on. IMO
at 48 MHz.
–
3.5
–
mA
VSYS = 3.3V, TA = 25 °C, All blocks
except CPU are on, CC IO on, USB
in Suspend Mode, no I/O sourcing
current
IDD_DS
VSYS = 3.0 to 3.6V. CC Attach,
I2C, WDT Wakeup on.
–
30
–
µA
Power Source = VSYS, DFP Mode,
Type-C Not Attached. CC Attach,
I2C and WDT enabled for Wakeup.
IDD_XR
Supply current while XRES
asserted
This does not include current
drawn due to the XRES’ internal
pull-up resistor.
–
30
–
µA
Power Source = VSYS = 3.3V,
Type-C device not attached,
TA = 25 °C
IDD20A
Deep Sleep Mode
SID_DS
XRES Current
SID307
Table 5. AC Specifications
Spec ID
SID.CLK#4
Parameter
FCPU
Description
Typ Max Units
Details/Conditions
DC
–
48
SID.PWR#20 TSLEEP
Wakeup from sleep mode
–
0
–
µs
SID.PWR#21 TDEEPSLEEP
Wakeup from Deep Sleep mode
–
–
35
µs
–
SID.XRES#5 TXRES
External reset pulse width
5
–
–
µs
–40 °C to +85 °C TA, all VDDIO
SYS.FES#1
Power-up to “Ready to accept I2C/CC
command”
–
5
25
ms
–
T_PWR_RDY
CPU input frequency
Min
Document Number: 002-03288 Rev. *E
MHz –40 °C to +85 °C TA, all VDDD
–
Page 16 of 33
PRELIMINARY
EZ-PD™ CCG3
I/O
Table 6. I/O DC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID.GIO#37 VIH_CMOS
Input voltage HIGH threshold 0.7 × VDDIO
–
–
V
CMOS input
SID.GIO#38 VIL_CMOS
Input voltage LOW threshold
–
–
0.3 × VDDIO
V
CMOS input
SID.GIO#39 VIH_VDDIO2.7-
LVTTL input, VDDIO < 2.7 V
0.7× VDDIO
–
–
V
–
SID.GIO#40 VIL_VDDIO2.7-
LVTTL input, VDDIO < 2.7 V
–
–
0.3 × VDDIO
V
–
2.0
–
–
V
–
–
SID.GIO#41 VIH_VDDIO2.7+ LVTTL input, VDDIO 2.7 V
SID.GIO#42 VIL_VDDIO2.7+
LVTTL input, VDDIO 2.7 V
–
–
0.8
V
SID.GIO#33 VOH_3V
Output voltage HIGH level
VDDIO –0.6
–
–
V
IOH = 4 mA at 3V VDDIO
SID.GIO#34 VOH_1.8V
Output voltage HIGH level
VDDIO –0.5
–
–
V
IOH = 1 mA at 1.8V VDDIO
SID.GIO#35 VOL_1.8V
Output voltage LOW level
–
–
0.6
V
IOL = 4 mA at 1.8V VDDIO
SID.GIO#36 VOL_3V
Output voltage LOW level
–
–
0.6
V
IOL = 10 mA (IOL_LED) at 3 V
VDDIO
SID.GIO#5
RPU
Pull-up resistor value
3.5
5.6
8.5
k
+25 °C TA, all VDDIO
SID.GIO#6
RPD
Pull-down resistor value
3.5
5.6
8.5
k
+25 °C TA, all VDDIO
–
–
2
nA
+25 °C TA, all VDDIO.
Guaranteed by
characterization.
SID.GIO#16 IIL
Input leakage current
(absolute value)
SID.GIO#17 CPIN
Max pin capacitance
–
3.0
7
pF
–40 °C to +85 °C TA, all
VDDIO, all package, all IOS.
Guaranteed by
characterization.
SID.GIO#43 VHYSTTL
Input hysteresis, LVTTL
VDDIO 2.7 V
15
40
–
mV
Guaranteed by
characterization
SID.GIO#44 VHYSCMOS
Input hysteresis CMOS
0.05 × VDDIO
–
–
mV
VDDIO < 4.5V. Guaranteed
by characterization.
SID69
Current through protection
diode to VDDIO/Vss
–
–
100
µA
Guaranteed by
characterization
Maximum total sink chip
current
–
–
85
mA
Guaranteed by
characterization
IDIODE
SID.GIO#45 ITOT_GPIO
Table 7. I/O AC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ Max Units
Details/Conditions
SID70
TRISEF
Rise time in Fast Strong mode
2
–
12
ns
3.3V VDDIO, Cload = 25 pF
SID71
TFALLF
Fall time in Fast Strong mode
2
–
12
ns
3.3V VDDIO, Cload = 25 pF
Document Number: 002-03288 Rev. *E
Page 17 of 33
PRELIMINARY
EZ-PD™ CCG3
XRES
Table 8. XRES DC Specifications
Spec ID
Parameter
Description
Min
Max
Units
–
–
V
CMOS input
–
0.3 × VDDIO
V
CMOS input
SID.XRES#2 VIL_XRES
Input voltage HIGH threshold
0.7 × VDDIO
on XRES pin
Input voltage LOW threshold on
–
XRES pin
SID.XRES#3 CIN_XRES
Input capacitance on XRES pin
–
–
7
pF
SID.XRES#4 VHYSXRES
Input voltage hysteresis on
XRES pin
–
0.05 × VDDIO
–
mV
SID.XRES#1 VIH_XRES
Details/
Conditions
Typ
Guaranteed by
characterization
Guaranteed by
characterization
Digital Peripherals
The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.
Pulse Width Modulation (PWM) for GPIO Pins
Table 9. PWM AC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
SID.TCPWM.3
TCPWMFREQ Operating frequency
SID.TCPWM.4
SID.TCPWM.5
Min
Typ
Max
Units
Details/Conditions
Fc max = CLK_SYS.
Maximum = 48 MHz
For all trigger events
Minimum possible width of
Overflow, Underflow, and CC
(Counter equals Compare
value) outputs
Minimum time between
successive counts
Minimum pulse width of PWM
output
Minimum pulse width between
quadrature-phase inputs
–
–
Fc
MHz
TPWMENEXT Input trigger pulse width
2/Fc
–
–
ns
TPWMEXT
Output trigger pulse width
2/Fc
–
–
ns
SID.TCPWM.5A TCRES
Resolution of counter
1/Fc
–
–
ns
SID.TCPWM.5B PWMRES
PWM resolution
1/Fc
–
–
ns
SID.TCPWM.5C QRES
Quadrature inputs resolution
1/Fc
–
–
ns
Min
Typ
Max
Units
Details/Conditions
I2C
Table 10. Fixed I2C DC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
SID149
II2C1
Block current consumption at 100 kHz
–
–
60
µA
–
SID150
II2C2
Block current consumption at 400 kHz
–
–
185
µA
–
SID151
II2C3
Block current consumption at 1 Mbps
–
–
390
µA
–
II2C4
I2C
–
–
1.4
µA
–
Min
Typ
Max
Units
Details/Conditions
–
–
1
Mbps
–
SID152
enabled in Deep Sleep mode
Table 11. Fixed I2C AC Specifications
(Guaranteed by Characterization)
Spec ID
SID153
Parameter
FI2C1
Description
Bit rate
Document Number: 002-03288 Rev. *E
Page 18 of 33
PRELIMINARY
EZ-PD™ CCG3
Table 12. Fixed UART DC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
–
–
125
µA
–
–
–
312
µA
–
Description
Min
Typ
Max
Units
Details/Conditions
Bit rate
–
–
1
Mbps
–
SID160
IUART1
Block current consumption at
100 Kbits/sec
SID161
IUART2
Block current consumption at
1000 Kbits/sec
Table 13. Fixed UART AC Specifications
(Guaranteed by Characterization)
Spec ID
SID162
Parameter
FUART
Table 14. Fixed SPI DC Specifications
(Guaranteed by Characterization)
Description
Min
Typ
Max
Units
Details/Conditions
SID163
Spec ID
ISPI1
Parameter
Block current consumption at 1 Mbit/sec
–
–
360
µA
–
SID164
ISPI2
Block current consumption at 4 Mbits/sec
–
–
560
µA
–
SID165
ISPI3
Block current consumption at 8 Mbits/sec
–
–
600
µA
–
Table 15. Fixed SPI AC Specifications
(Guaranteed by Characterization)
Spec ID
SID166
Parameter
FSPI
Description
Min
Typ
Max
Units
Details/Conditions
SPI Operating frequency (Master; 6X
oversampling)
–
–
8
MHz
–
Table 16. Fixed SPI Master Mode AC Specifications
(Guaranteed by Characterization)
Description
Min
Typ
Max
Units
Details/Conditions
SID167
Spec ID
TDMO
Parameter
MOSI Valid after SClock driving edge
–
–
15
ns
–
SID168
TDSI
MISO Valid before SClock capturing
edge
20
–
–
ns
Full clock, late MISO
sampling
SID169
THMO
Previous MOSI data hold time
0
–
–
ns
Referred to Slave capturing
edge
Document Number: 002-03288 Rev. *E
Page 19 of 33
PRELIMINARY
EZ-PD™ CCG3
Table 17. Fixed SPI Slave Mode AC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
40
–
–
ns
–
SID170
TDMI
MOSI Valid before Sclock capturing
edge
SID171
TDSO
MISO Valid after Sclock driving edge
–
–
42 + 3 × TCPU
ns
SID171A
TDSO_EXT
MISO Valid after Sclock driving edge
in Ext Clk mode
–
–
48
ns
–
SID172
THSO
Previous MISO data hold time
SID172A
TSSELSCK
SSEL Valid to first SCK Valid edge
TCPU = 1/FCPU
0
–
–
ns
–
100
–
–
ns
–
Min
Typ
System Resources
Power-on-Reset (POR) with Brown Out SWD Interface
Table 18. Imprecise Power On Reset (PRES)
Spec ID
Parameter
Description
SID185
VRISEIPOR
Power-on Reset (POR) rising trip
voltage
SID186
VFALLIPOR
POR falling trip voltage
Max
Units
Details/Conditions
0.80
–
1.50
V
Guaranteed by
characterization
0.70
–
1.4
V
Guaranteed by
characterization
Min
Typ
Max
Units
Table 19. Precise Power On Reset (POR)
Spec ID
Parameter
Description
SID190
VFALLPPOR
Brown-out Detect (BOD) trip voltage
in active/sleep modes
SID192
VFALLDPSLP
BOD trip voltage in Deep Sleep mode
Details/Conditions
1.48
–
1.62
V
Guaranteed by
characterization
1.1
–
1.5
V
Guaranteed by
characterization
Min
Typ
Max
Units
Details/Conditions
Table 20. SWD Interface Specifications
Spec ID
Parameter
Description
SID.SWD#1
F_SWDCLK1
3.3 V VDDIO 5.5 V
–
–
14
MHz
SWDCLK 1/3 CPU clock
frequency
SID.SWD#2
F_SWDCLK2
1.8 V VDDIO 3.3 V
–
–
7
MHz
SWDCLK 1/3 CPU clock
frequency
SID.SWD#3
T_SWDI_SETUP T = 1/f SWDCLK
0.25 × T
–
–
ns
Guaranteed by
characterization
SID.SWD#4
T_SWDI_HOLD
0.25 × T
–
–
ns
Guaranteed by
characterization
SID.SWD#5
T_SWDO_VALID T = 1/f SWDCLK
–
–
0.50 × T
ns
Guaranteed by
characterization
SID.SWD#6
T_SWDO_HOLD T = 1/f SWDCLK
1
–
–
ns
Guaranteed by
characterization
T = 1/f SWDCLK
Document Number: 002-03288 Rev. *E
Page 20 of 33
PRELIMINARY
EZ-PD™ CCG3
Internal Main Oscillator
Table 21. IMO DC Specifications
(Guaranteed by Design)
Spec ID
SID218
Parameter
IIMO1
Description
IMO operating current at 48 MHz
Min
Typ
Max
Units
Details/Conditions
–
–
1000
µA
–
Min
Typ
Max
Units
Details/Conditions
Table 22. IMO AC Specifications
Spec ID
Parameter
Description
SID.CLK#13
FIMOTOL
Frequency variation at 24, 36, and
48 MHz (trimmed)
–
–
±2
%
–25 °C TA 85 °C, all VDDD
SID226
TSTARTIMO
IMO start-up time
–
–
7
µs
Guaranteed by
characterization
SID229
TJITRMSIMO2
RMS jitter at 24 MHz
–
145
–
ps
Guaranteed by
characterization
SID.CLK#1
FIMO
IMO frequency
24
–
48
Min
Typ
Max
MHz –40 °C to +85 °C TA, all VDDD
Internal Low-Speed Oscillator
Table 23. ILO DC Specifications
(Guaranteed by Design)
Spec ID
Parameter
Description
Units
Details/Conditions
SID231
IILO1
ILO operating current
–
0.3
1.05
µA
Guaranteed by
characterization
SID233
IILOLEAK
ILO leakage current
–
2
15
nA
Guaranteed by
design
Min
Typ
Max
Units
Table 24. ILO AC Specifications
Spec ID
Parameter
Description
Details/Conditions
SID234
TSTARTILO1
ILO start-up time
–
–
2
ms
Guaranteed by
characterization
SID238
TILODUTY
ILO duty cycle
40
50
60
%
Guaranteed by
characterization
SID.CLK#5
FILO
ILO frequency
20
40
80
kHz
Document Number: 002-03288 Rev. *E
–
Page 21 of 33
PRELIMINARY
EZ-PD™ CCG3
Power Down
Table 25. PD DC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID.PD.1
Rp_std
DFP CC termination for default USB
Power
64
80
96
µA
–
SID.PD.2
Rp_1.5A
DFP CC termination for 1.5A power
166
180
194
µA
–
SID.PD.3
Rp_3.0A
DFP CC termination for 3.0A power
304
330
356
µA
–
SID.PD.4
Rd
UFP CC termination
4.59
5.1
5.61
kΩ
–
SID.PD.5
Rd_DB
UFP Dead Battery CC termination on
CC1 and CC2
4.08
5.1
6.12
kΩ
UFP Dead Battery CC
termination on CC1 and CC2.
SID.PD.6
RA
EMCA cable termination
0.8
1.0
1.2
kΩ
All supplies forced to 0 V and
0.2 V applied at VCONN
SID.PD.7
Ra_OFF
EMCA cable termination - Disabled
0.4
0.75
–
MΩ
2.7 V applied at VCONN with
RA disabled
SID.PD.8
Rleak_1
VCONN leaker for 0.1-µF load
–
–
216
kΩ
SID.PD.9
Rleak_2
VCONN leaker for 0.5-µF load
–
–
41.2
kΩ
SID.PD.10
Rleak_3
VCONN leaker for 1.0-µF load
–
–
19.6
kΩ
SID.PD.11
Rleak_4
VCONN leaker for 2.0-µF load
–
–
9.8
kΩ
SID.PD.12
Rleak_5
VCONN leaker for 5.0-µF load
–
–
4.1
kΩ
SID.PD.13
Rleak_6
VCONN leaker for 10-µF load
–
–
2.0
kΩ
SID.PD.14
Ileak
Leaker on VCONN for discharge upon
cable detach
150
–
–
µA
SID.PD.15
Vgndoffset
Ground offset tolerated by BMC
receiver
–400
–
400
mV
Document Number: 002-03288 Rev. *E
Managed Active Cable (MAC)
discharge
–
Relative to the remote BMC
transmitter
Page 22 of 33
PRELIMINARY
EZ-PD™ CCG3
SBU
Table 26. Analog Crossbar Switch Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID.SBU.1
Ron_sw
Switch ON Resistance
–
–
10
Ω
Voltage input from 0 V to
3.6 V
SID.SBU.2
Rpu_aux_1
AUX_P/N Pull-up Resistance –
100k
80
–
120
kΩ
–
SID.SBU.3
Rpu_aux_2
AUX_P/N Pull-up Resistance –
1M
0.8
–
1.2
MΩ
–
SID.SBU.4
Rpd_aux_1
AUX_P/N Pull-down Resistance
– 100k
80
–
120
kΩ
–
SID.SBU.5
Rpd_aux_2
AUX_P/N Pull-down Resistance
– 1M
0.8
–
1.2
MΩ
–
SID.SBU.6
Rpd_aux_3
AUX_P/N Pull-down Resistance
– 470k
329
–
611
kΩ
–
SID.SBU.7
Rpd_aux_4
AUX_P/N Pull-down Resistance
– 4.7M
3.29
–
6.11
MΩ
–
Charger Detect
Table 27. Charger Detect Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
–
SID.CD.1
VDAT_REF
BC1.2 Data Detect Voltage
Threshold
250
–
400
mV
SID.CD.2
VDM_SRC
BC1.2 DM Voltage Source
500
–
700
mV
With current sink of
25 µA–175 µA
SID.CD.3
VDP_SRC
BC1.2 DP Voltage Source
500
–
700
mV
With current sink of
25 µA–175 µA
SID.CD.4
IDM_SINK
BC1.2 DM Current Sink
25
–
175
µA
SID.CD.5
IDP_SINK
BC1.2 DP Current Sink
25
–
175
µA
–
SID.CD.6
IDP_SRC
BC1.2 DP DCD Current Source
7
–
13
µA
–
SID.CD.7
RDP_UP
USB FS DP Pull-up Termination
0.9
–
1.575
kΩ
–
SID.CD.8
RDM_UP
USB FS DM Pull-up Termination
0.9
–
1.575
kΩ
–
SID.CD.9
RDP_DWN
USB FS DP Pull-down
Termination
14.25
–
24.8
kΩ
–
SID.CD.10
RDM_DWN
USB FS DM Pull-down
Termination
14.25
–
24.8
kΩ
–
SID.CD.11
RDAT_LKG
DP/DM Data Line Leakage
Termination
300
–
500
kΩ
The charger detect function
and data line leakage is
enabled.
SID.CD.12
RDCP_DAT
BC1.2 DCP Port Resistance
between DP and DM
–
–
40
Ω
–
SID.CD.13
VSETH
USB FS Logic Threshold
1.28
–
1.54
V
–
Document Number: 002-03288 Rev. *E
–
Page 23 of 33
PRELIMINARY
EZ-PD™ CCG3
Analog to Digital Converter
Table 28. ADC DC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
–
8
–
bits
Guaranteed by
characterization
SID.ADC.1
Resolution
ADC resolution
SID.ADC.2
INL
Integral non-linearity
–1.5
–
1.5
LSB
Guaranteed by
characterization
SID.ADC.3
DNL
Differential non-linearity
–2.5
–
2.5
LSB
Guaranteed by
characterization
SID.ADC.4
Gain Error
Gain error
–1
–
1
LSB
Guaranteed by
characterization
Min
Typ
Max
Units
Table 29. ADC AC Specifications
Spec ID
SID.ADC.5
Parameter
SLEW_Max
Description
Rate of change of sampled voltage
signal
Document Number: 002-03288 Rev. *E
–
–
3
Details/Conditions
Guaranteed by
V/ms
characterization
Page 24 of 33
PRELIMINARY
EZ-PD™ CCG3
Ordering Information
Table 30 lists the EZ-PD CCG3 part numbers and features.
Table 30. EZ-PD CCG3 Ordering Information
Part Number
Application
Termination Resistor
Role
Package
Si ID
EMCA
42-CSP
1D01
Thunderbolt Active Cable
RA[3]
CYPD3126-42FNXIT
DRP
DRP
42-CSP
1D07
CYPD3120-40LQXIT
Dongle
UFP
40-QFN
1D00
CYPD3121-40LQXIT
Monitor/Dock (UFP),
Power Banks
RP, RD[4], RD_DB
RP, RD[4], RD_DB
RP[5], RD, RD_DB[6]
UFP
40-QFN
1D02
CYPD3122-40LQXIT
Monitor/Dock (DFP)
RP, RD, RD_DB
DFP
40-QFN
1D03
CYPD3125-40LQXIT
Notebooks, Smartphones RP, RD, RD_DB
DRP
40-QFN
1D04
CYPD3135-40LQXIT
Power Adapter
DFP
40-QFN
1D05
CYPD3105-42FNXIT
RP
Ordering Code Definitions
CY PD
X
X XX -
XX XX
X X X
T = Tape and Reel
Temperature Grade:
I = Industrial (–40 °C - 85 °C), Q = Extended industrial (–40 °C - 105 °C)
Lead: X = Pb-free
Package Type: FN = CSP; LQ = QFN
Number of pins in the package
Application and Feature Combination Designation
Number of Type-C Ports: 1 = 1 Port, 2 = 2 Port
Product Type: 3 = Third-generation product family, CCG3
Marketing Code: PD = Power Delivery product family
Company ID: CY = Cypress
Notes
3. Termination resistor denoting an EMCA.
4. Termination resistor denoting an upstream facing port.
5. Termination resistor denoting a downstream facing port.
6. Termination resistor denoting dead battery termination.
Document Number: 002-03288 Rev. *E
Page 25 of 33
PRELIMINARY
EZ-PD™ CCG3
Package Diagrams
Figure 10. 40-pin QFN Package Outline, 001-80659
001-80659 *A
Figure 11. 42-ball CSP Package Outline, 002-04062
002-04062 *A
Document Number: 002-03288 Rev. *E
Page 26 of 33
PRELIMINARY
Acronyms
Table 31. Acronyms Used in this Document (continued)
Table 31. Acronyms Used in this Document
Acronym
EZ-PD™ CCG3
Description
ADC
analog-to-digital converter
AES
advanced encryption standard
AHB
AMBA (advanced microcontroller bus
architecture) high-performance bus
Acronym
Description
NC
no connect
NMI
nonmaskable interrupt
NVIC
nested vectored interrupt controller
opamp
operational amplifier
OCP
overcurrent protection
application programming interface
OVP
overvoltage protection
advanced RISC machine, a CPU architecture
PCB
printed circuit board
BMC
Biphase Mark Code
PD
power delivery
CC
configuration channel
PGA
programmable gain amplifier
CCG3
Cable Controller Generation 3
PHY
physical layer
CPU
central processing unit
POR
power-on reset
CRC
cyclic redundancy check, an error-checking
protocol
PRES
precise power-on reset
CS
current sense
PSoC®
Programmable System-on-Chip™
DFP
downstream facing port
PWM
pulse-width modulator
RAM
random-access memory
DIO
digital input/output, GPIO with only digital capabilities, no analog. See GPIO.
API
ARM
®
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RX
receive
DRP
dual role port
EEPROM
electrically erasable programmable read-only
memory
electronically marked cable assembly, a USB
cable that includes an IC that reports cable
characteristics (e.g., current rating) to the Type-C
ports
SAR
successive approximation register
EMCA
SCB
serial communication block
SCL
I2C serial clock
EMI
electromagnetic interference
SDA
I2C serial data
ESD
electrostatic discharge
S/H
sample and hold
FS
full-speed
SHA
secure hash algorithm
GPIO
general-purpose input/output
HPD
hot plug detect
SPI
Serial Peripheral Interface, a communications
protocol
IC
integrated circuit
SRAM
static random access memory
IDE
integrated development environment
SWD
serial wire debug, a test protocol
I2C, or IIC
Inter-Integrated Circuit, a communications
protocol
TCPWM
timer/counter pulse-width modulator
ILO
internal low-speed oscillator, see also IMO
Thunderbolt
Trademark of Intel
IMO
internal main oscillator, see also ILO
TX
transmit
IOSS
input/output subsystem
I/O
input/output, see also GPIO
Type-C
a new standard with a slimmer USB connector and
a reversible cable, capable of sourcing up to
100 W of power
LDO
low-dropout regulator
LVD
low-voltage detect
UART
Universal Asynchronous Transmitter Receiver, a
communications protocol
LVTTL
low-voltage transistor-transistor logic
MCU
microcontroller unit
MMIO
memory mapped input/output
Document Number: 002-03288 Rev. *E
USB
Universal Serial Bus
USB PD
USB Power Delivery
USB-FS
USB Full-Speed
Page 27 of 33
PRELIMINARY
Table 31. Acronyms Used in this Document (continued)
Acronym
USBIO
Description
USB input/output, CCG2 pins used to connect to
a USB port
Document Conventions
Units of Measure
Table 32. Units of Measure
Symbol
USBPD SS USB PD subsystem
XRES
external reset I/O pin
Document Number: 002-03288 Rev. *E
EZ-PD™ CCG3
Unit of Measure
°C
degrees Celsius
Hz
hertz
KB
1024 bytes
kHz
kilohertz
k
kilo ohm
Mbps
megabits per second
MHz
megahertz
M
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
V
volt
Page 28 of 33
PRELIMINARY
EZ-PD™ CCG3
Document History Page
Document Title: EZ-PD™ CCG3 USB Type-C Port Controller
Document Number: 002-03288
Revision
ECN
Orig. of
Change
Submission
Date
**
4905678
VGT
09/11/2015
New data sheet.
*A
4953333
VGT
10/08/2015
Updated General Description:
Updated the number of GPIOs to 20.
Updated Functional Overview:
Updated GPIO:
Updated the number of GPIOs to 20.
Updated Pinouts:
Updated Table 2.
Updated Figure 4.
Added Figure 5.
*B
5007726
VGT
11/25/2015
Changed status from Advance to Preliminary.
Updated Features.
Added EZ-PD CCG3 Block Diagram.
Updated Functional Overview:
Updated USB-PD Subsystem (SS) (Updated description).
Added Full-Speed USB Subsystem.
Updated Pinouts:
Updated Table 2.
Updated Figure 4.
Updated Figure 5.
Added Applications.
Document Number: 002-03288 Rev. *E
Description of Change
Page 29 of 33
PRELIMINARY
EZ-PD™ CCG3
Document History Page (continued)
Document Title: EZ-PD™ CCG3 USB Type-C Port Controller
Document Number: 002-03288
Revision
ECN
Orig. of
Change
Submission
Date
*B (cont.)
5007726
VGT
11/25/2015
Updated Electrical Specifications:
Updated Absolute Maximum Ratings:
Updated Table 3.
Updated Device-Level Specifications:
Updated Table 4.
Updated Table 5.
Updated I/O:
Updated Table 6.
Updated XRES:
Updated Table 8.
Updated System Resources:
Updated Power-on-Reset (POR) with Brown Out SWD Interface:
Updated Table 18.
Updated Table 19.
Updated Table 20.
Updated Internal Main Oscillator:
Updated Table 22.
Updated Internal Low-Speed Oscillator:
Updated Table 23.
Updated Table 24.
Updated Power Down:
Updated Table 25.
Updated Analog to Digital Converter:
Updated Table 28.
Updated Table 29.
Updated Package Diagrams:
Added Figure 11 (spec 002-04062 *A).
*C
5080470
VGT
01/11/2016
Updated General Description.
Updated Features.
Updated Logic Block Diagram.
Updated Power Systems Overview.
Updated Pinouts:
Updated Table 2.
Added table “CCG3 Pin Description for 16-SOIC Device”.
Added figure “Pinout of 16-SOIC Package (Top View)”.
Updated Applications:
Updated Figure 6.
Updated Figure 7.
Updated figure “Power Adapter Application Diagram (16-SOIC Device)”.
Updated Figure 9.
Updated Ordering Information.
Updated Package Diagrams:
Added spec 51-85022 *E.
Added Errata.
Document Number: 002-03288 Rev. *E
Description of Change
Page 30 of 33
PRELIMINARY
EZ-PD™ CCG3
Document History Page (continued)
Document Title: EZ-PD™ CCG3 USB Type-C Port Controller
Document Number: 002-03288
Revision
ECN
Orig. of
Change
Submission
Date
*D
5137796
VGT
03/09/2016
Updated Pinouts:
Updated table “CCG3 Pin Description for 16-SOIC Device”.
Updated figure “Pinout of 16-SOIC Package (Top View)”.
Updated Applications:
Updated Figure 7.
Updated Figure 8.
Updated Ordering Information
Updated Errata.
Updated to new template.
*E
5240836
VGT
04/28/2016
Updated General Description:
Updated description.
Updated Features:
Updated Type-C and USB-PD Support:
Updated description.
Updated Packages:
Updated description.
Updated Logic Block Diagram.
Updated Functional Overview:
Updated Integrated Billboard Device:
Updated description.
Updated USB-PD Subsystem (SS):
Updated description.
Added Figure 2.
Updated Power Systems Overview:
Updated description.
Updated Figure 3.
Updated Pinouts:
Updated Table 2:
Updated details in “Description” column corresponding to VDDIO pin.
Removed table “CCG3 Pin Description for 16-SOIC Device”.
Removed figure “Pinout of 16-SOIC Package (Top View)”.
Updated Applications:
Removed figure “Power Adapter Application Diagram (16-SOIC Device)”.
Added Figure 8.
Document Number: 002-03288 Rev. *E
Description of Change
Page 31 of 33
PRELIMINARY
EZ-PD™ CCG3
Document History Page (continued)
Document Title: EZ-PD™ CCG3 USB Type-C Port Controller
Document Number: 002-03288
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
*E (cont.)
5240836
VGT
04/28/2016
Updated Electrical Specifications:
Updated Device-Level Specifications:
Updated Table 4.
Updated details in “Details/Conditions” column corresponding to
“SID.PWR#1_A” Spec ID and “VSYS” parameter.
Replaced “VDDD” with “5.5” in “Max” column corresponding to “SID.PWR#13”
Spec ID and “VDDIO” parameter.
Added “SID.PWR#13_A” Spec ID corresponding to “VDDIO” parameter and its
details.
Added “SID.PWR#1_C” and “SID.PWR#1_D” Spec IDs corresponding to
“VSYS” parameter and its details.
Replaced “enabled” with “disabled” in “Details/Conditions” column
corresponding to “SID.PwR#28” Spec ID and “VBUS” parameter.
Updated details in “Description” and “Details/Conditions” columns
corresponding to “SID307” Spec ID and “IDD_XR” parameter.
Updated System Resources:
Added SBU.
Added Charger Detect.
Updated Ordering Information:
Updated part numbers.
Updated details in “Application” column corresponding to part number
“CYPD3121-40LQXIT”.
Updated Ordering Code Definitions.
Updated Package Diagrams:
Removed spec 51-85022 *E.
Removed Errata.
Document Number: 002-03288 Rev. *E
Page 32 of 33
PRELIMINARY
EZ-PD™ CCG3
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC
cypress.com/psoc
Touch Sensing
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/support
cypress.com/touch
USB Controllers
Wireless/RF
cypress.com/psoc
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation 2015-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify
and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right
to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software
is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any
component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole
or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify
and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-03288 Rev. *E
Revised April 28, 2016
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