EZ-PD CCG4M USB Type-C Port Controller with Mux Datasheet.pdf

PRELIMINARY
EZ-PD™ CCG4M
USB Type-C Dual Port Controller with
USB 3.1 Gen 1/DP1.2 Mux
General Description
EZ-PD™ CCG4M is a USB Type-C dual port controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG4M
provides a complete dual USB Type-C and USB-Power Delivery port control solution for notebooks and PCs. EZ-PD CCG4M uses
Cypress’s proprietary M0S8 technology with a 32-bit, 48-MHz ARM® Cortex®-M0 processor with 128-KB flash and integrates two
complete Type-C Transceivers including the Type-C termination resistors RP and RD as well as a 6:4 mux for USB 3.0 and DisplayPort
signals.
Applications
■
Type-C Support
■
Notebooks and PCs
■
Features
■
32-bit MCU Subsystem
■
48-MHz ARM Cortex-M0 CPU
■ 128-KB Flash
■ 8-KB SRAM
■ In-system reprogrammable
■
Low-Power Operation
■
■
■
Integrated Digital Blocks
Four integrated timers or counters to meet response times
required by the USB-PD protocol
■ Four run-time serial communication blocks (SCBs) with
reconfigurable I2C, SPI, or UART functionality
■
2.7-V to 5.5-V operation
Integrated VCONN FETs to power EMCA cables
Independent supply voltage pin for GPIO that allows 1.71-V to
5.5-V signaling on the I/Os
System-Level ESD on CC Pins
■
± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based
on IEC61000-4-2 level 4C
Hot Swappable I/Os
Integrated 6:4 Mux
Six differential channels to 4 differential channels
Multiplexes USB 3.0 (5 Gbps) and DisplayPort 1.2 (5.4 Gbps)
signals to the USB Type-C connector
■ With DisplayPort 1.2, AUX signals are multiplexed to SBU pins
■
■
■
Port 1 I2C pins and CC1, CC2 pins are hot-swappable
Packages
■
■
Clocks and Oscillators
■
Two integrated transceivers (baseband PHY)
Integrated UFP (RD) and current sources for DFP (RP) on both
Type-C ports
Integrated dead battery termination for DRP applications
Supports two USB Type-C ports
6.0 mm  6.0 mm, 0.5 mm, 96-ball BGA
Supports industrial temperature range (–40 °C to +85 °C)
Integrated oscillator eliminating the need for external clock
Cypress Semiconductor Corporation
Document Number: 002-11084 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 18, 2016
PRELIMINARY
EZ-PD™ CCG4M
Logic Block Diagram
CCG4M: Single-Chip Type-C Controller
MCU Subsystem
I/O Subsystem
Integrated Digital Blocks
CC_PORT15
4 x SCB2
(I2C, SPI, UART)
CC_PORT25
Programmable I/O Matrix
CORTEX-M0
4 x TCPWM1
Flash
(128KB)
SRAM
(8KB)
Advanced High-Performance Bus (AHB)
48 MHz
Profiles and
Configurations
2 x Baseband MAC
2 x Baseband PHY
2x VCONN
FETs
(PORT1)
2x VCONN
FETs
(PORT2)
GPIOs6
3
Integrated Rd and Rp
4
4 x 8-bit SAR ADC
Integrated 6:4
Mux for USB 3.0
and DisplayPort
Serial Wire Debug
1 Timer,
counter, pulse-width modulation block
Serial communication block configurable as UART, SPI, or I2C
3 Termination resistor denoting a UFP
4 Current source to indicate a DFP
5 Configuration Channel
6 General-purpose input/output
2
Document Number: 002-11084 Rev. **
Page 2 of 34
PRELIMINARY
EZ-PD™ CCG4M
Contents
Functional Overview ........................................................ 4
CPU and Memory Subsystem ..................................... 4
USB-PD Subsystem (SS)............................................ 4
System Resources ...................................................... 5
Peripherals .................................................................. 5
GPIO ........................................................................... 6
Mux.............................................................................. 6
Pinouts .............................................................................. 7
Power............................................................................... 16
Electrical Specifications ................................................ 19
Absolute Maximum Ratings....................................... 19
Device-Level Specifications ...................................... 19
Digital Peripherals ..................................................... 23
Memory ..................................................................... 25
System Resources .................................................... 25
Document Number: 002-11084 Rev. **
Ordering Information......................................................
Ordering Code Definitions .........................................
Packaging........................................................................
Acronyms ........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Document History Page .................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC® Solutions ......................................................
Cypress Developer Community.................................
Technical Support .....................................................
28
28
29
31
32
32
33
34
34
34
34
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34
Page 3 of 34
PRELIMINARY
Functional Overview
CPU and Memory Subsystem
CPU
The Cortex-M0 CPU in EZ-PD CCG4M is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to higher
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and also includes a Wakeup
Interrupt Controller (WIC). The WIC can wake the processor up
from the Deep Sleep mode, allowing power to be switched off to
the main processor when the chip is in the Deep Sleep mode.
The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI)
input, which is made available to the user when it is not in use
for system functions requested by the user.
The CPU also includes a serial wire debug (SWD) interface,
which is a 2-wire form of JTAG. The debug configuration used for
EZ-PD CCG4M has four break-point (address) comparators and
two watchpoint (data) comparators.
Flash
EZ-PD™ CCG4M
USB-PD Subsystem (SS)
EZ-PD CCG4M has a USB-PD subsystem consisting of two USB
Type-C baseband transceivers and physical-layer logic. These
transceivers perform the BMC and the 4b/5b encoding and
decoding functions as well as the 1.2-V analog front end. This
subsystem integrates the required termination resistors to
identify the role of the EZ-PD CCG4M solution. RD is used to
identify EZ-PD CCG4M as a UFP in a DRP application. When
configured as a DFP, integrated current sources perform the role
of RP or pull-up resistors. These current sources can be
programmed to indicate the complete range of current capacity
on VBUS defined in the USB Type-C spec. EZ-PD CCG4M
responds to all USB-PD communication.
The USB-PD sub-system contains two 8-bit SAR (Successive
Approximation Register) ADC per port for analog to digital
conversions. The ADC includes a 8-bit DAC and a comparator.
The DAC output forms the positive input of the comparator. The
negative input of the comparator is from a 4-input multiplexer.
The four inputs of the multiplexer are a pair of global analog
multiplex busses an internal bandgap voltage and an internal
voltage proportional to the absolute temperature. All GPIO inputs
can be connected to the global Analog Multiplex Busses through
a switch at each GPIO that can enable that GPIO to be
connected to the mux bus for ADC use. The CC1 and CC2 pins
of both Type-C ports are not available to connect to the mux
busses.
The EZ-PD CCG4M device has a flash module with a flash
accelerator, tightly coupled to the CPU to improve average
access times from the flash block. The flash block is designed to
deliver two wait-states (WS) access time at 48 MHz and with
0-WS access time at 16 MHz. The flash accelerator delivers 85%
of single-cycle SRAM access performance on average. Part of
the flash module can be used to emulate EEPROM operation if
required.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
Document Number: 002-11084 Rev. **
Page 4 of 34
PRELIMINARY
EZ-PD™ CCG4M
Figure 1. USB-PD Subsystem
To/From System Resources
vref
iref
To/ from AHB
2 x 8-bit ADC
per Type-C port
From AMUX
VCONN FET Enable
V5V
TxRx Enable
VCONN
FETs
2 x Digital Baseband PHY
Tx_data
from AHB
Enable Logic
Tx
SRAM
4b5b
Encoder
SOP
Insert
BMC
Encoder
Rx_data
to AHB
Rp
TX
CRC
CC1
RD1
RX
Rx
SRAM
4b5b
Decoder
SOP
Detect
BMC
Decoder
CC2
Comp
CC control
CC detect
Deep Sleep Reference Enable
Ref
Active
Rd
DB
Rd
RD2
8kV IEC ESD
2 x Analog Baseband PHY
Deep Sleep
Vref & Iref Gen
Functional, Wakeup Interrupts
vref, iref
RD1 shorted to CC1 and RD2 shorted to CC2 for DRP applications using
bondwire. For DFP applications, RD1 and RD2 not shorted to CC1 and CC2.
Dead Battery (DB) Rd termination removed after MCU boots up
System Resources
Peripherals
Power System
Serial Communication Blocks (SCB)
The power system is described in detail in the section “Power”
on page 16. It provides assurance that voltage levels are as
required for each respective mode and either delay mode entry
(on power-on reset (POR), for example) until voltage levels are
as required for proper function or generate resets (Brown-Out
Detect (BOD)) or interrupts (Low Voltage Detect (LVD)). EZ-PD
CCG4M can operate from three different power sources over the
range of 2.7 to 5.5 V and has three different power modes,
transitions between which are managed by the power system.
EZ-PD CCG4M provides Sleep and Deep Sleep low-power
modes.
EZ-PD CCG4M has four SCBs, which can be configured to
implement an I2C, SPI, or UART interface. The hardware I2C
blocks implement full multi-master and slave interfaces capable
of multimaster arbitration. In the SPI mode, the SCB blocks can
be configured to act as a master or a slave.
Clock System
The clock system for EZ-PD CCG4M consists of the Internal
Main Oscillator (IMO) and the Internal Low-power Oscillator
(ILO).
Document Number: 002-11084 Rev. **
In the I2C mode, the SCB blocks are capable of operating at
speeds up to 1 Mbps (Fast Mode Plus) and have flexible
buffering options to reduce interrupt overhead and latency for the
CPU. These blocks also support I2C that creates a mailbox
address range in the memory of EZ-PD CCG4M and effectively
reduce I2C communication to reading from and writing to an
array in memory. In addition, the blocks support 8-deep FIFOs
for receive and transmit which, by increasing the time given for
the CPU to read data, greatly reduce the need for clock
stretching caused by the CPU not having read data on time.
The I2C peripherals are compatible with the I2C Standard-mode,
Fast-mode, and Fast-mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus
I/Os are implemented with GPIO in open-drain modes.
Page 5 of 34
PRELIMINARY
The I2C port on SCB2, SCB3, and SCB4 blocks of EZ-PD
CCG4M are not completely compliant with the I2C spec in the
following:
■
■
■
The GPIO cells for SCB2, SCB3, and SCB4 I2C port are not
overvoltage-tolerant and, therefore, cannot be hot-swapped or
powered up independently of the rest of the I2C system.
Fast-mode Plus has an IOL specification of 20 mA at a VOL of
0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a
VOL maximum of 0.6 V.
Fast-mode and Fast-mode Plus specify minimum Fall times,
which are not met with the GPIO cell; Slow strong mode can
help meet this spec depending on the bus load.
Timer/Counter/PWM Block (TCPWM)
EZ-PD CCG4M has four TCPWM blocks. Each implements a
16-bit timer, counter, pulse-width modulator (PWM), and
quadrature decoder functionality. The block can be used to
measure the period and pulse width of an input signal (timer),
find the number of times a particular event occurs (counter),
generate PWM signals, or decode quadrature signals.
GPIO
EZ-PD CCG4M has 30 GPIOs that includes the I2C and SWD
pins, which can also be used as GPIOs. The I2C pins from only
SCB 1 are overvoltage-tolerant. The number of available GPIOs
vary with the part numbers. The GPIO block implements the
following:
■
Seven drive strength modes:
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
Document Number: 002-11084 Rev. **
EZ-PD™ CCG4M
Open drain with strong pull-down
Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
❐
❐
■
Input threshold select (CMOS or LVTTL)
■
Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes
■
Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode)
■
Selectable slew rates for dV/dt related noise control to improve
EMI
During power-on and reset, the I/O pins are forced to the disable
state so as not to crowbar any inputs and/or cause excess
turn-on current. A multiplexing network known as a high-speed
I/O matrix is used to multiplex between various signals that may
connect to an I/O pin.
Mux
EZ-PD CCG4M integrates a 6:4 differential channel mux used
for switching USB 3.0 and/or DP 1.2 signals through the USB
Type-C connector. CCG4M can mux the following signals to the
USB Type-C connector:
■
USB 3.0 signals only
■
One lane of USB 3.0 signals and two lanes of DP 1.2 signals
■
Four lanes of DP 1.2 signals
In addition, the AUX signals are also multiplexed to the SBU pins.
The insertion loss is –1.2 dB and the return loss –21 dB at
5-Gbps USB 3.0 speed.
Page 6 of 34
PRELIMINARY
EZ-PD™ CCG4M
Pinouts
Table 1. Pinout for CYPD4255-96BZXI
Group
USB Type-C Port 1
USB Type-C Port 2
Mux
VBUS Control
VCONN Control
Name
Ball Location
Description
CC1_P1
K2
USB PD connector detect/Configuration Channel 1
CC2_P1
H2
USB PD connector detect/Configuration Channel 2
CC1_P2
K9
USB PD connector detect/Configuration Channel 1
CC2_P2
K10
USB PD connector detect/Configuration Channel 2
TX_P
L11
Differential USB 3.0 transmit signal
TX_M
K11
Differential USB 3.0 transmit signal
RX_P
H11
Differential USB 3.0 receive signal
RX_M
G11
Differential USB 3.0 receive signal
TX1_P
A8
Differential transmit signal 1
TX1_M
A7
Differential transmit signal 1
RX1_P
A11
Differential receive signal 1
RX1_M
A10
Differential receive signal 1
TX2_P
A4
Differential transmit signal 2
TX2_M
A5
Differential transmit signal 2
RX2_P
A1
Differential receive signal 2
RX2_M
A2
Differential receive signal 2
AUX_P
F11
Auxiliary signal for DisplayPort
AUX_M
E11
Auxiliary signal for DisplayPort
DP0_P
C1
Differential DisplayPort 0 signal
DP0_M
D1
Differential DisplayPort 0 signal
DP1_P
F1
Differential DisplayPort 1 signal
DP1_M
G1
Differential DisplayPort 1 signal
DP2_P
J1
Differential DisplayPort 2 signal
DP2_M
K1
Differential DisplayPort 2 signal
DP3_P
L2
Differential DisplayPort 3 signal
DP3_M
L3
Differential DisplayPort 3 signal
SBU1
B11
Sideband Use signal
SBU2
C11
Sideband Use signal31
VBUS_P_CTRL_P1
K3
Full rail control I/O for enabling/disabling Provider load FET
of USB Type-C port 1
VBUS_C_CTRL_P1
K4
Full rail control I/O for enabling/disabling Consumer load FET
of USB Type-C port 1 or SCB1 (see Table 3 through Table 6)
VBUS_DISCHARGE_P1
K8
I/O used for discharging VBUS line during voltage change
VBUS_P_CTRL_P2
B4
Full rail control I/O for enabling/disabling Provider load FET
of USB Type-C port 2
VBUS_C_CTRL_P2
B5
Full rail control I/O for enabling/disabling Consumer load FET
of USB Type-C port 2
VBUS_DISCHARGE_P2
B3
I/O used for discharging VBUS line during voltage change
VCONN_MON_P1/GPIO/
VSEL_1_P1
L7
Monitor VCONN for UVP condition on port 1 or GPIO or
Voltage selection control for VBUS on port 1
SCL_3/VCONN_MON_P2/
VSEL_1_P2
L10
SCB3 (see Table 3 through Table 6) or Monitor VCONN for
UVP condition on port 2 or Voltage selection control for VBUS
on port 2
Document Number: 002-11084 Rev. **
Page 7 of 34
PRELIMINARY
EZ-PD™ CCG4M
Table 1. Pinout for CYPD4255-96BZXI (continued)
Group
Overvoltage Protection
(OVP)
GPIOs and Serial
Interfaces
Reset
Name
Ball Location
Description
OVP_TRIP_P1/
VSEL_2_P1
K5
VBUS overvoltage output indicator for port 1 or voltage
selection control for VBUS on port 1 or SCB1 (see Table 3
through Table 6)
OVP_TRIP_P2
L8
VBUS overvoltage output indicator for port 2 or SCB3 (see
Table 3 through Table 6)
VBUS_MON_P1/GPIO
L4
VBUS overvoltage protection monitoring signal or GPIO
VBUS_MON_P2
B6
VBUS overvoltage protection monitoring signal
HPD_P1/GPIO
K7
Hot Plug Detect I/O for port 1 or GPIO
HPD_P2/GPIO
E10
Hot Plug Detect I/O for port 2 or GPIO
GPIO/MUX_CTRL_3_P2
B9
Mux control for port 2 or GPIO
GPIO/MUX_CTRL_2_P2
B8
Mux control for port 2 or GPIO or SCB4 (see Table 3 through
Table 6)
GPIO/MUX_CTRL_1_P2
B7
Mux control for port 2 or GPIO or SCB4 (see Table 3 through
Table 6)
VSEL_2_P2/GPIO
H10
I2C_SCL_SCB1_EC
L6
SCB1 (see Table 3 through Table 6)
I2C_SDA_SCB1_EC
K6
SCB1 (see Table 3 through Table 6) or SCB3 (see Table 3
through Table 6)
I2C_INT_EC
L5
I2C interrupt line
I2C_SCL_SCB2_AR/GPIO
E2
SCB2 (see Table 3 through Table 6) or GPIO
I2C_SDA_SCB2_AR/GPIO
D2
SCB2 (see Table 3 through Table 6) or GPIO
I2C_INT_AR_P1
F2
I2C interrupt line
I2C_INT_AR_P2
G2
I2C interrupt line or SCB2 (see Table 3 through Table 6)
Voltage selection control for VBUS on port 2 or GPIO
SDA_3/GPIO
J10
SCB3 (see Table 3 through Table 6) or GPIO
SCL_4
F10
SCB4 (see Table 3 through Table 6)
SDA_4
G10
SWD_IO/AR_RST#
B2
Serial Wire Debug I/O or SCB2 (see Table 3 through Table 6)
SWD_CLK/I2C_CFG_EC
C2
SWD Clock or I2C config line
XRES
H6
Reset input
Document Number: 002-11084 Rev. **
SCB4 (see Table 3 through Table 6)
Page 8 of 34
PRELIMINARY
EZ-PD™ CCG4M
Table 1. Pinout for CYPD4255-96BZXI (continued)
Group
Power
Ground
No Connect
Name
Ball Location
Description
VDDM
A3
3.0-V to 3.6-V supply for integrated mux
VDDM
A6
3.0-V to 3.6-V supply for integrated mux
VDDM
A9
3.0-V to 3.6-V supply for integrated mux
VDDM
B1
3.0-V to 3.6-V supply for integrated mux
VDDM
D11
3.0-V to 3.6-V supply for integrated mux
VDDM
E1
3.0-V to 3.6-V supply for integrated mux
VDDM
H1
3.0-V to 3.6-V supply for integrated mux
VDDM
J11
3.0-V to 3.6-V supply for integrated mux
VDDM
L1
VDDD
D10
VDDD supply input/output (2.7-V to 5.5-V)
3.0-V to 3.6-V supply for integrated mux
VCCD
B10
1.8-V regulator output for filter capacitor. This pin cannot drive
external load.
VDDIO
C10
1.71-V to 5.5-V supply for I/Os
V5V_P1
J2
2.7-V to 5.5-V supply for VCONN FET of Type-C port 1
V5V_P2
L9
2.7-V to 5.5-V supply for VCONN FET of Type-C port 2
GND
D5
Ground
GND
D6
Ground
GND
D7
Ground
GND
D8
Ground
GND
E4
Ground
GND
E5
Ground
GND
E6
Ground
GND
E7
Ground
GND
E8
Ground
GND
F4
Ground
GND
F5
Ground
GND
F6
Ground
GND
F7
Ground
GND
F8
Ground
GND
G4
Ground
GND
G5
Ground
GND
G6
Ground
GND
G7
Ground
GND
H7
Ground
NC
G8
No connect
NC
H4
No connect
NC
H5
No connect
NC
H8
No connect
Document Number: 002-11084 Rev. **
Page 9 of 34
PRELIMINARY
EZ-PD™ CCG4M
Figure 2. 96-Ball BGA Map for CYPD4255-96BZXI
1
2
3
4
5
6
7
8
9
10
11
A
RX2_P
RX2_M
VDDM
TX2_P
TX2_M
VDDM
TX1_M
TX1_P
VDDM
RX1_M
RX1_P
B
VDDM
SWD_IO/AR
_RST#
VBUS_DISC
HARGE_P2
VBUS_P_C
TRL_P2
GPIO/MUX_
CTRL_1_P2
GPIO/MUX_
CTRL_2_P2
GPIO/MUX_
CTRL_3_P2
VCCD
SBU1
C
DP0_P
SWD_CLK/I2
C_CFG_EC
VDDIO
SBU2
D
DP0_M
I2C_SDA_S
CB2_AR/
GPIO
E
VDDM
I2C_SCL_SC
B2_AR/GPIO
F
DP1_P
G
VBUS_C_CT VBUS_MON
RL_P2
_P2
GND
GND
GND
GND
VDDD
VDDM
GND
GND
GND
GND
GND
HPD_P2/
GPIO
AUX_M
I2C_INT_AR
_P1
GND
GND
GND
GND
GND
SCL_4
AUX_P
DP1_M
I2C_INT_AR
_P2
GND
GND
GND
GND
NC
SDA_4
RX_M
H
VDDM
CC2_P1
NC
NC
XRES
GND
NC
VSEL_2_P2/
GPIO
RX_P
J
DP2_P
V5V_P1
SDA_3/GPIO
VDDM
K
DP2_M
CC1_P1
VBUS_P_CT
RL_P1
L
VDDM
DP3_P
DP3_M
Document Number: 002-11084 Rev. **
VBUS_C_C
TRL_P1
OVP_TRIP_
P1/VSEL_2_
P1
I2C_SDA_S
CB1_EC
HPD_P1/
GPIO
VCONN_MO
VBUS_MON I2C_INT_EC I2C_SCL_SC N_P1/GPIO/
_P1/GPIO
B1_EC
VSEL_1_P1
VBUS_DISC
HARGE_P1
CC1_P2
CC2_P2
TX_M
OVP_TRIP_
P2
V5V_P2
SCL_3/VCON
N_MON_P2/
VSEL_1_P2
TX_P
Page 10 of 34
PRELIMINARY
EZ-PD™ CCG4M
Table 2. Pinout for CYPD4155-96BZXI
Group
USB Type-C Port 1
Mux
VBUS Control
Name
Ball Location
Description
CC1_P1
K2
USB PD connector detect/Configuration Channel 1
CC2_P1
H2
USB PD connector detect/Configuration Channel 2
TX_P
L11
Differential USB 3.0 transmit signal
TX_M
K11
Differential USB 3.0 transmit signal
RX_P
H11
Differential USB 3.0 receive signal
RX_M
G11
Differential USB 3.0 receive signal
TX1_P
A8
Differential transmit signal 1
TX1_M
A7
Differential transmit signal 1
RX1_P
A11
Differential receive signal 1
RX1_M
A10
Differential receive signal 1
TX2_P
A4
Differential transmit signal 2
TX2_M
A5
Differential transmit signal 2
RX2_P
A1
Differential receive signal 2
RX2_M
A2
Differential receive signal 2
AUX_P
F11
Auxiliary signal for DisplayPort
AUX_M
E11
Auxiliary signal for DisplayPort
DP0_P
C1
Differential DisplayPort 0 signal
DP0_M
D1
Differential DisplayPort 0 signal
DP1_P
F1
Differential DisplayPort 1 signal
DP1_M
G1
Differential DisplayPort 1 signal
DP2_P
J1
Differential DisplayPort 2 signal
DP2_M
K1
Differential DisplayPort 2 signal
DP3_P
L2
Differential DisplayPort 3 signal
DP3_M
L3
Differential DisplayPort 3 signal
SBU1
B11
Sideband Use signal
SBU2
C11
Sideband Use signal
VBUS_P_CTRL_P1
K3
Full rail control I/O for enabling/disabling Provider load FET of
USB Type-C port 1
VBUS_C_CTRL_P1
K4
Full rail control I/O for enabling/disabling Consumer load FET
of USB Type-C port 1 or SCB1 (see Table 3 through Table 6)
VBUS_DISCHARGE_P1
K8
I/O used for discharging VBUS line during voltage change
VCONN Control
VCONN_MON_P1/GPIO/V
SEL_1_P1
L7
Monitor VCONN for UVP condition on port 1 or GPIO or Voltage
selection control for VBUS on port 1
Overvoltage
Protection (OVP)
OVP_TRIP_P1/
VSEL_2_P1
K5
VBUS overvoltage output indicator for port 1 or Voltage
selection control for VBUS on port 1 or SCB1 (see Table 3
through Table 6)
Document Number: 002-11084 Rev. **
Page 11 of 34
PRELIMINARY
EZ-PD™ CCG4M
Table 2. Pinout for CYPD4155-96BZXI (continued)
Group
GPIOs and Serial
Interfaces
Reset
Power
Name
Ball Location
Description
VBUS_MON_P1/GPIO
L4
VBUS overvoltage protection monitoring signal or GPIO
HPD_P1/GPIO
K7
Hot Plug Detect I/O for port 1 or GPIO
SCL_3/GPIO
L10
SCB3 (see Table 3 through Table 6) or GPIO
SDA_3/GPIO
J10
SCB3 (see Table 3 through Table 6) or GPIO
SCL_4
F10
SCB4 (see Table 3 through Table 6)
SDA_4
G10
SCB4 (see Table 3 through Table 6)
I2C_SCL_SCB1_EC
L6
SCB1 (see Table 3 through Table 6)
I2C_SDA_SCB1_EC
K6
SCB1 (see Table 3 through Table 6) or SCB3 (see Table 3
through Table 6)
I2C_INT_EC
L5
I2C interrupt line
I2C_SCL_SCB2_AR/
GPIO
E2
SCB2 (see Table 3 through Table 6) or GPIO
I2C_SDA_SCB2_AR/
GPIO
D2
SCB2 (see Table 3 through Table 6) or GPIO
I2C_INT_AR_P1
F2
I2C interrupt line
GPIO
B3
GPIO
GPIO
B4
GPIO
GPIO
B5
GPIO
GPIO
B6
GPIO
GPIO
B7
GPIO or SCB4 (see Table 3 through Table 6)
GPIO
B8
GPIO or SCB4 (see Table 3 through Table 6)
GPIO
B9
GPIO
GPIO
E10
GPIO
GPIO
G2
GPIO or SCB2 (seeTable 3 through Table 6)
GPIO
H10
GPIO
L8
GPIO
GPIO or SCB3 (see Table 3 through Table 6)
SWD_IO/AR_RST#
B2
Serial Wire Debug I/O or SCB2 (see Table 3 through Table 6)
SWD_CLK/I2C_CFG_EC
C2
SWD Clock or I2C config line
XRES
H6
Reset input
VDDM
A3
3.0-V to 3.6-V supply for integrated mux
VDDM
A6
3.0-V to 3.6-V supply for integrated mux
VDDM
A9
3.0-V to 3.6-V supply for integrated mux
VDDM
B1
3.0-V to 3.6-V supply for integrated mux
VDDM
D11
3.0-V to 3.6-V supply for integrated mux
VDDM
E1
3.0-V to 3.6-V supply for integrated mux
VDDM
H1
3.0-V to 3.6-V supply for integrated mux
VDDM
J11
3.0-V to 3.6-V supply for integrated mux
VDDM
L1
3.0-V to 3.6-V supply for integrated mux
VDDD
D10
VDDD supply input/output (2.7-V to 5.5-V)
VCCD
B10
1.8-V regulator output for filter capacitor. This pin cannot drive
external load.
VDDIO
C10
1.71-V to 5.5-V supply for I/Os
V5V_P1
J2
Document Number: 002-11084 Rev. **
2.7-V to 5.5-V supply for VCONN FET of Type-C port 1
Page 12 of 34
PRELIMINARY
EZ-PD™ CCG4M
Table 2. Pinout for CYPD4155-96BZXI (continued)
Group
Ground
No Connect
Name
Ball Location
Description
GND
D5
Ground
GND
D6
Ground
GND
D7
Ground
GND
D8
Ground
GND
E4
Ground
GND
E5
Ground
GND
E6
Ground
GND
E7
Ground
GND
E8
Ground
GND
F4
Ground
GND
F5
Ground
GND
F6
Ground
GND
F7
Ground
GND
F8
Ground
GND
G4
Ground
GND
G5
Ground
GND
G6
Ground
GND
G7
Ground
GND
H7
Ground
NC
G8
No connect
NC
H4
No connect
NC
H5
No connect
NC
H8
No connect
NC
K9
No connect
NC
K10
No connect
NC
L9
No connect
Document Number: 002-11084 Rev. **
Page 13 of 34
PRELIMINARY
EZ-PD™ CCG4M
Figure 3. 96-Ball BGA Ball Map for CYPD4155-96BZXI
1
2
3
4
5
6
7
8
9
10
11
A
RX2_P
RX2_M
VDDM
TX2_P
TX2_M
VDDM
TX1_M
TX1_P
VDDM
RX1_M
RX1_P
B
VDDM
SWD_IO/AR
_RST#
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
VCCD
SBU1
C
DP0_P
SWD_CLK/I
2C_CFG_EC
VDDIO
SBU2
D
DP0_M
I2C_SDA_S
CB2_AR/
GPIO
E
VDDM
I2C_SCL_S
CB2_AR/
GPIO
F
DP1_P
G
GND
GND
GND
GND
VDDD
VDDM
GND
GND
GND
GND
GND
GPIO
AUX_M
I2C_INT_AR
_P1
GND
GND
GND
GND
GND
SCL_4
AUX_P
DP1_M
GPIO
GND
GND
GND
GND
NC
SDA_4
RX_M
H
VDDM
CC2_P1
NC
NC
XRES
GND
NC
GPIO
RX_P
J
DP2_P
V5V_P1
SDA_3/
GPIO
VDDM
K
DP2_M
CC1_P1
L
VDDM
DP3_P
VBUS_P_C VBUS_C_C OVP_TRIP_
P1/VSEL_2 I2C_SDA_S
TRL_P1
TRL_P1
CB1_EC
_P1
DP3_M
Document Number: 002-11084 Rev. **
VBUS_MON
_P1/GPIO
I2C_INT_
EC
HPD_P1/
GPIO
VCONN_M
I2C_SCL_S ON_P1/GPI
CB1_EC
O/VSEL_1_
P1
VBUS_DIS
CHARGE_
P1
NC
NC
TX_M
GPIO
NC
SCL_3/
GPIO
TX_P
Page 14 of 34
PRELIMINARY
EZ-PD™ CCG4M
Table 3. Serial Communication Block (SCB1) Configuration
Pin
K4
UART
UART_TX_SCB1
SPI Master
SPI_MOSI_SCB1
SPI Slave
I2C Master
I2C Slave
SPI_MOSI_SCB1
VBUS_C_CTRL_P1
VBUS_C_CTRL_P1
SPI_CLK_SCB1
VSEL_2_P1/
VCONN_MON_P1
VSEL_2_P1/
VCONN_MON_P1
K5
UART_RX_SCB1
SPI_CLK_SCB1
L6
UART_RTS_SCB1
SPI_MISO_SCB1
SPI_MISO_SCB1
I2C_SDA_SCB1
I2C_SDA_SCB1
K6
UART_CTS_SCB1
SPI_SEL_SCB1
SPI_SEL_SCB1
I2C_SCL_SCB1
I2C_SCL_SCB1
Table 4. Serial Communication Block (SCB2) Configuration
Pin
UART
SPI Master
SPI Slave
I2C Master
I2C Slave
E2
UART_TX_SCB2
SPI_CLK_SCB2
SPI_CLK_SCB2
I2C_SCL_SCB2
I2C_SCL_SCB2
D2
UART_RX_SCB2
SPI_MISO_SCB2
SPI_MISO_SCB2
I2C_SDA_SCB2
I2C_SDA_SCB2
G2
UART_RTS_SCB2
SPI_SEL_SCB2
SPI_SEL_SCB2
GPIO
GPIO
B2
UART_CTS_SCB2
SPI_MOSI_SCB2
SPI_MOSI_SCB2
SWD_IO
SWD_IO
Table 5. Serial Communication Block (SCB3) Configuration
Pin
UART
SPI Master
SPI Slave
I2C Master
I2C Slave
J10
UART_TX_SCB3
SPI_MISO_SCB3
SPI_MISO_SCB2
I2C_SDA_SCB3
I2C_SDA_SCB3
L10
UART_RX_SCB3
SPI_MOSI_SCB3
SPI_MOSI_SCB3
I2C_SCL_SCB3
I2C_SCL_SCB3
K6
UART_RTS_SCB3
SPI_SEL_SCB3
SPI_SEL_SCB3
I2C_SCL_SCB1
I2C_SCL_SCB1
L8
UART_CTS_SCB3
SPI_CLK_SCB3
SPI_CLK_SCB3
AR_RST#
AR_RST#
Table 6. Serial Communication Block (SCB4) Configuration
Pin
UART
SPI Master
SPI Slave
I2C Master
I2C Slave
G10
UART_TX_SCB4
SPI_MOSI_SCB4
SPI_MOSI_SCB4
I2C_SDA_SCB4
I2C_SDA_SCB4
F10
UART_RX_SCB4
SPI_MISO_SCB4
SPI_MISO_SCB4
I2C_SCL_SCB4
I2C_SCL_SCB4
B7
UART_RTS_SCB4
SPI_SEL_SCB4
SPI_SEL_SCB4
GPIO
GPIO
B8
UART_CTS_SCB4
SPI_CLK_SCB4
SPI_CLK_SCB4
GPIO
GPIO
Document Number: 002-11084 Rev. **
Page 15 of 34
PRELIMINARY
EZ-PD™ CCG4M
Power
The VCCD output of EZ-PD CCG4M must be bypassed to
ground via an external capacitor (in the range of 1 to 1.6 µF; X5R
ceramic or better).
The following power system diagram shows the set of power
supply pins as implemented in EZ-PD CCG4M.
CCG4M shall be able to operate from three possible external
supply sources: V5V_P1 for first Type-C port, V5V_P2 for
second Type- C port and VDDD.
CCG4M has the power supply input V5V_P1 and V5V_P2 pins
for providing power to EMCA cables through integrated VCONN
FETs. There are two VCONN FETs in CCG4M per Type-C port
to power either CC1 or CC2 pin. These FETs are capable of
providing a minimum of 1W on the CC1 and CC2 pins for the
EMCA cables. In USB-PD applications, the valid levels on
V5V_P1 and V5V_P2 supplies can range from 4.85 – 5.5 V.
Bypass capacitors must be used from VDDD and V5V_P1 or
V5V_P2 pins to ground; typical practice for systems in this
frequency range is to use a 0.1-µF capacitor on VDDD, V5V_P1
and V5V_P2. Note that these are simply rules of thumb and that
for critical applications, the PCB layout, lead inductance, and the
bypass capacitor parasitic should be simulated to design and
obtain optimal bypassing.
Figure 4 shows an example of the power supply bypass
capacitors.
The chip’s internal operating power supply is derived from
VDDD. In UFP mode, CCG4M operates in 2.7 – 5.5V. In DFP
and DRP modes, it operates at 3.0 – 5.5V range.
A separate I/O supply pin, VDDIO, allows the GPIOs to operate
at levels from 1.71 to 5.5 V. The VDDIO pin can be equal to or
less than the voltages connected to the V5V_P1 or V5V_P2 and
VDDD pins.
Figure 4. EZ-PD CCG4M Power and Bypass Scheme Example
[3]
[2]
CC1_P2
CC2_P2
[1]
V5V_P2
CC1_P1
CC2_P1
V5V_P1
VDDD
Core Regulator
(SRSS-Lite)
VDDIO
VCCD
GPIOs
Core
2 x CC
Tx/Rx
VSS
Note
1. V5V_P1 denoted power supply input for Type-C port 1
V5V_P2 denoted power supply input for Type-C port 2
2. CC1_1:USB PD connector detect/Configuration Channel 1 for Type-C port 1
CC1_2:USB PD connector detect/Configuration Channel 1 for Type-C port 2
3. CC2_1:USB PD connector detect/Configuration Channel 2 for Type-C port 1
CC2_2:USB PD connector detect/Configuration Channel 2 for Type-C port 2
Document Number: 002-11084 Rev. **
Page 16 of 34
PRELIMINARY
EZ-PD™ CCG4M
Figure 5. Dual Port Notebook Application Using CCG4M (CYD4255-96BZXI)
VBUS_SINK
100 KO
100 KO
100 KO
100 KO
10 O
VBUS_C_CTRL_P1
100 KO
VBUS_SOURCE
VBUS_1
49.9KO
100 KO
100 KO
5.0V
1µF
1µF
3.3V
5.0V
10 O
VBUS_P_CTRL_P1
100 KO
10O
1µF
VBUS_DISCHARGE_P1 10 O
USB 3.0 HOST
B10
VDDM
L11
TX +
K11 TX -
RX +
RX -
100 KO
VCCD
D10
C10
VDDD
VDDIO
V5V_P1
V5V_P2
B2 SWD_IO/
AR_RST#/GPIO
C2 SWD_CLK/I2C_CFG_EC/
GPIO
2
HS
J2
L9
0.1µF
1µF
A3, A6, A9,
B1, D11, E1,
H1, J11, L1
0.1µF
SSTX/RX
H11
RX +
G11 RX -
VBUS_C_CTRL_P1
VBUS_P_CTRL_P1
K4
HS
K3
VBUS_DISCHARGE_P1 K8
C1
DP0 +
D1 DP0 -
DP1 +
DP1 -
F1
DP1 +
G1 DP1 -
DP2 +
DP2 -
J1
DP2 +
K1 DP2 -
DP3 +
DP3 -
L2
DP3 +
L3 DP3 -
AUX +
AUX -
F11
AUX +
E11 AUX K7
HPD_P2
E10
TX1 +
TX1 -
A4
TX2 +
TX2 - A5
TX2 +
TX2 -
A11
RX1 +
RX1 - A10
CCG4M
(CYPD4255-96BZXI)
RX1 +
RX1 -
A1
RX2 +
RX2 - A2
RX2 +
RX2 -
B11
SBU1
SBU2 C11
SBU1
SBU2
11 KO
HPD_P2/GPIO
VBUS_MON_P1/GPIO
L4
0.1µF
1 KO
K5 VSEL_2_P1/
OVP_TRIP_P1
CC2_P1
CC1_P1
VSEL_2_P2/GPIO
H2
CC2
K2
CC1
VDDIO
VDDIO
POWER
SUB-SYSTEM
TYPE-C
RECEPTACLE 1
VBUS_1
HPD_P1/GPIO
L7 VSEL_1_P1/
VCONN_MON_P1/GPIO
H10
4.7 KO
H6
0.1µF
2.2 KO
EMBEDDED
CONTROLLER
L8
2.2 KO
L5
L6
K6
E2
D2
F2
G2
VDDIO
L10
2.2 KO
2.2 KO
J10
I2C_SCL
F10
I2C_SDA
G10
390pF
H4, H5,
H8, G8
NC
2.2 KO
VBUS
390pF
VBUS_2
XRES
GND
11 KO
OVP_TRIP_P2
VBUS_MON_P2
B6
0.1µF
1 KO
I2C_INT_EC
MUX_CTRL_3_P2/GPIO
I2C_SCL_SCB1_EC
MUX_CTRL_2_P2/GPIO
I2C_SDA_SCB1_EC
I2C_SCL_SCB2_AR/GPIO
MUX_CTRL_1_P2/GPIO
I2C_SDA_SCB2_AR/GPIO
GND
B9
GND
B8
B7
D5, D6, D7, D8, E4, E5, E6, E7, E8,
F4, F5, F6, F7, F8, G4, G5, G6, G7, H7
I2C_INT_AR_P1/GPIO
I2C_INT_AR_P2/GPIO
VSEL_1_P2/SCL_3/VCONN_MON_P2/GPIO
CC2_P2
SDA_3/GPIO
CC1_P2
SCL_4
SDA_4
VBUS_C_CTRL_P2
VBUS_DISCHARGE_P2
K10
CC2
K9
CC1
B5
390pF
390pF
TYPE-C
RECEPTACLE 2
VBUS_P_CTRL_P2
B3
B4
VBUS_SINK
VBUS
100 KO
DP/DM
DP/DM
TO DISPLAY PORT
CONTROLLER 2
HPD_P1
TX1 +
TX1 - A7
2
SSTX/RX
HPD
A8
DP/DM
DP/DM
DISPLAY PORT
SOURCE
DP0 +
DP0 -
2
SBU
TX +
TX -
100 KO
2
100 KO
2
100 KO
10 O
VBUS_C_CTRL_P2
100 KO
VBUS_2
VBUS_SOURCE
49.9KO
100 KO
VBUS_P_CTRL_P2
10 O
100 KO
10 O
VBUS_DISCHARGE_P2
10 O
100 KO
USB 3.0
HOST
HS
2
SSTX/RX
4
TX
4
RX
4
SBU
2
HPD_P2
DISPLAY PORT
CONTROLLER 2
ML_LANE_[0:3]N
4
ML_LANE_[0:3]P
4
AUX P/N
2
MUX
HPD_P2
I2C_SCL
Document Number: 002-11084 Rev. **
I2C_SDA
Page 17 of 34
PRELIMINARY
EZ-PD™ CCG4M
Figure 6. Single Port Notebook Application Using CCG4M (CYD4155-96BZXI)
VBUS_SINK
100 KO
100 KO
100 KO
100 KO
VBUS_C_CTRL_P1
10 O
100 KO
VBUS_SOURCE
VBUS
49.9KO
100 KO
100 KO
5.0V
5.0V
10 O
VBUS_P_CTRL_P1
3.3V
100 KO
1µF
10 O
10O
1µF
VBUS_DISCHARGE_P1 10 O
1µF
USB 3.0 HOST
2
B10
1µF
VDDM
0.1µF
A3, A6, A9,
B1, D11, E1,
H1, J11, L1
L11
TX +
K11 TX -
RX +
RX -
100 KO
VCCD
C10
D10
VDDD
C2 SWD_CLK/I2C_CFG_EC/
GPIO
VDDIO
V5V_P1
V5V_P2
B2 SWD_IO/
AR_RST#/GPIO
HS
J2
L9
0.1µF
SSTX/RX
H11
RX +
G11 RX -
TX +
TX -
VBUS_C_CTRL_P1
VBUS_P_CTRL_P1
VBUS_DISCHARGE_P1
C1
DP0 +
D1 DP0 -
DP1 +
DP1 -
F1
DP1 +
G1 DP1 -
DP2 +
DP2 -
J1
DP2 +
K1 DP2 L2
DP3 +
L3 DP3 -
DP3 +
DP3 -
HPD_P1
HPD
K7
E10
2
TX1 +
TX1 - A7
A4
CCG4M
(CYPD4155-96BZXI)
EMBEDDED
CONTROLLER
H6
0.1µF
2.2 KO
L8
2.2 KO
L5
L6
K6
E2
D2
F2
G2
VDDIO
2.2 KO
TYPE-C
RECEPTACLE 1
11 KO
VBUS_MON_P1/GPIO
L4
1 KO
CC2_P1
CC1_P1
GPIO
0.1µF
H2
CC2
K2
CC1
390pF
4.7 KO
2.2 KO
SBU1
SBU2
VBUS
VDDIO
VDDIO
RX2 +
RX2 -
B11
HPD_P1/GPIO
VBUS
RX1 +
RX1 -
A1
RX2 +
RX2 - A2
SBU1
SBU2 C11
GPIO
2
TX2 +
TX2 -
A11
RX1 +
RX1 - A10
L7 VSEL_1_P1/
VCONN_MON_P1/GPIO
POWER
SUB-SYSTEM
TX1 +
TX1 -
TX2 +
TX2 - A5
K5 VSEL_2_P1/
OVP_TRIP_P1
H10
HS
K8
A8
F11
AUX +
E11 AUX -
AUX +
AUX -
K3
DP/DM
DP/DM
DISPLAY PORT
SOURCE
DP0 +
DP0 -
K4
L10
2.2 KO
J10
I2C_SCL
F10
I2C_SDA
G10
D5, D6, D7, D8, E4, E5, E6, E7, E8, F4,
F5, F6, F7, F8, G4, G5, G6, G7, H7
390pF
XRES
GND
GPIO
I2C_INT_EC
GPIO
I2C_SCL_SCB1_EC
GPIO
I2C_SDA_SCB1_EC
B9
B8
B7
I2C_SCL_SCB2_AR/GPIO
GPIO
I2C_SDA_SCB2_AR/GPIO
GPIO
I2C_INT_AR_P1/GPIO
GPIO B4
GPIO
B5
GPIO B3
SCL_3/GPIO
GPIO
B6
SDA_3/GPIO
SCL_4
SDA_4
GND
NC
H4, H5,
H8, G8,
K9, K10
Document Number: 002-11084 Rev. **
Page 18 of 34
PRELIMINARY
EZ-PD™ CCG4M
Electrical Specifications
Absolute Maximum Ratings
Table 7. Absolute Maximum Ratings[4]
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
VDDD_MAX
Digital supply relative to VSS
–0.5
–
6
V
Absolute max
VDDM_MAX
Mux supply relative to VSS
–0.3
–
4.3
V
Absolute max
V5V_P1
Max supply voltage relative to VSS
–
–
6
V
Absolute max
V5V_P2
Max supply voltage relative to VSS
–
–
6
V
Absolute max
VDDIO_MAX
Max supply voltage relative to VSS
–
–
6
V
Absolute Max
VMUX_ABS
Mux USB/DP signal voltage
– 0.3
–
1.2
V
Absolute Max
VAUX_ABS
Mux AUX signal voltage
– 0.35
–
VDDM
V
Absolute Max
VGPIO_ABS
GPIO voltage
–0.5
–
VDDIO + 0.5
V
Absolute max
IGPIO_ABS
Maximum current per GPIO
–25
–
25
mA
Absolute max
IGPIO_injection
GPIO injection current, Max for VIH
> VDDD, and Min for VIL < VSS
–0.5
–
0.5
mA
Absolute max, current
injected per pin
ESD_HBM
Electrostatic discharge human
body model
2200
–
–
V
–
ESD_CDM
Electrostatic discharge charged
device model
500
–
–
V
–
LU
Pin current for latch-up
–200
–
200
mA
–
ESD_IEC_CON
Electrostatic discharge
IEC61000-4-2
8000
–
–
V
Contact discharge on
CC1, CC2 pins
ESD_IEC_AIR
Electrostatic discharge
IEC61000-4-2
15000
–
–
V
Air discharge for pins
CC1, CC2
Device-Level Specifications
All specifications are valid for –40 °C  TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 3.0 V to 5.5 V,
except where noted.
Table 8. DC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID.PWR#1
VDDD
Power supply input voltage
2.7
–
5.5
V
UFP Applications
SID.PWR#1_A
VDDD
Power supply input voltage
3.0
–
5.5
V
DFP/DRP Applications
SID.PWR#26
V5V_P1,
V5V_P2
Power supply input voltage
4.85
–
5.5
V
SID.VDDM
VDDM
Mux power supply input
voltage
3.0
3.3
3.6
V
SID.IDDM
IDDM
VDDM current supply
–
300
350
µA
PWR#13
VDDIO
GPIO power supply
1.71
–
5.5
V
–
SID.PWR#24
VCCD
Output voltage (for core logic)
–
1.8
–
V
–
SID.PWR#15
CEFC
External regulator voltage
bypass on VCCD
80
100
120
nF
X5R ceramic or better
SID.PWR#16
CEXC
Power supply decoupling
capacitor on VDDD
0.8
1
–
µF
X5R ceramic or better
–
Note
4. Usage above the absolute maximum conditions listed in Table 7 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 002-11084 Rev. **
Page 19 of 34
PRELIMINARY
EZ-PD™ CCG4M
Table 8. DC Specifications (continued)
Spec ID
SID.PWR#27
Parameter
CEXV
Description
Power Supply Decoupling
Capacitor on V5V_P1 and
V5V_P2
Min
Typ
Max
Units
Details/Conditions
–
0.1
–
µF
X5R ceramic or better
Active Mode, VDDD = 2.7 to 5.5 V. Typical values measured at VDD = 3.3 V.
SID.PWR#4
IDD12
Supply current
–
10
–
mA
V5V_P1 and V5V_P2 = 5 V,
TA = 25 °C,
CC I/O IN Transmit or Receive,
no I/O sourcing current, CPU at
24 MHz, two PD ports active
–
2.5
4.0
mA
VDDD = 3.3 V, TA = 25 °C, all
blocks except CPU are ON, CC
I/O ON, no I/O sourcing current
Sleep Mode, VDDD = 2.7 to 5.5 V
SID25A
IDD20A
I2C wakeup
WDT ON
IMO at 48 MHz
Deep Sleep Mode, VDDD = 2.7 to 3.6 V (Regulator on)
SID34
IDD29
VDDD = 2.7 to 3.6 V
I2C wakeup and WDT ON
–
360
–
µA
VDDD = 3.3 V, TA = 25 °C
SID_DS
IDD_DS
VDDD = 2.7 to 3.6 V
CC wakeup ON
–
32.5
–
µA
Power source = VDDD, Type-C
not attached, CC enabled for
wakeup, RP disabled
SID_DS1
IDD_DS1
VDDD = 2.7 to 3.6 V
CC wakeup ON
–
130
–
µA
Power source = VDDD, Type-C
not attached, CC enabled for
wakeup, RP and RD connected at
70 ms intervals by CPU. RP, RD
connection should be enabled for
both PD ports.
IDD_XR
Supply current while XRES
asserted
–
1
10
µA
–
Min
Typ
Max
Units
DC
–
48
MHz
XRES Current
SID307
Table 9. AC Specifications
Spec ID
Parameter
Description
Details/Conditions
3.0 V VDDD 5.5 V
SID.CLK#4
FCPU
CPU frequency
SID.PWR#20
TSLEEP
Wakeup from sleep mode
–
0
–
µs
Guaranteed by characterization
SID.PWR#21
TDEEPSLEEP
Wakeup from Deep Sleep
mode
–
–
35
µs
24-MHz IMO. Guaranteed by
characterization.
SID.XRES#5
TXRES
External reset pulse width
5
–
–
µs
Guaranteed by characterization
T_PWR_RDY
Power-up to “Ready to accept
I2C / CC command”
–
5
25
ms
Guaranteed by characterization
SYS.FES#1
Document Number: 002-11084 Rev. **
Page 20 of 34
PRELIMINARY
EZ-PD™ CCG4M
MUX
Table 10. Mux Specifications
Spec ID
Parameter
Min
Typ
Max
Units
Details/Conditions
COFF
USB 3.0/DP switch OFF capacitance
–
1.2
–
pF
VIOM = GND
f = 1 MHz
CON
USB 3.0/DP switch ON capacitance
–
2.3
–
pF
VIOM = GND
f = 1 MHz
COFF
AUX+/AUX– switch OFF capacitance
–
4.0
–
pF
VIOM = GND
f = 1 MHz
CON
AUX+/AUX– switch ON capacitance
–
7.0
–
pF
VIOM = GND
f = 1 MHz
IOZL
I/O leakage for TX_to_TX1/TX2,
RX_toRX1/RX2, DPx_to_TX/RX (x =
0,1, 2, 3), AUX_to_SBUy (y = 1, 2)
µA
VDDM = 3.6 V
VIOM (USB 3.0) = 0 V
VIOM (DP) = 0 V
VIOM (AUX) = 0 V
IOZH
I/O leakage for TX_to_TX1/TX2,
RX_toRX1/RX2, DPx_to_TX/RX
(x = 0,1, 2, 3), AUX_to_SBUy (y = 1, 2)
–
µA
VDDM = 3.6 V
VIOM (USB 3.0) = 1.2 V
VIOM (DP) = 1.2 V
VIOM (AUX) = 4.0 V
Switch on resistance USB 3.0/DP
–

VDDM = min, ION = –40 mA
VIN = 0 V
VIN = 1.2 V
AUX Switch
–

VDDM = min, IIN = –40 mA
VIN = 0 V
VIN = 3.0 V
–
RON
1
1
7.0
9.0
5
15
10.0
12.0
3.5
4.5
5.0
7.0
Linear region for analog switch
VP_IO
Linear region for analog switch
TX_to_TX1/TX2, RX_to_RX1/RX2,
DPx_to_TX/RX (x = 0, 1, 2, 3)
1.4
1.6
–
V
VDDM = 3.3 V
IPASS = 10 mA
VP_IOSB
Linear region for analog switch
AUX_to_SBUx (x = 1, 2)
4.0
4.2
–
V
VDDM = 3.3 V
IPASS = 10 mA
Table 11. Dynamic Mux Characteristics
Min and max apply for TA between –40 °C to 85 °C. Typical values are referenced to TA = 25 °C.
Spec ID
tstartup
tpd
Parameter
Min
Typ
Max
Units
Details/Conditions
Startup time
–
10
20
µs
Supply voltage valid or the device is
powered up and the channel is turned
on to its specified characteristics
VDDM = 3 V
Propagation delay 1
–
80
–
ps
From input port to output port USB/DP
Propagation delay 2
–
150
–
ps
From input port to output port AUX
Skew time 1
–
10
–
ps
From input port to output USB/DP. Bit
to bit skew
Skew time 2
–
20
–
ps
From input port to output AUX. Bit to
bit skew
tsk
VI_sub_dp
USB/DP input signal
–0.3
–
1.2
V
USB/DP switch analog signal
VI_aux
AUX+/AUX– input signal
–0.35
–
VDDM
V
AUX switch analog signal
Document Number: 002-11084 Rev. **
Page 21 of 34
PRELIMINARY
EZ-PD™ CCG4M
Table 12. Mux Switch AC Electrical Characteristics
Min and max apply for TA between –40 °C to 85 °C and TJ up to +125 °C (unless otherwise noted). Typical values are referenced to
TA = 25 °C, VDDM = 3.3 V.
Spec ID
Parameter
Frequency
BW_usb
–3 dB bandwidth of USB 3.0
Min
Typ
Max
Units
–
6
–
GHz
Details/
Conditions
IL
Differential insertion loss
2.5/2.7 GHz
–
–1.2/–1.3
–
dB
Vcom = 0 V
RL
Differential return loss
2.5/2.7 GHz
–
–21/–20
–
dB
Vcom = 0 V
Xtalk
Differential crosstalk
2.5/2.7 GHz
–
–38/–37
–
dB
Vcom = 0 V
dB
Vcom = 0 V
Xoff
Off isolation
2.5/2.7 GHz
dB
Vcom = 0 V
USB
DP
–25/–24
–
–23/–22
–
I/O
Table 13. I/O DC Specifications
Spec ID
Parameter
Description
Min
Typ
SID.GIO#37
VIH[5]
Input voltage HIGH threshold 0.7 × VDDIO
SID.GIO#38
VIL
Input voltage LOW threshold
–
SID.GIO#39
VIH[5]
LVTTL input, VDDIO < 2.7 V
0.7× VDDIO
SID.GIO#40
VIL
LVTTL input, VDDIO < 2.7 V
–
SID.GIO#41
VIH[5]
LVTTL input, VDDIO  2.7 V
2.0
SID.GIO#42
VIL
LVTTL input, VDDIO  2.7 V
–
Max
Units
Details/Conditions
–
–
V
CMOS input
–
0.3 × VDDIO
V
CMOS input
–
–
V
–
–
0.3 × VDDIO
V
–
–
–
V
–
–
0.8
V
–
SID.GIO#33
VOH
Output voltage HIGH level
VDDIO –0.6
–
–
V
IOH = 4 mA at 3-V VDDIO
SID.GIO#34
VOH
Output voltage HIGH level
VDDIO –0.5
–
–
V
IOH = 1 mA at 1.8-V VDDIO
SID.GIO#35
VOL
Output voltage LOW level
–
–
0.6
V
IOL = 4 mA at 1.8-V VDDIO
SID.GIO#36
VOL
Output voltage LOW level
–
–
0.6
V
IOL = 8 mA at 3 V VDDIO
SID.GIO#5
RPULLUP
Pull-up resistor
3.5
5.6
8.5
kΩ
–
SID.GIO#6
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
kΩ
–
SID.GIO#16
IIL
Input leakage current
(absolute value)
–
–
2
nA
SID.GIO#17
CIN
Input capacitance
–
–
7
pF
–
25 °C, VDDIO = 3.0 V
SID.GIO#43
VHYSTTL
Input hysteresis LVTTL
25
40
–
mV
VDDIO  2.7 V. Guaranteed
by characterization.
SID.GPIO#44
VHYSCMOS
Input hysteresis CMOS
0.05 × VDDIO
–
–
mV
Guaranteed by
characterization
SID69
IDIODE
Current through protection
diode to VDDIO/Vss
–
–
100
µA
Guaranteed by
characterization
SID.GIO#45
ITOT_GPIO
Maximum total source or sink
chip current
–
–
200
mA
Guaranteed by
characterization
Table 14. I/O AC Specifications
(Guaranteed by Characterization)
Spec ID
SID70
Parameter
TRISEF
Rise time
Description
Min
2
Typ
–
Max
12
SID71
TFALLF
Fall time
2
–
12
Units
Details/Conditions
ns 3.3-V VDDIO, Cload = 25 pF
ns 3.3-V VDDIO, Cload = 25 pF
Note
5. VIH must not exceed VDDIO + 0.2 V.
Document Number: 002-11084 Rev. **
Page 22 of 34
PRELIMINARY
EZ-PD™ CCG4M
XRES
Table 15. XRES DC Specifications
Spec ID
SID.XRES#1
Parameter
VIH
Description
Input voltage HIGH threshold
Min
Typ
0.7 × VDDIO –
Max
–
Units
Details/Conditions
V
CMOS input
SID.XRES#2
VIL
Input voltage LOW threshold
–
–
0.3 × VDDIO
V
CMOS input
SID.XRES#3
CIN
Input capacitance
–
–
7
pF
SID.XRES#4
VHYSXRES
Input voltage hysteresis
–
–
0.05 × VDDIO
mV
–
Guaranteed by
characterization
Digital Peripherals
The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.
Pulse Width Modulation (PWM) for GPIO Pins
Table 16. PWM AC Specifications
(Guaranteed by Characterization)
Spec ID
SID.TCPWM.3
Parameter
Description
TCPWMFREQ Operating frequency
Min
–
Typ
Fc
SID.TCPWM.4
Max Units
Details/Conditions
–
MHz Fc max = CLK_SYS. Maximum = 48 MHz
TPWMENEXT Input trigger pulse width
–
2/Fc
–
ns
SID.TCPWM.5
TPWMEXT
Output trigger pulse width
–
2/Fc
–
ns
SID.TCPWM.5A
TCRES
Resolution of counter
–
1/Fc
–
ns
SID.TCPWM.5B
PWMRES
PWM resolution
–
1/Fc
–
ns
SID.TCPWM.5C
QRES
Quadrature inputs resolution
–
1/Fc
–
ns
For all trigger events
Minimum possible width of Overflow,
Underflow, and CC (Counter equals
Compare value) outputs
Minimum time between successive
counts
Minimum pulse width of PWM output
Minimum pulse width between
quadrature-phase inputs
I2C
Table 17. Fixed I2C DC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID149
II2C1
Block current consumption at 100 kbps
–
–
60
µA
–
SID150
II2C2
Block current consumption at 400 kbps
–
–
185
µA
–
SID151
II2C3
Block current consumption at 1 Mbps
–
–
390
µA
–
II2C4
I2C
–
–
1.4
µA
–
Typ
–
Max
1
Units
Mbps
Details/Conditions
–
SID152
Table 18. Fixed
I2C
enabled in Deep Sleep mode
AC Specifications
(Guaranteed by Characterization)
Spec ID
SID153
Parameter
FI2C1
Description
Min
–
Description
Min
Typ
Max
Units
Details/Conditions
Bit rate
Table 19. Fixed UART DC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
SID160
IUART1
Block current consumption at
100 Kbit/sec
–
–
125
µA
–
SID161
IUART2
Block current consumption at
1000 Kbit/sec
–
–
312
µA
–
Document Number: 002-11084 Rev. **
Page 23 of 34
PRELIMINARY
EZ-PD™ CCG4M
Table 20. Fixed UART AC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID162
FUART
Bit rate
–
–
1
Mbps
–
Table 21. Fixed SPI DC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID163
ISPI1
Block current consumption
at 1 Mbit/sec
–
–
360
µA
–
SID164
ISPI2
Block current consumption
at 4 Mbit/sec
–
–
560
µA
–
SID165
ISPI3
Block current consumption
at 8 Mbit/sec
–
–
600
µA
–
Table 22. Fixed SPI AC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID166
FSPI
SPI Operating frequency
(Master; 6X oversampling)
–
–
8
MHz
–
Min
Typ
Max
Units
Details / Conditions
–
Table 23. Fixed SPI Master Mode AC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
SID167
TDMO
MOSI Valid after SClock
driving edge
–
–
15
ns
SID168
TDSI
MISO Valid before SClock
capturing edge
20
–
–
ns
Full clock, late MISO
sampling
SID169
THMO
Previous MOSI data hold
time
0
–
–
ns
Referred to Slave capturing
edge
Table 24. Fixed SPI Slave Mode AC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
40
–
–
ns
–
SID170
TDMI
MOSI Valid before Sclock
capturing edge
SID171
TDSO
MISO Valid after Sclock
driving edge
–
–
48 + 3 * TSCB
ns
SID171A
TDSO_EXT
MISO Valid after Sclock
driving edge in Ext Clk mode
–
–
48
ns
–
SID172
THSO
Previous MISO data hold
time
0
–
–
ns
–
SID172A
TSSELSCK
100
–
–
ns
–
SSEL Valid to first SCK valid
edge
Document Number: 002-11084 Rev. **
TSCB = TCPU = 1/24 MHz
Page 24 of 34
PRELIMINARY
EZ-PD™ CCG4M
Memory
Table 25. Flash AC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
–
–
20
ms
–
SID.MEM#4
TROWWRITE[6]
Row (block) write time (erase and
program)
SID.MEM#3
TROWERASE[6]
Row erase time
SID.MEM#8
TROWPROGRAM[6] Row program time after erase
SID178
TBULKERASE
[6]
Bulk erase time (128 KB)
SID180
TDEVPROG[6]
Total device program time
SID.MEM#6
FEND
Flash endurance
SID182
FRET1
SID182A
FRET2
–
–
13
ms
–
–
–
7
ms
–
–
–
35
ms
–
Guaranteed by
seconds
characterization
–
–
25
100 K
–
–
cycles
Guaranteed by
characterization
Flash retention. TA  55 °C, 100 K
P/E cycles
20
–
–
years
Guaranteed by
characterization
Flash retention. TA  85 °C, 10 K
P/E cycles
10
–
–
years
Guaranteed by
characterization
Min
Typ
Max
Units
System Resources
Power-on-Reset (POR) with Brown Out
Table 26. Imprecise Power On Reset (PRES)
Spec ID
Parameter
Description
Details/Conditions
SID185
VRISEIPOR
Rising trip voltage
0.80
–
1.50
V
Guaranteed by
characterization
SID186
VFALLIPOR
Falling trip voltage
0.75
–
1.4
V
Guaranteed by
characterization
Min
Typ
Max
Units
Table 27. Precise Power On Reset (POR)
Spec ID
Parameter
Description
Details/Conditions
SID190
VFALLPPOR
BOD trip voltage in active and
sleep modes
1.48
–
1.62
V
Guaranteed by
characterization
SID192
VFALLDPSLP
BOD trip voltage in Deep Sleep
1.1
–
1.5
V
Guaranteed by
characterization
SWD Interface
Table 28. SWD Interface Specifications
Description
Min
Typ
Max
Units
Details/Conditions
SID.SWD#1 F_SWDCLK1
Spec ID
Parameter
3.3 V  VDDIO  5.5 V
–
–
14
MHz
SWDCLK ≤ 1/3 CPU clock frequency
SID.SWD#2 F_SWDCLK2
1.8 V  VDDIO  3.3 V
–
–
7
MHz
SID.SWD#3 T_SWDI_SETUP
T = 1/f SWDCLK
0.25 * T
–
–
ns
Guaranteed by characterization
SID.SWD#4 T_SWDI_HOLD
T = 1/f SWDCLK
0.25 * T
–
–
ns
Guaranteed by characterization
SID.SWD#5 T_SWDO_VALID
T = 1/f SWDCLK
–
–
0.5*T
ns
Guaranteed by characterization
SID.SWD#6 T_SWDO_HOLD
T = 1/f SWDCLK
1
–
–
ns
Guaranteed by characterization
SWDCLK ≤ 1/3 CPU clock frequency
Note
6. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
Document Number: 002-11084 Rev. **
Page 25 of 34
PRELIMINARY
EZ-PD™ CCG4M
Internal Main Oscillator
Table 29. IMO DC Specifications
(Guaranteed by Design)
Spec ID
Parameter
SID218
IIMO
Description
Min
Typ
Max
Units
Details/Conditions
IMO operating current at 48 MHz
–
–
1000
µA
–
Min
Typ
Max
Units
Details/Conditions
–
–
±2
%
–
Table 30. IMO AC Specifications
Spec ID
Parameter
Description
SID.CLK#13 FIMOTOL
Frequency variation at 24, 36,
and 48 MHz (trimmed)
SID226
TSTARTIMO
IMO startup time
–
–
7
µs
–
SID229
TJITRMSIMO
RMS jitter at 48 MHz
–
145
–
ps
–
IMO frequency
24
–
48
MHz
–
Min
Typ
Max
FIMO
–
Internal Low-Speed Oscillator
Table 31. ILO DC Specifications
(Guaranteed by Design)
Spec ID
Parameter
Description
Units
Details/Conditions
SID231
IILO
ILO operating current at 32 kHz
–
0.3
1.05
µA
Guaranteed by
Characterization
SID233
IILOLEAK
ILO leakage current
–
2
15
nA
Guaranteed by Design
Details/Conditions
Table 32. ILO AC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
SID234
TSTARTILO
ILO startup time
–
–
2
ms
Guaranteed by
characterization
SID236
TILODUTY
ILO duty cycle
40
50
60
%
Guaranteed by
characterization
ILO Frequency
20
40
80
kHz
SID.CLK#5 FILO
–
Power Down
Table 33. PD DC Specifications
Spec ID
Parameter
Description
Min
Typ
Max Units
Details/Conditions
SID.PD.1
Rp_std
DFP CC termination for default USB
Power
64
80
96
µA
–
SID.PD.2
Rp_1.5A
DFP CC termination for 1.5A power
166
180
194
µA
–
SID.PD.3
Rp_3.0A
DFP CC termination for 3.0A power
304
330
356
µA
–
SID.PD.4
Rd
UFP CC termination
4.59
5.1
5.61
kΩ
–
4.08
5.1
6.12
kΩ
All supplies forced to 0 V and 0.6 V
applied at CC1 or CC2. Applicable
for DRP applications only.
Voltage drop from V5V_P1 and
SID.PD.15 Vdrop_V5V_CC1 V5V_P2 pins to CC1 pin while
sourcing 215 mA
–
–
100
mV
–
Voltage drop from V5V_P1 and
SID.PD.16 Vdrop_V5V_CC2 V5V_P2 pins to CC2 pin while
sourcing 215 mA
–
–
100
mV
–
SID.PD.5
Rd_DB
UFP Dead Battery CC termination on
CC1 and CC2
Document Number: 002-11084 Rev. **
Page 26 of 34
PRELIMINARY
EZ-PD™ CCG4M
Analog to Digital Converter
Table 34. ADC DC Specifications
Spec ID
Parameter
Description
SID.ADC.1 Resolution
ADC resolution
SID.ADC.2 INL
Integral non-linearity
Min
Typ
–
8
–1.5
–
Max
Units
Details/Conditions
–
bits
–
1.5
LSB
–
SID.ADC.3 DNL
Differential non-linearity
–2.5
–
2.5
LSB
–
SID.ADC.4 Gain Error
Gain error
–1.0
–
1.0
LSB
–
Min
Typ
Max
Units
Details/Conditions
–
–
3
V/ms
–
Table 35. ADC AC Specifications
Spec ID
Parameter
Description
Rate of change of sampled voltage
SID.ADC.5 SLEW_Max
signal
Document Number: 002-11084 Rev. **
Page 27 of 34
PRELIMINARY
EZ-PD™ CCG4M
Ordering Information
The EZ-PD CCG4M part numbers and features are listed in Table 36.
Table 36. EZ-PD CCG4M Ordering Information
Part Number
Application
Type-C
Ports
Dead Battery
Termination
Termination
Resistor
Role
Package
CYPD4255-96BZXI
Notebooks, Desktops
2
Yes
RP[7], RD[8]
DRP
96-ball BGA
Yes
RP[7],
DRP
96-ball BGA
CYPD4155-96BZXI
Notebooks, Desktops
1
RD
[8]
Ordering Code Definitions
CY PD
4 1/2 0
X
-
XX XX
X
I
T
T = Tape and Reel
Temperature Grade:
I = Industrial
Pb-free
Package Type: XX = BZ
BZ = BGA
Number of pins in the package: XX = 96
Device Role: Unique combination of role and termination:
X = 2 or 3 or 4 or 5
Feature: Unique Applications
Number of Type-C Ports: 1 = 1 Port, 2 = 2 Ports
Product Type: 4 = Fourth-generation product family
Marketing Code: PD = Power Delivery product family
Company ID: CY = Cypress
Notes
7. Termination resistor denoting an accessory or downstream facing port.
8. Termination resistor denoting a upstream facing port.
Document Number: 002-11084 Rev. **
Page 28 of 34
PRELIMINARY
EZ-PD™ CCG4M
Packaging
Table 37. Package Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Units
TA
Operating ambient temperature
–
–40
25
85
°C
TJ
Operating junction temperature
–
–40
–
100
°C
TJA
Package θJA (96-ball BGA)
–
–
62
–
°C/W
TJC
Package θJC (96-ball BGA)
–
–
23
–
°C/W
Table 38. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Maximum Time within 5 °C of Peak Temperature
96-ball BGA
245 °C
30 seconds
Table 39. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
96-ball BGA
MSL 3
Document Number: 002-11084 Rev. **
Page 29 of 34
PRELIMINARY
EZ-PD™ CCG4M
Figure 7. 96-Ball BGA(6 × 6 × 0.5 mm), 002-10631
E1
2X
0.10 C
E
B
(datum B)
A1 CORNER
A
11 10 9 8 7 6 5 4 3 2 1
7
A1 CORNER
A
B
C
D
E
F
G
H
J
K
L
6
SD
D
0.10 C 2X
eD
D1
(datum A)
6
SE
eE
TOP VIEW
BOTTOM VIEW
DETAIL A
0.10 C
A1
0.08 C
A
C
96XØb
5
SIDE VIEW
Ø0.15 M C A B
Ø0.05 M C
DETAIL A
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
MIN.
NOM.
MAX.
A
-
-
1.00
A1
0.16
-
-
D
6.00 BSC
E
6.00 BSC
D1
5.00 BSC
E1
5.00 BSC
MD
11
ME
11
N
96
b
0.25
0.30
eD
0.50 BSC
eE
0.50 BSC
SD
SE
0.00
0.00
2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
6. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
0.35
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
7. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK
METALIZED MARK, INDENTATION OR OTHER MEANS.
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
9. JEDEC SPECIFICATION NO. REF. : MO-225.
Document Number: 002-11084 Rev. **
002-10631 **
Page 30 of 34
PRELIMINARY
Acronyms
Table 40. Acronyms Used in this Document (continued)
Table 40. Acronyms Used in this Document
Acronym
EZ-PD™ CCG4M
Description
Acronym
Description
opamp
operational amplifier
OCP
overcurrent protection
OVP
overvoltage protection
PCB
printed circuit board
PD
power delivery
PGA
programmable gain amplifier
PHY
physical layer
ADC
analog-to-digital converter
API
application programming interface
ARM®
advanced RISC machine, a CPU architecture
CC
configuration channel
CPU
central processing unit
CRC
cyclic redundancy check, an error-checking
protocol
POR
power-on reset
CS
current sense
PRES
precise power-on reset
DFP
downstream facing port
PSoC®
Programmable System-on-Chip™
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
PWM
pulse-width modulator
DRP
dual role port
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
electrically erasable programmable read-only
EEPROM
memory
EMCA
a USB cable that includes an IC that reports cable
characteristics (e.g., current rating) to the Type-C
ports
RX
receive
SAR
successive approximation register
SCL
I2C serial clock
SDA
I2C serial data
EMI
electromagnetic interference
ESD
electrostatic discharge
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output
IC
integrated circuit
SRAM
static random access memory
IDE
integrated development environment
SWD
serial wire debug, a test protocol
TX
transmit
Type-C
a new standard with a slimmer USB connector and
a reversible cable, capable of sourcing up to 100 W
of power
UART
Universal Asynchronous Transmitter Receiver, a
communications protocol
USB
Universal Serial Bus
USBIO
USB input/output, CCG4M pins used to connect to
a USB port
XRES
external reset I/O pin
I2C, or IIC Inter-Integrated Circuit, a communications protocol
ILO
internal low-speed oscillator, see also IMO
IMO
internal main oscillator, see also ILO
I/O
input/output, see also GPIO
LVD
low-voltage detect
LVTTL
low-voltage transistor-transistor logic
MCU
microcontroller unit
NC
no connect
NMI
nonmaskable interrupt
NVIC
nested vectored interrupt controller
Document Number: 002-11084 Rev. **
S/H
sample and hold
SPI
Serial Peripheral Interface, a communications
protocol
Page 31 of 34
PRELIMINARY
EZ-PD™ CCG4M
Document Conventions
Units of Measure
Table 41. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
Hz
hertz
KB
1024 bytes
kHz
kilohertz
k
kilo ohm
Mbps
megabits per second
MHz
megahertz
M
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond

ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
V
volt
Document Number: 002-11084 Rev. **
Page 32 of 34
PRELIMINARY
EZ-PD™ CCG4M
Document History Page
Document Title: EZ-PD™ CCG4M USB Type-C Dual Port Controller with USB 3.1 Gen 1/DP1.2 Mux
Document Number: 002-11084
Revision
ECN
Orig. of
Change
Submission
Date
**
5131574
VGT
02/18/2016
Document Number: 002-11084 Rev. **
Description of Change
New datasheet
Page 33 of 34
PRELIMINARY
EZ-PD™ CCG4M
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including
any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide.
Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual
property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby
grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify and
reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right
to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software
is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any
component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole
or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify
and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-11084 Rev. **
Revised February 18, 2016
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 34 of 34