® PSoC Creator™ Component Datasheet Status Register 1.90 Features Up to 8-bit Status Register Interrupt support General Description The Status Register allows the firmware to read digital signals. When to Use a Status Register Use the Status Register when the firmware needs to query the state of internal digital signals. Input/Output Connections This section describes the input connections for the status register. An asterisk (*) in the list of I/Os indicates that the I/O may be hidden on the symbol under the conditions listed in the description of that I/O. clock – Input Status register clock. The clock input signal is ignored for bits configured as Transparent. status_0 - status_7 – Input * Status register input. The firmware queries the input signals by reading the status register. The number of inputs depends on the Inputs parameter. These inputs may be left floating with no external connection. If nothing is connected to these lines, the component will assign a constant logic 0. status[N:0] – Input * This optional input sweeps the individual input terminals into a single bus terminal. This pin is visible when the Display as bus parameter is enabled. N is the number of inputs - 1. This input may be left floating with no external connection. If nothing is connected to this line, the component will assign a constant logic 0. Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-96683 Rev. ** Revised March 19, 2015 Status Register ® PSoC Creator™ Component Datasheet intr – Output * This optional pin is shown on the symbol when the Generate interrupt parameter is enabled. This option is only valid if less than 8 inputs are selected. Component Parameters Drag a Status Register onto your design and double-click it to open the Configure dialog. Inputs Number of input terminals (1 to 8). The default value is 8. Display as bus This parameter displays the input as a bus instead of individual terminals. This option is unchecked by default. Generate interrupt This parameter displays the interrupt input on the symbol. It is not selected by default. An Interrupt is valid only if the number of inputs is less than 8. In addition to checking the Generate Interrupt box, the Interrupt mask must be set and the StatusReg_InterruptEnable()API must be called in order for the component to generate an interrupt. The Interrupt signal generation depends on the Mode parameter: Transparent – Goes high on the rising edge of the status input signal and goes low on the falling edge of the status input signal. Page 2 of 8 Document Number: 001-96683 Rev. ** ® PSoC Creator™ Component Datasheet Status Register Sticky – Goes high on the rising edge of the Clock (if the status input signal is high). It goes low after the Status register is read. The interrupt generation is tied to the setting of status bits. This feature is built into the status register logic as the masking (Mask register) and OR reduction of status. Only the lower 7 bits of the status input can be used with the built-in interrupt generation circuitry. Set all modes This button sets all bits to either Transparent or Sticky mode, depending on the mode selected from the combo box in the left hand side of this button. Mode These parameters are used to set specific bits of the Status Register to be held high after being registered, until a read is executed. That read clears all registered values. The settings are: Transparent – By default, a CPU read of this register transparently reads the state of the associated routing net and is asynchronous to the block clock. This mode can be used for transient state that is computed and registered internally in the UDB. Sticky (Clear on Read) – In this mode, the associated routing net is sampled on each cycle of the status and control clock. If the signal is high in a given sample, it is captured in the status bit and remains high, regardless of the subsequent state of the associated route. When CPU firmware reads the status register, the bit is cleared. The status register clearing is independent of mode and will occur even if the block clock is disabled; it is based on the bus clock and occurs as part of the read operation. Figure 1. Behavior of Transparent versus Sticky Modes Mode 0 From routing D D UDB Local Bus (n) 1 Q status_n Data latch AR clock Q Sticky latch UDB Read register Interrupt mask This option is shown in the Configure dialog only when the Generate interrupt is checked. These parameters allow you to set the interrupt mask value for each bit in the Status Register. By default, the interrupt mask value is 0 (disabled). Document Number: 001-96683 Rev. ** Page 3 of 8 ® Status Register PSoC Creator™ Component Datasheet Application Programming Interface Application Programming Interface (API) routines allow you to configure the component using software. By default, PSoC Creator assigns the instance name “Status_Reg_1” to the first instance of a status register in any given design. You can rename the component to any unique value that follows the syntactic rules for identifiers. The instance name becomes the prefix of every global function name, variable, and constant symbol. For readability, the instance name used in the following function is “StatusReg.” Functions Function Description StatusReg_Read() Reads the current value of the status register StatusReg_InterruptEnable() Enables the status register interrupt StatusReg_InterruptDisable() Disables the status register interrupt StatusReg_WriteMask() Writes the value assigned to the mask register StatusReg_ReadMask() Returns the current interrupt mask value from the mask register uint8 StatusReg_Read (void) Description: Reads the value of a status register. Parameters: None Return Value: Returns the current value of a status register. Side Effects: None void StatusReg_InterruptEnable (void) Description: Enables the status register interrupt. The default behavior is disabled. This is only valid if the status register generates an interrupt. Parameters: None. Return Value: None. Side Effects: Page 4 of 8 None. Document Number: 001-96683 Rev. ** ® PSoC Creator™ Component Datasheet Status Register void StatusReg_InterruptDisable (void) Description: Disables the status register interrupt. This is only valid if the status register generates an interrupt. Parameters: None. Return Value: None. Side Effects: None. void StatusReg_WriteMask (uint8 mask) Description: Writes the current mask value assigned to the status register. This is only valid if the status register generates an interrupt. Parameters: mask: The bitwise value to write into the mask register. A 1 enables the corresponding bit in the status register to generate an interrupt. A 0 disables the corresponding bit in the status register from generating an interrupt. Return Value: None. Side Effects: None. uint8 StatusReg_ReadMask (void) Description: Reads the current interrupt mask value assigned for the status register. This is only valid if the status register generates an interrupt. Parameters: None. Return Value: Returns the current bitwise value of the interrupt mask. A 1 in the corresponding bit of the status register enables generating an interrupt. A 0 in the corresponding bit of the status register disables generating an interrupt. Side Effects: None Sample Firmware Source Code PSoC Creator provides numerous example projects that include schematics and example code in the Find Example Project dialog. For component-specific examples, open the dialog from the Component Catalog or an instance of the component in a schematic. For general examples, open the dialog from the Start Page or File menu. As needed, use the Filter Options in the dialog to narrow the list of projects available to select. Refer to the “Find Example Project” topic in the PSoC Creator Help for more information. Document Number: 001-96683 Rev. ** Page 5 of 8 ® Status Register PSoC Creator™ Component Datasheet MISRA Compliance This section describes the MISRA-C:2004 compliance and deviations for the component. There are two types of deviations defined: project deviations – deviations that are applicable for all PSoC Creator components specific deviations – deviations that are applicable only for this component This section provides information on component-specific deviations. Project deviations are described in the MISRA Compliance section of the System Reference Guide along with information on the MISRA compliance verification environment. The Status Register component does not have any specific deviations. API Memory Usage The component memory usage varies significantly, depending on the compiler, device, number of APIs used and component configuration. The following table provides the memory usage for all APIs available in the given component configuration. The measurements have been done with the associated compiler configured in Release mode with optimization set for Size. For a specific design the map file generated by the compiler can be analyzed to determine the memory usage. PSoC 3 (Keil_PK51) Configuration Default PSoC 4 (GCC) PSoC 5LP (GCC) Flash RAM Flash RAM Flash RAM (Bytes) (Bytes) (Bytes) (Bytes) (Bytes) (Bytes) 46 0 92 0 92 0 Functional Description Low Power Mode Behavior None of the Status Register content is retained during low power modes (sleep, deep sleep, and hibernate). Each bit of the Status Register component is initialized with a ‘0’ value when the device wakes up from low power mode. Page 6 of 8 Document Number: 001-96683 Rev. ** ® PSoC Creator™ Component Datasheet Status Register DMA The DMA component can be used to read data directly from Status Register. The DMA Wizard can be used to configure DMA operations as follows: Name of DMA Source/Destination in DMA Wizard StatusReg_Status_PTR Direction Source DMA Req Signal DMA Req Type N/A N/A Description Stores Status Register value. Resources The Status Register component uses one status cell in the UDB array. Component Changes This section lists the major changes in the component from the previous version. Version Description of Changes Reason for Changes / Impact 1.90 Fixed MISRA violation MISRA violation is happens in StatusReg_WriteMask API if number of inputs is less than 8. 1.80.c Datasheet updates. Clarified the API section (StatusReg_WriteMask, StatusReg_ReadMask APIs). Clarified the Component Parameters section (Generate interrupt, Interrupt mask parameters). 1.80.b Datasheet updates. Updated Figure 1 to better illustrate Transparent Mode versus Sticky Mode. Added low power mode behavior section. Updated the table appearance in the Configure dialog. 1.80.a Updated datasheet with memory usage for PSoC 4. 1.80 Added MISRA Compliance section. 1.70 Added PSoC 5LP support. Corrected a display problem at 120 dpi resolution. The component does not have any specific deviations. Implemented StatusReg_InterruptEnable(), StatusReg_InterruptDisable(), StatusReg_WriteMask() and StatusReg_ReadMask() APIs. To support interrupt functionality. Updated the Configure dialog. Added Display as bus, Generate interrupt, Set all modes, Interrupt mask parameters and minor design changes. Document Number: 001-96683 Rev. ** Page 7 of 8 ® Status Register Version PSoC Creator™ Component Datasheet Description of Changes Reason for Changes / Impact Added interrupt pin and display as bus option for input terminals. Also implemented DMA capabilities and Debug window support. To have input terminals as bus and to support interrupt generation. 1.60 Updated the Configure dialog Changed the Bit display and addressed minor Configure dialog issues 1.50.b Datasheet edits 1.50.a Datasheet edits 1.50 Updated the Configure dialog. Created a customized interface. Added "Set All" buttons and changed Number of Inputs field to allow keyboard entry. Updated the dialog to comply with corporate standards. © Cypress Semiconductor Corporation, 2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in lifesupport systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 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The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 8 of 8 Document Number: 001-96683 Rev. **