PSoC® Creator™ Component Datasheet Digital Logic Gates 1.0 Features Industry-standard logic gates Configurable number of inputs up to 8 Optional array of gates General Description Logic gates provide basic boolean operations. The output of a logic gate is a boolean combinatorial function of the inputs. There are seven basic logic gates: AND, OR, Inverter (NOT), NAND, NOR, XOR, and XNOR. When to Use a Logic Gate Use logic gates when you want to perform basic logical operations. You can perform more complex operations with various combinations of the basic logic gates. Input/Output Connections This section describes the various input and output connections for the Logic Gates. An asterisk (*) in the list of I/Os indicates that the I/O may be hidden on the symbol under the conditions listed in the description of that I/O. Input 1 Every logic gate has at least one digital input Input 2 All logic gates, except the Inverter (NOT), have a second digital input. Inputs 3 - 8 * All logic gates, except the Inverter (NOT), can be configured to have up to eight input terminals. Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-50454 Rev. *E Revised July 13, 2015 Digital Logic Gates PSoC® Creator™ Component Datasheet Output All logic gates have one output. Component Parameters Drag a logic gate onto your design and double-click it to open the Configure dialog. Figure 1. Configure AND Dialog Logic gates provide the following parameters: NumTerminals For all logic gates, except Inverter (NOT), this parameter determines the number of input terminals. The minimum is 2 (default) and the maximum is 8. The Inverter (NOT) gate does not have this parameter. Page 2 of 7 Document Number: 001-50454 Rev. *E PSoC® Creator™ Component Datasheet Digital Logic Gates TerminalWidth This parameter determines the array width of the input and output terminals (default is 1). You can create an array of the logic gate, which may be useful when a logic function is performed across buses of inputs and a bus of outputs. It defines the number of wires in the buses that can be attached to the same number of discrete logic gates in parallel. Figure 2 is a conceptual example of an AND gate with 2 inputs and an array width of 3. In practice, only a single AND gate would be shown with 2 inputs and 1 output, each of which would connect to a bus with a width of 3 wires. Figure 2. Array Conceptual Example Resources All digital logic gates are converted to a sum of products and placed into a Universal Digital Block (UDB) programmable logic. This process results in digital logic gates being automatically optimized and placed into the PSoC device. Resource use depends on the specific logic created and cannot be determined before project compilation in PSoC Creator. Functional Description This section describes each of the logic gates separately. The gate logic descriptions use the following convention to describe logic levels: True = 1 = high logic level False = 0 = low logic level AND Gate The AND gate performs logical multiplication in the same way as the logical AND operator. It has two or more inputs and one output. As shown in Table 1, the output is true when all inputs are true. Otherwise, the output is false. Document Number: 001-50454 Rev. *E Page 3 of 7 PSoC® Creator™ Component Datasheet Digital Logic Gates Table 1. AND Truth Table Input 1 Input 2 Output 0 0 0 0 1 0 1 0 0 1 1 1 OR Gate The OR gate performs logical addition in the same way as the logical inclusive OR operator. It has two or more inputs and one output. As shown in Table 2 the output is true if the inputs are true. If all inputs are false then the output is false. Table 2. OR Truth Table Input 1 Input 2 Output 0 0 0 0 1 1 1 0 1 1 1 1 Inverter (NOT) Gate The Inverter, also called a NOT gate, performs the basic logic function called inversion. In other words, this gate changes one logic level (true/false) to the opposite logic level. The NOT gate has only one input and one output. As shown in Table 3, the output is false when the input is true and vice-versa. Table 3. Inverter (NOT) Truth Table Input Output 1 0 0 1 Page 4 of 7 Document Number: 001-50454 Rev. *E PSoC® Creator™ Component Datasheet Digital Logic Gates NAND Gate The NAND gate operates as an AND gate followed by a NOT gate. It acts in the manner of the logical operation AND followed by negation. It has two or more inputs and one output. As shown in Table 4, the output is false if all inputs are true. Otherwise, the output is true. Table 4. NAND Truth Table Input 1 Input 2 Output 0 0 1 0 1 1 1 0 1 1 1 0 NOR Gate The NOR gate operates as an OR gate followed by a NOT gate. It has two or more inputs and one output. As shown in Table 5, the output is true if all inputs are false. Otherwise, the output is false. Table 5. NOR Truth Table Input 1 Input 2 Output 0 0 1 0 1 0 1 0 0 1 1 0 Document Number: 001-50454 Rev. *E Page 5 of 7 PSoC® Creator™ Component Datasheet Digital Logic Gates XOR Gate The XOR (exclusive-OR) gate is useful as a parity generator. It has two or more inputs and one output. As shown in Table 6, the output is true when there are an odd number of true inputs. Otherwise, the output is false. Table 6. XOR Truth Table Input 1 Input 2 Input 3 Output 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 XNOR gate The XNOR (exclusive-NOR) gate operates as an XOR gate followed by a NOT gate. It has two or more inputs and one output. As shown in Table 7, the output is true when there is an even number of true inputs. Otherwise, the output is false. Table 7. XNOR Truth Table Input 1 Input 2 Input 3 Output 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0 Page 6 of 7 Document Number: 001-50454 Rev. *E PSoC® Creator™ Component Datasheet Digital Logic Gates Component Changes This section lists the major changes in the component from the previous version. Version Description of Changes 1.0.e Minor datasheet update. 1.0.d Minor datasheet update. 1.0.c Minor datasheet edits and updates 1.0.b Minor datasheet edits and updates 1.0.a Updated datasheet. Reason for Changes / Impact XNOR truth table was incorrect. © Cypress Semiconductor Corporation, 2009-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in lifesupport systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-50454 Rev. *E Page 7 of 7