Component - UART V2.20

®
PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
2.20
Features
 9-bit address mode with hardware address detection
 Baud rates from 110 to 921600 bps or arbitrary up to 4 Mbps
 RX and TX buffers = 4 to 65535
 Detection of Framing, Parity, and Overrun errors
 Full Duplex, Half Duplex, TX only, and RX only optimized hardware
 Two out of three voting per bit
 Break signal generation and detection
 8x or 16x oversampling
General Description
The UART provides asynchronous communications commonly referred to as RS232 or RS485.
The UART component can be configured for Full Duplex, Half Duplex, RX only, or TX only
versions. All versions provide the same basic functionality. They differ only in the amount of
resources used.
To assist with processing of the UART receive and transmit data, independent size configurable
buffers are provided. The independent circular receive and transit buffers in SRAM and hardware
FIFOs help to ensure that data will not be missed. This allows the CPU to spend more time on
critical real time tasks rather than servicing the UART.
For most use cases, you can easily configure the UART by choosing the baud rate, parity,
number of data bits, and number of start bits. The most common configuration for RS232 is often
listed as “8N1,” which is shorthand for eight data bits, no parity, and one stop bit. This is the
default configuration for the UART component. Therefore, in most applications you only need to
set the baud rate. A second common use for UARTs is in multidrop RS485 networks. The UART
component supports 9-bit addressing mode with hardware address detect, as well as a TX
output enable signal to enable the TX transceiver during transmissions.
UARTs have been around a long time, so there have been many physical-layer and protocollayer variations over time. These include, but are not limited to, RS423, DMX512, MIDI, LIN bus,
legacy terminal protocols, and IrDa. To support the commonly used UART variations, the
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-79351 Rev. **
Revised May 23, 2012
Universal Asynchronous Receiver Transmitter (UART)
®
PSoC Creator™ Component Datasheet
component provides configuration support for the number of data bits, stop bits, parity, hardware
flow control, and parity generation and detection.
As a hardware-compiled option, you can choose to output a clock and serial data stream that
outputs only the UART data bits on the clock’s rising edge. An independent clock and data
output is provided for both the TX and RX. The purpose of these outputs is to allow automatic
calculation of the data CRC by connecting a CRC component to the UART.
When to Use a UART
Use the UART any time a compatible asynchronous communications interface is required,
especially RS232 and RS485 and other variations. You can also use the UART to create more
advanced asynchronous based protocols such as DMX512, LIN, and IrDa, or customer or
industry proprietary.
Do not use a UART in those cases where a specific component has already been created to
address the protocol. For example if a LIN or MIDI component is provided, it has a specific
implementation providing both hardware and protocol layer functionality. The UART is not
needed in this case (subject to component availability).
Input/Output Connections
This section describes the various input and output connections for the UART. Some I/Os may
be hidden on the symbol under the conditions listed in the description of that I/O.
Input
clock
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May Be
Hidden
Y
Description
The clock input defines the baud rate (bit-rate) of the serial communication. The baud-rate
is one-eighth or one-sixteenth the input clock frequency depending on the Oversampling
Rate parameter. This input is visible if the Clock Selection parameter is set to External
Clock. If the internal clock is selected, you must define the desired baud rate during
configuration and PSoC Creator solves the necessary clock frequency.
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PSoC Creator™ Component Datasheet
Input
May Be
Hidden
Universal Asynchronous Receiver Transmitter (UART)
Description
reset
N
The reset input resets the UART state machines (RX and TX) to the idle state. This throws
out any data that was currently being transmitted or received. This input is a synchronous
reset that requires at least one rising edge of the clock. The reset input may be left floating
with no external connection. If nothing is connected to the reset line the component will
assign it a constant logic 0.
rx
Y
The rx input carries the input serial data from another device on the serial bus. This input
is visible and must be connected if the Mode parameter is set to RX Only, Half Duplex, or
Full UART (RX + TX).
cts_n
Y
The cts_n input shows that another device is ready to receive data. It is an active-low
input, (_n). This input is visible if the Flow Control parameter is set to Hardware.
Output
May Be
Hidden
Description
tx
Y
The tx output carries the output serial data to another device on the serial bus. This
output is visible if the Mode parameter is set to TX Only, Half Duplex, or Full UART (RX
+ TX). Cypress recommends that you use an external pull-up resistor to protect the
receiver from unexpected low impulses during active System Reset.
rts_n
Y
The rts output tells another device that your device is ready to receive data. This output is
active-low (_n). The RTS signal goes high when internal FIFO and RX buffer, allocated by
RX Buffer Size parameter (when it is greater than 4), are full. This output is visible if the
Flow Control parameter is set to Hardware.
tx_en
Y
The tx_en output is used primarily for RS485 communication to show that your device is
transmitting on the bus. This output goes high before a transmit starts and low when
transmit is complete. This shows a busy bus to the rest of the devices on the bus. This
output is visible when the Hardware TX Enable parameter is selected.
tx_interrupt
Y
The tx_interrupt output is the logical OR of the group of possible interrupt sources. This
signal goes high while any of the enabled interrupt sources are true. This output is visible
if the Mode parameter is set to TX Only or Full UART (RX + TX).
rx_interrupt
Y
The rx_interrupt output is the logical OR of the group of possible interrupt sources. This
signal goes high while any of the enabled interrupt sources are true. This output is visible
if the Mode parameter is set to RX Only, Half Duplex, or Full UART (RX + TX).
tx_data
Y
The tx_data output is used to shift out the TX data to a CRC component or other logic.
This output is visible when the Enable CRC outputs parameter is selected.
tx_clk
Y
The tx_clk output provides the clock edge used to shift out the TX data to a CRC
component or other logic. This output is visible when the Enable CRC outputs parameter
is selected.
rx_data
Y
The rx_data output is used to shift out the RX data to a CRC component or other logic.
This output is visible when the Enable CRC outputs parameter is selected.
rx_clk
Y
The rx_clk output provides the clock edge used to shift out the RX data to a CRC
component or other logic. This output is visible when the Enable CRC outputs parameter
is selected.
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Universal Asynchronous Receiver Transmitter (UART)
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PSoC Creator™ Component Datasheet
Schematic Macro Information
The default UART in the Component Catalog is a schematic macro using a UART component
with default settings. It is connected to digital input and output Pins components.
Component Parameters
Drag a UART component onto your design and double-click it to open the Configure dialog.
Hardware versus Software Options
Hardware configuration options change the way the project is synthesized and placed in the
hardware. You must rebuild the hardware if you make changes to any of these options. Software
configuration options do not affect synthesis or placement. When you set these parameters
before build time you are setting their initial value, which you can change at any time with the
API provided.
The following sections describe the UART parameters and how they are configured using the
dialog. They also indicate whether the options are hardware or software.
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PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
Configure Tab
The dialog is set up to look like a hyperterminal configuration window to avoid incorrect
configuration of two sides of the bus, because the PC using the hyperterminal is quite often the
other side of the bus.
All of these options are hardware configuration options.
Mode
This parameter defines the functional components you want to include in the UART. This can be
setup to be a bidirectional Full UART (TX + RX) (default), Half Duplex UART (uses half the
resources), RS232 Receiver (RX Only) or Transmitter (TX Only).
Bits per second
This parameter defines the baud-rate or bit-width configuration of the hardware for clock
generation. The default is 57600.
If the internal clock is used (set by the Clock Selection parameter), PSoC Creator generates the
necessary clock to achieve this baud rate.
Data bits
This parameter defines the number of data bits transmitted between start and stop of a single
UART transaction. Options are 5, 6, 7, 8 (default), or 9.

Eight data bits is the default configuration, sending a byte per transfer.
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Universal Asynchronous Receiver Transmitter (UART)

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PSoC Creator™ Component Datasheet
The 9-bit mode does not transmit 9 data bits; the ninth bit takes the place of the parity bit as
an indicator of address using Mark/Space parity. Mark/Space parity should be selected if you
are using 9 data bits mode.
Parity Type
This parameter defines the functionality of the parity bit location in the transfer. This can be set to
None (default), Odd, Even, or Mark/Space. If you selected 9 data bits, then select Mark/Space
as the Parity Type.
API control enabled
This check box is used to change parity by using the control register and the
UART_WriteControlRegister() function. The parity type can be dynamically changed between
bytes without disrupting UART operation if this option selected, but the component uses more
resources.
Stop bits
This parameter defines the number of stop bits implemented in the transmitter. This parameter
can be set to 1 (default) or 2 data bits.
Flow Control
This parameter allows you to choose between Hardware or None (default). When this
parameter is set to Hardware, the CTS and RTS signals become available on the symbol.
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PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
Advanced Tab
Hardware Configuration Options
Clock Selection
This parameter allows you to choose between an internally configured clock or an externally
configured clock or I/O for the baud-rate generation. When set to Internal Clock, the required
clock frequency is calculated and configured by PSoC Creator. In the External Clock mode, the
component does not control the baud rate but can calculate the expected baud rate.
If this parameter is set to Internal Clock, the clock input is not visible on the symbol.
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Universal Asynchronous Receiver Transmitter (UART)
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PSoC Creator™ Component Datasheet
Address Mode
This parameter defines how hardware and software interact to handle device addresses and
data bytes. This parameter can be set to the following types:





Software Byte by Byte – Hardware indicates the detection of an address byte
(UART_RX_STS_MRKSPC status) for every byte received. Software must read the byte and
determine if this address matches the device addresses defined as in the Address #1 or
Address #2 parameters or any other additional addresses.
Software Detect to Buffer – Hardware indicates the detection of an address byte
(UART_RX_STS_MRKSPC status). Software, embedded to RX ISR, reads the byte and
determines if this address matches the device addresses defined as in the Address #1 or
Address #2 parameters (uses UART_RX_STS_ADDR_MATCH status). It then copies all
addressed data, along with the address byte, into the RX buffer defined by the RX Buffer
Size parameter. RX Buffer Size should be set manually to greater than 4. Unaddressed data
is read from FIFO, but not written to the buffer.
Hardware Byte By Byte – Hardware detects addressed bytes and forces an interrupt (RX On Byte Received) to move all data along with the address from the hardware FIFO into the
data buffer defined by RX Buffer Size. Hardware does not save unaddressed bytes to the
FIFO, and does not generate any interrupt for them.
Hardware Detect to Buffer – Hardware detects addressed bytes and forces an interrupt (RX
- On Byte Received) to move only the data (address byte is not included) from the hardware
FIFO into the data buffer defined by RX Buffer Size. Hardware does not save unaddressed
bytes to the FIFO, and does not generate any interrupt for them.
None – No RX address detection is implemented.
RX Address #1/#2
The RX Address parameters indicate up to two device addresses that the UART may assume.
These parameters are stored in hardware for hardware address detection modes described in
the Address Mode parameter. The hardware for RX Address #2 does not implemented in Half
Duplex mode. The parameters are available to firmware for the software address modes.
Advanced Features


Break signal bits – Break signal bits parameter enables Break signal generation and
detection and defines the number of logic 0s bits transmitted. This option saves resources
when set to None.
Enable 2 out of 3 voting per bit – The Enable 2 out of 3 voting per bit parameter enables
or disables the error compensation algorithm. Disabling this option saves resources. For
more information, see the Functional Description section of this datasheet.
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PSoC Creator™ Component Datasheet

Universal Asynchronous Receiver Transmitter (UART)
Enable CRC outputs – The Enable CRC outputs parameter enables or disables tx_data,
tx_clk, rx_data, and rx_clk outputs. They are used to output a clock and serial data stream
that outputs only the UART data bits on the clock’s rising edge. The purpose of these outputs
is to allow automatic calculation of the data CRC. Disabling this option saves resources.
Hardware TX Enable
This parameter enables or disables the use of the TX-Enable output of the TX UART. This signal
is used in RS485 communications. The hardware provides the functionality of this output
automatically, based on buffer conditions.
Oversampling Rate
This parameter allows you to choose clock divider for the baud-rate generation.
Software Configuration Options
Interrupts
The Interrupt On parameters allow you to configure the interrupt sources. These values are
ORed with any of the other Interrupt On parameter to give a final group of events that can
trigger an interrupt. The software can reconfigure these modes at any time; these parameters
define an initial configuration.

RX - On Byte Received
(UART_RX_STS_FIFO_NOTEMPTY)

TX - On TX Complete
(UART_TX_STS_COMPLETE)

RX - On Parity Error
(UART_RX_STS_PAR_ERROR)

TX - On FIFO Empty
(UART_TX_STS_FIFO_EMPTY)

RX - On Stop Error
(UART_RX_STS_STOP_ERROR)

TX - On FIFO Full
(UART_TX_STS_FIFO_FULL)

RX - On Break
(UART_RX_STS_BREAK)

TX - On FIFO Not Full
(UART_TX_STS_FIFO_NOT_FULL)

RX - On Overrun Error
(UART_RX_STS_OVERRUN)

RX - On Address Match
(UART_RX_STS_ADDR_MATCH)

RX - On Address Detect
(UART_RX_STS_MRKSPC)
You may handle the ISR with an external interrupt component connected to the tx_interrupt or
rx_interrupt output. The interrupt output pin is visible depending on the selected Mode
parameter. It outputs the same signal to the internal interrupt based on the selected status
interrupts.
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Universal Asynchronous Receiver Transmitter (UART)
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PSoC Creator™ Component Datasheet
These outputs may then be used as a DMA request source to the DMA from the RX or TX buffer
independent of the interrupt, or as another interrupt, depending on the desired functionality.
RX Buffer Size (bytes)
This parameter defines how many bytes of RAM to allocate for an RX buffer. Data is moved from
the receive registers into this buffer.
Four bytes of hardware FIFO are used as a buffer when the buffer size selected is equal to 4
bytes. Buffer sizes greater than 4 bytes require the use of interrupts to handle moving the data
from the receive FIFO into this buffer. The UART_GetChar() or UART_ReadRXData() functions
get data from the correct source without any changes to your top-level firmware.
When the RX buffer size is greater than 4 bytes, the Internal RX Interrupt ISR is automatically
enabled and the RX – On Byte Received interrupt source is selected and disabled for use
because it causes incorrect handler functionality.
TX Buffer Size (bytes)
This parameter defines how many bytes of RAM to allocate for the TX buffer. Data is written into
this buffer with the UART_PutChar() and UART_PutArray() API commands.
Four bytes of hardware FIFO are used as a buffer when the buffer size selected equal to four
bytes; otherwise, the RAM buffer is allocated. Buffer sizes greater than four bytes require the use
of interrupts to handle moving the data from the transmit buffer into the hardware FIFO without
any changes to your top-level firmware.
When the TX buffer size is greater than four bytes, the Internal TX Interrupt ISR is
automatically enabled and the TX – On FIFO EMPTY interrupt source is selected and disabled
for use because it causes incorrect handler functionality.
The TX interrupt is not available in Half Duplex mode; therefore, the TX Buffer Size is limited to
four bytes when Half Duplex mode is selected.
Internal RX Interrupt ISR
Enables the ISR supplied by the component for the RX portion of the UART. This parameter is
set automatically depending on the RX Buffer Size parameter, because the internal ISR is
needed to handle transferring data from the FIFO to the RX buffer.
Internal TX Interrupt ISR
Enables the ISR supplied by the component for the TX portion of the UART. This parameter is
set automatically depending on the TX Buffer Size parameter, because the internal ISR is
needed to handle transferring data to the FIFO from the TX buffer.
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PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
Clock Selection
When the internal clock configuration is selected, PSoC Creator calculates the needed frequency
and clock source and generates the resource needed for implementation. Otherwise, you must
supply the clock and calculate the baud rate at one-eighth or one-sixteenth the input clock
frequency.
The clock tolerance should be a maximum of ±2 percent. A warning is generated if the clock
cannot be generated within this limit. In that case, you should change the Master Clock in the
DWR or you should use an external crystal-based clock.
Application Programming Interface
Application Programming Interface (API) routines allow you to configure the component using
software. The following table lists and describes the interface to each function. The subsequent
sections cover each function in more detail.
By default, PSoC Creator assigns the instance name “UART_1” to the first instance of a
component in a given design. You can rename the instance to any unique value that follows the
syntactic rules for identifiers. The instance name becomes the prefix of every global function
name, variable, and constant symbol. For readability, the instance name used in the following
table is “UART.”
Function
Description
UART_Start()
Initializes and enables the UART operation
UART_Stop()
Disables the UART operation
UART_ReadControlRegister()
Returns the current value of the control register
UART_WriteControlRegister()
Writes an 8-bit value into the control register
UART_EnableRxInt()
Enables the internal interrupt irq
UART_DisableRxInt()
Disables the internal interrupt irq
UART_SetRxInterruptMode()
Configures the RX interrupt sources enabled
UART_ReadRxData()
Returns the data in the RX Data register
UART_ReadRxStatus()
Returns the current state of the status register
UART_GetChar()
Returns the next byte of received data
UART_GetByte()
Reads the UART RX buffer immediately and returns the received character
and error condition
UART_GetRxBufferSize()
Returns the number of received bytes remaining in the RX buffer and returns
the count in bytes
UART_ClearRxBuffer()
Clears the memory array of all received data
UART_SetRxAddressMode()
Sets the software-controlled Addressing mode used by the RX portion of the
UART
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Universal Asynchronous Receiver Transmitter (UART)
Function
PSoC Creator™ Component Datasheet
Description
UART_SetRxAddress1()
Sets the first of two hardware-detectable addresses
UART_SetRxAddress2()
Sets the second of two hardware-detectable addresses
UART_EnableTxInt()
Enables the internal interrupt irq
UART_DisableTxInt()
Disables the internal interrupt irq
UART_SetTxInterruptMode()
Configures the TX interrupt sources enabled
UART_WriteTxData()
Sends a byte without checking for buffer room or status
UART_ReadTxStatus()
Reads the status register for the TX portion of the UART
UART_PutChar()
Puts a byte of data into the transmit buffer to be sent when the bus is
available
UART_PutString()
Places data from a string into the memory buffer for transmitting
UART_PutArray()
Places data from a memory array into the memory buffer for transmitting
UART_PutCRLF()
Writes a byte of data followed by a Carriage Return and Line Feed to the
transmit buffer
UART_GetTxBufferSize()
Determines the number of bytes used in the TX buffer. An empty buffer
returns 0
UART_ClearTxBuffer()
Clears all data from the TX buffer
UART_SendBreak()
Transmits a break signal on the bus
UART_SetTxAddressMode ()
Configures the transmitter to signal the next bytes as address or data
UART_LoadRxConfig()
Loads the receiver configuration. Half Duplex UART is ready for receive byte
UART_LoadTxConfig()
Loads the transmitter configuration. Half Duplex UART is ready for transmit
byte
UART_Sleep()
Stops the UART operation and saves the user configuration
UART_Wakeup()
Restores and enables the user configuration
UART_Init()
Initializes default configuration provided with customizer
UART_Enable()
Enables the UART block operation
UART_SaveConfig()
Save the current user configuration
UART_RestoreConfig()
Restores the user configuration
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PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
Global Variables
Variable
UART_initVar
Description
Indicates whether the UART has been initialized. The variable is initialized to 0 and
set to 1 the first time UART_Start() is called. This allows the component to restart
without reinitialization after the first call to the UART_Start() routine.
For correct operation of the component, the UART must be initialized before Send
or Put commands are run. Therefore, all APIs that write transmit data must check
that the component has been initialized using this variable.
If reinitialization of the component is required, then the UART_Init() function can be
called before the UART_Start() or UART_Enable() function.
UART_rxBuffer
This is a RAM-allocated RX buffer with a user-defined length. This buffer is used by
interrupts, when the RX Buffer Size parameter is set to more than 4, to store
received data. It is also used by UART_ReadRxData() and UART_GetChar() to
convey data to the user-level firmware.
UART_rxBufferWrite
This variable is used by the RX interrupt as a cyclic index for UART_rxBuffer to
write data. This variable is also used by the UART_ReadRxData() and
UART_GetChar() functions to identify new data. Cleared to zero by the
UART_ClearRxBuffer() function.
UART_rxBufferRead
This variable is used by the UART_ReadRxData() and UART_GetChar() functions
as a cyclic index for UART_rxBuffer to read data. Cleared to zero by the
UART_ClearRxBuffer() function.
UART_rxBufferLoopDetect
This variable is set to one in RX interrupt when the UART_rxBufferWrite index
overtakes the UART_rxBufferRead index. This is a preoverload condition that
affects UART_rxBufferOverflow when the next byte is received. It is set to zero
when the UART_ReadRxData() or UART_GetChar() function is called. Cleared to
zero by the UART_ClearRxBuffer() function.
UART_rxBufferOverflow
This variable is used to indicate overload condition. It set to one in RX interrupt
when there isn’t free space in UART_rxBuffer to write new data. This condition is
returned and cleared to zero by the UART_ReadRxStatus() function as an
UART_RX_STS_SOFT_BUFF_OVER bit along with RX Status register bits.
Cleared to zero by the UART_ClearRxBuffer() function.
UART_txBuffer
This is a RAM-allocated TX buffer of user-defined length. This buffer is used by
sending APIs when the TX Buffer Size parameter is set to more than 4, to store
data for transmitting. It is also used by the TX interrupt to move data into the
hardware FIFO.
UART_txBufferWrite
This variable is used by the UART_WriteTxData(), UART_PutChar(),
UART_PutString(), UART_PutArray(), and UART_PutCRLF() functions as a cyclic
index for UART_txBuffer to write data. This variable is also used by the TX interrupt
to identify new data for transmitting. Cleared to zero by the UART_ClearTxBuffer()
function.
UART_txBufferRead
This variable is used by the TX interrupt as a cyclic index for the UART_txBuffer to
read data. Cleared to zero by the UART_ClearRxBuffer() function.
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Universal Asynchronous Receiver Transmitter (UART)
®
PSoC Creator™ Component Datasheet
void UART_Start(void)
Description:
This is the preferred method to begin component operation. UART_Start() sets the initVar
variable, calls the UART_Init() function, and then calls the UART_Enable() function.
Parameters:
void
Return Value:
void
Side Effects:
If the initVar variable is already set, this function only calls the UART_Enable() function.
void UART_Stop(void)
Description:
Disables the UART operation.
Parameters:
void
Return Value:
void
Side Effects:
None
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PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
uint8 UART_ReadControlRegister(void)
Description:
Returns the current value of the control register.
Parameters:
void
Return Value: uint8: Contents of the control register The following defines can be used to interpret the
returned value. See the Control registers description near the end of this datasheet for more
information.
Value
UART_CTRL_HD_SEND
Configures whether the half duplex UART
(if enabled) is in RX mode (0), or in TX
mode (1).
UART_CTRL_HD_SEND_BREAK
Set to send a break signal on the bus.
This bit is written by the
UART_SendBreak() function.
UART_CTRL_MARK
Configures whether the parity bit during
the next transaction (in Mark/Space parity
mode) will be a 1 or 0.
UART_CTRL_PARITY_TYPE_MASK
Twp bit wide field configuring the parity for
the next transfer if software configurable.
The following defines, shifted left by
UART_CTRL_PARITY_TYPE0_SHIFT,
can be used to recognize the parity type:
UART__B_UART__NONE_REVB
No parity
UART__B_UART__EVEN_REVB
Even parity
UART__B_UART__ODD_REVB
Odd parity
UART__B_UART__MARK_SPACE_REVB
Mark/Space parity
UART_CTRL_RXADDR_MODE_MASK
UART__B_UART__AM_SW_BYTE_BYTE
Three bit wide field configuring the
expected hardware addressing operation
for the UART receiver. The following
defines, shifted left by
UART_CTRL_RXADDR_MODE0_SHIFT,
can be used to recognize the address
mode:
Software Byte-by-Byte address detection
UART__B_UART__AM_SW_DETECT_TO_
BUFFER
Software Detect to Buffer address
detection
UART__B_UART__AM_HW_BYTE_BY_
BYTE
Hardware Byte-by-Byte address detection
UART__B_UART__AM_HW_DETECT_TO_
BUFFER
Hardware Detect to Buffer address
detection
UART__B_UART__AM_NONE
Side Effects:
Description
No address detection
None
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Universal Asynchronous Receiver Transmitter (UART)
®
PSoC Creator™ Component Datasheet
void UART_WriteControlRegister(uint8 control)
Description:
Writes an 8-bit value into the control register
Parameters:
uint8 control: Control register value
Value
Description
UART_ CTRL_HD_SEND
Configures whether the half duplex UART
(if enabled) is in RX mode (0), or in TX
mode (1). Can be set and cleared using
the UART_LoadTxConfig() and
UART_LoadRxConfig() functions.
UART_ CTRL_HD_SEND_BREAK
Set to send a break signal on the bus.
This bit is best written using the
UART_SendBreak() function.
UART_CTRL_MARK
Configures whether the parity bit during
the next transaction (in Mark/Space parity
mode) will be a 1 or 0.
UART_CTRL_PARITY_TYPE_MASK
Two bit wide field configuring the parity
for the next transfer if software
configurable. The following defines,
shifted left by
UART_CTRL_PARITY_TYPE0_SHIFT,
can be used to set the parity type:
UART__B_UART__NONE_REVB
No parity
UART__B_UART__EVEN_REVB
Even parity
UART__B_UART__ODD_REVB
Odd parity
UART__B_UART__MARK_SPACE_REVB
Mark/Space parity
UART_CTRL_RXADDR_MODE_MASK
UART__B_UART__AM_SW_BYTE_BYTE
UART__B_UART__AM_SW_DETECT_TO_
BUFFER
Three bit wide field configuring the
expected hardware addressing operation
for the UART receiver. The following
defines, shifted left by
UART_CTRL_RXADDR_MODE0_SHIFT,
can be used to set the address mode:
Software Byte-by-Byte address detection
Software Detect to Buffer address
detection
Hardware Byte-by-Byte address
UART__B_UART__AM_HW_BYTE_BY_BYTE detection
UART__B_UART__AM_HW_DETECT_TO_
BUFFER
UART__B_UART__AM_NONE
Return Value:
void
Side Effects:
None
Page 16 of 51
Hardware Detect to Buffer address
detection
No address detection
Document Number: 001-79351 Rev. **
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PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
void UART_EnableRxInt(void)
Description:
Enables the internal receiver interrupt.
Parameters:
void
Return Value:
void
Side Effects:
Only available if the RX internal interrupt implementation is selected in the UART
void UART_DisableRxInt(void)
Description:
Disables the internal receiver interrupt.
Parameters:
void
Return Value:
void
Side Effects:
Only available if the RX internal interrupt implementation is selected in the UART
void UART_SetRxInterruptMode(uint8 intSrc)
Description:
Configures the RX interrupt sources enabled.
Parameters:
uint8 intSrc: Bit field containing the RX interrupts to enable. Based on the bit-field
arrangement of the status register. This value must be a combination of status register bitmasks shown below:
Value
Description
UART_RX_STS_FIFO_NOTEMPTY
Interrupt on byte received.
UART_RX_STS_PAR_ERROR
Interrupt on parity error.
UART_RX_STS_STOP_ERROR
Interrupt on stop error.
UART_RX_STS_BREAK
Interrupt on break.
UART_RX_STS_OVERRUN
Interrupt on overrun error.
UART_RX_STS_ADDR_MATCH
Interrupt on address match.
UART_RX_STS_MRKSPC
Interrupt on address detect.
Return Value:
void
Side Effects:
None
Document Number: 001-79351 Rev. **
Page 17 of 51
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Universal Asynchronous Receiver Transmitter (UART)
PSoC Creator™ Component Datasheet
uint8 UART_ReadRxData(void)
Description:
Returns the next byte of received data. This function returns data without checking the
status. You must check the status separately.
Parameters:
void
Return Value:
uint8: Received data from RX register
Side Effects:
None
uint8 UART_ReadRxStatus(void)
Description:
Returns the current state of the receiver status register and the software buffer overflow
status.
Parameters:
void
Return Value:
uint8: Current RX status register value
Value
Side Effects:
Description
UART_RX_STS_FIFO_NOTEMPTY
If set, indicates the FIFO has data available.
UART_RX_STS_PAR_ERROR
If set, indicates a parity error was detected.
UART_RX_STS_STOP_ERROR
If set, indicates a framing error was
detected. The framing error is caused when
the UART hardware sees the logic 0 where
the stop bit should be (logic 1).
UART_RX_STS_BREAK
If set, indicates a break was detected.
UART_RX_STS_OVERRUN
If set, indicates the FIFO buffer was
overrun.
UART_RX_STS_ADDR_MATCH
Indicates that the received byte matches
one of the two addresses available for
hardware address detection. It is not
implemented if Address Mode is set to
None. In Half Duplex mode, only Address
#1 is implemented for this detection.
UART_RX_STS_MRKSPC
Status of the mark/space parity bit. This bit
indicates whether a mark or space was
seen in the parity bit location of the transfer.
It is not implemented if Address Mode is
set to None.
UART_RX_STS_SOFT_BUFF_OVER
If set, indicates the RX buffer was overrun.
All status register bits are clear-on-read except UART_RX_STS_FIFO_NOTEMPTY.
UART_RX_STS_FIFO_NOTEMPTY clears immediately after RX data register read.
See the Registers section later in this datasheet.
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PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
uint8 UART_GetChar(void)
Description:
Returns the last received byte of data. UART_GetChar() is designed for ASCII characters
and returns a uint8 where 1 to 255 are values for valid characters and 0 indicates an error
occurred or no data is present.
Parameters:
void
Return Value:
uint8: Character read from UART RX buffer. ASCII character values from 1 to 255 are valid.
A returned zero signifies an error condition or no data available.
Side Effects:
None
uint16 UART_GetByte(void)
Description:
Reads UART RX buffer immediately, returns received character and error condition.
Parameters:
void
Return Value:
uint16: MSB contains status and LSB contains UART RX data. If the MSB is nonzero, an
error has occurred.
Side Effects:
None
uint8/uint16 UART_GetRxBufferSize(void)
Description:
Returns the number of received bytes remaining in the RX buffer.
Parameters:
void
Return Value:
uint8/uint16: Integer count of the number of bytes left in the RX buffer. Type depends on RX
Buffer Size parameter.
Side Effects:
None
void UART_ClearRxBuffer(void)
Description:
Clears the receiver memory buffer and hardware RX FIFO of all received data.
Parameters:
void
Return Value:
void
Side Effects:
None
Document Number: 001-79351 Rev. **
Page 19 of 51
Universal Asynchronous Receiver Transmitter (UART)
®
PSoC Creator™ Component Datasheet
void UART_SetRxAddressMode(uint8 addressMode)
Description:
Sets the software controlled Addressing mode used by the RX portion of the UART.
Parameters:
uint8 addressMode: Enumerated value indicating the mode of RX addressing to implement
Value
UART__B_UART__AM_SW_BYTE_BYTE
Description
Software Byte-by-Byte
address detection
UART__B_UART__AM_SW_DETECT_TO_BUFFER Software Detect to Buffer
address detection
UART__B_UART__AM_HW_BYTE_BY_BYTE
Hardware Byte-by-Byte
address detection
UART__B_UART__AM_HW_DETECT_TO_BUFFER Hardware Detect to Buffer
address detection
UART__B_UART__AM_NONE
Return Value:
void
Side Effects:
None
No address detection
void UART_SetRxAddress1(uint8 address)
Description:
Sets the first of two hardware-detectable receiver addresses.
Parameters:
uint8 address: Address #1 for hardware address detection
Return Value:
void
Side Effects:
None
void UART_SetRxAddress2(uint8 address)
Description:
Sets the second of two hardware-detectable receiver addresses.
Parameters:
uint8 address: Address #2 for hardware address detection
Return Value:
void
Side Effects:
None
Page 20 of 51
Document Number: 001-79351 Rev. **
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PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
void UART_EnableTxInt(void)
Description:
Enables the internal transmitter interrupt.
Parameters:
void
Return Value:
void
Side Effects:
Only available if the TX internal interrupt implementation is selected in the UART
configuration.
void UART_DisableTxInt(void)
Description:
Disables the internal transmitter interrupt.
Parameters:
void
Return Value:
void
Side Effects:
Only available if the TX internal interrupt implementation is selected in the UART
configuration.
void UART_SetTxInterruptMode(uint8 intSrc)
Description:
Configures the TX interrupt sources to be enabled (but does not enable the interrupt).
Parameters:
uint8 intSrc: Bit field containing the TX interrupt sources to enable
Value
Description
UART_TX_STS_COMPLETE
Interrupt on TX byte complete
UART_TX_STS_FIFO_EMPTY
Interrupt when TX FIFO is empty
UART_TX_STS_FIFO_FULL
Interrupt when TX FIFO is full
UART_TX_STS_FIFO_NOT_FULL
Interrupt when TX FIFO is not full
Return Value:
void
Side Effects:
None
void UART_WriteTxData(uint8 txDataByte)
Description:
Places a byte of data into the transmit buffer to be sent when the bus is available without
checking the TX status register. You must check status separately.
Parameters:
uint8 txDataByte: data byte
Return Value:
void
Side Effects:
None
Document Number: 001-79351 Rev. **
Page 21 of 51
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Universal Asynchronous Receiver Transmitter (UART)
PSoC Creator™ Component Datasheet
uint8 UART_ReadTxStatus(void)
Description:
Reads the status register for the TX portion of the UART.
Parameters:
void
Return Value:
uint8: Contents of the TX Status register
Value
Description
UART_TX_STS_COMPLETE
If set, indicates byte was transmitted
successfully
UART_TX_STS_FIFO_EMPTY
If set, indicates the TX FIFO is empty
UART_TX_STS_FIFO_FULL
If set, indicates the TX FIFO is full
UART_TX_STS_FIFO_NOT_FULL If set, indicates the FIFO is not full
Side Effects:
This function reads the TX status register, which is cleared on read.
void UART_PutChar(uint8 txDataByte)
Description:
Puts a byte of data into the transmit buffer to be sent when the bus is available. This is a
blocking API that waits until the TX buffer has room to hold the data.
Parameters:
uint8 txDataByte: Byte containing the data to transmit
Return Value:
void
Side Effects:
None
void UART_PutString(char* string)
Description:
Sends a NULL terminated string to the TX buffer for transmission.
Parameters:
char* string: Pointer to the null terminated string array residing in RAM or ROM
Return Value:
void
Side Effects:
If there is not enough memory in the TX buffer for the entire string, this function blocks until
the last character of the string is loaded into the TX buffer.
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PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
void UART_PutArray(uint8* string, uint8/uint16 byteCount)
Description:
Places N bytes of data from a memory array into the TX buffer for transmission.
Parameters:
uint8* string: Address of the memory array residing in RAM or ROM
uint8/uint16 byteCount: Number of bytes to be transmitted. The type depends on TX Buffer
Size parameter.
Return Value:
void
Side Effects:
If there is not enough memory in the TX buffer for the entire array, this function blocks until
the last byte of the array is loaded into the TX buffer.
void UART_PutCRLF(uint8 txDataByte)
Description:
Writes a byte of data followed by a carriage return (0x0D) and line feed (0x0A) to the transmit
buffer.
Parameters:
uint8 txDataByte: Data byte to transmit before the carriage return and line feed
Return Value:
void
Side Effects:
If there is not enough memory in the TX buffer for all three bytes, this function blocks until the
last of the three bytes are loaded into the TX buffer.
uint8/uint16 UART_GetTxBufferSize(void)
Description:
Determines the number of bytes used in the TX buffer. An empty buffer returns 0.
Parameters:
void
Return Value:
uint8/uint16: The number of bytes used in the TX buffer. The type depends on the TX Buffer
Size parameter.
Side Effects:
None
void UART_ClearTxBuffer(void)
Description:
Clears all data from the TX buffer and hardware TX FIFO.
Parameters:
void
Return Value:
void
Side Effects:
Data waiting in the transmit buffer is not sent; a byte that is currently transmitting finishes
transmitting.
Document Number: 001-79351 Rev. **
Page 23 of 51
Universal Asynchronous Receiver Transmitter (UART)
®
PSoC Creator™ Component Datasheet
void UART_SendBreak(uint8 retMode)
Description:
Transmits a break signal on the bus.
Parameters:
uint8 retMode: Send Break return mode. See the following table for options.
Options
Description
UART_SEND_BREAK
Initialize registers for break, send the Break
signal and return immediately
UART_WAIT_FOR_COMPLETE_REINIT Wait until break transmission is complete,
reinitialize registers to normal transmission
mode then return
UART_REINIT
Reinitialize registers to normal transmission
mode then return
UART_SEND_WAIT_REINIT
Performs both options: UART_SEND_BREAK
and UART_WAIT_FOR_COMPLETE_REINIT.
This option is recommended for most cases
Return Value:
void
Side Effects:
The UART_SendBreak() function initializes registers to send a break signal. Break signal
length depends on the break signal bits configuration. The register configuration should be
reinitialized before normal 8-bit communication can continue.
void UART_SetTxAddressMode(uint8 addressMode)
Description:
Configures the transmitter to signal the next bytes is address or data.
Parameters:
uint8 addressMode:
Options
Description
UART_SET_SPACE
Configure the transmitter to send the next byte as a data.
UART_SET_MARK
Configure the transmitter to send the next byte as an address.
Return Value:
void
Side Effects:
This function sets and clears UART_CTRL_MARK bit in the Control register.
void UART_LoadRxConfig(void)
Description:
Loads the receiver configuration in half duplex mode. After calling this function, the UART is
ready to receive data.
Parameters:
void
Return Value:
void
Side Effects:
Valid only in half duplex mode. You must make sure that the previous transaction is complete
and it is safe to unload the transmitter configuration.
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Document Number: 001-79351 Rev. **
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PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
void UART_LoadTxConfig(void)
Description:
Loads the transmitter configuration in half duplex mode. After calling this function, the UART
is ready to transmit data.
Parameters:
void
Return Value:
void
Side Effects:
Valid only in half duplex mode. You must make sure that the previous transaction is complete
and it is safe to unload the receiver configuration.
void UART_Sleep(void)
Description:
This is the preferred API to prepare the component for sleep. The UART_Sleep() API saves
the current component state. Then it calls the UART_Stop() function and calls
UART_SaveConfig() to save the hardware configuration.
Call the UART_Sleep() function before calling the CyPmSleep() or the CyPmHibernate()
function. Refer to the PSoC Creator System Reference Guide for more information about
power management functions.
Parameters:
void
Return Value:
void
Side Effects:
None
void UART_Wakeup(void)
Description:
This is the preferred API to restore the component to the state when UART_Sleep() was
called. The UART_Wakeup() function calls the UART_RestoreConfig() function to restore the
configuration. If the component was enabled before the UART_Sleep() function was called,
the UART_Wakeup() function will also re-enable the component.
Parameters:
void
Return Value:
void
Side Effects:
This function clears the RX and TX software buffers and hardware FIFOs and will not reset
any hardware state machines. Calling the UART_Wakeup() function without first calling the
UART_Sleep() or UART_SaveConfig() function may produce unexpected behavior.
Document Number: 001-79351 Rev. **
Page 25 of 51
Universal Asynchronous Receiver Transmitter (UART)
®
PSoC Creator™ Component Datasheet
void UART_Init(void)
Description:
Initializes or restores the component according to the customizer Configure dialog settings.
It is not necessary to call UART_Init() because the UART_Start() API calls this function and
is the preferred method to begin component operation.
Parameters:
None
Return Value:
None
Side Effects:
All registers will be set to values according to the customizer Configure dialog.
void UART_Enable(void)
Description:
Activates the hardware and begins component operation. It is not necessary to call
UART_Enable() because the UART_Start() API calls this function, which is the preferred
method to begin component operation.
Parameters:
None
Return Value:
None
Side Effects:
None
void UART_SaveConfig(void)
Description:
This function saves the component configuration and nonretention registers. It also saves
the current component parameter values, as defined in the Configure dialog or as modified
by appropriate APIs. This function is called by the UART_Sleep() function.
Parameters:
None
Return Value:
None
Side Effects:
All nonretention registers except FIFO are saved to RAM.
void UART_RestoreConfig(void)
Description:
Restores the user configuration of nonretention registers.
Parameters:
None
Return Value:
None
Side Effects:
All nonretention registers except FIFO loaded from RAM. This function should be called only
after UART_SaveConfig() is called, otherwise incorrect data will be loaded into the registers.
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Document Number: 001-79351 Rev. **
®
PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
Defines
The following defines are provided only for reference. The define values are determined by the
component customizer settings.
Define
Description
UART_INIT_RX_INTERRUPTS_MASK
Defines the initial configuration of the interrupt sources that you chose in
the configuration GUI. This is a mask of the bits in the status register
that have been enabled at configuration as sources for the RX interrupt.
UART_INIT_TX_INTERRUPTS_MASK
Defines the initial configuration of the interrupt sources that you chose in
the configuration GUI. This is a mask of the bits in the status register
that have been enabled at configuration as sources for the TX interrupt.
UART_TXBUFFERSIZE
Defines the amount of memory to allocate for the TX memory array
buffer. This does not include the four bytes included in the FIFO.
UART_RXBUFFERSIZE
Defines the amount of memory to allocate for the RX memory array
buffer. This does not include the four bytes included in the FIFO.
UART_NUMBER_OF_DATA_BITS
Defines the number of bits per data transfer, which is used to calculate
the Bit-Clock Generator and Bit Counter configuration registers.
UART_BIT_CENTER
Based on the number of data bits, this value is used to calculate the
center point for the RX Bit-Clock Generator which is loaded into the
configuration register at startup of the UART.
UART_RXHWADDRESS1
Defines the initial address selected in the configuration GUI. This
address is loaded into the corresponding hardware register at startup of
the UART.
UART_RXHWADDRESS2
Defines the initial address selected in the configuration GUI. This
address is loaded into the corresponding hardware register at startup of
the UART.
Sample Firmware Source Code
PSoC Creator provides many example projects that include schematics and example code in the
Find Example Project dialog. For component-specific examples, open the dialog from the
Component Catalog or an instance of the component in a schematic. For general examples,
open the dialog from the Start Page or File menu. As needed, use the Filter Options in the
dialog to narrow the list of projects available to select.
Refer to the “Find Example Project” topic in the PSoC Creator Help for more information.
Document Number: 001-79351 Rev. **
Page 27 of 51
Universal Asynchronous Receiver Transmitter (UART)
®
PSoC Creator™ Component Datasheet
Functional Description
The UART component provides synchronous communication commonly referred to as RS232 or
RS485. The UART can be configured for full duplex, half duplex, RX only, or TX only operation.
The following sections give an overview of how to use the UART component.
Default Configuration
The default configuration for the UART is as an 8-bit UART with no flow control and no parity,
running at a baud rate of 57.6 Kbps
UART Mode: Full UART (RX+TX)
This mode implements a full-duplex UART consisting of an asynchronous Receiver and
Transmitter. A single clock is needed in this mode to define the baud rate for both the receiver
and transmitter.
UART Mode: Half Duplex
This mode implements a full UART, but uses half as many resources as the full UART
configuration. In this configuration, the UART can be configured to switch between RX mode and
TX mode, but cannot perform RX and TX operations simultaneously. The RX or TX configuration
can be loaded by calling the UART_LoadRxConfig() or UART_LoadTxConfig() function.
In this mode, the TX – On FIFO Not Full status is not available, but the TX – On FIFO Full
status can be used instead. Because TX interrupts are not available in this mode, the TX buffer
size is limited to four bytes.
In Half Duplex mode, the Address2 parameter does not work for hardware address match status
(UART_RX_STS_ADDR_MATCH), but it can still be used by software.
Half Duplex mode example:


This example assumes the component has been placed in a design with the name UART_1.
Configure UART to Mode: Half Duplex, Bits per second: 115200, Data bits: 8, Parity Type:
None, Rx Buffer Size: 4, Tx Buffer Size:4.
#include <device.h>
void main()
{
uint8 recByte;
uint8 tmpStat;
CyGlobalIntEnable;
/* Enable interrupts */
UART_1_Start();
UART_1_LoadTxConfig();
/* Start UART */
/* Configure UART for transmitting */
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PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
UART_1_PutString("Half Duplex Test");
/* Send message */
/* make sure that data has been transmitted */
CyDelay(30);
/* Appropriate delay could be used */
/* Alternatively, check TX_STS_COMPLETE status bit */
UART_1_LoadRxConfig(); /* Configure UART for receiving */
while(1)
{
recByte = UART_1_GetChar();
/* Check for receive byte */
if(recByte > 0)
/* If byte received */
{
UART_1_LoadTxConfig();
/* Configure UART for transmitting */
UART_1_PutChar(recByte);
/* Send received byte back */
do
/* wait until transmission complete */
{
/* Read Status register */
tmpStat = UART_1_ReadTxStatus();
/* Check the TX_STS_COMPLETE status bit */
}while(~tmpStat & UART_1_TX_STS_COMPLETE);
UART_1_LoadRxConfig();
/* Configure UART for receiving */
}
}
}
UART Mode: RX Only
This mode implements only the receiver portion of the UART. A single clock is needed in this
mode to define the baud rate for the receiver.
UART Mode: TX Only
This mode implements only the transmitter portion of the UART. A single clock is needed in this
mode to define the baud rate for the transmitter.
UART Flow Control: None, Hardware
Flow control on the UART provides separate RX and TX status indication lines to the existing
bus. When hardware flow control is enabled, a ‘Request to Send’ (RTS) line and a ‘Clear to
Send’ (CTS) line are available between this UART and another UART. The CTS line is an input
to the UART that is set by the other UART in the system when it is OK to send data on the bus.
The RTS line is an output of the UART informing the other UART on the bus that it is ready to
receive data. The RTS line of one UART is connected to the CTS line of the other UART and
vice versa. These lines are only valid before a transmission is started. If the signal is set or
cleared after a transfer is started the change will only affect the next transfer.
UART Parity: None
In this mode, there is no parity bit. The data flow is "Start, Data, Stop."
Document Number: 001-79351 Rev. **
Page 29 of 51
Universal Asynchronous Receiver Transmitter (UART)
®
PSoC Creator™ Component Datasheet
UART Parity: Odd
Odd parity begins with the parity bit equal to 1. Each time a 1 is encountered in the data stream,
the parity bit is toggled. At the end of the data transmission the state of the parity bit is
transmitted. Odd parity ensures that there is always a transition on the UART bus. If all data is
zero then the parity bit sent will equal 1. The data flow is "Start, Data, Parity, Stop." Odd parity is
the most common parity type used.
UART Parity: Even
Even parity begins with the parity bit equal to 0. Each time a 1 is encountered in the data stream,
the parity bit is toggled. At the end of the data transmission the state of the parity bit is
transmitted. The data flow is "Start, Data, Parity, Stop."
UART Parity: Mark/Space, Data bits: 9
Mark/Space parity is most typically used to define whether the data sent was an address or
standard data. A mark (1) in the parity bit indicates data was sent and a space (0) in the parity bit
indicates an address was sent. The mark or space is sent in the parity bit position in the data
transmission. The data flow is "Start, Data, Parity, Stop," similar to the other parity modes, but
this bit is set by software before the transfer rather than being calculated based on the data bit
values. This parity is available for RS485 and similar protocols.
TX Usage Model
Firmware should use the UART_SetTxAddressMode API with the UART_SET_MARK parameter
to configure the transmitter for the first address byte in the packet. This API sets the
UART_CTRL_MARK bit in the control register. After setting the MARK parity, the first byte sent
is an address and the remaining bytes are sent as data with SPACE parity. The transmitter
automatically sends data bytes after the first address byte. Before sending another packet, the
UART_CTRL_MARK bit in control register should be cleared for at least for one clock. This can
be done by calling the UART_SetTxAddressMode API with the UART_SET_SPACE parameter.
This is shown in the code example below.
Send addressed packet example:


This example assumes the component has been placed in a design with the name
UART_TX.
Configure UART to Data bits: 9, Parity Type: Mark/Space.
#include <device.h>
void main()
{
UART_TX_Start();
/*Set UART_CTRL_MARK bit in Control register*/
UART_TX_SetTxAddressMode(UART_TX_SET_MARK);
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PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
/*Send data packet with the address in first byte*/
/*The address byte is character '1', which is equal to 0x31 in hex format*/
UART_TX_PutString("1UART TEST\r");
/*Clear UART_CTRL_MARK bit in Control register*/
UART_TX_SetTxAddressMode(UART_TX_SET_SPACE);
}
RX Usage Model
There are four different modes for the receiver.
1. Software Byte by Byte
Use this mode when you need custom code.
The UART_RX_STS_MRKSPC bit in the status register indicates that the address or data byte
reached the receiver.
Receive addressed packet example:



This example assumes the component has been placed in a design with the name
UART_RX.
Configure UART to Data bits: 9, Parity Type: Mark/Space, Interrupts: RX - On Byte
Received, Address Mode: Software Byte by Byte, Address#1: 31.
Connect external ISR to rx_interrupt pin with the name “isr_rx.”
#include <device.h>
#define STR_LEN_MAX
60u
char rx_buffer[STR_LEN_MAX];
uint8 packet_receivedRX = 0u;
void main()
{
CyGlobalIntEnable;
isr_rx_Start();
UART_RX_Start();
/* Enable interrupts */
if(packet_receivedRX == 1u)
{
/* add analyze here */
packet_receivedRX = 0u;
}
}
Source Code Example for ISR routine
uint8 rec_status = 0u;
uint8 rec_data = 0;
static uint8 pointerRX = 0u;
static uint8 address_detected = 0u;
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Universal Asynchronous Receiver Transmitter (UART)
®
PSoC Creator™ Component Datasheet
rec_status = UART_RX_RXSTATUS_REG;
if(rec_status & UART_RX_RX_STS_FIFO_NOTEMPTY)
{
rec_data = UART_RX_RXDATA_REG;
if(rec_status & UART_RX_RX_STS_MRKSPC)
{
if (rec_data == UART_RX_RXHWADDRESS1) /* Use any other address */
{
address_detected = 1;
}
else
{
address_detected = 0;
}
}
else
{
if(address_detected)
{
if(pointerRX >= STR_LEN_MAX)
{
pointerRX = 0u;
}
/* Detect end of packet */
if(rec_data == '\r')
{
/* write null terminated string */
rx_buffer[pointerRX++] = 0u;
pointerRX = 0u;
paket_receivedRX = 1u;
}
else
{
rx_buffer[pointerRX++] = rec_data;
}
}
}
}
2. Software Detect to Buffer
All necessary code is implemented in RX ISR in this mode.

Configure UART to Data bits: 9, Parity Type: Mark/Space, RX Buffer Size: 20, Address
Mode: Software Detect to Buffer, Address#1: 31.
Receive addressed packet example:
void main()
{
uint8 rec_data = 0u;
CyGlobalIntEnable;
UART_RX_Start();
for(;;)
{
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/* Enable interrupts */
Document Number: 001-79351 Rev. **
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PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
rec_data = UART_RX_GetChar();
if(rec_data > 0u)
{
/* add analyze here */
}
}
}
3. Hardware Byte By Byte
The hardware filters unaddressed packets. The main code for this mode will look similar to the
previous example.

Configure UART to Data bits: 9, Parity Type: Mark/Space, RX Buffer Size: 20, Address
Mode: Hardware Byte By Byte, Address#1: 31.
4. Hardware Detect to Buffer
This is the preferred mode for a project that doesn’t require an address byte. The hardware filters
the unaddressed packets within an address byte. The main code receives the addressed data
only bytes.

Configure UART to Data bits: 9, Parity Type: Mark/Space, RX Buffer Size: 20, Address
Mode: Hardware Detect to Buffer, Address#1: 31.
UART Stop Bits: One, Two
The number of stop bits is available as a synchronization mechanism. In slower systems, it is
sometimes necessary for the stop command to occupy two bit times in order to allow the
receiving side to process the data before more data is sent. Sending two bit-widths of the stop
signal, the transmitter allows the receiver extra time to interpret the data byte and parity. The
second stop bit is not checked for a framing error by the receiver. The data flow is the same,
"Start, Data, [Parity], Stop.” The stop bit time can be configured to either one or two bit widths.
2 out of 3 Voting
The 2 out of 3 voting feature enables an error compensation algorithm. This algorithm essentially
oversamples the middle of each bit three times and performs a majority vote to decide whether
the bit is a 0 or a 1. If 2 out of 3 voting is not enabled, the middle of each bit is only sampled
once.
When enabled, this parameter requires additional hardware resources to implement a 3-bit
counter based on the RX input for three oversampling clock cycles. The following diagram shows
the implementation of 8-bit and 16-bit oversampling, with and without 2 out of 3 voting.
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Universal Asynchronous Receiver Transmitter (UART)
Falling edge
detection
PSoC Creator™ Component Datasheet
8x Sample
Range
Start bit
bit0
16x
Sample
Range
rx
without 2 out
of 3 voting
clock 8x
rx_state
IDLE
CHECK_START
1
count
0
GET_DATA
7
6
with 2 out of 3 voting
per bit
sample
4
2
3
1
0
7
6
rx
2
2/3 count
1
2/3
sample
range
5
4
3
2
5
4
3
rx
0
7
6
1
2
3
5
4
3
2
1
0
7
6
1
2
3
sampled values
<2 ? 0 : 1
2/3 sample
with 2 out of 3 voting per bit
and oversampling rate 16x
5
clock 16x
2/3 count
2/3
sample
range
6
5
4
3
2
1
0
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0 15 14 13 12 11 10 9
1 2 3
1 2 3
rx
rx
8
7
2/3 sample
sample
Falling edge detection is implemented to recognize the start bit. After this detection, the counter
starts down counting from the half bit length to 0, and the receiver switches to CHECK_START
state. When the counter reaches 0, the RX line is sampled three times. If the RX line is verified
to be low (for example, at least 2 out of 3 bits were 0), the receiver goes to the GET_DATA state.
Otherwise, the receiver will return to the IDLE state. The start bit detection sequence is the same
for 8x or 16x oversampling rates.
Once the receiver has entered the GET_DATA state, the RX input is fed into a counter that is
enabled on counter cycles 3 to 5 (3 cycles). This counter counts the number of 1s seen on the
RX input. If the counter value is 2 or greater, the output of this counter is 1; otherwise, the output
is 0. This value is sampled into the datapath as the RX value on the fifth clock edge. If voting is
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PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
not enabled, the RX input is simply sampled on the fourth clock edge after the detection of the
start bit, and continues every eighth positive clock edge after that.
When an oversampling rate of 16x is enabled, the voting algorithm occurs on counter cycles 7 to
9 and the output of the counter is sampled by the datapath as the RX value on the ninth cycle. If
voting is not enabled, the RX input is sampled on the eighth clock edge and continues on every
sixteenth clock edge after that.
Block Diagram and Configuration
The UART is implemented in the UDB blocks and is described in Figure 1.
Figure 1. UDB Implementation
Registers
The API functions previously described provide support for the common run time functions
required for most applications. The following sections provide brief descriptions of the UART
registers for the advanced user.
RX and TX Status
The status registers (RX and TX have independent status registers) are read-only registers that
contain the various status bits defined for the UART. The value of these registers can be
accessed using the UART_ReadRxStatus() and UART_ReadTxStatus() function calls.
The interrupt output signals (tx_interrupt and rx_interrupt) are generated by ORing the masked
bit fields within each register. The masks can be set using the UART_SetRxInterruptMode() and
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Universal Asynchronous Receiver Transmitter (UART)
®
PSoC Creator™ Component Datasheet
UART_SetTxInterruptMode() function calls. Upon receiving an interrupt, the interrupt source can
be retrieved by reading the respective status register with the UART_GetRxInterruptSource()
and UART_GetTxInterruptSource() function calls. The status registers are clear-on-read so the
interrupt source is held until one of the UART_ReadRxStatus() or UART_ReadTxStatus()
functions is called. All operations on the status register must use the following defines for the bit
fields because these bit fields may be moved within the status register at build time.
There are several bit-fields masks defined for the status registers. Any of these bit fields may be
included as an interrupt source. The #defines are available in the generated header file (.h).
The status data is registered at the input clock edge of the UART. Several of these bits are sticky
and are cleared on a read of the status register. They are assigned as clear-on-read for use as
an interrupt output for the UART. All other bits are configured as transparent and represent the
data directly from the inputs of the status register; they are not sticky and therefore are not clearon-read.
All bits configured as sticky are indicated with an asterisk (*) in the following defines:
RX Status Register
Define
Description
UART_RX_STS_MRKSPC *
Status of the mark/space parity bit. This bit indicates whether a mark or
space was seen in the parity bit location of the transfer. It is only
implemented if the address mode is not set to None.
UART_RX_STS_BREAK *
Indicates that a break signal was detected in the transfer.
UART_RX_STS_PAR_ERROR *
Indicates that a parity error was detected in the transfer.
UART_RX_STS_STOP_ERROR *
This bit indicates framing error. The framing error is caused when the
UART hardware sees the logic 0 where the stop bit should be (logic 1).
UART_RX_STS_OVERRUN *
Indicates that the receive FIFO buffer has been overrun.
UART_RX_STS_FIFO_NOTEMPTY
Indicates whether the Receive FIFO is Not Empty.
UART_RX_STS_ADDR_MATCH *
Indicates that the received byte matches one of the two addresses
available for hardware address detection. It is only implemented if the
address mode is not set to None. In Half Duplex mode, only Address #1
is implemented for this detection.
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PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
TX Status Register
Define
Description
UART_TX_STS_FIFO_FULL
UART_TX_STS_FIFO_NOT_FULL
Indicates that the transmit FIFO is full. This should not be confused with
the transmit buffer implemented in memory because the status of that
buffer is not indicated in hardware; it must be checked in firmware.
1
Indicates that the transmit FIFO is not full.
UART_TX_STS_FIFO_EMPTY
Indicates that the transmit FIFO is empty.
UART_TX_STS_COMPLETE *
Indicates that the last byte has been transmitted from FIFO.
Control
The control register allows you to control the general operation of the UART. This register is
written with the UART_WriteControlRegister() function and read with the
UART_ReadControlRegister() function. The control register is not used if simple UART options
are selected in the customizer; for more details, see Resources. When you read or write the
control register you must use the bit-field definitions as defined in the header (.h) file. The
#defines for the control register are as follows:
UART_CTRL_HD_SEND
Used to dynamically reconfigure between RX and TX operation in half duplex mode. This bit is
set by the UART_LoadTxConfig() function and cleared by the UART_LoadRxConfig() function.
UART_CTRL_HD_SEND_BREAK
When set, will send a break signal on the bus. This bit is written by the UART_SendBreak()
function.
UART_CTRL_MARK
Used to control the Mark/Space parity operation of the transmit byte. When set, this bit indicates
that the next byte transmitted on the bus will include a 1 (Mark) in the parity bit location. All
subsequent bytes will contain a 0 (Space) in the parity bit location until this bit is cleared and
reset by firmware.
1
Not available in half-duplex mode.
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Universal Asynchronous Receiver Transmitter (UART)
PSoC Creator™ Component Datasheet
UART_CTRL_PARITY_TYPE_MASK
The parity type control is a 2-bit-wide field that defines the parity operation for the next transfer.
This bit field is two consecutive bits in the control register. All operations on this bit field must use
the #defines associated with the parity types available. These are:
Value
Description
UART__B_UART__NONE_REVB
No parity
UART__B_UART__EVEN_REVB
Even parity
UART__B_UART__ODD_REVB
Odd parity
UART__B_UART__MARK_SPACE_REVB
Mark/Space parity
This bit field is configured at initialization with the parity type defined in the Parity Type
configuration parameter and may be modified during run time using the
UART_WriteControlRegister() function call.
UART_CTRL_RXADDR_MODE_MASK
The RX address mode control is a 3-bit field used to define the expected hardware addressing
operation for the UART receiver. This bit field is three consecutive bits in the control register. All
operations on this bit field must use the #defines associated with the compare modes available.
These are:
Value
Description
UART__B_UART__AM_SW_BYTE_BYTE
Software Byte by Byte address detection
UART__B_UART__AM_SW_DETECT_TO_BUFFER
Software Detect to Buffer address detection
UART__B_UART__AM_HW_BYTE_BY_BYTE
Hardware Byte by Byte address detection
UART__B_UART__AM_HW_DETECT_TO_BUFFER
Hardware Detect to Buffer address detection
UART__B_UART__AM_NONE
No address detection
This bit field is configured at initialization with the Address Mode configuration parameter and
can be modified during run time using the UART_WriteControlRegister() function call.
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PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
TX Data (8-bits)
The TX data register contains the data to be transmitted. This is implemented as a FIFO. There
is a software state machine to control data from the transmit memory buffer to handle larger
portions of data to be sent. All functions dealing with the transmission of data must go through
this register in order to place the data onto the bus. If there is data in this register and flow
control indicates that data can be sent, then the data is transmitted on the bus. As soon as this
register (FIFO) is empty, no more data is transmitted on the bus until it is added to the FIFO.
DMA may be set up to fill this FIFO when empty using the TX data register address defined in
the header file.
Value
UART_TXDATA_REG
Description
TX data register
RX Data
The RX data register contains the received data, implemented as a FIFO. There is a software
state machine to control data movement from this receive FIFO into the memory buffer.
Typically, the RX interrupt indicates that data has been received, at which time the data can be
retrieved with either the CPU or DMA. DMA may be set up to retrieve data from this register
whenever the FIFO is not empty using the RX data register address defined in the header file.
Value
UART_RXDATA_REG
Description
RX data register
Constants
There are several constants defined for the status and control registers as well as some
enumerated types. Most of these are described earlier for the status and control registers.
However, there are more constants needed in the header file. Each of the register definitions
requires either a pointer into the register data or a register address. Due to multiple endianness`
of the compilers the CY_GET_REGX and CY_SET_REGX macros must be used to access
registers greater than 8 bits in length. These macros require the use of the defines ending in
_PTR for each of the registers.
The control and status register bits must be allowed to be placed and routed by the fitter engine
during build time. Constants are created to define the placement of the bits. For each of the
status and control register bits, there is an associated _SHIFT value that defines the bit’s offset
within the register. These are used in the header file to define the final bit mask as a _MASK
definition (the _MASK extension is only added to bit fields greater than a single bit; all single bit
values drop the _MASK extension).
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Universal Asynchronous Receiver Transmitter (UART)
PSoC Creator™ Component Datasheet
Resources
The UART component is placed throughout the UDB array. The component utilizes the following
resources.
Resource Type
Configuration
Datapath
Cells
Macrocel
ls
Status
Cells
Control
Cells
DMA
Channels
Interrupts
Full UART
3
59
2
2
–
2
Simple UART
3
22
2
1
–
0
Half Duplex
1
21
1
2
–
0
RX Only
1
12
1
1
–
0
TX Only
1
10
1
1
–
0
API Memory Usage
The component memory usage varies significantly, depending on the compiler, device, number
of APIs used and component configuration. The following table provides the memory usage for
all APIs available in the given component configuration.
The measurements have been done with associated compiler configured in Release mode with
optimization set for Size. For a specific design the map file generated by the compiler can be
analyzed to determine the memory usage.
PSoC 3 (Keil_PK51)
Configuration
PSoC 5 (GCC)
PSoC 5LP (GCC)
Flash
SRAM
Flash
SRAM
Flash
SRAM
Bytes
Bytes
Bytes
Bytes
Bytes
Bytes
Full UART
1681
24
1880
35
1776
27
Simple UART
564
5
890
10
770
6
Half Duplex
590
4
950
5
906
5
RX Only
236
3
456
5
388
5
TX Only
431
4
624
6
556
6
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Document Number: 001-79351 Rev. **
®
PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
DC and AC Electrical Characteristics
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted.
Specifications are valid for 1.71 V to 5.5 V, except where noted.
DC Characteristics
Parameter
IDD(Full)
Description
[3]
Operating current
[4]
[3]
Operating current
[4]
[3]
Operating current for receive operation
[4]
[4]
Operating current for transmit operation
Units
–
520
–
µA/Mbps
–
850
–
µA/Mbps
–
130
–
µA/Mbps
–
360
–
µA/Mbps
–
100
–
µA/Mbps
–
140
–
µA/Mbps
–
220
–
µA/Mbps
–
70
–
µA/Mbps
–
100
–
µA/Mbps
–
50
–
µA/Mbps
–
200
–
µA/Mbps
Component current consumption (RX Only)
Idle current
[3]
Operating current
IDD(TX)
Max
Component current consumption (Half Duplex)
Idle current
IDD(RX)
[2]
Component current consumption (Simple UART)
Idle current
IDD(HalfDuplex)
Typ
Component current consumption (Full UART)
Idle current
IDD(Simple)
Min
[4]
Component current consumption (TX Only)
Idle current
[3]
Operating current
[4]
2. Device IO and clock distribution current not included. The values are at 25 °C.
3. Current consumed by component while it is enabled but not transmitting/receiving data.
4. Current consumed by component while it is enabled and transmitting/receiving data.
Document Number: 001-79351 Rev. **
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Universal Asynchronous Receiver Transmitter (UART)
PSoC Creator™ Component Datasheet
AC Characteristics
Parameter
fCLOCK
Description
Min
Typ
Full UART
–
Simple UART
[5]
Max
Units
–
28
MHz
–
–
38
MHz
Half Duplex UART
–
–
45
MHz
RX Only
–
–
57
MHz
TX Only
–
–
50
MHz
1/fCLOCK
–
–
ns
–
–
fCLOCK/
Oversampling
Mbps
8x Oversampling
–
3.9
–
%
16x Oversampling
–
4.6
–
%
–
STA
–
%
Component clock frequency
tCLOCK
Сlock period
fb
Bit rate
TCLOCK
Сlock tolerance
%ERR
Error
tRES
Reset pulse width
tCTS_TX
[6]
[7]
tCLOCK + 5
–
–
ns
CTS_N inactive to TX_EN active and start bit on
TX
1
–
2
tCLOCK
tTX_TXDATA
Delay from TX to TX_DATA
–
1
–
tCLOCK
tTX_TXCLK
Delay from TX change to TX_CLK active
8x Oversampling
–
5
–
tCLOCK
16x Oversampling
–
9
–
tCLOCK
5
–
–
tS_RES
Reset setup time
tRTS_RX
RTS_N inactive to RX data
tRX_RXCLK
Delay from RX to RX_CLK
tRX_RXINT
ns
[8]
–
–
STA
ns
8x Oversampling
4
–
5
tCLOCK
16x Oversampling
8
–
9
tCLOCK
5. The values provide a maximum safe operating frequency of the component. The component may run at higher clock
frequencies, at which point you will need to validate the timing requirements with STA results.
6. The maximum component clock frequency depends on the selected mode and additional features.
7. %ERR is present on the system when PSoC Creator cannot generate the exact frequency clock. The value must be calculated
as described later in this datasheet.
8. tRTS_RX value depends on the Static Timing Analysis results and must be calculated as described later in this datasheet.
Page 42 of 51
Document Number: 001-79351 Rev. **
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PSoC Creator™ Component Datasheet
Parameter
Universal Asynchronous Receiver Transmitter (UART)
Description
Min
Typ
[5]
Max
Units
tRXCLK_RTS
Delay from last RX_CLK raise to RTS_N active
–
1
–
tCLOCK
tRX_RXDATA
Delay from RX to RX_DATA
0
–
1
tCLOCK
Full UART options:
Mode:
Full UART
Parity:
Even
API control enabled:
Enable
Flow Control:
Hardware (pins)
Address Mode:
Software Byte by Byte
RX Buffer Size (bytes) 5
TX Buffer Size (bytes) 5
Break signal bits:
13
2 out of 3 voting:
Enable
CRC outputs:
Enable (Output pins)
Hardware TX:
Enable (Output pin)
Oversampling rate:
16x
Reset:
Input pin
Simple UART options:
Mode:
Full UART
Parity:
None
API control enabled:
Disable
Flow Control:
None
Address Mode:
None
RX Buffer Size (bytes) 4
TX Buffer Size (bytes) 4
Break signal bits:
None
2 out of 3 voting:
Disable
CRC outputs:
Disable
Hardware TX:
Disable
Oversampling rate:
8x
Reset:
None
Half Duplex UART options:
Mode:
Half Duplex
All other options same as the Simple UART
RX Only options:
Mode:
RX Only
All other options same as the Simple UART
TX Only options:
Mode:
TX Only
TxBitClkGenDP
False (To switch go to Expression View of Advanced tab).
All other options same as the Simple UART
Document Number: 001-79351 Rev. **
Page 43 of 51
®
Universal Asynchronous Receiver Transmitter (UART)
PSoC Creator™ Component Datasheet
Figure 2. TX Mode Timing Diagram
tCTS_TX
CTS_N
TX_EN
Start
bit
TX
N-1
0
Parity
bit
N
Start
bit
Stop
bit
0
1
TX_CLK
tTX_TXCLK
TX_DATA
0
N-1
N
0
1
tTX_TXDATA
tS_RES
TX_INTERRUPT
Clear on read
Clear on reset
RESET
8x
tRES
16x
CLOCK
tCLOCK
tCLOCK
Figure 3. RX Mode Timing Diagram
RX
N-1
N
Parity
bit
Stop
bit
idle
Start
bit
N-1
0
tRX_RXINT
N
Parity
bit
Stop
bit
Start
bit
tRX_RXCLK
RX_CLK
tRXCLK_RTS
RTS_N
tRTS_RX
Fifo full
tRX_RXDATA
RX_DATA
N-1
N
0
N-1
N
RX_INTERRUPT
Clear on read
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Document Number: 001-79351 Rev. **
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PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
How to Use STA Results for Characteristics Data
Nominal route maximums are gathered through multiple test passes with Static Timing Analysis
(STA). You can calculate the maximums for your designs with the STA results using the
following mechanisms:
fCLOCK
Maximum component clock frequency appears in Timing results in the clock summary
as the IntClock (if internal clock is selected) or the named external clock. The
following graphic shows an example of the internal clock limitations from the
_timing.html.
tCLOCK Calculate clock period from the following equation:
t CLOCK =
fb
f CLOCK
Bit rate is equal to сlock frequency (fCLOCK) divided by the oversampling rate. Use
oversampling rate 8x for maximum baud rate calculations, as shown in the equation
below:
fb =
TCLOCK
1
f CLOCK
Oversampli ng
Calculate clock tolerance using the following method:
Assume that UART is configured as 8x oversampling, 2 out of 3 voting disabled, 8
data bits, parity none, and one Stop bit. The Receiver samples the RX line at the
fourth clock of every bit. A new frame is recognized by the falling edge at the
beginning of the active-low Start bit. The receive UART resets its counters on this
falling edge, and expects the mid Start bit to occur after three clock cycles, and the
midpoint of each subsequent bit to appear every eight clock cycles. If the UART clock
has 0-percent error, the sampling happens exactly at the midpoint of the Stop bit. But,
because the UART clock will not have zero error, the sampling happens earlier or
later than the midpoint on every bit. This error keeps accumulating and results in the
maximum error on the Stop bit. If you sample a bit one-half bit period (8 ÷ 2 = ±4
clocks) too early or too late, you will sample at the bit transition and have incorrect
data.
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Universal Asynchronous Receiver Transmitter (UART)
®
PSoC Creator™ Component Datasheet
The bit transition time usually equals 25 percent of the bit time for the normal signal
quality. This value depends on RS-232 cable length, cable quality, and transceiver
parameters. These factors are not taken into account in this analysis.
Another error to include in this budget is the synchronization error when the falling
edge of the Start bit is detected. The UART starts on the next rising edge of its 8x
clock after Start bit detection. Because the 8x clock and the received data stream are
asynchronous, the falling edge of the Start bit could occur just after an 8x clock rising
edge. This means that the UART has a 1 clock error built in at the synchronization
point and this makes the clock tolerance asymmetrical. So, our error budget reduces
to +3 and -4 periods.
The total clock periods from the falling edge of the Start bit to the middle of the Stop
bit is equal to 9.5 × 8 = 76. The total clock tolerance is:
+3 ÷ 76 × 100% = +3.9%, -4 ÷ 76 × 100% = -5.2%.
The clock tolerance for 16x oversampling is:
+7 ÷ (9.5 × 16) × 100% = +4.6%
-8 ÷ (9.5 × 16) × 100% = -5.2%
The 2 out of 3 voting per bit feature makes the sampling wider on ±1 clock. For the
faster clock this doesn’t affect on clock tolerance budget because voting algorithm will
compensate one missed bit. For the slower clock case this feature affects the
following byte receive procedure. This effect could be eliminated by using 2 stop bits
feature, otherwise it makes clock tolerance requirements symmetrical and they
become:
8x oversampling, voting enabled: ±3.9%
16x oversampling, voting enabled: ±4.6%
This total tolerance must be split between the receiver and transmitter in any
proportion. For example, if the device on one side of the UART bus (microcontroller or
PC) runs on a standard 100-ppm crystal oscillator, the device on the other side can
use almost the entire tolerance budget.
%ERR
This error is present on the system when PSoC Creator cannot generate the exact
frequency clock required by the UART because of the PLL clock frequency and
divider value. You can see the difference in the design wide resources (DWR) as the
desired and nominal frequency for the CharComp_clock. The error is calculated using
the following equation:
% ERR =
Page 46 of 51
f des − f nom
* 100%
f des
Document Number: 001-79351 Rev. **
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PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
For example, for a UART configured for 115200 bits per second and 8x oversampling,
the system needs a 921.6-kHz clock. When the PLL is configured for 66 MHz, the
DWR uses a divide by 72 and generates 66000 ÷ 72 = 916,667-kHz clock. For this
example the error is:
(921.6 – 916,667) ÷ 912.6 × 100 = ~0.5%
The summation of this error plus the clock accuracy error should not exceed the clock
tolerance (TCLOCK), or you will see error in the data.
Clock accuracy depends on the selected IMO clock. It is equal to ±1% for the 3-MHz
IMO. The total error is: 0.5 + 1 = 1.5% and it is less than the minimum clock tolerance
for 8x oversampling.
Other IMO clock settings have larger accuracy error and are not recommended for
use with UART.
PSoC 5 silicon has minimum IMO clock accuracy of ±5 percent; therefore, you should
use an external crystal-based clock in this case.
tCTS_TX
This parameter is characterized based on the UART implementation analysis. The
state machine synchronously, to the fCLOCK clock, checks the falling edge CTS_N
signal and sets TX_EN with up to one clock delay. The TX_EN signal has additional
synchronization on the output to remove possible glitches. This adds one clock delay.
The Shift register starts pushing TX data out at the same time as the TX_EN signal
goes high.
tTX_TXCLK
The delay time from TX output to TX_CLK, based on the UART implementation
analysis, is equal to half a bit length and is delayed one clock to be at the middle of
the TX_DATA signal.
 Oversampli ng 
t TX _ TXCLK = t CLOCK ∗ 
+ 1
2


Document Number: 001-79351 Rev. **
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Universal Asynchronous Receiver Transmitter (UART)
®
PSoC Creator™ Component Datasheet
tTX_TXDATA This parameter is characterized based on the UART implementation analysis. The TX
signal is additionally synchronized to the fCLOCK on the TX_DATA output; therefore,
one clock delay is present between these signals.
tRES
This parameter is characterized based on the UART implementation analysis and on
the results of STA. The reset input is synchronous, requiring at least one rising edge
of the component clock. Setup time should be added to guarantee not missing the
reset signal.
t RES = t CLOCK + t S _ RES
tS_RES
RESET activation time is the pin to internal register routing path delay time plus clock
to output delay time. This is provided in the STA results as shown below:
tRX_RXCLK The delay time from RX to RX_CLK, based on the UART implementation analysis, is
equal to half a bit length and is delayed up to one clock to be in the middle of the
RX_DATA signal.
 Oversampli ng 
t RX _ RXCLK = t CLOCK ∗ 
+ 1
2


tRX_RXINT
The RX_INTERRUPT signal is generated when the Stop bit is received at RX_CLK
tRX_RXDATA The RX signal is additionally synchronized to the fCLOCK on the RX_DATA output,
therefore up to one clock delay is present between these signals.
tRXCLK_RTS Delay from the last RX_CLK raise to RTS_N active. This happens when the 4-byte
FIFO is full. The RTS_N signal is automatically set by hardware as soon as input
FIFO is full. The FIFO is loaded with one component clock cycle delay from the last
RX_CLK rising edge.
tRTS_RX
The delay time between RTS_N Inactive to RX data is equal to:
tRTS_RX = tPD_RTS + RTSPD_PCB + tCTS_TX(transmitter) + RXPD_PCB + tS_RX]
Where:
tPD_RTS is the path delay of RTS_N to the pin. This is provided in the STA results
Clock To Output section as shown below.
Page 48 of 51
Document Number: 001-79351 Rev. **
®
PSoC Creator™ Component Datasheet
Universal Asynchronous Receiver Transmitter (UART)
RTSPD_PCB is the PCB path delay from the RTS_N pin of the receiver component to
the CTS_N pin of the transmitter device.
tCTS_TX(transmitter) must come from the Transmitter datasheet.
RXPD_PCB is the PCB path delay from the TX pin of the transmitter device to the RX
pin of the receiver component.
tS_RX is the path delay time of the RX signal. This is provided in the STA results
Register to Register section as shown below.
Document Number: 001-79351 Rev. **
Page 49 of 51
®
Universal Asynchronous Receiver Transmitter (UART)
PSoC Creator™ Component Datasheet
Component Changes
This section lists the major changes in the component from the previous version.
Version
2.20
Description of Changes
Changed sampling time with and without Voting
option. Now RX line is sampled on fourth clock
edge , and on 3th to 5th with majority voting
enabled.
Reason for Changes / Impact
This change gives symmetrical clock tolerance.
Refer to section “2 out of 3 Voting” for more
details.
Added PSoC 5LP support.
2.10
Changed the parameter type for
UART_PutString() API from uint8* to char*.
The common usage of this API is with an embedded
string as a parameter: UART_PutString(“Hello
World”). The “char“ type should be used for this
usage without compiler warnings.
UART_ClearRxBuffer()/ UART_ClearTxBuffer()
APIs clears hardware FIFO too.
Hardware FIFO needs to be cleared to guarantee
that no more data is pending for
reception/transmission.
Fixed typo with the parameter for
UART_SendBreak() API.
UART_WAIT_FOR_COMLETE_REINT changed
to UART_WAIT_FOR_COMPLETE_REINT.
Typo fix.
Added all UART APIs with CYREENTRANT
keyword when they included in .cyre file.
Not all APIs are truly reentrant. Comments in the
component API source files indicate which functions
are candidates.
This change is required to eliminate compiler
warnings for functions that are not reentrant used in
a safe way: protected from concurrent calls by flags
or Critical Sections.
Updated Address Mode functionality.
These modes are upgraded for automatically skip
unaddressed packets.
Fixed Hardware Flow control mode when internal
RX buffer is used. The code in the RX ISR stops
to read data from the FIFO when internal buffer
overruns. As a result, the RTS signal holds the
transmitter UART.
The data was read from the hardware FIFO and
moved to the s/w buffer regardless of whether the
s/w buffer has overrun.
Updated internal clock component with
cy_clock_v1_60.
Clock v1_60 is the latest component version.
Limited RX and TX Buffer Size minimum value to
4.
UART always uses 4 bytes FIFO as a buffer.
Minor datasheet edits and updates
2.0.a
Minor datasheet edits and updates
Page 50 of 51
Document Number: 001-79351 Rev. **
®
PSoC Creator™ Component Datasheet
Version
2.0
Description of Changes
tx_en output registered
Universal Asynchronous Receiver Transmitter (UART)
Reason for Changes / Impact
Any combinatorial output can glitch, depend on
placement and delay between signals.
To remove glitching the outputs should be
registered.
Reset input registered.
Registering improves maximum baud rate when
Reset input is used.
Added characterization data to datasheet
Minor datasheet edits and updates
1.50
Added Sleep/Wakeup and Init/Enable APIs.
To support low-power modes, as well as to provide
common interfaces to separate control of
initialization and enabling of most components.
Break signal has length selection (11 to 14 bits)
and added parameter to SendBreak function.
Break signal length for UART is not specified,
therefore 11 to 14 bits selection is provided.
Added 16x oversampling mode.
16x oversample mode reduces jitter effect on error
at higher speeds.
Software option removed from Parity Type
selection, API control enabled check box has
been added instead.
This allowed a way to select a default value when
needed parity API control.
If updating from version 1.20 of the UART
component with this option selected, it is
recommended to select the "None" parity option in
version 1.50.
© Cypress Semiconductor Corporation,2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for
use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in lifesupport systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PSoC® is a registered trademark, and PSoC Creator™ and Programmable System-on-Chip™ are trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks
referenced herein are property of the respective corporations.
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foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create
derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in
conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as
specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein.
Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in lifesupport systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application
implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-79351 Rev. **
Page 51 of 51
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