® PSoC Creator™ Component Datasheet Voltage Reference (Vref) 1.50 Features Voltage references and supplies Multiple options Bandgap principle to achieve temperature, and voltage stability General Description This component works with both PSoC 3 and PSoC 5 devices. The Voltage Reference (Vref) component provides one of several voltage reference outputs. The 1.024-V and 0.256-V outputs are temperature compensated using the bandgap principle to achieve excellent stability. Note The Vref component is not intended to source or sink current. It has low drive strength. If high drive strength is needed, buffer the Vref with an Opamp or PGA component. Every Vref is associated with some analog resource. To enable a Vref, the associated resource must be enabled. All Vrefs default their AutoEnable parameter to true. Since auto-enable Vrefs automatically enable the associated analog resource, all Vrefs are automatically enabled by default. When to Use a Vref Use Vref components for threshold detectors, reference inputs to analog-to-digital converters, comparators, and programmable gain amplifiers. They can also be used whenever you need a known voltage. Input/Output Connections The Vref component has a single output terminal that provides access to the selected voltage reference. Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-62102 Rev. *C Revised November 8, 2011 Voltage Reference (Vref) ® PSoC Creator™ Component Datasheet Component Parameters Drag a Vref onto your design and double click it to open the Configure dialog. Basic Tab VRef Name This is the Vref value. Options include: 1.024 V (default) – Based on bandgap; see DC and AC Electrical Characteristics section for more information. Vssa(GND) – Internal Vssa voltage. Vdda/2 – Derived from Vdda with a resistive divider; see DC and AC Electrical Characteristics section for more information. Vdda(HiZ) – The Vdda voltage reference is provided with a resistive divider and so has high impedance. Vdda(HiZ) cannot be used if Vdda/2 is used elsewhere. See the Precision Reference chapter of the chip Technical Reference Manual (TRM) for details. Vccd – Special 1.8-V reference that is only available for SIO pins. Available in Production PSoC 3 or later only. 0.256 V – Derived from the 1.024 bandgap with a resistive divider; see DC and AC Electrical Characteristics section for more information. Page 2 of 6 Document Number: 001-62102 Rev. *C ® PSoC Creator™ Component Datasheet Voltage Reference (Vref) Vddd – Internal Vddd voltage. Available in Production PSoC 3 or later only. Vbat – Internal Vbat voltage. Available in Production PSoC 3 or later only. Vdda – Internal Vdda voltage. Available in Production PSoC 3 or later only. Advanced Tab AutoEnable The AutoEnable parameter applies to the 1.024-V and 0.256 V-Vref components. When AutoEnable is set to true (default), the Vref is enabled automatically when the device is initialized and the static analog routes are established. The 1.024-V and 0.256-V Vref components may need to consume a comparator when AutoEnable is true. When a 1.024-V or 0.256-V Vref is connected to intended analog block connections such as the comparator, the device automatically enables the Vref when the connected components are enabled. AutoEnable is not necessary in these cases. See the Precision Reference chapter of the chip Technical Reference Manual (TRM) for details. Note Vref components that require AutoEnable set to true have reduced routing capability because specific analog routing resources are required to supply the auto-enable Vref. When AutoEnable is set to false, the 1.024-V and 0.256-V Vref components are only powered up when the associated analog block is powered up. See the TRM for details. Document Number: 001-62102 Rev. *C Page 3 of 6 Voltage Reference (Vref) ® PSoC Creator™ Component Datasheet IgnoreSleep The IgnoreSleep parameter applies to 1.024-V and 0.256-V Vref components. When IgnoreSleep is set to true, the Vref remains active when the device goes into a sleep state. This increases the power consumption of the device in the sleep state. The default IgnoreSleep value is false. The affected Vrefs consume a comparator when IgnoreSleep is true. Also, if IgnoreSleep is true, AutoEnable is automatically set to true. IgnoreSleep cannot be true for PSoC 5 devices. Placement For a design project, the list of available voltage references is determined by what is available from the selected family or device. If you place a Vref component in a library project schematic at the generic level, you do not see any references available. In this case, you need to specify a family or device when creating the schematic. AutoEnable Vref Connecting to an Amux Switchable Connection The auto-enable 1.024-V or 0.256-V Vref component must be all by itself when connected to an Amux switchable connection. This restriction is introduced so the software can handle the autoenable Vref feature without ambiguities. In general, the software must split up signals connected to auto-enable Vrefs, but that is not possible for Amux switchable connections. In the following example, in order for Design 1 to work, it must be converted to Design2. If you choose to set the AutoEnable parameter of the Vref component to false, this restriction does not apply. Page 4 of 6 Document Number: 001-62102 Rev. *C ® PSoC Creator™ Component Datasheet Voltage Reference (Vref) Resources When AutoEnable is enabled for an unintended analog block, the 1.024-V Vref consumes a comparator, which will be automatically removed from available comparator resources. A comparator is required to satisfy device requirements of having the analog block associated with the Vref powered up. So, a comparator is allocated to be able to control the power settings and use that Vref. Functional Description The Vref component provides one of the available voltage references. Connection is through a single terminal. The Vref component may be shared among several components. DC and AC Electrical Characteristics The following values indicate expected performance and are based on initial characterization data. Note that the 1.024-V voltage reference calibration occurs for the buffered ADC_DelSig reference. All of the other 1.024-V references (about 7 or 8 different ones) can be off by several millivolts. Vref Characteristics Parameter Vref Description Conditions Precision reference voltage Temperature drift Initial trimming 1 Long term drift Thermal cycling drift (stability) 1 1 Min Typ Max Units 1.023 (–0.1%) 1.024 1.025 (+0.1%) – – 20 ppm/°C – 100 – ppm/Khr – 100 – ppm V Based on device characterization (Not production tested). Document Number: 001-62102 Rev. *C Page 5 of 6 Voltage Reference (Vref) ® PSoC Creator™ Component Datasheet Component Changes This section lists the major changes in the component from the previous version. Version Description of Changes Reason for Changes / Impact 1.50.c Minor datasheet edits and updates 1.50.b Updated description of Vdda(HiZ) Description was unclear. Updated AutoEnable section to include quarter volt Vref 0.256-V Vref has the same AutoEnable properties as the 1.024-V Vref. 1.50.a Added characterization data to datasheet Datasheet edits 1.50 Added AutoEnable and IgnoreSleep parameters to the customizer. The AutoEnable and IgnoreSleep parameters provide additional functionality and a more intuitive user experience. Added the special purpose Vccd Vref for use with SIO pins. The Vccd reference is used with SIO pins. Added Vbat, Vddd, and Vdda references. The Vbat, Vddd, and Vdda references were added to provide additional functionality. © Cypress Semiconductor Corporation, 2010-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PSoC® is a registered trademark, and PSoC Creator™ and Programmable System-on-Chip™ are trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in lifesupport systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 6 of 6 Document Number: 001-62102 Rev. *C