MPC5604E Microcontroller Data Sheet

Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5604E
Rev. 5.1, Feb 2016
MPC5604E
100 LQFP
14 mm x 14 mm
MPC5604E Microcontroller
Data Sheet
•
•
•
•
•
•
•
Single issue, 32-bit CPU core complex (e200z0h)
— Compliant with Power Architecture® embedded
category
— Variable Length Encoding (VLE) only
Memory
— 512 KB on-chip Code Flash with ECC and
erase/program controller
— additional 64 (4 × 16) KB on-chip Data Flash
with ECC for EEPROM emulation
— 96 KB on-chip SRAM with ECC
Fail-safe protection
— Programmable watchdog timer
— Non-maskable interrupt
— Fault collection unit
Nexus 2+ interface
Interrupts and events
— 16-channel eDMA controller
— 16 priority level controller
— Up to 32 external interrupts for 100-pin LQFP
— Upto 22 external interrupts for 64-pin LQFP
— PIT implements four 32-bit timers
— 120 interrupts are routed via INTC
General purpose I/Os
— Individually programmable as input, output or
special function
— 39 on LQFP64
— 71 on LQFP1001
1 general purpose eTimer unit
— 6 timers each with up/down capabilities
— 16-bit resolution, cascadeable counters
64 LQFP
10 mm x 10 mm
•
•
•
•
•
•
•
•
•
— Quadrature decode with rotation direction flag
— Double buffer input capture and output compare
Communications interfaces
— 2 LINFlex channels (1 × Master/Slave, 1 ×
Master Only)
— 3 DSPI controllers with automatic chip select
generation (up to 2/2/4 chip selects)
— 1 FlexCAN interface (2.0B Active) with 32
message buffers
One 10-bit analog-to-digital converter (ADC)
— 7 input channels
– 4 channels routed to the pins
– 3 internal connections: 1x temperature
sensor, 1x core voltage, 1x IO voltage
— Conversion time < 1 μ s including sampling
time at full precision
— 4 analog watchdogs with interrupt capability
On-chip CAN/UART bootstrap loader with Boot
Assist Module (BAM)
On-chip TSENS
100 MBit Fast Ethernet Controller (FEC)
— Supports precision timestamps
— MII on 100-pin LQFP package
— MII-lite on 64-pin LQFP package
JPEG/MJPEG 8/12bit Encoder
6 x stereo channels audio interface
2x I2C controller module
CRC module
1.The 100-pin package is not a production package.
It is used for software development only.
Freescale reserves the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2016. All rights reserved.
Table of Contents
1
2
3
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . .6
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2.1 Power supply and reference voltage pins . . . . . .8
2.2.2 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.2.3 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .21
3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .22
3.4 Recommended operating conditions . . . . . . . . . . . . . .23
3.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . .24
3.5.1 General notes for specifications at
maximum junction temperature . . . . . . . . . . . . .25
3.6 Electromagnetic Interference (EMI) characteristics . . .26
3.7 Electrostatic Discharge (ESD) characteristics. . . . . . . .27
3.8 Power management electrical characteristics. . . . . . . .27
3.8.1 Power Management Overview . . . . . . . . . . . . .27
3.8.2 Voltage regulator electrical characteristics . . . .29
3.8.3 Voltage monitor electrical characteristics. . . . . .31
3.9 Power Up/Down reset sequencing . . . . . . . . . . . . . . . .31
3.10 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . .33
3.11 Main oscillator electrical characteristics . . . . . . . . . . . .34
3.12 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . .35
4
5
6
3.13 16 MHz RC oscillator electrical characteristics . . . . . .
3.14 Analog-to-Digital Converter (ADC) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14.1 Input impedance and ADC accuracy . . . . . . . .
3.14.2 ADC conversion characteristics . . . . . . . . . . . .
3.15 Temperature sensor electrical characteristics . . . . . . .
3.16 Flash memory electrical characteristics. . . . . . . . . . . .
3.17 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.17.1 Pad AC specifications . . . . . . . . . . . . . . . . . . .
3.18 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . .
3.18.1 Generic timing diagrams . . . . . . . . . . . . . . . . .
3.18.2 RESET pin characteristics . . . . . . . . . . . . . . . .
3.18.3 Nexus and JTAG timing . . . . . . . . . . . . . . . . . .
3.18.4 GPIO timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.18.5 External interrupt timing (IRQ pin) . . . . . . . . . .
3.18.6 FlexCAN timing . . . . . . . . . . . . . . . . . . . . . . . .
3.18.7 LINFlex timing . . . . . . . . . . . . . . . . . . . . . . . . .
3.18.8 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.18.9 Video interface timing. . . . . . . . . . . . . . . . . . . .
3.18.10Fast ethernet interface. . . . . . . . . . . . . . . . . . .
3.18.11I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.18.12SAI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 100 LQFP mechanical outline drawing . . . . . . . . . . . .
4.2 64 LQFP mechanical outline drawing . . . . . . . . . . . . .
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
37
37
42
43
43
46
46
49
49
50
51
53
54
54
54
55
60
61
63
64
67
67
71
74
75
MPC5604E Microcontroller Data Sheet, Rev. 5.1
2
Freescale Semiconductor
Overview
1
Overview
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5604E series of
microcontroller units (MCUs).
MPC5604E microcontrollers are members of a new family of next generation microcontrollers built on the Power Architecture.
This document describes the features of the family and options available within the family members, and highlights important
electrical and physical characteristics of the devices.
The MPC5604E microcontroller is a gateway system designed to move data from different sources via Ethernet to a receiving
system and vice versa. The supported data sources and sinks are:
•
•
•
•
Video data (with 8/10/12 bits per data word)
Audio data (6× stereo channels)
RADAR data (2 × 12 bit with <1μs per sample, digitized externally and read in via SPI)
Other serial communication interfaces including CAN, LIN, and SPI
The Ethernet module has a bandwidth of 10/100 Mbits/sec and supports precision time stamps (IEEE1588). Unshielded twisted
pair cables are used to transfer data (via Ethernet) in the car, resulting in a significant reduction of wiring costs by providing
inexpensive high bandwidth data links.
1.1
Device summary
Table 1 summarizes the MPC5604E device.
NOTE
The 100-pin package is not a production package. It is used for software development only.
Table 1. Device summary
MPC5604E
Feature
CPU
100-pin LQFP1
64-pin LQFP
e200z0h, 64 MHz, VLE only, no SPE
Flash with ECC
CFlash: 512 KB (LC) DFlash: 64 KB (LC, area optimized)
RAM with ECC
96 KB
DMA
16 channels
PIT
yes
SWT
yes
FCU
yes
Ethernet
100 Mbits MII
100 Mbits MII-Lite
Video Encoder
8bpp/12bpp
Audio Interface
6x Stereo (4x synchronous + 2x synchronous/asynchronous)
ADC (10-bit)
Timer I/O (eTimer)
SCI (LINFlex)
SPI (DSPI)
1× 4 channels + VDD_IO + VDDCore + TSens
1×6 channels
2×
DSPI_0: 2 chip selects
DSPI_1: 2 chip selects
DSPI_2: 4 chip selects
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
3
Overview
Table 1. Device summary (continued)
MPC5604E
Feature
100-pin LQFP1
CAN (FlexCAN)
1×
IIC
2×
Supply
3.3 V IO
1.2V Core with dedicated ballast source pin in two modes:
• internal ballast or
• external supply (using power on reset pin)
1× FMPLL
Phase Lock Loop (PLL)
Internal RC Oscillator
16 MHz
External crystal
Oscillator
4 MHz - 40 MHz
CRC
yes
Debug
JTAG, Nexus2+
Ambient Temperature
1
1.2
64-pin LQFP
JTAG
–40 to 125 °C
The 100-pin package is not a production package. It is used for software development only.
Block diagram
Figure 1 shows a top-level block diagram of the MPC5604E MCU.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
4
Freescale Semiconductor
Overview
Internal and
External Ballast
e200z0 Core
32-bit
General
Purpose
Registers
Integer
Execution
Unit
Special
Purpose
Registers
Exception
Handler
Instruction
Unit
Variable
Length
Encoded
Instructions
Branch
Prediction
Unit
Load/Store
Unit
1.2 V Regulator
Control
XOSC
16 MHz
RC Oscillator
FMPLL
(System)
JTAG
Nexus2+
JTAG Port
Nexus2+
eDMA
16 channels
Instruction Bus
(32-bit)
Master
Interrupt
Controller
Data Bus
(32-bit)
Master
FEC
Master
PTP
MII
Master
96 KB
SRAM
(ECC)
PDI
TSENS
ME
PCU
video_clk
Slave
MJPEG
64 KB
Data
Flash
(ECC)
Slave
Output
Buffer
512 KB
Code
Flash
(ECC)
Slave
RGM
Slave
CGM
Crossbar Switch (XBAR, AMBA 2.0 v6 AHB)
ADC
BAM
CRC
DSPI
eDMA
eTimer
FCD
FCU
FEC
FlexCAN
FMPLL
I2C
SAI
LINFlex
ME
Analog-to-Digital Converter
Boot Assist Module
Cylic Redundancy Check
Deserial Serial Peripheral Interface
Enhanced Direct Memory Access
Enhanced Timer
Fractional Clock Divider
Fault Collection Unit
Fast Ethernet Controller
Flexible Controller Area Network
Frequency-Modulated Phase-Locked Loop
Inter-Integrated Circuit serial interface
Serial Audio Interface 6xStereo
Serial Communication Interface (LIN support)
Mode Entry Module
CGM
PCU
RGM
TSENS
MJPEG
PDI
PIT
PTP
SIUL
SRAM
SSCM
STM
SWT
FCU
SIUL
BAM
SWT
STM
PIT
SSCM
FCD
3 x SAI
3 x I2C
CRC
FlexCAN
3 x DSPI
2 x LINFlex
ADC
10-bit
4+3 channels
eTimer
Peripheral Bridge
Clock Generation Module
Power Control Unit
Reset Generation Module
Temperature sensor
12-bit Motion JPEG Encoder
Parallel Data Interface (image sensor)
Periodic Interrupt Timer
IEEE 1588 Precision Time Stamps
System Integration Unit
Static Random-Access Memory
System Status and Configuration Module
System Timer Module
Software Watchdog Timer
Figure 1. MPC5604E block diagram
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
5
Package pinouts and signal descriptions
2
Package pinouts and signal descriptions
2.1
Package pinouts
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
C[6]
C[5]
C[4]
A[15]
C[3]
VSS_LV
VDD_LV
C[2]
VSS_HV
VDD_HV
C[1]
C[0]
B[15]
B[14]
B[13]
B[12]
The LQFP pinouts are shown in the following figures.
NMI
A[0]
A[1]
A[2]
A[3]
64 LQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
B[11]
VSS_HV
B[10]
B[9]
B[8]
TDO
TCK
TMS
TDI
B[7]
VDD_HV
VSS_HV
VSS_LV
VDD_LV
B[6]
B[5]
VDD_HV_ADC
VSS_HV_ADC
VDD_HV_S_BALLAST
A[8]
A[9]
A[10]
A[11]
A[12]
A[13]
A[14]
POR_B
B[4]
B[0]
B[1]
B[2]
B[3]
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS_LV
VDD_LV
A[4]
A[5]
A[6]
VDD_HV
VSS_HV
XTAL
EXTAL
RESET
A[7]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Note:
1. All VDD_HV and VSS_HV pins must be shorted on the board. The ADC supply (VDD_HV_ADC) and ground
(VSS_HV_ADC) should be managed independently from other high-voltage supplies, (it may still be supplied from the same
high-voltage source, but caution must be taken while routing it on the board.)
2. All VDD_LV and VSS_LV pins must be shorted on the board.
Figure 2. 64-pin LQFP pinout (top view)
MPC5604E Microcontroller Data Sheet, Rev. 5.1
6
Freescale Semiconductor
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
C[6]
C[5]
D[7]
E[6]
C[4]
A[15]
C[3]
VSS_LV
VDD_LV
C[2]
E[5]
E[4]/
VSS_HV
VDD_HV
E[3]
E[2]
D[6]
C[1]
C[0]
B[15]
D[5]
B[14]
D[4]
B[13]
B[12]
Package pinouts and signal descriptions
NMI
A[0]
C[7]
A[1]
C[8]
A[2]
C[9]
A[3]
D[0]
D[8]
100 LQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
B[11]
VSS_HV
B[10]
D[3]
E[1]
B[9]
D[15]
E[0]
B[8]
TDO
TCK
TMS
TDI
B[7]
VDD_HV
VSS_HV
VSS_LV
VDD_LV
D[14]
B[6]
B[5]
D[13]
D[12]
D[11]
D[10]
VDD_HV_S_BALLAST
VSS_HV
VDD_HV
A[8]
A[9]
A[10]
A[11]
A[12]
A[13]
A[14]
C[12]
POR_B
C[13]
C[14]
C[15]
D[9]
B[4]
VDD_HV_ADC
VSS_HV_ADC
VSS_LV
VDD_LV
B[0]
B[1]
B[2]
B[3]
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS_LV
VDD_LV
D[2]
D[1]
A[4]
A[5]
A[6]
VDD_HV
VSS_HV
XTAL
EXTAL
RESET
A[7]
C[10]
C[11]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1. All VDD_HV and VSS_HV pins must be shorted on the board. The ADC supply (VDD_HV_ADC) and ground
(VSS_HV_ADC) should be managed independently from other high-voltage supplies, (it may still be supplied from the same
high-voltage source, but caution must be taken while routing it on the board.)
2. All VDD_LV and VSS_LV pins must be shorted on the board.
Figure 3. 100-pin LQFP pinout (top view)1
1.The 100-pin package is not a production package. It is used for software development only.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
7
Package pinouts and signal descriptions
2.2
Signal descriptions
The following sections provide signal descriptions and related information about the functionality and configuration of the
MPC5604E devices.
2.2.1
Power supply and reference voltage pins
Table 2 lists the power supply and reference voltage for the MPC5604E devices.
Table 2. Supply pins
Supply
Multi-bonded Power
Supplies/Ground
Port Pin
Pin
Description
64-pin
100-pin1
VREG control and power supply pins. Pins available on 64-pin and 100-pin package.
VDD_HV_S_BALLAST
VDD_HV_S_BALLAST0
Ballast Source/Supply Voltage
VDD_HV_S_BALLAST1
Ballast Source/Supply Voltage
23
34
ADC0 reference and supply voltage. Pins available on 64-pin and 100-pin package.
VDD_HV_ADC0
ADC0 supply voltage with respect to ground
(VSS_HV_ADC)
VDD_HV_ADC0
ADC0 high reference voltage with respect
to ground (VSS_HV_ADC)
VSS_HV_ADC0
ADC0 ground voltage with respect to
ground
VSS_HV_ADC0
ADC0 low reference voltage with respect to
ground
VDD_HV_ADC
VSS_HV_ADC
21
30
22
31
11
18
38
61
55
87
-
36
12
19
37
60
Power supply pins (3.3 V). Pins available on 64-pin and 100-pin package.
VDD_HV
VDD_HV_IO0_0
Input/output ground voltage
VDD_HV_OSC0
Crystal oscillator amplifier supply voltage
VDD_HV_IO0_2
3.3 V Input/Output Supply Voltage (supply)
VDD_HV_FLA1
Code and data flash supply voltage
VDD_HV_IO0_3
3.3 V Input/Output Supply Voltage (supply)
VDD_HV_FLA0
Code and data flash supply voltage
VDD_HV
VSS_HV
HV Supply
VSS_HV_IO0_0
Input/output ground voltage
VSS_HV_OSC0
Crystal oscillator amplifier ground
VSS_HV_IO0_2
Input/output ground voltage
Vss_HV_FLA1
Code and data flash supply ground
Vss_IO0_4
Vss_HV_FLA0
VSS_HV
Input/output ground voltage
35
56
Code and data flash supply voltage
HV Ground
88
47
74
MPC5604E Microcontroller Data Sheet, Rev. 5.1
8
Freescale Semiconductor
Package pinouts and signal descriptions
Table 2. Supply pins (continued)
Supply
Port Pin
Multi-bonded Power
Supplies/Ground
Pin
Description
64-pin
100-pin1
7
12
58
92
35
58
-
33
6
11
59
93
36
59
-
32
Power supply pins (1.2 V). Pins available on 64-pin and 100-pin package.
VDD_LV_COR0_3
VDD_LV_PLL0
VDD_LV
VDD_LV_COR0_2
VDD_LV_FLA0
VDD_LV_COR0_1
VDD_LV_FLA1
VDD_LV
VSS_LV_COR0_3
VSS_LV_PLL0
VSS_LV_COR0_2
VSS_LV
VSS_LV_FLA0
VSS_LV_COR0_1
VSS_LV_FLA1
VSS_LV
1
2.2.2
1.2 V supply pins for core logic and code
Flash. Decoupling capacitor must be
connected between these pins and the
nearest VSS_LV_COR0_3 pin.
1.2 V PLL supply voltage
1.2 V supply pins for core logic and code
Flash. Decoupling capacitor must be
connected between these pins and the
nearest VSS_LV_COR0_2 pin.
Code and data flash supply voltage
1.2 V supply pins for core logic and code
Flash. Decoupling capacitor must be
connected between these pins and the
nearest VSS_LV_COR0_1 pin.
Code and data flash supply voltage
Core supply
1.2 V supply pins for core logic and code
Flash. Decoupling capacitor must be
connected betwee.n these pins and the
nearest VDD_LV_COR0_3 pin.
PLL supply ground
1.2 V supply pins for core logic and code
Flash. Decoupling capacitor must be
connected betwee.n these pins and the
nearest VDD_LV_COR0_2 pin.
Code and data flash supply ground
1.2 V supply pins for core logic and data
Flash. Decoupling capacitor must be
connected between these pins and the
nearest VDD_LV_COR0_1 pin.
Code and data flash supply ground
Core ground
The 100-pin package is not a production package. It is used for software development only.
System pins
Table 3 and Table 4 contain information on pin functions for the MPC5604E devices. The pins listed in Table 3 are
single-function pins. The pins shown in Table 4 are multi-function pins, programmable via their respective Pad Configuration
Register (PCR) values.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
9
Package pinouts and signal descriptions
Table 3. System pins
Pad speed1
Symbol
Description
Pin
Direction
SRC = 0 SRC = 1
64-pin
100-pin2
Dedicated pins
NMI
Non-maskable Interrupt
XTAL
Oscillator amplifier output
Input only
Slow
—
1
1
Output only
—
—
13
20
Input for oscillator amplifier circuit and
internal clock generator
Input only
—
—
14
21
JTAG test data input
Input only
Slow
Medium
40
63
TMS
JTAG state machine control
Input only
Slow
Medium
41
64
TCK3
JTAG clock
Input only
Slow
—
42
65
TDO3
JTAG test data output
Output only
Slow
Medium
43
66
Bidirectional
Medium
—
15
22
Input only
—
—
31
45
EXTAL
TDI3
3
Reset pin
RESET
Bidirectional reset with Schmitt trigger
characteristics and noise filter
POR_B
Power-on reset
1
SRC values refer to the value assigned to the Slew Rate Control bits of the pad configuration register.
The 100-pin package is not a production package. It is used for software development only.
3
Additional board pull resistors are recommended when JTAG pins are not being used on the board or application.
2
2.2.3
Pin muxing
Table 4 defines the pin list and muxing for the MPC5604E devices.
Each row of Table 4 shows all the possible ways of configuring each pin, via “alternate functions”. The default function
assigned to each pin after reset is the ALT0 function.Pins marked as external interrupt capable can also be used to resume from
STOP and HALT mode.
MPC5604E devices provide four main I/O pad types depending of the associated functions:
•
•
•
Slow pads are the most common, providing a compromise between transition time and low electromagnetic emission.
Medium pads provide fast enough transition for serial communication channels with controlled current to reduce
electromagnetic emission.
Fast pads provide maximum speed. They are used for improved Nexus debugging capability.
Medium and Fast pads can be used in slow configuration to reduce the electromagnetic emissions, at the cost of reducing AC
performance.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
10
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. Pin muxing
Port
pin
PCR
register
Alternate
function1,2,8
Functions
Peripheral3
I/O
direction4
Pad speed5
SRC = 0
Pin6
SRC = 1
64-pin
100-pin7
Port A (16-bit)
A[0]
PCR[0]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[0]
D[0]
—
—
D[11]
SIN
EIRQ[0]
SIUL
SAI0
—
—
VID
DSPI 1
SIUL
I/O
I/O
—
—
I
I
I
Slow
Medium
2
2
A[1]
PCR[1]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[1]
D[1]
SOUT
—
D[10]
EIRQ[1]
SIUL
SAI0
DSPI1
—
VID
SIUL
I/O
I/O
O
—
I
I
Slow
Medium
3
4
A[2]
PCR[2]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[2]
D[2]
SCK
D[0]
D[9]
ETC[5]
EIRQ[2]
SIUL
SAI0
DSPI1
SAI1
VID
ETIMER0
SIUL
I/O
I/O
I/O
I/O
I
I
I
Slow
Medium
4
6
A[3]
PCR[3]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[3]
D[3]
—
D[0]
D[8]
SIN
EIRQ[3]
SIUL
SAI0
—
SAI2
VID
DSPI2
SIUL
I/O
I/O
—
I/O
I
I
I
Slow
Medium
5
8
A[4]
PCR[4]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[4]
SYNC
SOUT
—
D[7]
ETC[3]
EIRQ[4]
SIUL
SAI0
DSPI2
—
VID
ETIMER0
SIUL
I/O
I/O
O
—
I
I
I
Slow
Medium
8
15
A[5]
PCR[5]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[5]
SYNC
SCK
D[0]
CLK
ETC[4]
EIRQ[5]
SIUL
SAI1
DSPI2
SAI1
VID
ETIMER0
SIUL
I/O
I/O
I/O
I/O
I
I
I
Medium
Fast
9
16
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
11
Package pinouts and signal descriptions
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2,8
Functions
3
Peripheral
I/O
direction4
Pad speed5
SRC = 0
Pin6
SRC = 1
64-pin
100-pin7
A[6]
PCR[6]
ALT0
ALT1
ALT2
ALT3
—
—
—
—
GPIO[6]
SYNC
CS0
—
VSYNC
D[0]
ETC[1]
EIRQ[6]
SIUL
SAI2
DSPI2
—
VID
VID
ETIMER0
SIUL
I/O
I/O
I/O
—
I
I
I
I
Slow
Medium
10
17
A[7]
PCR[7]
ALT0
ALT1
ALT2
ALT3
—
—
—
—
GPIO[7]
BCLK
CS1
—
HREF
D[1]
ETC[2]
EIRQ[7]
SIUL
SAI0
DSPI2
—
VID
VID
ETIMER0
SIUL
I/O
I/O
I/O
—
I
I
I
I
Slow
Medium
16
23
A[8]
PCR[8]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[8]
BCLK
CS0
D[0]
D[6]
RX
EIRQ[8]
SIUL
SAI1
DSPI1
SAI2
VID
LIN1
SIUL
I/O
I/O
I/O
I/O
I
I
I
Slow
Medium
24
37
A[9]
PCR[9]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[9]
BCLK
CS1
TX
D[5]
EIRQ[9]
SIUL
SAI2
DSPI1
LIN1
VID
SIUL
I/O
I/O
I/O
O
I
I
Slow
Medium
25
38
A[10]
PCR[10]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[10]
MCLK
ETC[5]
—
D[4]
SIN
EIRQ[10]
SIUL
SAI2
ETIMER0
—
VID
DSPI0
SIUL
I/O
I/O
I/O
—
I
I
I
Slow
Medium
26
39
A[11]
PCR[11]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[11]
TX
CS1
CS0
D[3]
RX
RX
SIUL
CAN0
DSPI0
DSPI1
VID
LIN0
LIN1
I/O
O
O
I/O
I
I
I
Slow
Medium
27
40
MPC5604E Microcontroller Data Sheet, Rev. 5.1
12
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2,8
Functions
3
Peripheral
I/O
direction4
Pad speed5
SRC = 0
SRC = 1
Pin6
64-pin
100-pin7
A[12]
PCR[12]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[12]
TX
CS0
TX
D[2]
RX
EIRQ[11]
SIUL
LIN0
DSPI0
LIN1
VID
CAN0
SIUL
I/O
O
I/O
O
I
I
I
Slow
Medium
28
41
A[13]
PCR[13]
ALT0
ALT1
ALT2
ALT3
—
GPIO[13]
CLK
F[0]
CS0
EIRQ[12]
SIUL
IIC1
FCU0
DSPI0
SIUL
I/O
I/O
O
I/O
I
Slow
Medium
29
42
A[14]
PCR[14]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[14]
DATA
F[1]
CS1
SIN
EIRQ[13]
SIUL
IIC1
FCU0
DSPI0
DSPI0
SIUL
I/O
I/O
O
O
I
I
Slow
Medium
30
43
A[15]
PCR[15]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[15]
SCK
PPS3
MCLK
SCK
ETC[0]
EIRQ[18]
SIUL
DSPI0
CE_RTC
SAI1
DSPI1
ETIMER0
SIUL
I/O
I/O
O
I/O
I
I
I
Slow
Medium
61
95
Port B (16-bit)
B[0]
PCR[16]
ALT0
ALT1
ALT2
ALT3
—
GPIO[16]
TX
ALARM2
BCLK
AN[0]
SIUL
CAN0
CE_RTC
SAI1
ADC08
I/O
O
O
I/O
I
Slow
Medium
17
26
B[1]
PCR[17]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[17]
—
—
D[0]
AN[1]
RX
TRIGGER2
SIUL
—
—
SAI1
ADC08
CAN0
CE_RTC
I/O
—
—
I/O
I
I
I
Slow
Medium
18
27
B[2]
PCR[18]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[18]
TX
PPS2
ALARM1
AN[2]
TRIGGER1
SIUL
LIN0
CE_RTC
CE_RTC
ADC08
CE_RTC
I/O
O
O
O
I
I
Slow
Medium
19
28
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
13
Package pinouts and signal descriptions
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2,8
Functions
3
Peripheral
I/O
direction4
Pad speed5
SRC = 0
Pin6
SRC = 1
64-pin
100-pin7
B[3]
PCR[19]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[19]
ETC[2]
SOUT
PPS1
AN[3]
RX
EIRQ[14]
SIUL
ETIMER0
DSPI0
CE_RTC
ADC08
LIN0
SIUL
I/O
I/O
I/O
O
I
I
I
Slow
Medium
20
29
B[4]
PCR[20]
ALT0
ALT1
ALT2
ALT3
—
GPI[20]
—
—
—
RX_DV
SIUL
—
—
—
FEC
I
—
—
—
I
Slow
Medium
32
50
B[5]
PCR[21]
ALT0
ALT1
ALT2
ALT3
GPIO[21]
TX_D0
DEBUG[0]
—
SIUL
FEC
SSCM
—
I/O
O
I/O
—
Slow
Medium
33
55
B[6]
PCR[22]
ALT0
ALT1
ALT2
ALT3
GPIO[22]
TX_D1
DEBUG[1]
—
SIUL
FEC
SSCM
—
I/O
O
I/O
—
Slow
Medium
34
56
B[7]
PCR[23]
ALT0
ALT1
ALT2
ALT3
GPIO[23]
TX_D2
DEBUG[2]
—
SIUL
FEC
SSCM
—
I/O
O
I/O
—
Slow
Medium
39
62
B[8]
PCR[24]
ALT0
ALT1
ALT2
ALT3
GPIO[24]
TX_D3
DEBUG[3]
—
SIUL
FEC
SSCM
—
I/O
O
I/O
—
Slow
Medium
44
67
B[9]
PCR[25]
ALT0
ALT1
ALT2
ALT3
GPIO[25]
TX_EN
DEBUG[4]
—
SIUL
FEC
SSCM
—
I/O
O
I/O
—
Slow
Medium
45
70
B[10]
PCR[26]
ALT0
ALT1
ALT2
ALT3
GPIO[26]
MDC
DEBUG[5]
—
SIUL
FEC
SSCM
—
I/O
O
I/O
—
Slow
Medium
46
73
B[11]
PCR[27]
ALT0
ALT1
ALT2
ALT3
GPIO[27]
MDIO
DEBUG[6]
—
SIUL
FEC
SSCM
—
I/O
I/O
I/O
—
Slow
Medium
48
75
B[12]
PCR[28]
ALT0
ALT1
ALT2
ALT3
—
GPIO[28]
—
DEBUG[7]
—
TX_CLK
SIUL
—
SSCM
—
FEC
I/O
—
I/O
—
I
Slow
Medium
49
76
MPC5604E Microcontroller Data Sheet, Rev. 5.1
14
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2,8
Functions
3
Peripheral
Pad speed5
I/O
direction4
SRC = 0
SRC = 1
Pin6
64-pin
100-pin7
B[13]
PCR[29]
ALT0
ALT1
ALT2
ALT3
—
GPI[29]
—
—
—
RX_D0
SIUL
—
—
—
FEC
I
—
—
—
I
Slow
Medium
50
77
B[14]
PCR[30]
ALT0
ALT1
ALT2
ALT3
—
GPI[30]
—
—
—
RX_D1
SIUL
—
—
—
FEC
I
—
—
—
I
Slow
Medium
51
79
B[15]
PCR[31]
ALT0
ALT1
ALT2
ALT3
—
GPI[31]
—
—
—
RX_D2
SIUL
—
—
—
FEC
I
—
—
—
I
Slow
Medium
52
81
Port C (64-pin: 7-bit; 100-pin: 16-bit)
C[0]
PCR[32]
ALT0
ALT1
ALT2
ALT3
—
GPI[32]
—
—
—
RX_D3
SIUL
—
—
—
FEC
I
—
—
—
I
Slow
Medium
53
82
C[1]
PCR[33]
ALT0
ALT1
ALT2
ALT3
—
—
GPI[33]
—
—
—
RX_CLK
EIRQ[15]
SIUL
—
—
—
FEC
SIUL
I
—
—
—
I
I
Slow
Medium
54
83
C[2]
PCR[34]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[34]
ETC[0]
TX
PPS1
D[0]
RX
EIRQ[16]
SIUL
ETIMER0
CAN0
CE_RTC
VID
LIN0
SIUL
I/O
I/O
O
O
I
I
I
Slow
Medium
57
91
C[3]
PCR[35]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[35]
ETC[1]
TX
SYNC
D[1]
RX
EIRQ[17]
SIUL
ETIMER0
LIN0
SAI1
VID
CAN0
SIUL
I/O
I/O
O
I/O
I
I
I
Slow
Medium
60
94
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
15
Package pinouts and signal descriptions
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2,8
Functions
3
Peripheral
I/O
direction4
Pad speed5
SRC = 0
Pin6
SRC = 1
64-pin
100-pin7
C[4]
PCR[36]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[36]
CLK_OUT
ETC[4]
MCLK
TRIGGER1
ABS[0]
EIRQ[19]
SIUL
MC_CGL
ETIMER0
SAI0
CE_RTC
MC_RGM
SIUL
I/O
O
I/O
I/O
I
I
I
Medium
Fast
62
96
C[5]
PCR[37]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[37]
CLK
ETC[3]
CS2
ABS[2]
EIRQ[20]
SIUL
IIC0
ETIMER0
DSPI2
MC_RGM
SIUL
I/O
—
I/O
O
I
I
Slow
Medium
63
99
C[6]
PCR[38]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[38]
DATA
CS0
CS3
FAB
EIRQ[21]
SIUL
IIC0
DSPI1
DSPI2
MC_RGM
SIUL
I/O
—
I/O
O
I
I
Slow
Medium
64
100
C[7]
PCR[39]
ALT0
ALT1
ALT2
ALT3
—
GPIO[39]
TXD
—
—
RXD
SIUL
LIN0
—
—
LIN1
I/O
O
—
—
I
Slow
Medium
—
3
C[8]
PCR[40]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[40]
TXD
—
—
RXD
EIRQ[22]
SIUL
LIN1
—
—
LIN0
SIUL
I/O
O
—
—
I
I
Slow
Medium
—
5
C[9]
PCR[41]
ALT0
ALT1
ALT2
ALT3
—
—
GPI[41]
—
—
—
SIN
EIRQ[23]
SIUL
—
—
—
DSPI0
SIUL
I
—
—
—
I
I
Slow
Medium
—
7
C[10]
PCR[42]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[42]
ETC[5]
ETC[4]
—
SIN
EIRQ[24]
SIUL
ETIMER0
ETIMER0
—
DSPI1
SIUL
I/O
I/O
I/O
—
I
I
Slow
Medium
—
24
C[11]
PCR[43]
ALT0
ALT1
ALT2
ALT3
GPIO[43]
ETC[2]
ETC[1]
ETC[3]
SIUL
ETIMER0
ETIMER0
ETIMER0
I/O
I/O
I/O
I/O
Slow
Medium
—
25
MPC5604E Microcontroller Data Sheet, Rev. 5.1
16
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2,8
Functions
3
Peripheral
I/O
direction4
Pad speed5
SRC = 0
SRC = 1
Pin6
64-pin
100-pin7
C[12]
PCR[44]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[44]
PPS1
PPS2
ALARM1
TRIGGER1
TRIGGER2
EIRQ[25]
SIUL
CE_RTC
CE_RTC
CE_RTC
CE_RTC
CE_RTC
SIUL
I/O
O
O
O
I
I
I
Slow
Medium
—
44
C[13]
PCR[45]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[45]
—
—
—
D[1]
EIRQ[26]
SIUL
—
—
—
VID
SIUL
I/O
—
—
—
I
I
Slow
Medium
—
46
C[14]
PCR[46]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[46]
—
—
—
D[0]
EIRQ[27]
SIUL
—
—
—
VID
SIUL
I/O
—
—
—
I
I
Slow
Medium
—
47
C[15]
PCR[47]
ALT0
ALT1
ALT2
ALT3
—
GPI[47]
—
—
—
COL
SIUL
—
—
—
FEC
I
—
—
—
I
Slow
Medium
—
48
Port D (100-pin package: 16-bit)
D[0]
PCR[48]
ALT0
ALT1
ALT2
ALT3
GPIO[48]
MDO0
—
—
SIUL
NEXUS
—
—
I/O
O
—
—
Slow
Medium
—
9
D[1]
PCR[49]
ALT0
ALT1
ALT2
ALT3
GPIO[49]
MCK0
—
—
SIUL
NEXUS
—
—
I/O
O
—
—
Slow
Medium
—
14
D[2]
PCR[50]
ALT0
ALT1
ALT2
ALT3
GPIO[50]
EVTO
—
—
SIUL
NEXUS
—
—
I/O
O
—
—
Slow
Medium
—
13
D[3]
PCR[51]
ALT0
ALT1
ALT2
ALT3
GPIO[51]
MSEO1
—
—
SIUL
NEXUS
—
—
I/O
O
—
—
Slow
Medium
—
72
D[4]
PCR[52]
ALT0
ALT1
ALT2
ALT3
GPIO[52]
MSEO0
—
—
SIUL
NEXUS
—
—
I/O
O
—
—
Slow
Medium
—
78
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
17
Package pinouts and signal descriptions
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2,8
Functions
3
Peripheral
I/O
direction4
Pad speed5
SRC = 0
Pin6
SRC = 1
64-pin
100-pin7
D[5]
PCR[53]
ALT0
ALT1
ALT2
ALT3
GPIO[53]
MDO3
—
—
SIUL
NEXUS
—
—
I/O
O
—
—
Slow
Medium
—
80
D[6]
PCR[54]
ALT0
ALT1
ALT2
ALT3
GPIO[54]
MDO2
—
—
SIUL
NEXUS
—
—
I/O
O
—
—
Slow
Medium
—
84
D[7]
PCR[55]
ALT0
ALT1
ALT2
ALT3
GPIO[55]
MDO1
—
—
SIUL
NEXUS
—
—
I/O
—
—
—
Slow
Medium
—
98
D[8]
PCR[56]
ALT0
ALT1
ALT2
ALT3
—
GPI[56]
—
—
—
EVTI
SIUL
—
—
—
NEXUS
I
—
—
—
I
Slow
Medium
—
10
D[9]
PCR[57]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[57]
ETC[3]
ETC[2]
—
RXD
EIRQ[28]
SIUL
ETIMER0
ETIMER0
—
CAN0
SIUL
I/O
I/O
I/O
—
I
I
Slow
Medium
—
49
D[10]
PCR[58]
ALT0
ALT1
ALT2
ALT3
GPIO[58]
TXD
—
—
SIUL
CAN0
—
—
I/O
O
—
—
Slow
Medium
—
51
D[11]
PCR[59]
ALT0
ALT1
ALT2
ALT3
GPIO[59]
ETC[0]
ETC[5]
ETC[4]
SIUL
ETIMER0
ETIMER0
ETIMER0
I/O
I/O
I/O
I/O
Slow
Medium
—
52
D[12]
PCR[60]
ALT0
ALT1
ALT2
ALT3
—
GPIO[60]
ETC[1]
ETC[0]
—
SIN
SIUL
ETIMER0
ETIMER0
—
DSPI0
I/O
I/O
I/O
—
I
Slow
Medium
—
53
D[13]
PCR[61]
ALT0
ALT1
ALT2
ALT3
—
—
GPI[61]
—
—
—
CRS
EIRQ[29]
SIUL
—
—
—
FEC
SIUL
I
—
—
—
I
I
Slow
Medium
—
54
MPC5604E Microcontroller Data Sheet, Rev. 5.1
18
Freescale Semiconductor
Package pinouts and signal descriptions
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2,8
Functions
3
Peripheral
I/O
direction4
Pad speed5
SRC = 0
SRC = 1
Pin6
64-pin
100-pin7
D[14]
PCR[62]
ALT0
ALT1
ALT2
ALT3
—
—
GPI[62]
—
—
—
RX_ER
EIRQ[30]
SIUL
—
—
—
FEC
SIUL
I
—
—
—
I
I
Slow
Medium
—
57
D[15]
PCR[63]
ALT0
ALT1
ALT2
ALT3
GPIO[63]
F[0]
—
—
SIUL
FCU0
—
—
I/O
O
—
—
Slow
Medium
—
69
Port E (100-pin package: 7-bit)
E[0]
PCR[64]
ALT0
ALT1
ALT2
ALT3
GPIO[64]
F[1]
—
—
SIUL
FCU0
—
—
I/O
O
—
—
Slow
Medium
—
68
E[1]
PCR[65]
ALT0
ALT1
ALT2
ALT3
GPIO[65]
TX_ER
—
—
SIUL
FEC
—
—
I/O
O
—
—
Slow
Medium
—
71
E[2]
PCR[66]
ALT0
ALT1
ALT2
ALT3
—
—
GPI[66]
—
—
—
RXD
EIRQ[31]
SIUL
—
—
—
LIN1
SIUL
I
—
—
—
I
I
Slow
Medium
—
85
E[3]
PCR[67]
ALT0
ALT1
ALT2
ALT3
GPIO[67]
TXD
—
—
SIUL
LIN1
—
—
I/O
O
—
—
Slow
Medium
—
86
E[4]
PCR[68]
ALT0
ALT1
ALT2
ALT3
GPIO[68]
CS0
CS0
CS0
SIUL
DSPI0
DSPI1
DSPI2
I/O
I/O
I/O
I/O
Slow
Medium
—
89
E[5]
PCR[69]
ALT0
ALT1
ALT2
ALT3
GPIO[69]
SCK
SCK
SCK
SIUL
DSPI0
DSPI1
DSPI2
I/O
I/O
I/O
I/O
Slow
Medium
—
90
E[6]
PCR[70]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[70]
SOUT
SOUT
SOUT
SIN
SIN
SIN
SIUL
DSPI0
DSPI1
DSPI2
DSPI0
DSPI2
DSPI2
I/O
O
O
O
I
I
I
Slow
Medium
—
97
1
ALT0 is the primary (default) function for each port after reset.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
19
Package pinouts and signal descriptions
2
3
4
5
6
7
8
Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIU module. PCR.PA = 00 → ALT0;
PCR.PA = 01 → ALT1; PCR.PA = 10 → ALT2; PCR.PA = 11 → ALT3. This is intended to select the output functions; to use
one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA bitfields.
For this reason, the value corresponding to an input only function is reported as “—”.
Module included on the MCU.
Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the
values of the PSMIO.PADSELx bitfields inside the SIUL module.
Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register.
Additional board pull resistors are recommended when JTAG pins are not being used on the board or application.
The 100-pin package is not a production package. It is used for software development only.
Do not use ALT multiplexing when ADC channels are used.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
20
Freescale Semiconductor
Electrical characteristics
3
Electrical characteristics
3.1
Introduction
This section contains electrical characteristics of the device as well as temperature and power considerations.
This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take
precautions to avoid application of any voltage higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This can be done by the
internal pull-up or pull-down, which is provided by the product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and its demands on the system.
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller
Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” for System Requirement is included in the Symbol column.
CAUTION
All of the following figures are indicative and must be confirmed during either silicon validation, silicon characterization or
silicon reliability trial.
3.2
Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding, the classifications listed in Table 5 are used and the parameters are tagged accordingly in the tables where
appropriate.
Table 5. Parameter classifications
Classification tag
Tag description
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
21
Electrical characteristics
3.3
Absolute maximum ratings
Table 6. Absolute Maximum Ratings1
Conditions
Min
Max2
Unit
SR Device ground
—
VSS
VSS
V
VDD_HV_IO
SR 3.3 V Input/Output Supply Voltage
(supply).
Code Flash supply with VDD_HV_IO3
and Data Flash with VDD_HV_IO2
—
VSS _ 0.3
VSS + 6.0
V
VSS_HV_IO
SR 3.3 VInput/Output Supply Voltage
(ground).
Code Flash ground with VSS_HV_IO3
and Data Flash with VSS_HV_IO2
—
VSS _ 0.1
VSS + 0.1
V
Symbol
VSS
VDD_HV_OSC
SR 3.3 V Crystal Oscillator Amplifier
Supply voltage (supply)
VSS_HV_OSC
SR 3.3 V Crystal Oscillator Amplifier
Supply voltage (ground)
The oscillator and flash supply segments are
double-bounded with the VDD_HV_IO segments. See
VDD_HV_IO and VSS_HV_IO specifications.
VDD_HV_ADC03
SR 3.3 V ADC_0 Supply and High
Reference voltage
—
VSS _ 0.3
VSS_HV_ADC0
SR 3.3 V ADC_0 Ground and Low
Reference voltage
—
VSS _ 0.1
VDD_HV_REG
SR 3.3 V Voltage Regulator Supply
voltage
—
VSS _ 0.3
TVDD
SR Slope characteristics on all VDD
during power up4
—
—
VDD_LV_COR
SR 1.2 V supply pins for core logic
(supply)
—
VSS _ 0.3
VSS_LV_COR
SR 1.2 V supply pins for core logic
(ground)
—
VSS _ 0.1
SR Voltage on any pin with respect to
ground (VSS_HV_IO)
—
VSS_HV_IO _ 0.3
IINJPAD
SR Input current on any pin during
overload condition
—
IINJSUM
SR Absolute sum of all input currents
during overload condition
VIN
TSTORAGE
TJ
TA
1
Parameter
—
VSS + 6.0
V
VSS + 0.1
V
VSS + 6.0
V
0.1
V/us
VSS + 1.4
V
VSS + 0.1
V
VDD_HV_IO +0.5
V
–10
10
mA
—
–50
50
mA
SR Storage temperature
—
–55
150
°C
SR Junction temperature under bias
—
–40
150
°C
SR Ambient temperature under bias
fCPU<64 MHz
–40
125
°C
fCPU<64 MHz
Video use
case with
internal supply
–40
105
°C
Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect
device reliability or cause permanent damage to the device.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
22
Freescale Semiconductor
Electrical characteristics
2
Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device
stress have not yet been determined.
3
MPC5604E’s I/O, flash, and oscillator circuit supplies are interconnected. The ADC supply managed independently
from other supplies.
4
Guaranteed by device validation.
3.4
Recommended operating conditions
Table 7. Recommended operating conditions
Conditions
Min
Max1
Unit
SR Device ground
—
VSS
VSS
V
VDD_HV_IO
SR 3.3 V input/output supply voltage
—
3.0
3.6
V
VSS_HV_IO
SR Input/output ground voltage
—
0
0
V
Symbol
VSS
Parameter
VDD_HV_OSC
SR 3.3 V Crystal Oscillator Amplifier Supply
voltage (supply)
VSS_HV_OSC
SR 3.3 V Crystal Oscillator Amplifier Supply
voltage (ground)
The oscillator and flash supply segments
are double-bounded with the VDD_HV_IOx
segments. See VDD_HV_IOx and
VSS_HV_IOx specifications.
—
SR 3.3 V ADC_0 Supply and High Reference
voltage
—
3.0
3.6
V
SR 3.3 V voltage regulator supply voltage
—
3.0
3.6
V
VDD_LV_EXTCOR
SR Externally supplied core voltage
—
1.15
1.32
V
VDD_LV_REGCOR
SR Internal supply voltage
—
—
—
V
VSS_LV_REGCOR
SR Internal reference voltage
—
0
0
V
VDD_LV_COR
SR Internal supply voltage
—
—
—
V
VSS_LV_COR
SR Internal reference voltage
—
0
0
V
VSS_HV_ADC0
SR Ground and Low Reference voltage
—
0
0
V
–40
150
°C
fCPU<64 MHz
–40
125
°C
fCPU<64 MHz
Video use case
with internal
supply
–40
105
°C
VDD_HV_ADC02
VDD_HV_REG
TJ
SR Junction temperature under bias
SR Ambient temperature under bias
TA
1
Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics
and I/Os DC electrical specification may not be guaranteed.
2 MPC5604E’s I/O, flash, and oscillator circuit supplies are interconnected. The ADC supply managed independently
from other supplies.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
23
Electrical characteristics
3.5
Thermal characteristics
Table 8. Thermal characteristics for 100-pin LQFP1
Symbol
RθJA
Parameter
Conditions
Thermal resistance junction-to-ambient,
natural convection2
Thermal resistance junction-to-ambient
2
1
2
3
4
5
6
51
°C/W
Four layer board—2s2p
38
°C/W
@ 200 ft./min. , single layer
board—1s
41
°C/W
@ 200 ft./min.3, four layer
board—2s2p
32
°C/W
—
23
°C/W
—
11
°C/W
—
2
°C/W
Thermal resistance junction to board4
RθJCtop Thermal resistance junction to case (top)
ΨJT
Single layer board—1s
3
RθJMA
RθJB
Typical
Unit
value
5
Junction to package top natural convection6
Thermal characteristics are targets based on simulation that are subject to change per device
characterization.
Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test
board meets JEDEC specification for this package.
Flow rate of forced air flow.
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface
layer.
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written as Psi-JT.
Table 9. Thermal characteristics for 64-pin LQFP1
Symbol
RθJA
Parameter
Conditions
Thermal resistance junction-to-ambient,
natural convection2
Thermal resistance
junction-to-ambient2
RθJMA
RθJB
RθJCtop Thermal resistance junction to case (top)5
ΨJT
Single layer board—1s
64
°C/W
Four layer board—2s2p
45
°C/W
52
°C/W
39
°C/W
—
28
°C/W
—
14
°C/W
—
3
°C/W
ft./min.3,
@ 200
board—1s
single layer
@ 200 ft./min.3, four layer
board—2s2p
Thermal resistance junction to board4
Junction to package top natural
convection6
Typical
Unit
value
1
Thermal characteristics are targets based on simulation that are subject to change per device
characterization.
2 Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test
board meets JEDEC specification for this package.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
24
Freescale Semiconductor
Electrical characteristics
3
Flow rate of forced air flow.
Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
5
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface
layer.
6
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written as Psi-JT.
4
3.5.1
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from Equation 1:
TJ = TA + (RθJA * PD)
Eqn. 1
where:
TA
= ambient temperature for the package (°C)
RθJA
= junction to ambient thermal resistance (°C/W)
PD
= power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal
performance. There are two values in common usage: the value determined on a single layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer
to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board
is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually
appropriate if the board has low power dissipation and the components are well separated.
When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction to case thermal resistance
and a case to ambient thermal resistance:
RθJA = RθJC + RθCA
Eqn. 2
where:
RθJA
= junction to ambient thermal resistance (°C/W)
RθJC
= junction to case thermal resistance (°C/W)
RθCA = case to ambient thermal resistance (°C/W)
RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to
ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the
interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit
board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal
Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at
the top center of the package case using Equation 3:
TJ = TT + (ΨJT x PD)
Eqn. 3
where:
TT
= thermocouple temperature on top of the package (°C)
ΨJT
= thermal characterization parameter (°C/W)
PD
= power dissipation in the package (W)
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
25
Electrical characteristics
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects
of the thermocouple wire.
References:
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134
U.S.A.
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
1.
2.
3.
3.6
C.E. Triplett and B. Joiner, An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller
Module, Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
G. Kromann, S. Shidore, and S. Addison, Thermal Modeling of a PBGA for Air-Cooled Applications, Electronic
Packaging and Production, pp. 53-58, March 1998.
B. Joiner and V. Adams, Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in
Thermal Modeling, Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
Electromagnetic Interference (EMI) characteristics
Table 10. EMI Testing Specifications1
Symbol
Radiated
emissions
Parameter
VEME
Conditions
Clocks
Frequency
Range
VDD = 3.3 V
TA = +25 °C
Oscillator Frequency = 8 150 kHz–50 MHz
MHz;
50–150 MHz
System Bus Frequency =
Device
64 MHz;
150–500 MHz
Configuration, test
CPU Freq = 64MHZ
500–1000 MHz
conditions and EM
No PLL Frequency
testing per standard
Modulation
IEC Level
IEC61967-2.
External Oscillator Freq = 150 kHz–50 MHz
8 MHz
50–150 MHz
System Bus Freq = 64
MHz
150–500 MHz
CPU Freq = 64MHZ
500–1000 MHz
Level
(Typ)
Unit
2
14
dBμV
11
7
M
1
11
dBμV
7
1
2% PLL Freq Modulation
IEC Level
1
N
EMI testing and I/O port waveforms per standard IEC61967-2.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
26
Freescale Semiconductor
Electrical characteristics
3.7
Electrostatic Discharge (ESD) characteristics
Table 11. ESD ratings1,2
Symbol
Parameter
VESD(HBM)
SR Electrostatic discharge (Human Body Model)
VESD(CDM)
SR
Conditions
Value
Unit
—
2000
V
Electrostatic discharge (Charged Device Model)
750 (corners)
—
V
500 (other)
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification
3.8
Power management electrical characteristics
3.8.1
Power Management Overview
The device supports the following power modes:
•
•
Internal voltage regulation mode
External voltage regulation mode
3.8.1.1
Internal voltage regulation mode
In this mode, the following supplies are involved:
•
VDD_HV_IO (3.3V) — This is the main supply provided externally.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
27
Electrical characteristics
•
VDD_LV_COR (1.2V) — This is the core logic supply. In the internal regulation mode, the core supply is derived from
the main supply via an on-chip linear regulator driving an internal PMOS ballast transistor. The PMOS ballast
transistors are located in the pad ring and their source connectors are directly bonded to a dedicated pin. See Figure 4.
Pads Pins
Vss_HV_IO0_X
3.3V
Vdd_HV_IO0_X
Vdd_HV_S_Ballast0/1
Vreg
LVD
...
POR_B
1.2V
...
Vdd_LV_REGCOR0
Vdd_LV_COR0_X
(3 supply pairs)
Vss_LV_COR0_X
Figure 4. Internal Regulation Mode
The core supply can also be provided externally. Table 12 shows how to connect VDD_HV_S_BALLAST pin for internal and
external core supply mode.
NOTE
VDD_HV_S_BALLAST pin is the supply pin, which carries the entire core logic current in the
internal regulation mode, while in external regulation mode it is used as a signal to bypass
the regulator.
Table 12. Core Supply Select
Mode
VDD_HV_S_Ballast
Internal supply mode (via internal PMOS ballast
transistors)
VDD_HV_IO (3.3V)
External supply mode (e.g., via external switched
regulator)
VDD_LV_COR (1.2V)
MPC5604E Microcontroller Data Sheet, Rev. 5.1
28
Freescale Semiconductor
Electrical characteristics
3.8.1.2
External voltage regulation mode
In the external regulation mode, the core supply is provided externally using a switched regulator. This saves on-chip power
consumption by avoiding the voltage drop over the ballast transistor. The external supply mode is selected via a board level
supply change at the VDD_HV_S_BALLAST pin.
Pads Pins
Vss_HV_IO0_X
Vdd_HV_IO0_X
3.3V
Vdd_HV_S_Ballast0/1
1.2V
(1.15V-1.32V)
Vreg
relaxed
LVD
...
POR_B
Power
Supply, e.g.,
switched or
linear
1.2V
...
Vdd_LV_REGCOR0
Vdd_LV_COR0_X
(3 supply pairs)
Vss_LV_COR0_X
Figure 5. External Regulation Mode
3.8.1.3
Recommended power supply sequencing1
For MPC5604E, the external supplies need to be maintained as per the following relations:
•
•
•
3.8.2
VDD_HV_IO should be always greater or equal to VDD_HV_S_Ballast
VDD_HV_IO should be always greater than VDD_LV_COR0_X
VDD_HV_IO should be always greater than VDD_HV_ADC
Voltage regulator electrical characteristics
1.Investigations are in process to relax power supply sequencing recommendation.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
29
Electrical characteristics
\
CREG2 (LV_COR/LV_CFLA)
GND
600 nF
VDD_HV_IO
VDD_LV_COR0_2
VSS_LV_COR0_2
VDD_HV_S_BALLAST0
VREF
VDD_LV_COR0_0
Voltage Regulator
I
VDD_HV_S_BALLAST1
CREG1 (LV_COR/LV_DFLA)
+
CDEC1 (Ballast decoupling)
-
VDD_LV_COR0_3
DEVICE
VSS_HV_IO
GND
DEVICE
VSS_LV_COR0_0
VSS_LV_COR0_1
VSS_HV_IO
VDD_HV_IO
VDD_LV_COR0_1
600 nF
GND
GND
CREG3 (LV_COR/LV_PLL)
CDEC2 (supply/IO decoupling)
Figure 6. Voltage regulator capacitance connection
Table 13. Voltage regulator electrical characteristics
Symbol
C
Parameter
Value
Conditions1
Unit
Min
Typ
Max
CREGn2
SR —
Internal voltage regulator external
capacitance
—
200
—
600
nF
RREG
SR —
Stability capacitor equivalent serial
resistance
—
0.05
—
0.2
Ω
Decoupling capacitance3 ballast
—
1004
CDEC1
SR —
—
400
CDEC2
SR —
—
100 nF
1 μF
—
—
1.32
—
1.15
1.28
1.32
—
—
150
IMREG = 200 mA
—
—
2
IMREG = 0 mA
—
—
1
T
VMREG
Decoupling capacitance regulator
supply
Main regulator output voltage
CC
P
IMREG
IMREGINT
SR —
Before exiting from
reset
After trimming
Main regulator current provided to
VDD_LV domain
Main regulator module current
CC D consumption
—
4705
—
nF
—
—
V
mA
mA
MPC5604E Microcontroller Data Sheet, Rev. 5.1
30
Freescale Semiconductor
Electrical characteristics
Table 13. Voltage regulator electrical characteristics (continued)
Symbol
IDD_BV
1
C
CC D
Parameter
Value
Conditions1
In-rush current on VDD_BV during
power-up6
Unit
—
Min
Typ
Max
—
—
407
mA
VDD = 3.3 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
It is required by the device in internal voltage regulation mode only.
This capacitance value is driven by the constraints of the external voltage regulator that supplies the VDD_BV
voltage. A typical value is in the range of 470 nF. This capacitance should be placed close to the device pin.
This value is acceptable to guarantee operation from 3.0 V to 3.6 V
External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV
in operating range.
In-rush current is seen only for short time during power-up and on standby exit (max 20 µs, depending on external
LV capacitances to be load)
The duration of the in-rush current depends on the capacitance placed on LV pins. BV decaps must be sized
accordingly. Refer to IMREG value for minimum amount of current to be provided in cc.
2
3
4
5
6
7
3.8.3
Voltage monitor electrical characteristics
The device implements a POR module to ensure correct power-up initialization, as well as three low voltage detectors to
monitor the VDD_HV and the VDD_LV voltage while device is supplied:
•
•
•
POR monitors VDD_HV during the power-up phase to ensure device is maintained in a safe reset state
LVDHV3 monitors VDD_HV to ensure device reset below minimum functional supply
LVDLVCOR monitors low voltage digital power domain
Table 14. Low voltage monitor electrical characteristics
Symbol
1
3.9
Parameter
VPORH
T Power-on reset threshold
VPORUP
D Supply for functional POR module
Conditions1
Value
Unit
Min
Max
—
1.5
2.7
V
TA = 25°C
1.0
—
V
—
—
2.95
V
VDDHVLVDMOK_H
P
VDD_HV low voltage detector high threshold
VDDHVLVDMOK_L
P VDD_HV low voltage detector low threshold
—
2.6
—
V
VMLVDDOK_H
P Digital supply low voltage detector high
—
—
1.235
V
VMLVDDOK_L
P Digital supply low voltage detector low
—
1.095
—
V
VDD_HV = 3.3V ± 10% TA = –40 °C to TA MAX, unless otherwise specified
Power Up/Down reset sequencing
The MPC5604E implements a precise sequence to ensure each module is started only when all conditions for switching it ON
are available. This prevents overstress event or miss-functionality within and outside the device:
•
A POR module working on voltage regulator supply is controlling the correct start-up of the regulator. This is a key
module ensuring safe configuration for all Voltage regulator functionality when supply is below 1.5 V. Associated POR
(or POR) signal is active low.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
31
Electrical characteristics
•
•
Several Low Voltage Detectors, working on voltage regulator supply are monitoring the voltage of the critical modules
(Voltage regulator, I/Os, Flash and Low voltage domain). LVDs are gated low when POWER_ON is active.
A POWER_OK signal is generated when all critical supplies monitored by the LVD are available. This signal is active
high and released to all modules including I/Os, Flash and RC16 oscillator needed during power-up phase and reset
phase. When POWER_OK is low the associated module are set into a safe state.
VDD_HV_REG
VPORH
VLVDHV3H
3.3V
VPOR_UP
0V
3.3V
POWER_ON
0V
3.3V
LVDM (HV)
0V
VDD_LV_REGCOR
VMLVDOK_H
1.2V
0V
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
1.2V
0V
~1us
Internal Reset Generation Module
FSM
P0
P1
1.2V
0V
Figure 7. Power-up typical sequence
VLVDHV3L
VDD_HV_REG
VPORH
3.3V
0V
3.3V
LVDM (HV)
0V
3.3V
POWER_ON
0V
1.2V
0V
VDD_LV_REGCOR
3.3V
LVDD (LV)
0V
3.3V
POWER_OK
0V
RC16MHz Oscillator
1.2V
0V
Internal Reset Generation Module
FSM
IDLE
P0
1.2V
0V
Figure 8. Power-down typical sequence
MPC5604E Microcontroller Data Sheet, Rev. 5.1
32
Freescale Semiconductor
Electrical characteristics
3.10
DC electrical characteristics
Table 15 gives the DC electrical characteristics at 3.3 V (3.0 V < VDD_HV_IO < 3.6 V).
Table 15. DC electrical characteristics (3.3 V)1
Symbol
1
2
Parameter
Conditions
Min
Max
Unit
VIL
D Minimum low level input voltage
—
–0.42
—
V
VIL
P Maximum low level input voltage
—
—
0.35 VDD_HV_IO
V
VIH
P Minimum high level input voltage
—
0.65 VDD_HV_IO
—
V
VIH
D
Maximum high level input
voltage
—
—
VDD_HV_IO + 0.42
V
VHYS
T
Schmitt trigger hysteresis
—
0.1 VDD_HV_IO
—
V
VOL_S
P Slow, low level output voltage
IOL = 2 mA
—
0.1VDD_HV_IO
V
VOH_S
P Slow, high level output voltage
IOH = –2 mA
0.8VDD_HV_IO
—
V
VOL_M
P Medium, low level output voltage
IOL = 2 mA
—
0.1VDD_HV_IO
V
VOH_M
P
Medium, high level output
voltage
IOH = –3 mA
0.8VDD_HV_IO
—
V
VOL_F
P Fast, high level output voltage
IOL = 11 mA
—
0.1VDD_HV_IO
V
VOH_F
P Fast, high level output voltage
IOH = –11 mA
0.8VDD_HV_IO
—
V
µA
IPU
P Equivalent pull-up current
VIN = VIL
–95
—
IPD
P Equivalent pull-down current
VIN = VIH
—
95
IIL
P
Input leakage current
(all bidirectional ports)
TA = –40 to
125 °C
—
1
µA
IIL
P
Input leakage current
(all ADC input-only ports)
TA = –40 to
125 °C
—
0.5
µA
VILR
D
Minimum RESET, low level input
voltage
—
–0.42
—
V
VILR
P
Maximum RESET, low level
input voltage
—
—
0.35 VDD_HV_IO
V
VIHR
P
Minimum RESET, high level
input voltage
—
0.65 VDD_HV_IO
—
V
VIHR
D
Maximum RESET, high level
input voltage
—
—
VDD_HV_IO + 0.42
V
VHYSR
D
RESET, Schmitt trigger
hysteresis
—
0.1 VDD_HV_IO
—
V
VOLR
D RESET, low level output voltage IOL = 0.5 mA
—
0.1VDD_HV_IO
V
VIN = VIL
–130
—
VIN = VIH
—
–10
—
—
10
IPU
RESET, equivalent pull-up
D current
CIN
D Input capacitance
µA
pF
These specifications are design targets and subject to change per device characterization.
“SR” parameter values must not exceed the absolute maximum ratings shown in Table 6.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
33
Electrical characteristics
Table 16. Supply current
Value1
Conditions
Symbol
Unit
Parameter
I
DD_LV_CORE
C
P
P
RUN Mode, I/O currents not included,
worst case over temperature for
system clock
HALT Mode2
V
DD_LV_CORx
externally forced at 1.3 V
STOP Mode3
V
DD_LV_CORx
externally forced at 1.3 V
IDD_FLASH
Min
Typ
Max
—
75
120
—
4
25
—
4
25
—
4
7
—
9
14
—
3.5
6
—
7.5
12
Code Flash
FLASH supply current
during read
VDD_HV_IO at 3.3 V
FLASH supply current
Supply
during erase operation
current
on 1 Flash module
VDD_HV_IO at 3.3 V
mA
C
Data Flash
IDD_ADC
C
I
DD_OSC
C
FLASH supply current
during read
VDD_HV_IO at 3.3 V
FLASH supply current
during erase operation
on 1 Flash module
VDD_HV_IO at 3.3 V
ADC supply current
VDD_HV_ADC0 at 3.3 V
ADC Freq = 16MHz
—
1.8
3
OSC supply current
VDD_HV_OSC at 3.3 V
16 MHz
—
0.74
4
1
All values to be confirmed after characterization/data collection.
Halt mode configurations: Code fetched from SRAM, Code Flash and Data Flash in low power mode, OSC/PLL0 are OFF,
Core clock frozen, all peripherals are disabled.
3 STOP "P" mode DUT configuration: Code fetched from SRAM, Code Flash and Data Flash off, OSC/PLL0 are OFF, Core clock
frozen, all peripherals are disabled.
2
3.11
Main oscillator electrical characteristics
The MPC5604E provides an oscillator/resonator driver.
Table 17. Main oscillator electrical characteristics
Symbol
Parameter
Min
Max
Unit
40
MHz
fOSC
SR Oscillator frequency
4
gm
P Transconductance
4
VOSC
tOSCSU
T Oscillation amplitude on XTAL pin
1,2
T Start-up time
15.846 mA/V
1.3
2.25
V
—
5
ms
MPC5604E Microcontroller Data Sheet, Rev. 5.1
34
Freescale Semiconductor
Electrical characteristics
1
The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and excessive capacitive
loads can cause long start-up time.
2
Value captured when amplitude reaches 90% of XTAL
Table 18. Input clock characteristics
Symbol
Min
Typ
Max
Unit
fOSC
SR Oscillator frequency
4
—
40
MHz
fCLK
SR Frequency in bypass
—
—
100
MHz
trCLK
SR Rise/fall time in bypass
—
—
1
ns
47.5
50
52.5
%
SR Duty cycle
tDC
3.12
Parameter
FMPLL electrical characteristics
Table 19. PLLMRFM electrical specifications1
(VDDPLL = 3.0 V to 3.6 V, VSS = VSSPLL = 0 V, TA = TL to TH)
Value
Symbol
Parameter
PLL reference frequency range2
Conditions
Unit
Min
Max
4
40
MHz
fref_crystal
fref_ext
D
fpll_in
D
Phase detector input frequency range
(after pre-divider)
—
4
16
MHz
fFMPLLO
D
Clock frequency range in normal
mode
—
4
120
MHz
Measured using
clock
division—typicall
y /16
20
150
MHz
UT
VCO free running frequency
Crystal reference
fVCO
P
fsys
D
On-chip PLL frequency2
—
16
64
MHz
tCYC
D
System clock period
—
—
1 / fsys
ns
—
20
150
MHz
fSYS maximum
500
500
–6
6
ns
fSCM
CJITTER
D
Self-clocked mode
T
CLKOUT
period
jitter5,6,7,8
frequency3,4
Peak-to-peak (clock
edge to clock edge)
Long-term jitter (avg.
over 2 ms interval)
ps
tlpll
D
PLL lock time 9, 10
—
—
200
μs
tdc
D
Duty cycle of reference
—
40
60
%
fLCK
D
Frequency LOCK range
—
–6
6
% fsys
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
35
Electrical characteristics
Table 19. PLLMRFM electrical specifications1
(VDDPLL = 3.0 V to 3.6 V, VSS = VSSPLL = 0 V, TA = TL to TH) (continued)
Value
Symbol
Parameter
fUL
D
fCS
fDS
D
fMOD
D
Frequency un-LOCK range
Modulation Depth
Modulation frequency12
Conditions
Unit
Min
Max
–18
18
Center spread
±0.25
±4.011
Down Spread
–0.5
–8.0
—
100
—
—
% fsys
%fsys
kHz
1
All values given are initial design targets and subject to change.
Considering operation with PLL not bypassed.
3
Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside
the fLOR window.
4 f
VCO self clock range is 20-150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in
enhanced mode.
5 This value is determined by the crystal manufacturer and board design.
6 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency
increase the CJITTER percentage for a given interval.
7 Proper PC board layout procedures must be followed to achieve specifications.
8 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C
JITTER and
either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
9 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for
this PLL, load capacitors should not exceed these limits.
10 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
11 This value is true when operating at frequencies above 60 MHz, otherwise f
CS is 2% (above 64 MHz).
12 Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.
2
3.13
16 MHz RC oscillator electrical characteristics
Table 20. 16 MHz RC oscillator electrical characteristics
Symbol
fRC
1
Parameter
C RC oscillator frequency
ΔRCMVAR
Fast internal RC oscillator variation in
temperature and supply with respect to
P
fRC at TA = 55 °C in high-frequency
configuration
ΔRCMTRIM
T
Post Trim Accuracy: The variation of
the PTF1 from the 16 MHz oscillator
Conditions
Min
Typ
Max
Unit
TA = 25 °C
8.5
16
24
MHz
—
–5
—
5
%
TA = 25 °C
–2
—
2
%
PTF = Post Trimming Frequency: The frequency of the output clock after trimming at typical supply voltage and
temperature
MPC5604E Microcontroller Data Sheet, Rev. 5.1
36
Freescale Semiconductor
Electrical characteristics
3.14
Analog-to-Digital Converter (ADC) electrical characteristics
The device provides a 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter.
Offset Error OSE
Gain Error GE
1023
1022
1021
1020
1019
1 LSB ideal = VDD_ADC / 1024
1018
(2)
code out
7
(1)
6
(1) Example of an actual transfer curve
5
(5)
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
4
(4) Integral non-linearity error (INL)
(4)
(5) Center of a step of the actual transfer curve
3
(3)
2
1
1 LSB (ideal)
0
1
2
3
4
5
6
7
1017 1018 1019 1020 1021 1022 1023
Vin(A) (LSBideal)
Offset Error OSE
Figure 9. ADC characteristics and error definitions
3.14.1
Input impedance and ADC accuracy
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it sources charge
during the sampling phase, when the analog signal source is a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
37
Electrical characteristics
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being
substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path
to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 kΩ is obtained (REQ
= 1 / (fc×CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage
partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit
must be designed to respect the Equation 4:
Eqn. 4
R S + R F + R L + R SW + R AD
V A • --------------------------------------------------------------------------- < 1
--- LSB
R EQ
2
Equation 4 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW
and RAD) can be neglected with respect to external resistances.
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
RS
VA
Filter
RF
Current Limiter
RL
CF
Channel
Selection
Sampling
RSW1
RAD
CP1
CP2
RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
Current Limiter Resistance
RL
RSW1 Channel Selection Switch Impedance
RAD Sampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance
Figure 10. Input equivalent circuit
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are
initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 10): A charge sharing phenomenon
is installed when the sampling phase is started (A/D switch close).
MPC5604E Microcontroller Data Sheet, Rev. 5.1
38
Freescale Semiconductor
Electrical characteristics
Voltage Transient on CS
VCS
VA
VA2
ΔV < 0.5 LSB
1
2
τ1 < (RSW + RAD) CS << TS
τ2 = RL (CS + CP1 + CP2)
VA1
TS
t
Figure 11. Transient behavior during sampling phase
In particular two different transient periods can be distinguished:
•
A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series,
and the time constant is
Eqn. 5
CP • CS
τ 1 = ( R SW + R AD ) • --------------------CP + CS
Equation 5 can again be simplified considering only CS as an additional worst condition. In reality, the transient is
faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS
is always much longer than the internal time constant:
Eqn. 6
τ 1 < ( R SW + R AD ) • C S « T S
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance
according to Equation 7:
Eqn. 7
V A1 • ( C S + C P1 + C P2 ) = V A • ( C P1 + C P2 )
•
A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance
RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality
would be faster), the time constant is:
Eqn. 8
τ 2 < R L • ( C S + C P1 + C P2 )
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
39
Electrical characteristics
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed
well before the end of sampling time TS, a constraints on RL sizing is obtained:
Eqn. 9
10 • τ 2 = 10 • R L • ( C S + C P1 + C P2 ) < TS
Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source
impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2
(at the end of the charge transfer transient) will be much higher than VA1. Equation 10 must be respected (charge
balance assuming now CS already charged at VA1):
Eqn. 10
VA2 • ( C S + C P1 + C P2 + C F ) = V A • C F + V A1 • ( C P1 + C P2 + C S )
The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to
provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of
the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing.
Analog Source Bandwidth (VA)
Noise
TC ≤ 2 RFCF (Conversion Rate vs. Filter Pole)
fF = f0 (Anti-aliasing Filtering Condition)
2 f0 ≤ fC (Nyquist)
f0
f
Anti-Aliasing Filter (fF = RC Filter pole)
fF
f
Sampled Signal Spectrum (fC = conversion Rate)
f0
fC
f
Figure 12. Spectral representation of input signal
Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF),
according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater
than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS,
which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a
specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the
sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the
sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage
drop on CS; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled
voltage on CS:
MPC5604E Microcontroller Data Sheet, Rev. 5.1
40
Freescale Semiconductor
Electrical characteristics
Eqn. 11
VA
C P1 + C P2 + C F
------------ = -------------------------------------------------------V A2
C P1 + C P2 + C F + C S
From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of
half a count, a constraint is evident on CF value:
Eqn. 12
C F > 2048 • C S
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
41
Electrical characteristics
3.14.2
ADC conversion characteristics
Table 21. ADC conversion characteristics
Symbol
fCK
fs
Parameter
Unit
Min
Typ
Max
ADC clock frequency
(depends on ADC
SR configuration)
(The duty cycle depends on
ADCClk2 frequency)
—
1
—
64
MHz
SR Sampling frequency
—
—
—
1.53
MHz
500
—
—
ns
—
—
28.2
µs
500
—
—
ns
—
—
—
2.5
pF
Sample time3
tADC_S
Value
Conditions1
fADC = 20 MHz,
ADC_conf_sample_input = 17
D
fADC = 9 MHz,
INPSAMP = 255
Conversion time4
fADC = 20 MHz5,
ADC_conf_comp = 3
tADC_C
P
CS6
D
CP16
D ADC input pin capacitance 1
—
—
—
0.87
pF
6
D ADC input pin capacitance 2
—
—
—
1
pF
CP2
ADC input sampling
capacitance
RSW16
D
Internal resistance of analog
source
—
—
—
0.6
kΩ
RAD6
D
Internal resistance of analog
source
—
—
—
2
kΩ
IINJ
T
Current injection on one ADC input,
different from the converted one.
Remains within TUE specification
–5
—
5
mA
INL
P Integral Non Linearity
No overload
–1.5
—
1.5
LSB
DNL
P Differential Non Linearity
No overload
–1.0
—
1.0
LSB
OFS
T Offset error
—
—
±1
—
LSB
GNE
T Gain error
—
—
±1
—
LSB
TUE
P
Total unadjusted error
without current injection
—
–3
—
3
LSB
TUE
T
Total unadjusted error with
current injection
—
–3
—
3
LSB
TUE
P Total unadjusted error
—
–3
—
3
LSB
-2
—
2
LSB
—
—
—
LSB
No overload
-3
—
3
LSB
overload conditions on adjacent
channel
—
—
—
LSB
Input current injection
TUEP
TUEX
Total Unadjusted Error for
No overload
precise
channels,
input
only
CC
overload conditions on adjacent
pins
channel
Total Unadjusted Error for
CC extended channel,
MPC5604E Microcontroller Data Sheet, Rev. 5.1
42
Freescale Semiconductor
Electrical characteristics
1
2
3
4
5
6
7
3.15
VDD = 3.3 V to 3.6 V, TA = –40 to +125 °C, unless otherwise specified and analog input voltage from VAGND to
VAREF.
ADCClk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the
end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC_S depend on programming.
This parameter does not include the sample time tADC_S, but only the time for determining the digital result and the
time to load the result register with the conversion result.
20 MHz ADC clock. Specific prescaler is programmed on MC_PLL_CLK to provide 20 MHz clock to the ADC.
See Figure 10.
Does not include packaging and bonding capacitances
Temperature sensor electrical characteristics
Table 22. Temperature sensor electrical characteristics
Value
Symbol
3.16
C
Parameter
Temperature
monitoring range
Conditions
Unit
min
typical
max
—
–40
—
150
°C
—
—
5.14
—
mV/°C
—
CC
C
—
CC
C Sensitivity
—
CC
C Accuracy
TJ = –40 to 25 °C
–10
—
10
°C
—
CC
C
TJ = –25 to 125 °C
–10
—
10
°C
Flash memory electrical characteristics
Table 23. Code flash program and erase specifications1
Symbol
TDWPRG
Parameter
Double Word Program5
KB)5, 6
Typical
Min Value
Value2
(0 Cycles)
Initial
Max4
Max3
(100000
(100
Cycles)
Cycles)
Unit
—
22
50
500
μs
—
1.45
1.65
33
s
TBKPRG
Bank Program (512
TER8K
Sector Erase (8KB)
—
0.2
0.4
5.0
s
TER16K
Sector Erase (16KB)
—
0.3
0.5
5.0
s
TER32K
Sector Erase (32KB)
—
0.3
0.6
5.0
s
TER64K
Sector Erase (64KB)
—
0.6
0.9
5.0
s
TER128K
Sector Erase (128KB)
—
0.8
1.3
7.5
s
TER512K
Bank Erase (512KB)
—
4.8
7.6
55
s
TPABT
Program Abort Latency
—
—
10
10
μs
TEABT
Erase Abort Latency
—
—
30
30
μs
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
43
Electrical characteristics
Table 23. Code flash program and erase specifications1
Symbol
1
2
3
4
5
6
Parameter
Typical
Min Value
Value2
(0 Cycles)
Initial
Max4
Max3
(100000
(100
Cycles)
Cycles)
Unit
TEABT
Erase Suspend Latency
—
—
30
30
μs
TEABT
Erase Suspend Request Rate
10
—
—
—
ms
NER
Endurance (8KB, 16KB sectors)
Endurance (32KB, 64KB sectors)
Endurance (128KB sectors)
100
10
1
—
—
—
Kcycles
TDR
Data Retention at 1K cycles
Data Retention at 10K cycles
Data Retention at 100K cycles
20
10
5
—
—
—
Years
TBC = To be confirmed
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
The maximum program & erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
Actual hardware programming times. This does not include software overhead.
Typical Bank programming time assumes that all cells are programmed in a single pulse. In reality some cells will
require more than one pulse, adding a small overhead to total bank programming time (see Initial Max column).
Table 24. Data flash program and erase specifications1
Symbol
1
2
Parameter
Typical
Min Value
Value2
(0 Cycles)
Initial
Max4
Max3
(100000
(100
Cycles)
Cycles)
Unit
TDWPRG
Word Program5
—
30
TBC
TBC
μs
TBKPRG
Bank Program (64 KB)5, 6
—
0.49
TBC
TBC
s
TER16K
Sector Erase (16KB)
—
0.7
TBC
TBC
s
TER512K
Bank Erase (64KB)
—
1.9
TBC
TBC
s
TPABT
Program Abort Latency
—
—
12
12
μs
TEABT
Erase Abort Latency
—
—
30
30
μs
TEABT
Erase Suspend Latency
—
—
30
30
μs
TEABT
Erase Suspend Request Rate
10
—
—
—
ms
NER
Endurance (16KB sectors)
100
—
—
—
K cycles
TDR
Data Retention at 1K cycles
Data Retention at 10K cycles
Data Retention at 100K cycles
20
10
1
—
—
—
Years
@85C
TBC = To be confirmed
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
44
Freescale Semiconductor
Electrical characteristics
3
Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
The maximum program & erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
5
Actual hardware programming times. This does not include software overhead.
6
Typical Bank programming time assumes that all cells are programmed in a single pulse. In reality some cells will
require more than one pulse, adding a small overhead to total bank programming time (see Initial Max column).
4
Table 25. Flash read access timing
Symbol
Fmax
Fmax
1
C
Parameter
Maximum working frequency for Code Flash at
C given number of WS in worst conditions
C
Maximum working frequency for Data Flash at
given number of WS in worst conditions
Conditions1
Max
2 wait states
66
0 wait states
18
8 wait states
66
Unit
MHz
MHz
VDD_HV = 3.3 V ± 10%, TA = –40 to 125 °C, unless otherwise specified
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
45
Electrical characteristics
3.17
3.17.1
AC specifications
Pad AC specifications
Table 26 gives the AC electrical characteristics at 3.3 V (3.0 V < VDD_HV_IO < 3.6 V) operation.
Table 26. Pad AC specifications (3.3 V, INVUSRO[PAD3V5V] = 1)
Symbol
Parameter
Pad
Tswitchon
tr/tf
Propagation delay from
vdd/2 of internal signal
to Pchannel / Nchannel
switch on condition
Slope at rising/falling
edge
Slow
Freq
Current
Slew
Frequency
of
Operation
Slew rate at rising edge
of current
Load
drive
(pF)
Rise/Fall1
(ns)
Unit
Min
Typ
Max
25
3
—
40
ns
50
3
—
40
ns
100
3
—
40
ns
200
3
—
40
ns
25
4
—
40
ns
50
6
—
50
ns
100
10
—
75
ns
200
14
—
100
ns
25
—
—
4
MHz
50
—
—
2
MHz
100
—
—
2
MHz
200
—
—
2
MHz
25
0.01
—
2
mA/ns
50
0.01
—
2
mA/ns
100
0.01
—
2
mA/ns
200
0.01
—
2
mA/ns
MPC5604E Microcontroller Data Sheet, Rev. 5.1
46
Freescale Semiconductor
Electrical characteristics
Table 26. Pad AC specifications (3.3 V, INVUSRO[PAD3V5V] = 1)
Symbol
Parameter
Pad
Tswitchon
tr/tf
Propagation delay from
vdd/2 of internal signal
to Pchannel / Nchannel
switch on condition
Slope at rising/falling
edge
Medium
Freq
Current
Slew
Tswitchon
tr/tf
Frequency
of
Operation
Slew rate at rising edge
of current
Propagation delay from
vdd/2 of internal signal
to Pchannel / Nchannel
switch on condition
Slope at rising/falling
edge
Fast
Freq
Current
Slew
Frequency
of
Operation
Slew rate at rising edge
of current
Load
drive
(pF)
Rise/Fall1
(ns)
Unit
Min
Typ
Max
25
1
—
15
ns
50
1
—
15
ns
100
1
—
15
ns
200
1
—
15
ns
25
2
—
12
ns
50
4
—
25
ns
100
8
—
40
ns
200
14
—
70
ns
25
—
—
40
MHz
50
—
—
20
MHz
100
—
—
13
MHz
200
—
—
7
MHz
25
2.5
—
7
mA/ns
50
2.5
—
7
mA/ns
100
2.5
—
7
mA/ns
200
2.5
—
7
mA/ns
25
1
—
6
ns
50
1
—
6
ns
100
1
—
6
ns
200
1
—
6
ns
25
1
—
4
ns
50
1.5
—
7
ns
100
3
—
12
ns
200
5
—
18
ns
25
—
—
72
MHz
50
—
—
55
MHz
100
—
—
40
MHz
200
—
—
25
MHz
25
3
—
40
mA/ns
50
3
—
40
mA/ns
100
3
—
40
mA/ns
200
3
40
mA/ns
—
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
47
Electrical characteristics
Table 26. Pad AC specifications (3.3 V, INVUSRO[PAD3V5V] = 1)
Symbol
Load
drive
(pF)
Parameter
Pad
Min
Typ
Max
25
1
—
8
ns
tr/tf
Slope at rising/falling
edge
25
1
—
5
ns
TRise/TFall
Delay at rising/falling
edge
25
3
—
12
ns
|TRise - TFall
Delay between rising and
falling edge
25
0.05
—
1
ns
Frequency
of
Operation
25
—
—
50
MHz
Slew rate at rising edge
of current
25
3
—
25
mA/ns
Freq
Current
Slew
1
Unit
Propagation delay from
vdd/2 of internal signal
to Pchannel / Nchannel
switch on condition
Tswitchon
Symmetric
Rise/Fall1
(ns)
Slope at rising/falling edge
VDD_HV_IO/2
Pad
Data Input
Rising
Edge
Output
Delay
Falling
Edge
Output
Delay
VOH
VOL
Pad
Output
Figure 13. Pad output delay
MPC5604E Microcontroller Data Sheet, Rev. 5.1
48
Freescale Semiconductor
Electrical characteristics
3.18
AC timing characteristics
3.18.1
Generic timing diagrams
The generic timing diagrams in Figure 14 and Figure 15 apply to all I/O pins with pad types fast, slow and medium. See
Section 2.2, “Signal descriptions” for the pad type for each pin.
CLKOUT
VDD_HV_IOx/2
A
B
I/O OUTPUTS
VDD_HV_IOx/2
A—Maximum output delay time
B—Minimum output hold time
Figure 14. Generic output delay/hold timing
CLKOUT
VDD_HV_IOx/2
B
A
I/O INPUTS
VDD_HV_IOx/2
A—Minimum input setup time
B—Minimum input hold time
Figure 15. Generic Input setup/hold timing
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
49
Electrical characteristics
3.18.2
RESET pin characteristics
The MPC5604E implements a dedicated bidirectional RESET pin.
Figure 16. Start-up reset requirements
VDD
VDDMIN
RESET
VIH
VIL
device reset forced by RESET
device start-up phase
Figure 17. Noise filtering on reset signal
VRESET
hw_rst
VDD
‘1’
VIH
VIL
‘0’
filtered by
hysteresis
filtered by
lowpass filter
WFRST
filtered by
lowpass filter
unknown reset
state
device under hardware reset
WFRST
WNFRST
MPC5604E Microcontroller Data Sheet, Rev. 5.1
50
Freescale Semiconductor
Electrical characteristics
Table 27. RESET electrical characteristics
Symbol
C
Value2
Conditions1
Parameter
Unit
Min
Typ
Max
VIH
SR P
Input High Level CMOS
(Schmitt Trigger)
—
0.65VDD
—
VDD+0.4
V
VIL
SR P
Input low Level CMOS
(Schmitt Trigger)
—
−0.4
—
0.35VDD
V
VHYS
CC C
Input hysteresis CMOS
(Schmitt Trigger)
—
0.1VDD
—
—
V
VOL
CC P Output low level
Push Pull, IOL = 3 mA,
—
—
0.1VDD
V
CL = 25 pF,
VDD = 3.3 V ± 10%
—
—
12
CL = 50 pF,
VDD = 3.3 V ± 10%
—
—
25
CL = 100 pF,
VDD = 3.3 V ± 10%
—
—
40
Output transition time
output pin3
MEDIUM configuration
Ttr
CC D
ns
WFRST SR P
RESET input filtered
pulse
—
—
—
40
ns
WNFRST SR P
RESET input not filtered
pulse
—
500
—
—
ns
VDD = 3.3 V ± 10%
10
—
150
µA
|IWPU| CC P
Weak pull-up current
absolute value
1
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified
All values need to be confirmed during device validation.
3 C includes device and package capacitance (C
L
PKG < 5 pF).
2
3.18.3
Nexus and JTAG timing
Table 28. Nexus debug port timing1
Value
No.
Symbol
C
Parameter
Unit
Min
Typ
Max
1
tMCYC
CC D MCKO Cycle Time
2
—
8
tCYC
2A
tMCYCP
CC D MCKO cycle period
15
—
—
ns
2B
tMDC
CC D
52
%
3
tMDOV
CC D MCKO low to MDO data valid2
MCKO duty cycle
48
—
–0.1
—
0.22
tMCYC
valid2
–0.1
—
0.22
tMCYC
–0.1
—
0.22
tMCYC
4
tMSEOV
CC D MCKO low to MSEO data
5
tEVTOV
CC D MCKO low to EVTO data valid2
6
tTCYC
CC D TCK cycle time
50
—
—
ns
7
tTDC
CC D TCK Duty Cycle
40
—
60
%
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
51
Electrical characteristics
Table 28. Nexus debug port timing1 (continued)
Value
No.
8
9
1
2
Symbol
C
Parameter
Unit
Min
Typ
Max
tNTDIS
CC D TDI data setup time
0.2
—
—
tTCYC
tNTMSS
CC D TMS data setup time
0.2
—
—
tTCYC
tNTDIH
CC D TDI data hold time
0.1
—
—
tTCYC
tNTMSH
CC D TMS data hold time
0.1
—
—
tTCYC
10
tTDOV
CC D TCK low to TDO data valid
—
—
25
ns
11
tTDOV
CC D TCK low to TDO data invalid
0.1
—
—
tTCYC
All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal.
MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
2A
2B
MCKO
3
4
5
MDO
MSEO
EVTO
Output Data Valid
Figure 18. Nexus output timing
7
TCK
6
Figure 19. Nexus event trigger and test clock timings
MPC5604E Microcontroller Data Sheet, Rev. 5.1
52
Freescale Semiconductor
Electrical characteristics
TCK
8
9
TMS, TDI
10
11
TDO
Figure 20. Nexus TDI, TMS, TDO Timing
3.18.4
GPIO timing
The GPIO specifications for setup time and output valid relative to CLKOUT are the same for all pins on the device regardless
of the primary pin function.
Table 29. GPIO Timing
No.
Symbol
1
tREAD
2
tWRITE
Characteristic
GPIO Read Time
GPIO Write Time
Min.
Max.
Unit
5
—
tCYC
6
—
tCYC
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
53
Electrical characteristics
3.18.5
External interrupt timing (IRQ pin)
Table 30. External interrupt timing1
No.
Symbol
C
Parameter
Conditions
Min
Max Unit
1
tIPWL
CC
D
IRQ pulse width low
—
4
—
tCYC
2
tIPWH
CC
D
IRQ pulse width high
—
4
—
tCYC
3
tICYC
CC
D
IRQ edge to edge time2
—
4+N3
—
tCYC
1
IRQ timing specified at fSYS = 64 MHz and VDD_HV_IOx = 3.0 V, TA = TL to TH, and CL = 200 pF with SRC = 0b00.
Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
3 N = ISR time to clear the flag
2
IRQ
1
2
3
Figure 21. External interrupt timing
3.18.6
FlexCAN timing
Table 31. FlexCAN timing1
1
Num
Characteristic
Symbol
Min. Value Max. Value
Unit
1
CTNX Output Valid after CLKOUT Rising Edge (Output Delay)
tCANOV
—
26.0
ns
2
CNRX Input Valid to CLKOUT Rising Edge (Setup Time)
tCANSU
—
9.8
ns
FlexCAN timing specified at fSYS = 64 MHz, VDD = 1.35 V to 1.65 V, VDDEH = 3.0 V to 5.5 V, VRC33 and
VDDPLL = 3.0 V to 3.6 V, TA = TL to TH, and CL = 50 pF with SRC = 0b00.
3.18.7
LINFlex timing
Minimum design target for interface frequency is 2 MBit/s.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
54
Freescale Semiconductor
Electrical characteristics
3.18.8
DSPI timing
Table 32. DSPI timing
No.
1
Symbol
tSCK
CC
C
D
Parameter
DSPI cycle time
Conditions
Min
Max
Master (MTFE = 0)
62.5
—
Slave (MTFE = 0)
128
—
31.25
—
Master (MTFE = 1,CPHA=1)
ns
2
tCSC
CC
D
CS to SCK delay
—
16
—
ns
3
tASC
CC
D
After SCK delay
—
16
—
ns
4
tSDC
CC
D
SCK duty cycle
—
5
tA
CC
D
Slave access time
SS active to SOUT valid
—
40
ns
6
tDIS
CC
D
Slave SOUT disable time
SS inactive to SOUT High-Z or
invalid
—
10
ns
7
tPCSC CC
D
PCSx to PCSS time
—
13
—
ns
8
tPASC CC
D
PCSS to PCSx time
—
13
—
ns
Master (MTFE = 0)
12
—
Slave
2
—
9
10
11
12
tSUI
tHI
tSUO
tHO
CC
D
0.4 * tSCK 0.6 * tSCK
Data setup time for inputs
CC
D
Master (MTFE = 1, CPHA = 1)
12
—
Master (MTFE = 0)
–5
—
Slave
4
—
Data hold time for inputs
CC
D
Master (MTFE = 1, CPHA = 1)
–5
—
Master (MTFE = 0)
—
4
Slave
—
33
Data valid (after SCK edge)
D
ns
NA1
Master (MTFE = 1, CPHA = 0)
CC
ns
NA1
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
—
11
Master (MTFE = 0)
–2
—
Slave
6
—
Data hold time for outputs
ns
NA1
Master (MTFE = 1, CPHA = 0)
–2
ns
ns
NA1
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
1
Unit
—
This mode is not feasible at 32 MHz.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
55
Electrical characteristics
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
10
9
SIN
First Data
Last Data
Data
12
SOUT
First Data
11
Data
Last Data
Figure 22. DSPI classic SPI timing — Master, CPHA = 0
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
SIN
Data
First Data
12
SOUT
First Data
Last Data
11
Data
Last Data
Figure 23. DSPI classic SPI timing — Master, CPHA = 1
MPC5604E Microcontroller Data Sheet, Rev. 5.1
56
Freescale Semiconductor
Electrical characteristics
3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
First Data
SOUT
9
6
Data
Last Data
Data
Last Data
10
First Data
SIN
11
12
Figure 24. DSPI classic SPI timing — Slave, CPHA = 0
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
12
SOUT
First Data
9
SIN
Data
Last Data
Data
Last Data
6
10
First Data
Figure 25. DSPI classic SPI timing — Slave, CPHA = 1
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
57
Electrical characteristics
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
SIN
10
First Data
Last Data
Data
12
SOUT
11
First Data
Last Data
Data
Figure 26. DSPI modified transfer format timing — Master, CPHA = 0
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
First Data
Data
12
SOUT
First Data
Data
Last Data
11
Last Data
Figure 27. DSPI modified transfer format timing — Master, CPHA = 1
MPC5604E Microcontroller Data Sheet, Rev. 5.1
58
Freescale Semiconductor
Electrical characteristics
3
2
SS
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
First Data
SOUT
Data
6
Last Data
10
9
Data
First Data
SIN
12
11
5
Last Data
Figure 28. DSPI modified transfer format timing — Slave, CPHA = 0
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
12
First Data
SOUT
9
SIN
Data
Last Data
Data
Last Data
6
10
First Data
Figure 29. DSPI modified transfer format timing — Slave, CPHA = 1
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
59
Electrical characteristics
8
7
PCSS
PCSx
Figure 30. DSPI PCS Strobe (PCSS) timing
3.18.9
Video interface timing
Table 33 details the MPC5604E’s video encoder block’s pixel input clocking requirement.
Table 33. Input pixel clock characteristics
No.
Parameter
Min
Max
Unit
1
PDI Clock Period
10
—
ns
2
PDI Clock Duty Cycle
50
50
%
3
Input setup time
2
—
ns
4
Input Hold Time
2
—
ns
5
Input Pixel Clock Slew Rate
—
2
ns
VCLKIN
1
3
4
VID_DATA[15:0]
VID_LINE_V
Input Data Valid
VID_FRAME_V
Figure 31. Video interface timing
MPC5604E Microcontroller Data Sheet, Rev. 5.1
60
Freescale Semiconductor
Electrical characteristics
3.18.10 Fast ethernet interface
MII signals use CMOS signal levels compatible with devices operating at either 5.0 V or 3.3 V. Signals are not TTL compatible.
They follow the CMOS electrical characteristics.
3.18.10.1 MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. In addition, the system clock frequency must exceed four times the RX_CLK frequency.
Table 34. MII receive signal timing
No.
Parameter
Min
Max
Unit
1
Rx Clock Period
40
—
ns
2
RXD[3:0], RX_DV, RX_ER to RX_CLK setup
5
—
ns
3
RX_CLK to RXD[3:0], RX_DV, RX_ER hold
5
—
ns
4
Rx Clock Duty Cycle
40
60
%
4
RX_CLK (input)
1
RXD[3:0] (inputs)
RX_DV
RX_ER
2
3
Figure 32. MII receive signal timing diagram
3.18.10.2 MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. In addition, the system clock frequency must exceed four times the TX_CLK frequency.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of
TX_CLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs.
Refer to the Ethernet chapter for details of this option and how to enable it.
Table 35. MII transmit signal timing1
No.
1
Parameter
Min
Max
Unit
5
TX Clock Period
40
—
ns
6
TX_CLK to TXD[3:0], TX_EN, TX_ER invalid
5
—
ns
7
TX_CLK to TXD[3:0], TX_EN, TX_ER valid
—
25
ns
8
TX Clock Duty Cycle
40
60
%
Output pads configured with SRC = 0b11.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
61
Electrical characteristics
TX_CLK (input)
6
TXD[3:0] (outputs)
TX_EN
TX_ER
7
Figure 33. MII transmit signal timing diagram
3.18.10.3 MII async inputs signal timing (CRS and COL)
Table 36. MII async inputs signal timing1
No.
9
1
Parameter
Min
Max
Unit
1.5
—
TX_CLK period
CRS, COL minimum pulse width
Output pads configured with SRC = 0b11.
CRS, COL
9
Figure 34. MII async inputs timing diagram
3.18.10.4 MII serial management channel timing (MDIO and MDC)
The FEC functions correctly with a maximum MDC frequency of 5 MHz.
Table 37. MII serial management channel timing (MDIO and MDC)
No.
Parameter
Min
Max
Unit
1
MDIO Input delay setup
28
—
ns
2
MDIO Input delay hold
0
—
ns
3
MDIO Output delay valid
—
25
ns
4
MDIO Output delay Invalid
0
—
ns
5
MDC clock period
100
—
ns
6
MDC Duty Cycle
40
60
%
MPC5604E Microcontroller Data Sheet, Rev. 5.1
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Freescale Semiconductor
Electrical characteristics
3.18.11 I2C timing
Table 38. I2C SCL and SDA input timing specifications
Value
No.
1
Symbol
Parameter
Unit
Min
Max
1
—
D Start condition hold time
2
—
IP bus cycle1
2
—
D Clock low time
8
—
IP bus cycle1
4
—
D Data hold time
0.0
—
ns
6
—
D Clock high time
4
—
IP bus cycle1
7
—
D Data setup time
0.0
—
ns
8
—
D Start condition setup time (for repeated start condition only)
2
—
IP bus cycle1
9
—
D Stop condition setup time
2
—
IP bus cycle1
Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device. It is equal to the system clock
(Sys_clk).
Table 35. I2C SCL and SDA output timing specifications
Value
No.
Symbol
Parameter
Unit
Min Max
11
—
D Start condition hold time
6
—
IP bus cycle2
21
—
D Clock low time
10
—
IP bus cycle1
33
—
D SCL/SDA rise time
—
99.6
ns
41
—
D Data hold time
7
—
IP bus cycle1
51
—
D SCL/SDA fall time
—
99.5
ns
1
6
—
D Clock high time
10
—
IP bus cycle1
71
—
D Data setup time
2
—
IP bus cycle1
81
—
D Start condition setup time (for repeated start condition only)
20
—
IP bus cycle1
91
—
D Stop condition setup time
10
—
IP bus cycle1
1
Programming IBFD (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings
listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period.
The actual position is affected by the prescale and division values programmed in IFDR.
2 Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device.
3 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL
or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
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63
Electrical characteristics
2
5
6
SCL
3
1
8
7
4
9
SDA
Figure 36. I2C input/output timing
3.18.12 SAI timing
All timing requirements are specified relative to the clock period or to the minimum allowed clock period of a device.
Table 39. Master Mode SAI Timing
Value
No.
Parameter
Unit
Min
Max
Operating voltage
2.7
3.6
S1
SAI_MCLK cycle time
40
—
S2
SAI_MCLK pulse width high/low
45%
55%
S3
SAI_BCLK cycle time
80
—
S4
SAI_BCLK pulse width high/low
45%
55%
S5
SAI_BCLK to SAI_FS output valid
—
15
S6
SAI_BCLK to SAI_FS output invalid
0
—
S7
SAI_BCLK to SAI_TXD valid
—
15
S8
SAI_BCLK to SAI_TXD invalid
0
—
ns
S9
SAI_RXD/SAI_FS input setup before SAI_BCLK 28
—
ns
S10
SAI_RXD/SAI_FS input hold after SAI_BCLK
—
ns
0
V
ns
MCLK period
BCLK period
ns
ns
ns
ns
MPC5604E Microcontroller Data Sheet, Rev. 5.1
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Freescale Semiconductor
Electrical characteristics
Figure 37. SAI timing master modes
Table 40. Slave Mode SAI Timing
Value
No.
Parameter
Unit
Min
Max
Operating voltage
2.7
3.6
S11
SAI_BCLK cycle time (input)
80
—
S12
SAI_BCLK pulse width high/low (input)
45%
55%
S13
SAI_FS input setup before SAI_BCLK
10
—
S14
SAI_FS input hold after SAI_BCLK
2
—
S15
SAI_BCLK to SAI_TXD/SAI_FS output valid
—
28
S16
SAI_BCLK to SAI_TXD/SAI_FS output invalid
0
—
S17
SAI_RXD setup before SAI_BCLK
10
—
S18
SAI_RXD hold after SAI_BCLK
2
—
V
ns
BCLK period
ns
ns
ns
ns
ns
ns
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
65
Electrical characteristics
Figure 38. SAI timing slave modes
MPC5604E Microcontroller Data Sheet, Rev. 5.1
66
Freescale Semiconductor
Package mechanical data
4
Package mechanical data
4.1
100 LQFP mechanical outline drawing
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
67
Package mechanical data
Figure 39. 100 LQFP package mechanical drawing (part 1)
MPC5604E Microcontroller Data Sheet, Rev. 5.1
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Freescale Semiconductor
Package mechanical data
Figure 40. 100 LQFP package mechanical drawing (part 2)
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
69
Package mechanical data
Figure 41. 100 LQFP package mechanical drawing (part 3)
MPC5604E Microcontroller Data Sheet, Rev. 5.1
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Freescale Semiconductor
Package mechanical data
4.2
64 LQFP mechanical outline drawing
Figure 42. 64 LQFP package mechanical drawing (part 1)
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
71
Package mechanical data
Figure 43. 64LQFP package mechanical drawing (part 2)
MPC5604E Microcontroller Data Sheet, Rev. 5.1
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Package mechanical data
Figure 44. 64LQFP package mechanical drawing (part 3)
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
73
Ordering information
5
Ordering information
MPC 56
0
4
E
E F1 M LH R
Qualification status
Automotive platform (56 = Power architecture in 90 nm)
Core version (0 = e200z0h)
Config
Product (E = Family)
EEPROM (E = Data Flash)
Optional fields
Temperature spec
Package code (LH = 64LQFP)
Tape and Reel (R = Tape and reel)
Qualification status
Config
4 = SAI + ENET + MJPEG
3 = SAI + ENET
M = MC status
S = Auto qualified
P = PC status
Optional fields
F = ATMC
1 = Maskset revision 1
2 = Maskset revision 2
Tempearture spec
C = - 40 to 85 oC
V = - 40 to 105 oC
M = - 40 to 125 oC
Figure 45. Commercial product code structure
Table 5-41. Orderable part number summary
Part number1
Flash/SRAM Package
Speed
SPC5604EEF1MLH and SPC5604EEF1MLHR
Key Features
SAI + ENET + MJPEG
512K / 96K
64 LQFP
64 MHz
SPC5603EEF1MLH and SPC5603EEF1MLHR
1
SAI + ENET
All packaged devices are PPC, rather than MPC or SPC, until product qualifications are complete.
The unpackaged device prefix is PCC, rather than SCC, until product qualification is complete.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
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Document revision history
6
Document revision history
Table 42. Revision history
Revision
Date
1
15 Feb 2011
Initial Release
13 June 2011
• In the Recommended operating conditions table, changed the external supply voltage changed
from 1.14 V to 1.15 V
• Added a footnote in the Device Summary table
• Changed the description of VDD_HV_S_BALLAST0 in the Supply pins table
1 Nov 2011
• Editorial changes and improvements
• In the Low voltage monitor electrical characteristics table, changed the marking of VPORUP from
P to D
• In the DC electrical characteristics table, changed the IOL of the Medium, low level output
voltage to 2 mA. From the same table, removed VOL_SYM and VOH_SYM. Revised the IPU and IPD
• In the Main oscillator electrical characteristics table, changed the minimum value of
transconductance to 4 mA/V
• In the 16 MHz RC oscillator electrical characteristics table, changed the marking of fRC from P
to C and revised its minimum and value.
• In the ADC conversion characteristics table, changed the minimum and maximum value of TUE
from TBD to -3 and 3
• In the Pin muxing table, C5 port ABS[2] assignment changed from SIUL to MC_RGM
• IRevised the 64-pin and 100-pin package pinouts and added a footnote.
• In the Supply pins table, revised the description of ADC0 pins
• In the Supply pins table, added a column Port Pin and renamed the Symbol column
• IRemoved Power Supply segment table
• In the Pin Muxing table, clarified the peripherals in the following port pins: C5, A3, A8, A10, A12,
A15, C3, C4, C5, C6, C12
• In the Low voltage monitor electrical characteristics table, changed the maximum value of
VMLVDDOK_H
• In the ADC conversion characteristics, changed the ADC sampling time to 500 ns
3.1
2 Dec 2011
• Inserted values for TBDs in the table EMI Testing Specifications
• From Supply Pins table, removed VVD_HV_ADV0
• In the PLLMRFM electrical specifications table, added the value of Self-clocked mode
frequency
• In the ADC conversion characteristics table, added the value of INJ
4
23 Jan 2012
• System Pin table, swapped the description of XTAL and EXTAL
03 Feb 2015
On the first page:
• added 32 external interrupts for 100-pin LQFP and updated 22 external interrupts for 64-pin
LQFP.
• changed "8 input channels" to "7 input channels".
• changed "4 internal connection..." to "3 internal connection...".
• Removed “1 x VGate Current”.
• In Table 1., “Device summary”, removed VGate current from the equation for ADC (10-bit).
• In Figure 1., “MPC5604E block diagram”: changed "4+4 channels" to "4+3 channels".
• Updated Table 2., “Supply pins”.
• In Table 4., “Pin muxing”, function of port pins B4, B13, B14, B15, C0, C1, C9, C15, D8, D13,
D14, and E2 changed from GPIO to GPI.
• Added new section - Section 5, “Ordering information”.
• In Figure 2., “64-pin LQFP pinout (top view)”, changed VSS (pin 47) to VSS_HV.
• In Figure 3., “100-pin LQFP pinout (top view)”, changed VSS (pin 74) to VSS_HV.
• Updated “optional fields” entries in Figure 45., “Commercial product code structure”.
2
3
5
Substantive changes
MPC5604E Microcontroller Data Sheet, Rev. 5.1
Freescale Semiconductor
75
Document revision history
Table 42. Revision history (continued)
Revision
Date
5.1
16 Feb 2016
Substantive changes
• Changed the DS document from Advanced Information to Technical Data
• Updated Figure 45., “Commercial product code structure” and Table 5-41., “Orderable part
number summary”.
MPC5604E Microcontroller Data Sheet, Rev. 5.1
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Freescale Semiconductor
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Document Number: MPC5604E
Rev. 5.1
Feb 2016