MPC5604E Microcontroller
Reference Manual
Devices Supported:
MPC5604E
MPC5604ERM
Rev. 5
07/2015
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
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MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
Chapter 1
Overview
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Chipset overview ...............................................................................................................................9
Target applications ..........................................................................................................................10
Features ...........................................................................................................................................10
Block diagram .................................................................................................................................11
Application examples ......................................................................................................................13
1.5.1 CMOS vision sensor gateway ...........................................................................................13
Audio source gateway .....................................................................................................................16
Critical performance parameters .....................................................................................................18
Chip-level features ..........................................................................................................................18
1.8.1 High performance e200z0 core CPU ................................................................................19
1.8.2 Crossbar switch (XBAR) ..................................................................................................20
1.8.3 System clocks and clock generation .................................................................................20
1.8.4 Frequency Modulated Phase Lock Loop (FMPLL) ..........................................................21
1.8.5 Main oscillator ..................................................................................................................21
1.8.6 Internal RC oscillator ........................................................................................................21
1.8.7 Voltage regulator (VREG) ................................................................................................22
1.8.8 System Integration Unit (SIU-Lite) ..................................................................................22
1.8.9 Boot Assist Module (BAM) ..............................................................................................22
1.8.10 Junction temperature sensor ..............................................................................................23
1.8.11 JTAG controller (JTAGC) .................................................................................................23
1.8.12 Nexus Debug Interface (NDI) ...........................................................................................24
1.8.13 DMA controller .................................................................................................................24
1.8.14 DMA channel multiplexer (DMA_MUX) ........................................................................25
1.8.15 Software Watchdog Timer (SWT) ....................................................................................25
1.8.16 System Timer Module (STM) ...........................................................................................25
1.8.17 Periodic Interrupt Timers (PIT) ........................................................................................26
1.8.18 FlexCAN module ..............................................................................................................26
1.8.19 Deserial Serial Peripheral Interface (DSPI) ......................................................................27
1.8.20 Serial communication interface module (LINFlex) ..........................................................27
1.8.21 eTimer ...............................................................................................................................28
1.8.22 Successive approximation Analog-to-Digital Converter (ADC) ......................................29
1.8.23 Fault Collection Unit (FCU) .............................................................................................30
1.8.24 Cyclic Redundancy Check (CRC) ....................................................................................30
1.8.25 Video encoder ...................................................................................................................30
1.8.26 Serial Audio Interface (SAI) .............................................................................................30
1.8.27 Ethernet AVB (FEC + PTP + RTC) ..................................................................................31
1.8.27.1 Precision Time Protocol ..................................................................................31
1.8.27.2 RTC .................................................................................................................32
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Chapter 2
Memory Map
Chapter 3
Signal Description
3.1
3.2
3.3
3.4
3.5
Introduction .....................................................................................................................................37
Signal Properties Summary .............................................................................................................37
Supply pins ......................................................................................................................................47
System pins .....................................................................................................................................49
Pinouts .............................................................................................................................................50
Chapter 4
Clock Architecture
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Clock related modules .....................................................................................................................53
High-level block diagrams ..............................................................................................................53
Memory Map ...................................................................................................................................59
Internal RC oscillator (IRC) digital interface ..................................................................................61
4.4.1 Introduction .......................................................................................................................61
4.4.2 Functional description .......................................................................................................61
4.4.3 Register description ..........................................................................................................62
External crystal oscillator (XOSC) digital interface .......................................................................63
4.5.1 Main features ....................................................................................................................63
4.5.2 Functional description .......................................................................................................63
4.5.3 Register description ..........................................................................................................64
Frequency-modulated phase-locked loop (FMPLL) .......................................................................65
4.6.1 Introduction .......................................................................................................................65
4.6.2 Overview ...........................................................................................................................65
4.6.3 Features .............................................................................................................................66
4.6.4 Memory map .....................................................................................................................66
4.6.5 Register description ..........................................................................................................67
4.6.5.1 Control Register (CR) .....................................................................................67
4.6.5.2 Modulation Register (MR) ..............................................................................69
4.6.6 Functional description .......................................................................................................70
4.6.6.1 Normal mode ..................................................................................................70
4.6.6.2 Progressive clock switching ............................................................................71
4.6.6.3 Normal mode with frequency modulation ......................................................71
4.6.6.4 Powerdown mode ...........................................................................................72
4.6.7 Recommendations .............................................................................................................72
Clock Monitor Unit (CMU) ............................................................................................................73
4.7.1 Overview ...........................................................................................................................73
4.7.2 Main features ....................................................................................................................73
4.7.3 Functional description .......................................................................................................73
4.7.4 Crystal clock monitor ........................................................................................................74
4.7.4.1 FMPLL clock monitor ....................................................................................74
4.7.4.2 Frequency meter .............................................................................................74
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4.7.5
4.8
4.9
Memory map and register description ..............................................................................75
4.7.5.1 Control status register (CMU_CSR) ...............................................................76
4.7.5.2 Frequency display register (CMU_FDR) .......................................................77
4.7.5.3 High-frequency reference register A (CMU_HFREFR_A) ............................77
4.7.5.4 Low-frequency reference register A (CMU_LFREFR_A) .............................78
4.7.5.5 Interrupt status register (CMU_ISR) ..............................................................78
4.7.5.6 Measurement duration register (CMU_MDR) ...............................................79
Boot and power management concept ............................................................................................79
Safety concept .................................................................................................................................81
Chapter 5
Clock Generation Module (MC_CGM)
5.1
5.2
5.3
5.4
Introduction .....................................................................................................................................83
5.1.1 Overview ...........................................................................................................................83
5.1.2 Features .............................................................................................................................84
External Signal Description ............................................................................................................85
Memory Map and Register Definition ............................................................................................85
5.3.1 Register Descriptions ........................................................................................................85
5.3.1.1 PLL Clock Divider Register (PLL_CLK_DIV) .............................................86
5.3.1.2 System Clock Divider Register (SYSTEM_CLK_DIV) ................................86
5.3.1.3 RTC Clock Divider Register (RTC_CLK_DIV) .............................................87
5.3.1.4 Output Clock Enable Register (CGM_OC_EN) .............................................87
5.3.1.5 Output Clock Division Select Register (CGM_OCDS_SC) ...........................88
5.3.1.6 System Clock Select Status Register (CGM_SC_SS) ....................................89
Functional Description ....................................................................................................................89
5.4.1 System Clock Generation .................................................................................................89
5.4.1.1 System Clock Source Selection ......................................................................90
5.4.1.2 System Clock Disable .....................................................................................90
5.4.2 Output Clock Multiplexing ...............................................................................................90
5.4.3 Output Clock Division Selection ......................................................................................91
Chapter 6
Mode Entry Module (MC_ME)
6.1
6.2
6.3
Introduction .....................................................................................................................................93
6.1.1 Overview ...........................................................................................................................93
6.1.2 Features .............................................................................................................................95
6.1.3 Modes of Operation ..........................................................................................................95
External Signal Description ............................................................................................................96
Memory Map and Register Definition ............................................................................................96
6.3.1 Memory Map ....................................................................................................................97
6.3.2 Register Description .......................................................................................................105
6.3.2.1 Global Status Register (ME_GS) ..................................................................105
6.3.2.2 Mode Control Register (ME_MCTL) ...........................................................107
6.3.2.3 Mode Enable Register (ME_ME) .................................................................108
6.3.2.4 Interrupt Status Register (ME_IS) ................................................................110
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6.4
6.3.2.5 Interrupt Mask Register (ME_IM) ................................................................111
6.3.2.6 Invalid Mode Transition Status Register (ME_IMTS) .................................112
6.3.2.7 Debug Mode Transition Status Register (ME_DMTS) ................................113
6.3.2.8 RESET Mode Configuration Register (ME_RESET_MC) ..........................116
6.3.2.9 TEST Mode Configuration Register (ME_TEST_MC) ...............................116
6.3.2.10 SAFE Mode Configuration Register (ME_SAFE_MC) ...............................117
6.3.2.11 DRUN Mode Configuration Register (ME_DRUN_MC) ............................117
6.3.2.12 RUN0..3 Mode Configuration Register (ME_RUN0..3_MC) ......................118
6.3.2.13 HALT0 Mode Configuration Register (ME_HALT0_MC) ..........................118
6.3.2.14 STOP0 Mode Configuration Register (ME_STOP0_MC) ...........................119
6.3.2.15 Peripheral Status Register 0 (ME_PS0) ........................................................121
6.3.2.16 Peripheral Status Register 1 (ME_PS1) ........................................................121
6.3.2.17 Peripheral Status Register 2 (ME_PS2) ........................................................122
6.3.2.18 Peripheral Status Register 3 (ME_PS3) ........................................................122
6.3.2.19 Run Peripheral Configuration Registers (ME_RUN_PC0…7) ....................123
6.3.2.20 Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) ............124
6.3.2.21 Peripheral Control Registers (ME_PCTLn) .................................................124
Functional Description ..................................................................................................................125
6.4.1 Mode Transition Request ................................................................................................125
6.4.2 Modes Details .................................................................................................................127
6.4.2.1 RESET MODE .............................................................................................127
6.4.2.2 DRUN Mode .................................................................................................127
6.4.2.3 SAFE Mode ..................................................................................................128
6.4.2.4 Test Mode ......................................................................................................129
6.4.2.5 RUN0..3 Modes ............................................................................................129
6.4.2.6 HALT0 Mode ................................................................................................130
6.4.2.7 STOP0 Mode ................................................................................................130
6.4.3 Mode Transition Process .................................................................................................131
6.4.3.1 Target Mode Request ....................................................................................131
6.4.3.2 Target Mode Configuration Loading ............................................................132
6.4.3.3 Peripheral Clocks Disable .............................................................................132
6.4.3.4 Processor Low-Power Mode Entry ...............................................................133
6.4.3.5 Processor and System Memory Clock Disable .............................................133
6.4.3.6 Clock Sources Switch-On .............................................................................133
6.4.3.7 Flash Modules Switch-On ............................................................................134
6.4.3.8 Pad Outputs-On .............................................................................................134
6.4.3.9 Peripheral Clocks Enable ..............................................................................134
6.4.3.10 Processor and Memory Clock Enable ...........................................................134
6.4.3.11 Processor Low-Power Mode Exit .................................................................134
6.4.3.12 System Clock Switching ...............................................................................135
6.4.3.13 Pad Switch-Off ..............................................................................................136
6.4.3.14 Clock Sources (with no Dependencies) Switch-Off .....................................136
6.4.3.15 Clock Sources (with Dependencies) Switch-Off ..........................................136
6.4.3.16 Flash Switch-Off ...........................................................................................136
6.4.3.17 Current Mode Update ...................................................................................136
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6.4.4 Protection of Mode Configuration Registers ..................................................................139
6.4.5 Mode Transition Interrupts .............................................................................................139
6.4.5.1 Invalid Mode Configuration Interrupt ..........................................................139
6.4.5.2 Invalid Mode Transition Interrupt .................................................................140
6.4.5.3 SAFE Mode Transition Interrupt ..................................................................141
6.4.5.4 Mode Transition Complete interrupt ............................................................141
6.4.6 Peripheral Clock Gating ..................................................................................................141
6.4.7 Application Example ......................................................................................................142
Chapter 7
Reset Generation Module (MC_RGM)
7.1
7.2
7.3
7.4
Introduction ...................................................................................................................................145
7.1.1 Overview .........................................................................................................................145
7.1.2 Features ...........................................................................................................................146
7.1.3 Reset Sources ..................................................................................................................147
External Signal Description ..........................................................................................................148
Memory Map and Register Definition ..........................................................................................148
7.3.1 Register Descriptions ......................................................................................................150
7.3.1.1 Functional Event Status Register (RGM_FES) ............................................151
7.3.1.2 Destructive Event Status Register (RGM_DES) ..........................................152
7.3.1.3 Functional Event Reset Disable Register (RGM_FERD) .............................153
7.3.1.4 Functional Event Alternate Request Register (RGM_FEAR) ......................155
7.3.1.5 Functional Event Short Sequence Register (RGM_FESS) ...........................156
7.3.1.6 Functional Bidirectional Reset Enable Register (RGM_FBRE) ..................157
Functional Description .................................................................................................................158
7.4.1 Reset State Machine ........................................................................................................158
7.4.1.1 PHASE0 Phase .............................................................................................160
7.4.1.2 PHASE1 Phase .............................................................................................161
7.4.1.3 PHASE2 Phase .............................................................................................161
7.4.1.4 PHASE3 Phase .............................................................................................161
7.4.1.5 IDLE Phase ...................................................................................................161
7.4.2 Destructive Resets ..........................................................................................................161
7.4.3 External Reset .................................................................................................................162
7.4.4 Functional Resets ............................................................................................................162
7.4.5
Alternate Event Generation .........................................................................................163
7.4.6 Boot Mode Capturing .....................................................................................................163
Chapter 8
Power Control Unit (MC_PCU)
8.1
8.2
8.3
Introduction ...................................................................................................................................165
8.1.1 Overview .........................................................................................................................165
8.1.2 Features ...........................................................................................................................166
External Signal Description ..........................................................................................................166
Memory Map and Register Definition .......................................................................................167
8.3.1 Memory Map ..................................................................................................................167
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8.3.2
Register Descriptions ......................................................................................................168
8.3.2.1 Power Domain Status Register (PCU_PSTAT) ...........................................168
Chapter 9
Power Management
9.1
9.2
9.3
Power management overview .......................................................................................................169
9.1.1 Internal voltage regulation mode ....................................................................................169
9.1.2 External voltage regulation mode ...................................................................................170
9.1.3 Voltage Regulator Electrical Characteristics ..................................................................171
Power sequencing ..........................................................................................................................171
Power Management Unit (PMU) ..................................................................................................172
Chapter 10
Interrupt Controller (INTC)
10.1
10.2
10.3
10.4
Introduction ...................................................................................................................................173
Features .........................................................................................................................................173
Block diagram ...............................................................................................................................174
Modes of operation ........................................................................................................................175
10.4.1 Normal mode ..................................................................................................................175
10.4.1.1 Software vector mode ...................................................................................175
10.4.1.2 Hardware vector mode ..................................................................................176
10.4.1.3 Debug mode ..................................................................................................176
10.4.1.4 Stop mode .....................................................................................................176
10.5 Memory map and registers description .........................................................................................177
10.5.1 Module memory map ......................................................................................................177
10.5.2 Registers description .......................................................................................................177
10.5.2.1 INTC Module Configuration Register (INTC_MCR) ..................................178
10.5.2.2 INTC Current Priority Register for Processor (INTC_CPR) ........................178
10.5.2.3 INTC Interrupt Acknowledge Register (INTC_IACKR) .............................180
10.5.2.4 INTC End-of-Interrupt Register (INTC_EOIR) ...........................................180
10.5.2.5 INTC Software Set/Clear Interrupt Registers
(INTC_SSCIR0_3–INTC_SSCIR4_7) .........................................................................181
10.5.2.6 INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR220_221) .......182
10.6 Functional description ...................................................................................................................184
10.6.1 Interrupt request sources .................................................................................................193
10.6.1.1 Peripheral interrupt requests .........................................................................193
10.6.1.2 Software configurable interrupt requests ......................................................193
10.6.1.3 Unique vector for each interrupt request source ...........................................193
10.6.2 Priority management .......................................................................................................193
10.6.2.1 Current priority and preemption ...................................................................193
10.6.2.1.1Priority arbitrator subblock .................................................................194
10.6.2.1.2Request selector subblock ...................................................................194
10.6.2.1.3Vector encoder subblock ....................................................................194
10.6.2.1.4Priority comparator subblock ..............................................................194
10.6.2.2 Last-in first-out (LIFO) .................................................................................194
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10.6.3 Handshaking with processor ...........................................................................................195
10.6.3.1 Software vector mode handshaking ..............................................................195
10.6.3.1.1Acknowledging interrupt request to processor
195
10.6.3.1.2End of interrupt exception handler .....................................................195
10.6.3.2 Hardware vector mode handshaking .............................................................196
10.7 Initialization/application information ............................................................................................197
10.7.1 Initialization flow ............................................................................................................197
10.7.2 Interrupt exception handler .............................................................................................197
10.7.2.1 Software vector mode ...................................................................................198
10.7.2.2 Hardware vector mode ..................................................................................198
10.7.3 ISR, RTOS, and task hierarchy .......................................................................................199
10.7.4 Order of execution ..........................................................................................................200
10.7.5 Priority ceiling protocol ..................................................................................................201
10.7.5.1 Elevating priority ..........................................................................................201
10.7.5.2 Ensuring coherency .......................................................................................201
10.7.6 Selecting priorities according to request rates and deadlines .........................................201
10.7.7 Software configurable interrupt requests ........................................................................202
10.7.7.1 Scheduling a lower priority portion of an ISR ..............................................202
10.7.7.2 Scheduling an ISR on another processor ......................................................203
10.7.8 Lowering priority within an ISR .....................................................................................203
10.7.9 Negating an interrupt request outside of its ISR .............................................................203
10.7.9.1 Negating an interrupt request as a side effect of an ISR ...............................203
10.7.9.2 Negating multiple interrupt requests in one ISR ..........................................203
10.7.9.3 Proper setting of interrupt request priority ...................................................204
10.7.10Examining LIFO contents ...............................................................................................204
Chapter 11
Wakeup Unit (WKPU)
11.1 Introduction ...................................................................................................................................205
11.1.1 Overview .........................................................................................................................205
11.1.2 Features ...........................................................................................................................205
11.2 External signal description ............................................................................................................206
11.3 Memory map and register description ...........................................................................................206
11.3.1 Memory map ...................................................................................................................206
11.3.2 Register descriptions .......................................................................................................206
11.3.2.1 NMI Status Flag Register (NSR) ..................................................................206
11.3.2.2 NMI Configuration Register (NCR) .............................................................207
11.4 Functional description ...................................................................................................................209
11.4.1 General ............................................................................................................................209
11.4.2 Non-Maskable Interrupts ................................................................................................209
11.4.2.1 NMI management .........................................................................................210
Chapter 12
System Status and Configuration Module (SSCM)
12.1 Introduction ...................................................................................................................................213
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12.2
12.3
12.4
12.5
12.1.1 Overview .........................................................................................................................213
12.1.2 Features ...........................................................................................................................213
12.1.3 Modes of Operation ........................................................................................................214
External Signal Description ..........................................................................................................214
Memory Map/Register Definition .................................................................................................214
12.3.1 Register Descriptions ......................................................................................................214
12.3.1.1 System Status Register ..................................................................................215
12.3.1.2 System Memory and ID Register ..................................................................216
12.3.1.3 Error Configuration .......................................................................................217
12.3.1.4 Debug Status Port Register ...........................................................................218
12.3.1.5 Primary Boot Address ...................................................................................220
Functional Description ..................................................................................................................220
Initialization/Application Information ..........................................................................................220
12.5.1 Reset ................................................................................................................................220
Chapter 13
System Integration Unit Lite (SIUL)
13.1
13.2
13.3
13.4
Introduction ...................................................................................................................................221
Overview .......................................................................................................................................221
Features .........................................................................................................................................222
External signal description ............................................................................................................223
13.4.1 Detailed signal descriptions ............................................................................................223
13.4.1.1 General-purpose I/O pins (GPIO[0:70]) .......................................................223
13.4.1.2 External interrupt request input pins (EIRQ[0:31]) ......................................223
13.5 Memory map and register description ...........................................................................................223
13.5.1 SIUL memory map .........................................................................................................224
13.5.2 Register protection ..........................................................................................................225
13.5.3 Register description ........................................................................................................225
13.5.3.1 MCU ID Register #1 (MIDR1) .....................................................................225
13.5.3.2 MCU ID Register #2 (MIDR2) .....................................................................227
13.5.3.3 Interrupt Status Flag Register (ISR) .............................................................228
13.5.3.4 Interrupt Request Enable Register (IRER) ...................................................228
13.5.3.5 Interrupt Rising-Edge Event Enable Register (IREER) ...............................229
13.5.3.6 Interrupt Falling-Edge Event Enable Register (IFEER) ...............................229
13.5.3.7 Interrupt Filter Enable Register (IFER) ........................................................230
13.5.3.8 Pad Configuration Registers (PCR[0:70]) ....................................................230
13.5.3.9 Pad Selection for Multiplexed Inputs Registers (PSMI0–PSMI25) .............232
13.5.3.10 GPIO Pad Data Output Registers (GPDO0_3–GPDO68_71) ......................235
13.5.3.11 GPIO Pad Data Input Registers (GPDI0_3–GPDI68_71) ............................236
13.5.3.12 Parallel GPIO Pad Data Out Registers (PGPDO0 – PGPDO2) ....................237
13.5.3.13 Parallel GPIO Pad Data In Register (PGPDI0 – PGPDI2) ...........................237
13.5.3.14 Masked Parallel GPIO Pad Data Out Register (MPGPDO0–MPGPDO4) ..238
13.5.3.15 Interrupt Filter Maximum Counter Registers (IFMC0–IFMC31) ................239
13.5.3.16 Interrupt Filter Clock Prescaler Register (IFCPR) .......................................240
13.6 Functional description ...................................................................................................................241
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13.6.1 Pad control ......................................................................................................................241
13.6.2 General purpose input and output pads (GPIO) ..............................................................241
13.6.3 External interrupts ...........................................................................................................242
13.7 Pin muxing ....................................................................................................................................243
Chapter 14
e200z0h Core
14.1 Overview .......................................................................................................................................245
14.2 Features .........................................................................................................................................245
14.2.1 Microarchitecture summary ............................................................................................246
14.2.1.1 Block diagram ...............................................................................................247
14.2.1.2 Instruction unit features ................................................................................248
14.2.1.3 Integer unit features ......................................................................................248
14.2.1.4 Load/Store unit features ................................................................................248
14.2.1.5 e200z0h system bus features .........................................................................248
14.2.1.6 Nexus features ...............................................................................................249
14.3 Core registers and programmer’s model .......................................................................................249
14.3.1 Unimplemented SPRs and read-only SPRs ....................................................................252
14.4 Instruction summary ......................................................................................................................252
Chapter 15
Crossbar Switch (XBAR)
15.1
15.2
15.3
15.4
15.5
Introduction ...................................................................................................................................253
Block diagram ...............................................................................................................................253
Overview .......................................................................................................................................254
Features .........................................................................................................................................254
Modes of operation ........................................................................................................................255
15.5.1 Normal mode ..................................................................................................................255
15.5.2 Debug mode ....................................................................................................................255
15.6 Functional description ...................................................................................................................255
15.6.1 Overview .........................................................................................................................255
15.6.2 General operation ............................................................................................................255
15.6.3 Master ports ....................................................................................................................256
15.6.4 Slave ports .......................................................................................................................256
15.6.5 Priority assignment .........................................................................................................256
15.6.6 Arbitration .......................................................................................................................257
15.6.6.1 Fixed priority operation ................................................................................257
15.6.6.1.1Parking 257
Chapter 16
Miscellaneous Control Module (MCM)
16.1
16.2
16.3
16.4
Introduction ...................................................................................................................................259
Overview .......................................................................................................................................259
Features .........................................................................................................................................259
Memory Map and Registers Description ......................................................................................259
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16.4.1 Memory Map ..................................................................................................................260
16.4.2 Registers Description ......................................................................................................261
16.4.2.1 Processor Core Type (PCT) register .............................................................261
16.4.2.2 Revision (REV) register ................................................................................261
16.4.2.3 IPS Module Configuration (IMC) register ....................................................262
16.4.2.4 Miscellaneous Interrupt Register (MIR) .......................................................263
16.4.2.5 Miscellaneous User-Defined Control Register (MUDCR) ...........................263
16.4.2.6 ECC registers ................................................................................................264
16.4.2.7 ECC Configuration Register (ECR) .............................................................265
16.4.2.8 ECC Status Register (ESR) ...........................................................................266
16.4.2.9 ECC Error Generation Register (EEGR) ......................................................268
16.4.2.10 Flash ECC Address Register (FEAR) ...........................................................270
16.4.2.11 Flash ECC Master Number Register (FEMR) ..............................................271
16.4.2.12 Flash ECC Attributes (FEAT) register ..........................................................272
16.4.2.13 Flash ECC Data Register (FEDR) ................................................................272
16.4.2.14 RAM ECC Address Register (REAR) ..........................................................273
16.4.2.15 RAM ECC Syndrome Register (RESR) .......................................................274
16.4.2.16 RAM ECC Master Number Register (REMR) .............................................276
16.4.2.17 RAM ECC Attributes (REAT) register .........................................................277
16.4.2.18 RAM ECC Data Register (REDR) ...............................................................277
16.4.3 MCM_reg_protection .....................................................................................................278
Chapter 17
Internal Static RAM (SRAM)
17.1
17.2
17.3
17.4
Introduction ...................................................................................................................................281
SRAM operating mode ..................................................................................................................281
Register memory map ...................................................................................................................281
SRAM ECC mechanism ................................................................................................................281
17.4.1 Access timing ..................................................................................................................282
17.4.2 Reset effects on SRAM accesses ....................................................................................283
17.5 Functional description ...................................................................................................................283
17.6 Initialization and application information .....................................................................................283
Chapter 18
Flash Memory
18.1 Introduction ...................................................................................................................................285
18.2 Platform flash controller ................................................................................................................286
18.2.1 Introduction .....................................................................................................................286
18.2.1.1 Overview .......................................................................................................286
18.2.1.2 Features .........................................................................................................287
18.2.2 Modes of operation .........................................................................................................287
18.2.3 External signal descriptions ............................................................................................287
18.2.4 Memory map and registers description ...........................................................................288
18.2.4.1 Memory map .................................................................................................288
18.2.4.2 Registers description .....................................................................................290
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18.2.4.2.1Platform Flash Configuration Register 0 (PFCR0) .............................290
18.2.4.2.2Platform Flash Configuration Register 1 (PFCR1) .............................293
18.2.4.2.3Platform Flash Access Protection Register (PFAPR) .........................295
18.2.5 Functional description .....................................................................................................296
18.2.6 Basic interface protocol ..................................................................................................297
18.2.7 Access protections ..........................................................................................................297
18.2.8 Read cycles — buffer miss .............................................................................................297
18.2.9 Read cycles — buffer hit ................................................................................................298
18.2.10Write cycles .....................................................................................................................298
18.2.11Error termination .............................................................................................................298
18.2.12Access pipelining ............................................................................................................299
18.2.13Flash error response operation ........................................................................................299
18.2.14Bank0 page read buffers and prefetch operation ............................................................299
18.2.14.1 Instruction/data prefetch triggering ..............................................................301
18.2.14.2 Per-master prefetch triggering ......................................................................301
18.2.14.3 Buffer allocation ...........................................................................................301
18.2.14.4 Buffer invalidation ........................................................................................301
18.2.15Bank1 temporary holding register ..................................................................................302
18.2.16Read-While-Write functionality .....................................................................................302
18.2.17Wait state emulation ........................................................................................................304
18.2.18Timing diagrams .............................................................................................................305
18.3 Code Flash Memory (C90LC) .......................................................................................................311
18.3.1 Overview .........................................................................................................................311
18.3.2 Features ...........................................................................................................................311
18.3.3 Block Diagram ................................................................................................................311
18.3.4 Functional Description ....................................................................................................312
18.3.4.1 Macrocell Structure .......................................................................................312
18.3.5 Code flash sectorization ..................................................................................................313
18.3.5.1 Test Flash Block ............................................................................................314
18.3.5.2 Shadow block ................................................................................................315
18.3.5.3 User Mode Operation ....................................................................................316
18.3.5.4 Reset ..............................................................................................................316
18.3.5.5 Disable Mode (Power-Down) .......................................................................317
18.3.5.6 Sleep Mode (Low Power Mode) ...................................................................317
18.3.6 Registers Description ......................................................................................................318
18.3.6.1 Module Configuration Register (MCR) ........................................................319
18.3.6.2 Low/Mid Address Space Block Locking register (LML) .............................324
18.3.6.3 Non-Volatile Low/Mid Address Space Block Locking register (NVLML) .324
18.3.6.4 High address space Block Locking register (HBL) ......................................326
18.3.6.5 Non Volatile High address space Block Locking register (NVHBL) ...........327
18.3.6.6 Secondary Low/Mid Address Space Block Locking register (SLL) ............327
18.3.6.7 Non-Volatile Secondary Low/Mid Address Space Block Locking register
(NVSLL) .......................................................................................................................328
18.3.6.8 Low/Mid Address Space Block Select register (LMS) ................................330
18.3.6.9 High address space Block Select register (HBS) ..........................................331
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18.3.6.10 Address Register (ADR) ...............................................................................332
18.3.6.11 Bus Interface Unit 0 register (BIU0) ............................................................333
18.3.6.12 Bus Interface Unit 1 register (BIU1) ............................................................333
18.3.6.13 Bus Interface Unit 2 register (BIU2) ............................................................334
18.3.6.13.1Non-volatile Bus Interface Unit 2 register (NVBIU2) .....................334
18.3.6.14 Non Volatile Bus Interface Unit 3 register (NVBIU3) .................................335
18.3.6.15 User Test 0 register (UT0) ............................................................................335
18.3.6.16 User Test 1 register (UT1) ............................................................................337
18.3.6.17 User Test 2 register (UT2) ............................................................................338
18.3.6.18 User Multiple Input Signature Register 0 (UMISR0) ...................................339
18.3.6.19 User Multiple Input Signature Register 1 (UMISR1) ...................................339
18.3.6.20 User Multiple Input Signature Register 2 (UMISR2) ...................................340
18.3.6.21 User Multiple Input Signature Register 3 (UMISR3) ...................................341
18.3.6.22 User Multiple Input Signature Register 4 (UMISR4) ...................................341
18.3.6.23 Non-Volatile Private Censorship Password 0 register (NVPWD0) ..............342
18.3.6.24 Non-Volatile Private Censorship Password 1 register (NVPWD1) ..............343
18.3.6.25 Non-Volatile System Censoring Information 0 register (NVSCI0) ..............343
18.3.6.26 Non-Volatile System Censoring Information 1 register (NVSCI1) ..............344
18.3.6.27 Non-Volatile User Options register (NVUSRO) ...........................................345
18.3.7 Programming Considerations .........................................................................................346
18.3.7.1 Modify Operations ........................................................................................346
18.3.7.1.1Double Word Program ........................................................................347
18.3.7.1.2Block Erase .........................................................................................349
18.3.7.1.3Erase Suspend/Resume .......................................................................350
18.3.7.1.4User Test Mode ...................................................................................350
18.3.7.2 Error correction code ....................................................................................354
18.3.7.2.1ECC algorithms ...................................................................................355
18.3.7.3 EEprom emulation ........................................................................................355
18.3.7.4 Eprom Emulation ..........................................................................................355
18.3.7.4.1All ‘1’s No Error .................................................................................355
18.3.7.5 Protection strategy ........................................................................................356
18.3.7.5.1Modify protection ...............................................................................356
18.3.7.5.2Censored Mode ...................................................................................356
18.4 Data Flash Memory .......................................................................................................................357
18.4.1 Block Overview ..............................................................................................................357
18.4.2 Features ...........................................................................................................................358
18.4.3 Block Diagram ................................................................................................................358
18.4.4 Functional Description ....................................................................................................359
18.4.4.1 Macrocell Structure .......................................................................................359
18.4.4.2 Data flash sectorization .................................................................................359
18.4.4.3 Test Flash Block ............................................................................................360
18.4.4.4 Reset ..............................................................................................................361
18.4.4.5 Power-down mode ........................................................................................361
18.4.4.6 Slave Mode ...................................................................................................362
18.4.5 Register description ........................................................................................................362
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18.4.5.1 Module Configuration Register (MCR) ........................................................363
18.4.5.2 Low/Mid Address Space Block Locking register (LML) .............................367
18.4.5.3 Non-Volatile Low/Mid Address Space Block Locking register (NVLML) .368
18.4.5.4 Secondary Low/Mid Address Space Block Locking register (SLL) ............369
18.4.5.5 Non-Volatile Secondary Low/Mid Address Space Block Locking register
(NVSLL) .......................................................................................................................370
18.4.5.6 Low/Mid Address Space Block Select register (LMS) ................................371
18.4.5.7 Address Register (ADR) ...............................................................................372
18.4.5.8 User Test 0 register (UT0) ............................................................................373
18.4.5.9 User Test 1 register (UT1) ............................................................................375
18.4.5.10 User Multiple Input Signature Register 0 (UMISR0) ...................................376
18.4.5.11 User Multiple Input Signature Register 1 (UMISR1) ...................................376
18.4.6 Programming considerations ..........................................................................................377
18.4.6.1 Modify operation ..........................................................................................377
18.4.6.2 Word program ...............................................................................................378
18.4.6.3 Sector erase ...................................................................................................379
18.4.6.3.1Erase suspend/resume .........................................................................380
18.4.6.4 User Test Mode .............................................................................................381
18.4.6.4.1Array integrity self check ...................................................................381
18.4.6.4.2Margin read .........................................................................................382
18.4.6.4.3ECC logic check .................................................................................383
18.4.7 Error correction code ......................................................................................................384
18.4.7.1 ECC algorithms .............................................................................................384
18.4.7.2 ECC Algorithms Features .............................................................................384
18.4.8 Protection strategy ..........................................................................................................385
18.4.8.1 Modify protection .........................................................................................385
Chapter 19
Enhanced Direct Memory Access (eDMA)
19.1 Introduction ...................................................................................................................................387
19.1.1 Overview .........................................................................................................................387
19.1.2 Features ...........................................................................................................................388
19.2 Memory map/register definition ....................................................................................................393
19.2.1 Register descriptions .......................................................................................................394
19.2.1.1 eDMA Control Register (DMACR) .............................................................394
19.2.1.2 eDMA Error Status (DMAES) ......................................................................397
19.2.1.3 eDMA Enable Request (DMAERQL) ..........................................................400
19.2.1.4 eDMA Enable Error Interrupt (DMAEEIL) .................................................400
19.2.1.5 eDMA Set Enable Request (DMASERQ) ....................................................401
19.2.1.6 eDMA Clear Enable Request (DMACERQ) ................................................402
19.2.1.7 eDMA Set Enable Error Interrupt (DMASEEI) ...........................................402
19.2.1.8 eDMA Clear Enable Error Interrupt (DMACEEI) .......................................403
19.2.1.9 eDMA Clear Interrupt Request (DMACINT) ..............................................403
19.2.1.10 eDMA Clear Error (DMACERR) .................................................................404
19.2.1.11 eDMA Set START Bit (DMASSRT) ............................................................405
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19.2.1.12 eDMA Clear DONE Status (DMACDNE) ...................................................405
19.2.1.13 eDMA Interrupt Request (DMAINTL) ........................................................406
19.2.1.14 eDMA Error (DMAERRL) ...........................................................................407
19.2.1.15 eDMA Hardware Request Status (DMAHRSL) ...........................................407
19.2.1.16 eDMA Channel n Priority (DCHPRIn), n = 0,..., {15} ................................408
19.2.1.17 Transfer Control Descriptor (TCD) ..............................................................409
19.3 Functional description ...................................................................................................................419
19.3.1 eDMA microarchitecture ................................................................................................419
19.3.2 eDMA basic data flow ....................................................................................................420
19.4 Initialization/application information ............................................................................................423
19.4.1 eDMA initialization ........................................................................................................423
19.4.2 eDMA programming errors ............................................................................................424
19.4.3 eDMA arbitration mode considerations ..........................................................................425
19.4.3.1 Fixed group arbitration, fixed channel arbitration ........................................425
19.4.3.2 Round-robin group arbitration, fixed channel arbitration .............................425
19.4.3.3 Round-robin group arbitration, round-robin channel arbitration ..................425
19.4.3.4 Fixed group arbitration, round-robin channel arbitration .............................426
19.4.4 eDMA transfer ................................................................................................................426
19.4.4.1 Single request ................................................................................................426
19.4.4.2 Multiple requests ...........................................................................................427
19.4.5 TCD status ......................................................................................................................429
19.4.5.1 Minor loop complete .....................................................................................429
19.4.5.2 Active channel TCD reads ............................................................................429
19.4.5.3 Preemption status ..........................................................................................430
19.4.6 Channel linking ...............................................................................................................430
19.4.7 Dynamic programming ...................................................................................................431
19.4.7.1 Dynamic priority changing ...........................................................................431
19.4.7.2 Dynamic channel linking ..............................................................................431
19.4.7.3 Dynamic scatter/gather .................................................................................432
19.4.7.3.1Method 1 (channel not using major loop channel linking) .................432
19.4.7.3.2Method 2 (channel using major loop linking) ....................................433
19.4.8 Hardware request release timing .....................................................................................434
Chapter 20
DMACHMUX
20.1 Introduction ...................................................................................................................................435
20.1.1 Overview .........................................................................................................................435
20.1.2 Features ...........................................................................................................................435
20.1.3 Modes of Operation ........................................................................................................436
20.2 External Signal Description ..........................................................................................................436
20.2.1 Overview .........................................................................................................................436
20.3 Memory Map and Register Definition ..........................................................................................436
20.3.1 Register Descriptions ......................................................................................................437
20.3.1.1 Channel Configuration Registers ..................................................................437
20.4 DMA request mapping ..................................................................................................................438
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20.5 Functional Description ..................................................................................................................440
20.5.1 DMA Channels with periodic triggering capability .......................................................440
20.5.2 DMA Channels with no triggering capability .................................................................442
20.5.3 "Always Enabled" DMA Sources ...................................................................................442
20.6 Initialization/Application Information ..........................................................................................443
20.6.1 Reset ................................................................................................................................443
20.6.2 Enabling and Configuring Sources .................................................................................443
20.6.3 Freezing in STOP and HALT mode ................................................................................446
Chapter 21
Video Encoder Wrapper
21.1 Introduction ...................................................................................................................................447
21.1.1 Features ...........................................................................................................................448
21.2 Block Diagram ..............................................................................................................................449
21.2.1 MJPEG Video Encoder ...................................................................................................449
21.2.2 MJPEG Operation Modes ...............................................................................................450
21.2.2.1 Configuration Mode ......................................................................................451
21.2.2.2 Encoding Mode .............................................................................................453
21.2.2.3 Rate Control operation ..................................................................................454
21.3 Memory Map and Register Definition ..........................................................................................455
21.3.1 Memory Map ..................................................................................................................455
21.3.2 Register Descriptions ......................................................................................................457
21.3.2.1 Status_config .................................................................................................457
21.3.2.2 Picture_size ...................................................................................................459
21.3.2.3 Pixel count ....................................................................................................460
21.3.2.4 Dma_address .................................................................................................460
21.3.2.5 Dma_vstart_address ......................................................................................461
21.3.2.6 Dma_vend_address .......................................................................................461
21.3.2.7 Dma_alarm_address ......................................................................................462
21.3.2.8 Subchannel buffer start .................................................................................462
21.3.2.9 JPEG In Offset Address ................................................................................463
21.3.2.10 RC_REGS_SEL ............................................................................................463
21.3.2.11 LUMTH ........................................................................................................464
21.3.2.12 MODE ...........................................................................................................465
21.3.2.13 CFG_MODE .................................................................................................466
21.3.2.14 CHRTH .........................................................................................................467
21.3.2.15 Status registers ..............................................................................................468
21.3.2.16 JPEG Stat 0 ...................................................................................................468
21.3.2.17 JPEG Stat 1 ...................................................................................................468
21.3.2.18 JPEG Stat 2 ...................................................................................................469
21.3.2.19 JPEG Stat 3 ...................................................................................................469
21.3.2.20 JPEG Stat 4 ...................................................................................................470
21.3.2.21 JPEG Stat 5 ...................................................................................................470
21.3.2.22 JPEG Stat 6 ...................................................................................................471
21.3.2.23 JPEG Stat 7 ...................................................................................................471
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21.3.2.24 JPEG Stat 8 ...................................................................................................472
21.3.2.25 JPEG Stat 9 ...................................................................................................472
21.3.2.26 JPEG Stat 10 .................................................................................................473
21.3.2.27 JPEG Stat 11 .................................................................................................473
21.3.2.28 JPEG Stat 12 .................................................................................................474
21.3.2.29 JPEG Stat 13 .................................................................................................475
21.3.2.30 JPEG Stat 14 .................................................................................................475
21.3.2.31 JPEG Stat 15 .................................................................................................476
21.4 Functional Description ..................................................................................................................476
21.4.1 Input interface .................................................................................................................477
21.4.1.1 External Sync Interface Timing Diagram .....................................................477
21.4.1.2 ITU-BT656 sync information extraction ......................................................478
21.4.1.3 Video In Data Format for embedded Sync Mode .........................................480
21.4.1.4 Video In Format for External Sync Mode ....................................................481
21.4.2 Circular buffer .................................................................................................................482
21.4.3 Subchannel Mode ...........................................................................................................483
21.4.4 Programming Sequence ..................................................................................................485
Chapter 22
Integrated Interchip Sound (I S) / Synchronous Audio Interface (SAI)
2
22.1 Introduction ...................................................................................................................................487
22.1.1 Features ...........................................................................................................................487
22.1.2 Modes of Operation ........................................................................................................487
22.1.2.1 Run Mode .....................................................................................................487
22.1.2.2 Debug Mode .................................................................................................487
22.2 External signals .............................................................................................................................488
22.3 Memory Map and Registers ..........................................................................................................488
22.3.1 SAI Transmit Control Register (I2S_TCSR) ..................................................................490
22.3.2 SAI Transmit Configuration 1 Register (I2S_TCR1) .....................................................490
22.3.3 SAI Transmit Configuration 4 Register (I2S_TCR4) .....................................................493
22.3.4 SAI Transmit Configuration 5 Register (I2S_TCR5) .....................................................494
22.3.5 SAI Transmit Data Register (I2S_TDR) .........................................................................495
22.3.6 SAI Transmit FIFO Register (I2S_TFR) ........................................................................495
22.3.7 SAI Transmit Mask Register (I2S_TMR) .......................................................................496
22.3.8 SAI Receive Control Register (I2S_RCSR) ...................................................................496
22.3.9 SAI Receive Configuration 1 Register (I2S_RCR1) ......................................................499
22.3.10SAI Receive Configuration 2 Register (I2S_RCR2) ......................................................499
22.3.11SAI clocking ...................................................................................................................504
22.3.11.1 Audio Master Clock ......................................................................................504
22.3.11.2 Bit Clock .......................................................................................................505
22.3.11.3 Bus Clock ......................................................................................................505
22.3.12SAI resets ........................................................................................................................505
22.3.12.1 Software reset ...............................................................................................505
22.3.12.2 FIFO reset .....................................................................................................506
22.3.13Synchronous Modes ........................................................................................................506
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22.3.13.1 Synchronous Mode .......................................................................................506
22.3.13.2 Multiple SAI Synchronous Mode .................................................................506
22.3.14Frame sync configuration ...............................................................................................507
22.3.15Data FIFO .......................................................................................................................507
22.3.15.1 Data alignment ..............................................................................................507
22.3.15.2 FIFO pointers ................................................................................................508
22.3.16Word mask register .........................................................................................................509
22.3.17Interrupts and DMA requests ..........................................................................................509
22.3.17.1 FIFO data ready flag .....................................................................................509
22.3.17.2 FIFO warning flag ........................................................................................509
22.3.17.3 FIFO error flag ..............................................................................................509
22.3.17.4 Sync error flag ..............................................................................................510
22.3.17.5 Word start flag ...............................................................................................510
Chapter 23
SAI Instantiation
23.1 Introduction ...................................................................................................................................511
23.1.1 SAI/I2S Overview ...........................................................................................................511
23.1.2 External Signals Multiplexing ........................................................................................512
23.1.3 SAI/I2S Clocking ............................................................................................................512
23.1.3.1 SAI/I2S Clock Selection ...............................................................................512
23.1.3.2 CLKMODE in SAI/I2S TCR2 Register .......................................................512
23.1.3.3 CLKMODE in SAI/I2S RCR2 Register .......................................................513
23.1.3.4 Configuring clock source for SAI/I2S audio master clock ...........................514
Chapter 24
Deserial Serial Peripheral Interface (DSPI)
24.1
24.2
24.3
24.4
24.5
Introduction ...................................................................................................................................515
Block diagram ...............................................................................................................................515
Overview .......................................................................................................................................516
Features .........................................................................................................................................516
Modes of operation ........................................................................................................................517
24.5.1 Master mode ...................................................................................................................517
24.5.2 Slave mode ......................................................................................................................517
24.5.3 Module disable mode ......................................................................................................518
24.5.4 Debug mode ....................................................................................................................518
24.6 External signal description ............................................................................................................518
24.6.1 Signal overview ..............................................................................................................518
24.6.2 Signal names and descriptions ........................................................................................519
24.6.2.1 Peripheral Chip Select / Slave Select (CS_0) ...............................................519
24.6.2.2 Peripheral Chip Selects 1–3 (CS1:3) ............................................................519
24.6.2.3 Peripheral Chip Select 4 / Master Trigger (CS4/MTRIG) ............................519
24.6.2.4 Peripheral Chip Select 5/Peripheral Chip Select Strobe (CS_5) ..................519
24.6.2.5 Serial Input (SIN_x) ......................................................................................519
24.6.2.6 Serial Output (SOUT_x) ...............................................................................519
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24.6.2.7 Serial Clock (SCK_x) ...................................................................................520
24.7 Memory map and registers description .........................................................................................520
24.7.1 Memory map ...................................................................................................................520
24.7.2 Registers description .......................................................................................................521
24.7.2.1 DSPI Module Configuration Register (DSPIx_MCR) .................................521
24.7.2.2 DSPI Hardware Configuration Register (DSPI_HCR) .................................524
24.7.2.3 DSPI Transfer Count Register (DSPIx_TCR) ..............................................525
24.7.2.4 DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn) .........525
24.7.2.5 DSPI Status Register (DSPIx_SR) ................................................................531
24.7.2.6 DSPI DMA / Interrupt Request Select and Enable Register (DSPIx_RSER)
.......................................................................................................................533
24.7.2.7 DSPI PUSH TX FIFO Register (DSPIx_PUSHR) .......................................534
24.7.2.8 DSPI POP RX FIFO Register (DSPIx_POPR) .............................................536
24.7.2.9 DSPI Transmit FIFO Registers 0–4 (DSPIx_TXFRn) .................................537
24.7.2.10 DSPI Receive FIFO Registers 0–4 (DSPIx_RXFRn) ...................................537
24.8 Functional description ...................................................................................................................538
24.8.1 Modes of operation .........................................................................................................539
24.8.1.1 Master mode .................................................................................................539
24.8.1.2 Slave mode ....................................................................................................540
24.8.1.3 Module disable mode ....................................................................................540
24.8.1.4 Debug mode ..................................................................................................540
24.8.2 Start and stop of DSPI transfers ......................................................................................540
24.8.3 Serial Peripheral Interface (SPI) configuration ..............................................................541
24.8.3.1 SPI master mode ...........................................................................................541
24.8.3.2 SPI slave mode ..............................................................................................542
24.8.3.3 FIFO disable operation .................................................................................542
24.8.3.4 Transmit First In First Out (TX FIFO) buffering mechanism ......................542
24.8.3.4.1Filling the TX FIFO ............................................................................543
24.8.3.4.2Draining the TX FIFO ........................................................................543
24.8.3.5 Receive First In First Out (RX FIFO) buffering mechanism ........................543
24.8.3.5.1Filling the RX FIFO ............................................................................544
24.8.3.5.2Draining the RX FIFO ........................................................................544
24.8.4 DSPI baud rate and clock delay generation ....................................................................544
24.8.4.1 Baud rate generator .......................................................................................544
24.8.4.2 CS to SCK delay (tCSC) ................................................................................545
24.8.4.3 After SCK delay (tASC) .................................................................................545
24.8.4.4 Delay after transfer (tDT) .............................................................................546
24.8.4.5 Peripheral Chip Select strobe enable (CS5_x) ..............................................546
24.8.5 Transfer formats ..............................................................................................................547
24.8.5.1 Classic SPI transfer format (CPHA = 0) .......................................................548
24.8.5.2 Classic SPI transfer format (CPHA = 1) .......................................................549
24.8.5.3 Modified SPI transfer format (MTFE = 1, CPHA = 0) ................................549
24.8.5.4 Modified SPI transfer format (MTFE = 1, CPHA = 1) ................................551
24.8.5.5 Continuous selection format .........................................................................551
24.8.5.6 Clock polarity switching between DSPI transfers ........................................553
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24.8.5.7 Fast Continuous Selection Format ................................................................553
24.8.6 Continuous Serial communications clock .......................................................................555
24.8.7 Interrupts/DMA requests ................................................................................................556
24.8.7.1 End of queue interrupt request (EOQF) ........................................................556
24.8.7.2 Transmit FIFO fill interrupt or DMA request (TFFF) ..................................557
24.8.7.3 Transfer complete interrupt request (TCF) ...................................................557
24.8.7.4 Transmit FIFO underflow interrupt request (TFUF) ....................................557
24.8.7.5 Receive FIFO drain interrupt or DMA request (RFDF) ...............................557
24.8.7.6 Receive FIFO overflow interrupt request (RFOF) .......................................557
24.8.7.7 FIFO overrun request (TFUF) or (RFOF) ....................................................557
24.8.8 Power saving features .....................................................................................................558
24.8.8.1 Module disable mode ....................................................................................558
24.9 Initialization and application information .....................................................................................558
24.9.1 Managing queues ............................................................................................................558
24.9.2 Baud rate settings ............................................................................................................559
24.9.3 Delay settings ..................................................................................................................560
24.9.4 MPC5604E DSPI compatibility with QSPI of the MPC500 MCUs ..............................560
24.9.5 Calculation of FIFO pointer addresses ...........................................................................561
24.9.5.1 Address calculation for first-in entry and last-in entry in TX FIFO .............562
24.9.5.2 Address calculation for first-in entry and last-in entry in RX FIFO .............562
Chapter 25
LIN Controller (LINFlex)
25.1
25.2
25.3
25.4
25.5
Introduction ...................................................................................................................................565
Main features .................................................................................................................................565
General description .......................................................................................................................566
Fractional baud rate generation .....................................................................................................567
Operating modes ...........................................................................................................................570
25.5.1 Initialization mode ..........................................................................................................570
25.5.2 Normal mode ..................................................................................................................570
25.5.3 Low power mode (Sleep) ................................................................................................571
25.6 Test modes .....................................................................................................................................571
25.6.1 Loop Back mode .............................................................................................................571
25.6.2 Self Test mode .................................................................................................................571
25.7 Memory map and registers description .........................................................................................572
25.7.1 Memory map ...................................................................................................................572
25.7.2 Register description ........................................................................................................574
25.7.2.1 LIN control register 1 (LINCR1) ..................................................................575
25.7.2.2 LIN interrupt enable register (LINIER) ........................................................578
25.7.2.3 LIN status register (LINSR) .........................................................................579
25.7.2.4 LIN error status register (LINESR) ..............................................................582
25.7.2.5 UART mode control register (UARTCR) .....................................................583
25.7.2.6 UART mode status register (UARTSR) ........................................................585
25.7.2.7 LIN timeout control status register (LINTCSR) ...........................................587
25.7.2.8 LIN output compare register (LINOCR) ......................................................588
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25.7.2.9 LIN timeout control register (LINTOCR) ....................................................588
25.7.2.10 LIN fractional baud rate register (LINFBRR) ..............................................589
25.7.2.11 LIN Integer Baud Rate Register (LINIBRR) ................................................590
25.7.2.12 LIN checksum field register (LINCFR) ........................................................590
25.7.2.13 LIN control register 2 (LINCR2) ..................................................................591
25.7.2.14 Buffer identifier register (BIDR) ..................................................................592
25.7.2.15 Buffer data register least significant (BDRL) ...............................................593
25.7.2.16 Buffer data register most significant (BDRM) .............................................594
25.7.2.17 Identifier filter enable register (IFER) ..........................................................594
25.7.2.18 Identifier filter match index (IFMI) ..............................................................596
25.7.2.19 Identifier filter mode register (IFMR) ..........................................................596
25.7.2.20 Identifier filter control register (IFCR2n) .....................................................598
25.7.2.21 Identifier filter control register (IFCR2n + 1) ...............................................599
25.8 Functional description ...................................................................................................................600
25.8.1 UART mode ....................................................................................................................600
25.8.1.1 Buffer in UART mode ..................................................................................600
25.8.1.2 UART transmitter .........................................................................................601
25.8.1.3 UART receiver ..............................................................................................601
25.8.1.4 Clock gating ..................................................................................................602
25.8.2 LIN mode ........................................................................................................................602
25.8.2.1 Master mode .................................................................................................602
25.8.2.1.1LIN header transmission .....................................................................602
25.8.2.1.2Data transmission (transceiver as publisher) ......................................602
25.8.2.1.3Data reception (transceiver as subscriber) ..........................................603
25.8.2.1.4Data discard ........................................................................................603
25.8.2.1.5Error detection ....................................................................................603
25.8.2.1.6Error handling .....................................................................................603
25.8.2.2 Slave mode ....................................................................................................604
25.8.2.2.1Data transmission (transceiver as publisher) ......................................604
25.8.2.2.2Data reception (transceiver as subscriber) ..........................................604
25.8.2.2.3Data discard ........................................................................................605
25.8.2.2.4Error detection ....................................................................................605
25.8.2.2.5Error handling .....................................................................................605
25.8.2.2.6Valid header ........................................................................................606
25.8.2.2.7Valid message .....................................................................................606
25.8.2.2.8Overrun ...............................................................................................606
25.8.2.3 Slave mode with identifier filtering ..............................................................606
25.8.2.3.1Filter mode ..........................................................................................606
25.8.2.3.2Identifier filter mode configuration ....................................................607
25.8.2.4 Slave mode with automatic resynchronization .............................................608
25.8.2.4.1Deviation error on the Synch Field .....................................................609
25.8.2.5 Clock gating ..................................................................................................610
25.8.3 8-bit timeout counter .......................................................................................................610
25.8.3.1 LIN timeout mode .........................................................................................610
25.8.3.1.1LIN Master mode ................................................................................610
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25.8.3.1.2LIN Slave mode ..................................................................................611
25.8.3.2 Output compare mode ...................................................................................611
25.8.4 Interrupts .........................................................................................................................612
Chapter 26
FlexCAN Module
26.1 Introduction ...................................................................................................................................613
26.1.1 Overview .........................................................................................................................614
26.1.2 FlexCAN Module Features .............................................................................................615
26.1.3 Modes of Operation ........................................................................................................616
26.2 External Signal Description ..........................................................................................................617
26.2.1 Overview .........................................................................................................................617
26.2.2 Signal Descriptions .........................................................................................................617
26.2.2.1 CAN Rx ........................................................................................................617
26.2.2.2 CAN Tx .........................................................................................................617
26.3 Memory Map/Register Definition .................................................................................................617
26.3.1 FlexCAN Memory Mapping ...........................................................................................617
26.3.2 Message Buffer Structure ................................................................................................618
26.3.3 Rx FIFO Structure ...........................................................................................................622
26.3.4 Register Descriptions ......................................................................................................623
26.3.4.1 Module Configuration Register (MCR) ........................................................624
26.3.4.2 Control Register (CTRL) ..............................................................................628
26.3.4.3 Free Running Timer (TIMER) ......................................................................632
26.3.4.4 Rx Global Mask (RXGMASK) ....................................................................633
26.3.4.5 Rx 14 Mask (RX14MASK) ..........................................................................634
26.3.4.6 Rx 15 Mask (RX15MASK) ..........................................................................634
26.3.4.7 Error Counter Register (ECR) ......................................................................634
26.3.4.8 Error and Status Register (ESR) ...................................................................636
26.3.4.9 Interrupt Masks 1 Register (IMASK1) .........................................................639
26.3.4.10 Interrupt Flags 1 Register (IFLAG1) ............................................................640
26.3.4.11 Rx Individual Mask Registers (RXIMR0–RXIMR31) .................................641
26.4 Functional Description ..................................................................................................................642
26.4.1 Overview .........................................................................................................................642
26.4.2 Transmit Process .............................................................................................................642
26.4.3 Arbitration process ..........................................................................................................643
26.4.4 Receive Process ..............................................................................................................643
26.4.5 Matching Process ............................................................................................................645
26.4.6 Data Coherence ...............................................................................................................646
26.4.6.1 Message Buffer Deactivation ........................................................................646
26.4.6.2 Message Buffer Lock Mechanism ................................................................647
26.4.7 Rx FIFO ..........................................................................................................................648
26.4.8 CAN Protocol Related Features ......................................................................................649
26.4.8.1 Remote Frames .............................................................................................649
26.4.8.2 Overload Frames ...........................................................................................649
26.4.8.3 Time Stamp ...................................................................................................649
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26.4.8.4 Protocol Timing ............................................................................................650
26.4.8.5 Arbitration and Matching Timing .................................................................652
26.4.9 Modes of Operation Details ............................................................................................653
26.4.9.1 Freeze Mode .................................................................................................653
26.4.9.2 Module Disable Mode ..................................................................................653
26.4.9.3 Stop Mode .....................................................................................................654
26.4.10Interrupts .........................................................................................................................655
26.4.11Bus Interface ...................................................................................................................655
26.5 Initialization/Application Information ..........................................................................................656
26.5.1 FlexCAN Initialization Sequence ...................................................................................656
26.5.2 FlexCAN Addressing and RAM size configurations .....................................................657
Chapter 27
Analog-to-Digital Converter (ADC)
27.1 Overview .......................................................................................................................................659
27.2 Introduction ...................................................................................................................................659
27.2.1 Features ...........................................................................................................................659
27.2.2 Block Diagram ................................................................................................................660
27.3 Register descriptions .....................................................................................................................661
27.3.1 Introduction .....................................................................................................................661
27.3.2 Control logic registers .....................................................................................................662
27.3.2.1 Main Configuration Register (MCR) ............................................................662
27.3.2.2 Main Status Register (MSR) .........................................................................665
27.3.3 Interrupt registers ............................................................................................................666
27.3.3.1 Interrupt Status Register (ISR) ......................................................................666
27.3.3.2 Interrupt Mask Register (IMR) .....................................................................667
27.3.3.3 Watchdog Threshold Interrupt Status Register (WTISR) .............................669
27.3.3.4 Watchdog Threshold Interrupt Mask Register (WTIMR) ............................670
27.3.4 DMA registers .................................................................................................................671
27.3.4.1 DMA Enable Register (DMAE) ...................................................................671
27.3.4.2 DMA Channel Select Register 0 (DMAR0) .................................................672
27.3.5 Threshold registers ..........................................................................................................672
27.3.5.1 Introduction ...................................................................................................672
27.3.5.2 Threshold Register (THRHLR[0:3]) ............................................................672
27.3.6 Conversion timing registers CTR[0..1] ...........................................................................673
27.3.7 Mask registers .................................................................................................................676
27.3.7.1 Introduction ...................................................................................................676
27.3.7.2 Normal Conversion Mask Register 0 (NCMR0) ..........................................676
27.3.7.3 Injected Conversion Mask Register 0 (JCMR0) ...........................................677
27.3.8 Power Down Exit Delay Register (PDEDR) ..................................................................677
27.3.9 Data registers ..................................................................................................................678
27.3.9.1 Introduction ...................................................................................................678
27.3.9.2 Channel Data Register (CDR[0..6]) .............................................................678
27.3.9.3 Channel Watchdog Select Register (CWSELR0) .........................................679
27.3.9.4 Channel Watchdog Enable Register (CWENR0) .........................................680
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27.4 Functional description ...................................................................................................................680
27.4.1 Analog channel conversion .............................................................................................680
27.4.1.1 Normal conversion ........................................................................................680
27.4.1.2 Start of normal conversion ............................................................................680
27.4.1.3 Normal conversion operating modes ............................................................681
27.4.1.4 Injected channel conversion ..........................................................................682
27.4.2 Analog clock generator and conversion timings .............................................................683
27.4.3 ADC sampling and conversion timing ............................................................................683
27.4.4 Programmable analog watchdog .....................................................................................685
27.4.4.1 Introduction ...................................................................................................685
27.4.5 DMA functionality ..........................................................................................................686
27.4.6 Interrupts .........................................................................................................................686
27.4.7 Power-down mode ..........................................................................................................687
27.4.8 Auto-clock-off mode .......................................................................................................687
Chapter 28
Enhanced Motor Control Timer (eTimer)
28.1 Introduction ...................................................................................................................................689
28.1.1 Overview .........................................................................................................................689
28.1.2 Features ...........................................................................................................................689
28.1.3 Customization .................................................................................................................690
28.1.4 Module Block Diagram ..................................................................................................690
28.1.5 Channel Block Diagram ..................................................................................................691
28.2 External Signal Descriptions .........................................................................................................692
28.2.1 TIO[5:0] - Timer Input/Outputs ......................................................................................692
28.2.2 TAI[2] - Timer Auxiliary Input .......................................................................................692
28.3 Functional Description ..................................................................................................................692
28.3.1 General ............................................................................................................................692
28.3.2 Counting Modes ..............................................................................................................693
28.3.2.1 STOP Mode ..................................................................................................693
28.3.2.2 COUNT Mode ..............................................................................................694
28.3.2.3 EDGE-COUNT Mode ..................................................................................694
28.3.2.4 GATED-COUNT Mode ................................................................................694
28.3.2.5 QUADRATURE-COUNT Mode ..................................................................694
28.3.2.6 SIGNED-COUNT Mode ..............................................................................694
28.3.2.7 TRIGGERED-COUNT Mode ......................................................................695
28.3.2.8 ONE-SHOT Mode ........................................................................................695
28.3.2.9 CASCADE-COUNT Mode ..........................................................................695
28.3.2.10 PULSE-OUTPUT Mode ...............................................................................696
28.3.2.11 FIXED-FREQUENCY PWM Mode ............................................................696
28.3.2.12 VARIABLE-FREQUENCY PWM Mode .....................................................696
28.3.2.13 Usage of Compare Registers .........................................................................698
28.3.2.14 Usage of Compare Load Registers ...............................................................699
28.3.2.15 MODULO COUNTING Mode .....................................................................699
28.3.2.16 Compare Register and OFLAG Operation ...................................................700
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28.4
28.5
28.6
28.7
28.8
28.9
28.3.3 Other Features .................................................................................................................701
28.3.3.1 Redundant OFLAG Checking ......................................................................701
28.3.3.2 Loopback Checking ......................................................................................701
28.3.3.3 Input Capture Mode ......................................................................................701
28.3.3.4 Master/Slave Mode .......................................................................................701
28.3.3.5 Watchdog Timer ............................................................................................701
Memory Map and Registers ..........................................................................................................702
28.4.1 Overview .........................................................................................................................702
28.4.2 Module Memory Map .....................................................................................................702
28.4.3 Register Descriptions ......................................................................................................703
28.4.4 Timer Channel Registers .................................................................................................703
28.4.4.1 Compare Register 1 (COMP1) .....................................................................703
28.4.4.2 Compare Register 2 (COMP2) .....................................................................703
28.4.4.3 Capture Register 1 (CAPT1) .........................................................................704
28.4.4.4 Capture Register 2 (CAPT2) .........................................................................704
28.4.4.5 Load Register (LOAD) .................................................................................704
28.4.4.6 Hold Register (HOLD) .................................................................................705
28.4.4.7 Counter Register (CNTR) .............................................................................705
28.4.4.8 Control Register 1 (CTRL1) .........................................................................705
28.4.4.9 Control Register 2 (CTRL2) .........................................................................709
28.4.4.10 Control Register 3 (CTRL3) .........................................................................711
28.4.4.11 Status Register (STS) ....................................................................................712
28.4.4.12 Interrupt and DMA Enable Register (INTDMA) .........................................714
28.4.4.13 Comparator Load Register 1 (CMPLD1) .....................................................715
28.4.4.14 Comparator Load Register 2 (CMPLD2) .....................................................715
28.4.4.15 Compare and Capture Control Register (CCCTRL) .....................................715
28.4.4.16 Input Filter Register (FILT) ..........................................................................718
28.4.4.16.1Input Filter Considerations ...............................................................718
28.4.5 Watchdog Timer Registers ..............................................................................................718
28.4.5.1 Watchdog Time-out Registers (WDTOL and WDTOH) ..............................719
28.4.6 Configuration Registers ..................................................................................................719
28.4.6.1 Channel Enable Register (ENBL) .................................................................719
28.4.6.2 DMA Request Select Registers (DREQ0, DREQ1) .....................................720
Resets ............................................................................................................................................721
Clocks ............................................................................................................................................721
Interrupts .......................................................................................................................................722
DMA ..............................................................................................................................................722
ADC Trigger ..................................................................................................................................723
Chapter 29
Fault Collection Unit (FCU)
29.1 Introduction ...................................................................................................................................725
29.1.1 Overview .........................................................................................................................725
29.1.1.1 General description .......................................................................................725
29.1.2 Features ...........................................................................................................................728
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29.1.3 Modes of operation .........................................................................................................728
29.1.3.1 Normal mode ................................................................................................728
29.1.3.2 Test mode ......................................................................................................728
29.2 Memory map and register definition .............................................................................................728
29.2.1 Memory map ...................................................................................................................729
29.2.2 Register summary ...........................................................................................................729
29.2.3 Register descriptions .......................................................................................................731
29.2.3.1 Module Configuration Register (FCU_MCR) ..............................................731
29.2.3.2 Fault Flag Register (FCU_FFR) ...................................................................732
29.2.3.3 Frozen Fault Flag Register (FCU_FFFR) .....................................................734
29.2.3.4 Fake Fault Generation Register (FCU_FFGR) .............................................735
29.2.3.5 Fault Enable Register (FCU_FER) ...............................................................736
29.2.3.6 Key Register (FCU_KR) ..............................................................................736
29.2.3.7 Timeout Register (FCU_TR) ........................................................................737
29.2.3.8 Timeout Enable Register (FCU_TER) ..........................................................738
29.2.3.9 Module State Register (FCU_MSR) .............................................................738
29.2.3.10 Microcontroller State Register (FCU_MCSR) .............................................739
29.2.3.11 Frozen MC State Register (FCU_FMCSR) ..................................................740
29.3 Functional description ...................................................................................................................741
29.3.1 State machine ..................................................................................................................742
29.3.2 Output generation protocol .............................................................................................743
29.3.2.1 Dual-rail protocol ..........................................................................................744
29.3.2.2 Time switching protocol ...............................................................................745
29.3.2.3 Bi-Stable protocol .........................................................................................745
Chapter 30
Periodic Interrupt Timer (PIT_RTI)
30.1 Front Matter ...................................................................................................................................747
30.1.1 Preface ............................................................................................................................747
30.1.1.1 Conventions ..................................................................................................747
30.1.1.2 Acronyms and Abbreviations .......................................................................747
30.1.1.3 Glossary ........................................................................................................748
30.2 Introduction ...................................................................................................................................748
30.2.1 Overview .........................................................................................................................749
30.2.2 Features ...........................................................................................................................749
30.3 Signal Description .........................................................................................................................749
30.4 Memory Map and Register Description ........................................................................................749
30.4.1 Memory Map ..................................................................................................................749
30.4.2 Register Descriptions ......................................................................................................751
30.4.2.1 PIT Module Control Register (PITMCR) .....................................................751
30.4.2.2 Timer Load Value Register n (LDVALn) .....................................................752
30.4.2.3 Current Timer Value Register n (CVALn) ....................................................752
30.4.2.4 Timer Control Register n (TCTRLn) ............................................................753
30.4.2.5 Timer Flag Register n (TFLGn) ....................................................................754
30.5 Functional Description ..................................................................................................................754
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30.5.1 General ............................................................................................................................754
30.5.1.1 Timers ...........................................................................................................754
30.5.1.2 Debug Mode .................................................................................................755
30.5.2 Interrupts .........................................................................................................................755
30.6 Initialization and Application Information ....................................................................................756
30.6.1 Example Configuration ...................................................................................................756
Chapter 31
Software Watchdog Timer (SWT)
31.1 Introduction ...................................................................................................................................757
31.1.1 Overview .........................................................................................................................757
31.1.2 Features ...........................................................................................................................757
31.1.3 Modes of operation .........................................................................................................757
31.2 External signal description ............................................................................................................757
31.3 Memory map and register definition .............................................................................................758
31.3.1 Memory map ...................................................................................................................758
31.3.2 Register descriptions .......................................................................................................758
31.3.2.1 SWT Module Control Register (SWT_MCR) ..............................................758
31.3.2.2 SWT Interrupt Register (SWT_IR) ...............................................................760
31.3.2.3 SWT Time-Out Register (SWT_TO) ............................................................760
31.3.2.4 SWT Window Register (SWT_WN) ............................................................761
31.3.2.5 SWT Service Register (SWT_SR) ................................................................761
31.3.2.6 SWT Counter Output Register (SWT_CO) ..................................................762
31.3.2.7 SWT Service Key Register (SWT_SK) ........................................................762
31.4 Functional description ...................................................................................................................763
Chapter 32
System Timer Module (STM)
32.1
32.2
32.3
32.4
32.5
Overview .......................................................................................................................................765
Features .........................................................................................................................................765
Modes of operation ........................................................................................................................765
External signal description ............................................................................................................765
Memory map and registers description .........................................................................................765
32.5.1 Memory map ...................................................................................................................765
32.5.2 Registers description .......................................................................................................766
32.5.2.1 STM Control Register (STM_CR) ...............................................................766
32.5.2.2 STM Count Register (STM_CNT) ...............................................................767
32.5.2.3 STM Channel Control Register (STM_CCRn) ............................................768
32.5.2.4 STM Channel Interrupt Register (STM_CIRn) ............................................768
32.5.2.5 STM Channel Compare Register (STM_CMPn) ..........................................769
32.6 Functional description ...................................................................................................................769
Chapter 33
Cyclic Redundancy Check (CRC)
33.1 Introduction ...................................................................................................................................771
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33.2
33.3
33.4
33.5
33.6
33.1.1 Glossary ..........................................................................................................................771
Main features .................................................................................................................................771
33.2.1 Standard features .............................................................................................................771
Block diagram ...............................................................................................................................772
33.3.1 IPS bus interface .............................................................................................................772
Functional description ...................................................................................................................773
Memory map and registers description .........................................................................................774
33.5.1 CRC Configuration Register (CRC_CFG) .....................................................................775
33.5.2 CRC Input Register (CRC_INP) .....................................................................................776
33.5.3 CRC Current Status Register (CRC_CSTAT) .................................................................777
33.5.4 CRC Output Register (CRC_OUTP) ..............................................................................777
Use cases and limitations ..............................................................................................................778
Chapter 34
Boot Assist Module (BAM)
34.1
34.2
34.3
34.4
34.5
Overview .......................................................................................................................................783
Features .........................................................................................................................................783
Boot modes ....................................................................................................................................783
Memory map .................................................................................................................................783
Functional description ...................................................................................................................784
34.5.1 Entering boot modes .......................................................................................................784
34.5.2 Reset Configuration Half Word (RCHW) .......................................................................784
34.5.3 Single chip boot mode ....................................................................................................786
34.5.3.1 Boot and alternate boot .................................................................................786
34.5.4 Boot through BAM .........................................................................................................786
34.5.4.1 Executing BAM ............................................................................................786
34.5.4.2 BAM software flow ......................................................................................787
34.5.4.3 BAM resources .............................................................................................788
34.5.4.4 Download and execute the new code ............................................................789
34.5.4.5 Download 64-bit password and password check ..........................................789
34.5.4.6 Download start address, VLE bit and code size ...........................................791
34.5.4.7 Download data ..............................................................................................792
34.5.4.8 Execute code .................................................................................................792
34.5.5 Boot from UART—autobaud disabled ...........................................................................792
34.5.5.1 Configuration ................................................................................................792
34.5.5.2 UART boot mode download protocol ...........................................................793
34.5.6 Bootstrap with FlexCAN—autobaud disabled ...............................................................793
34.5.6.1 Configuration ................................................................................................793
34.6 FlexCAN boot mode download protocol ......................................................................................794
34.6.1 Autobaud feature .............................................................................................................794
34.6.1.1 Configuration ................................................................................................795
34.6.1.2 Boot from UART with autobaud enabled .....................................................795
34.6.1.2.1Choosing the host baud rate ................................................................796
34.6.1.3 Boot from FlexCAN with autobaud enabled ................................................799
34.6.1.3.1Choosing the host baud rate ............................................................801
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34.6.2 Interrupt ..........................................................................................................................802
Chapter 35
Inter-Integrated Circuit Bus Controller Module (I2C)
35.1 Introduction ...................................................................................................................................803
35.1.1 Overview .........................................................................................................................803
35.1.2 Features ...........................................................................................................................803
35.1.3 Modes of Operation ........................................................................................................804
35.1.4 Block Diagram ................................................................................................................804
35.2 External Signal Description ..........................................................................................................804
35.2.1 Overview .........................................................................................................................804
35.2.2 Detailed Signal Descriptions ..........................................................................................805
35.2.2.1 SCL ...............................................................................................................805
35.2.2.2 SDA ..............................................................................................................805
35.3 Memory Map/Register Definition .................................................................................................805
35.3.1 Overview .........................................................................................................................805
35.3.2 Module Memory Map .....................................................................................................805
35.3.3 Register Descriptions ......................................................................................................806
35.3.3.1 I2C Address Register ....................................................................................806
35.3.3.2 I2C Frequency Divider Register ...................................................................806
35.3.3.3 I2C Control Register .....................................................................................813
35.3.3.4 I2C Status Register ........................................................................................814
35.3.3.5 I2C Data I/O Register ....................................................................................815
35.3.3.6 I2C Interrupt Config Register .......................................................................816
35.4 Functional Description ..................................................................................................................816
35.4.1 General ............................................................................................................................816
35.4.2 I-Bus Protocol ................................................................................................................816
35.4.2.1 START Signal ...............................................................................................817
35.4.2.2 Slave Address Transmission .........................................................................818
35.4.2.3 Data Transfer .................................................................................................818
35.4.2.4 STOP Signal ..................................................................................................818
35.4.2.5 Repeated START Signal ...............................................................................819
35.4.2.6 Arbitration Procedure ...................................................................................819
35.4.2.7 Clock Synchronization ..................................................................................819
35.4.2.8 Handshaking .................................................................................................820
35.4.2.9 Clock Stretching ............................................................................................820
35.4.3 Interrupts .........................................................................................................................820
35.4.3.1 General ..........................................................................................................820
35.4.3.2 Interrupt Description .....................................................................................820
35.5 Initialization/Application Information ..........................................................................................821
35.5.1 I2C Programming Examples ...........................................................................................821
35.5.1.1 Initialization Sequence ..................................................................................821
35.5.1.2 Generation of START ...................................................................................821
35.5.1.3 Post-Transfer Software Response .................................................................821
35.5.1.4 Generation of STOP ......................................................................................822
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35.5.1.5 Generation of Repeated START ...................................................................823
35.5.1.6 Slave Mode ...................................................................................................823
35.5.1.7 Arbitration Lost .............................................................................................823
Chapter 36
Fast Ethernet Controller (FEC)
36.1 Overview .......................................................................................................................................825
36.1.1 Features ...........................................................................................................................827
36.2 Modes of Operation .......................................................................................................................828
36.2.1 Full- and Half-Duplex Operation ....................................................................................828
36.2.2 Interface Options .............................................................................................................828
36.2.2.1 10-Mbps and 100-Mbps Media Independent Interface (MII) .......................828
36.2.3 Address Recognition Options .........................................................................................828
36.2.4 Internal Loopback ...........................................................................................................828
36.3 Memory Map and Register Definition ..........................................................................................828
36.3.1 Top Level Module Memory Map ....................................................................................829
36.3.2 Detailed Memory Map (Control/Status Registers) .........................................................829
36.3.3 Message Information Block (MIB) Counters Memory Map ..........................................830
36.3.4 Register Descriptions ......................................................................................................832
36.3.4.1 Ethernet Interrupt Event Register (EIR) .......................................................832
36.3.4.2 Ethernet Interrupt Mask Register (EIMR) ....................................................834
36.3.4.3 Receive Descriptor Active Register (RDAR) ...............................................835
36.3.4.4 Transmit Descriptor Active Register (TDAR) ..............................................836
36.3.4.5 Ethernet Control Register (ECR) ..................................................................837
36.3.4.6 MII Management Frame Register (MMFR) .................................................838
36.3.4.7 MII Speed Control Register (MSCR) ...........................................................839
36.3.4.8 MIB Control Register (MIBC) .....................................................................841
36.3.4.9 Receive Control Register (RCR) ..................................................................841
36.3.4.10 Transmit Control Register (TCR) .................................................................843
36.3.4.11 Physical Address Low Register (PALR) .......................................................844
36.3.4.12 Physical Address Upper Register (PAUR) ....................................................845
36.3.4.13 Opcode/Pause Duration Register (OPDR) ....................................................845
36.3.4.14 Descriptor Individual Address Upper Register (IAUR) ...............................846
36.3.4.15 Descriptor Individual Address Lower Register (IALR) ...............................847
36.3.4.16 Descriptor Group Address Upper Register (GAUR) ....................................847
36.3.4.17 Descriptor Group Address Lower Register (GALR) ....................................848
36.3.4.18 Transmit FIFO Watermark Register (TFWR) ...............................................849
36.3.4.19 FIFO Receive Bound Register (FRBR) ........................................................849
36.3.4.20 FIFO Receive Start Register (FRSR) ............................................................850
36.3.4.21 Receive Buffer Descriptor Ring Start Register (ERDSR) ............................851
36.3.4.22 Transmit Buffer Descriptor Ring Start Register (ETDSR) ...........................852
36.3.4.23 Maximum Receive Buffer Size Register (EMRBR) .....................................852
36.4 Functional Description ..................................................................................................................853
36.4.1 Network Interface Options ..............................................................................................853
36.4.2 FEC Frame Transmission ................................................................................................854
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36.4.2.1 Transmit Inter-Packet Gap (IPG) Time .........................................................855
36.4.2.2 Collision Handling ........................................................................................855
36.4.2.3 Transmission Error Handling ........................................................................855
36.4.2.3.1Transmitter Underrun .........................................................................855
36.4.2.3.2Retransmission Attempts Limit Expired .............................................856
36.4.2.3.3Late Collision ......................................................................................856
36.4.2.3.4Heartbeat .............................................................................................856
36.4.3 FEC Frame Reception .....................................................................................................856
36.4.3.1 Receive Inter-Packet Gap (IPG) Time ..........................................................857
36.4.3.2 Ethernet Address Recognition ......................................................................857
36.4.3.2.1Hash Algorithm ...................................................................................860
36.4.3.3 Reception Error Handling .............................................................................863
36.4.3.3.1Overrun ...............................................................................................863
36.4.3.3.2Non-Octet (Dribbling Bits) .................................................................863
36.4.3.3.3CRC
863
36.4.3.3.4Frame Length Violation ......................................................................864
36.4.3.3.5Truncation ...........................................................................................864
36.4.4 Full-Duplex Flow Control ..............................................................................................864
36.4.5 Internal and External Loopback ......................................................................................865
36.5 Initialization/Application Information ..........................................................................................865
36.5.1 Initialization Sequence ....................................................................................................865
36.5.1.1 Hardware Controlled Initialization ...............................................................865
36.5.1.2 User Initialization (Prior to Asserting ECR[ETHER_EN]) ..........................866
36.5.1.3 Microcontroller Initialization ........................................................................866
36.5.1.4 User Initialization (after asserting ECR[ETHER_EN]) ................................867
36.5.2 Buffer Descriptors ...........................................................................................................867
36.5.2.1 Driver/DMA Operation with Buffer Descriptors ..........................................867
36.5.2.2 Ethernet Transmit Buffer Descriptor (TxBD) ...............................................868
36.5.2.2.1Driver/DMA Operation with Transmit Buffer Descriptors ................869
36.5.2.3 Ethernet Receive Buffer Descriptor (RxBD) ................................................870
36.5.2.3.1Driver/DMA Operation with Receive Buffer Descriptors ..................871
Chapter 37
IEEE 1588
37.1
37.2
37.3
37.4
37.5
37.6
37.7
37.8
Introduction ...................................................................................................................................873
IEEE1588 Block Diagram .............................................................................................................874
Time Stamp Unit (TSU) Key Features ..........................................................................................874
IEEE1588 Real Time Clock (RTC) Key Features .........................................................................875
IEEE1588 Implementation Assumptions ......................................................................................876
Modes of Operation .......................................................................................................................876
Memory Map/Register Definition .................................................................................................877
Time Stamp Unit Mode Registers .................................................................................................879
37.8.1 Time Stamp Unit Parsing Definitions Register 1 (PTP_TSPDR1) .................................879
37.8.2 Time Stamp Unit Parsing Definitions Register 2(PTP_TSPDR2) ..................................880
37.8.3 Time Stamp Unit Parsing Definitions Register 3 (PTP_TSPDR3) .................................881
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37.8.4 Time Stamp Unit Parsing Definitions Register 4 (PTP_TSPDR4) .................................882
37.8.5 Time Stamp Unit Parsing Definitions Register 5 (PTP_TSPDR5) .................................883
37.8.6 Time Stamp Unit Parsing Definitions Register 6 (PTP_TSPDR6) .................................884
37.8.7 Time Stamp Unit Parsing Definitions Register 7 (PTP_TSPDR7) .................................886
37.8.8 Time Stamp Unit Parsing Offset Values (PTP_TSPOV) ................................................887
37.8.9 Time Stamp Unit Mode Register (PTP_TSMR) .............................................................889
37.8.10Timer PTP Event Register (PTP_TMR_PEVENT)/ Timer PTP Mask Register
(PTP_TMR_PEMASK) ..............................................................................................................890
37.8.11Time Stamp Unit Receiver Time High (TMR_UC_RXTS_H)/Time Stamp Unit Receiver
Time Low (TMR_UC_RXTS_L)/Time Stamp Unit Transmitter Time High
(TMR_UC_TXTS_H)/Time Stamp Unit Transmitter Time Low (TMR_UC_TXTS_L) ...........893
37.9 IEEE1588 Timer Mode Registers .................................................................................................894
37.9.1 Timer Control Register (TMR_CTRL) ...........................................................................894
37.9.2 Timer Event Register (TMR_TEVENT)/Timer Event Mask Register (TMR_TEMASK)
.........................................................................................................................................896
37.9.3 Timer Counter Register (TMR_CNT_L/TMR_CNT_H) ...............................................898
37.9.4 Timer Addend Register (TMR_ADD) ............................................................................899
37.9.5 Timer Accumulator Register (TMR_ACC) ....................................................................900
37.9.6 Timer Prescale Register (TMR_PRSC) ..........................................................................901
37.9.7 Timer Offset Register (TMROFF_L/TMROFF_H) .......................................................902
37.9.8 Alarm Time Register (TMR_ALARM_L/TMR_ALARM_H) ......................................903
37.9.9 Timer Fixed Interval Period Register (TMR_FIPERn) ..................................................903
37.9.10FIPER Start Register (TMR_FSV_L/TMR_FSV_H) .....................................................905
37.9.11External Trigger Time Stamp Register (TMR_ETTS_L/TMR_ETTS_H) .....................905
37.10 Time Stamp Unit (TSU) ................................................................................................................906
37.10.1PTP Event Interrupts .......................................................................................................907
37.11 IEEE1588 Real Time Clock (RTC) ...............................................................................................908
37.11.1RTC Clock Sources .........................................................................................................910
37.11.2Prescale Output Clock and Pulse per Second Edge Alignment ......................................910
37.12 PTP Frame Reception ....................................................................................................................910
37.12.1Out-of-Band Mode ..........................................................................................................910
37.13 PTP Frame Transmission ...............................................................................................................911
37.14 Cycle Delay from Time Stamp Location .......................................................................................911
37.15 Initialization Sequence ..................................................................................................................911
37.15.1TSU Mode Registers .......................................................................................................911
37.15.2RTC Mode Registers .......................................................................................................912
37.15.3Enable Sequence .............................................................................................................912
Chapter 38
Nexus Debug Interface (NDI)
38.1 Overview .......................................................................................................................................913
38.1.1 Features ...........................................................................................................................913
38.2 Nexus Port Controller (NPC) ........................................................................................................914
38.2.1 Features ...........................................................................................................................914
38.2.2 Modes of Operation ........................................................................................................914
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38.3
38.4
38.5
38.6
38.2.2.1 Reset ..............................................................................................................915
38.2.2.2 Disabled-Port Mode ......................................................................................915
38.2.2.3 Full-Port Mode ..............................................................................................915
External Signal Description ..........................................................................................................915
38.3.1 Overview .........................................................................................................................915
38.3.2 Detailed Signal Descriptions ..........................................................................................916
38.3.2.1 EVTO_B - Event Out ....................................................................................916
38.3.2.2 MDO - Message Data Out ............................................................................916
38.3.2.3 MSEO_B - Message Start/End Out ..............................................................916
38.3.2.4 TCK - Test Clock Input .................................................................................916
38.3.2.5 TDI - Test Data Input ....................................................................................916
38.3.2.6 TDO - Nexus Test Data Output ....................................................................917
38.3.2.7 TMS - Test Mode Select ...............................................................................917
Register Definition ........................................................................................................................917
38.4.1 Register Descriptions ......................................................................................................917
38.4.1.1 Bypass Register .............................................................................................917
38.4.1.2 Instruction Register .......................................................................................917
38.4.1.3 Nexus Device ID Register (DID) ..................................................................918
38.4.1.4 Port Configuration Register (PCR) ...............................................................919
Functional Description ..................................................................................................................921
38.5.1 NPC_HNDSHK module .................................................................................................921
38.5.2 NPC Reset Configuration ...............................................................................................922
38.5.3 Auxiliary Output Port .....................................................................................................922
38.5.3.1 Output Message Protocol ..............................................................................922
38.5.3.2 Output Messages ...........................................................................................923
38.5.3.3 Rules of Message ..........................................................................................924
38.5.4 IEEE 1149.1-2001 (JTAG) TAP .....................................................................................925
38.5.4.1 Enabling the NPC TAP controller .................................................................925
38.5.4.2 Retrieving device IDCODE ..........................................................................927
38.5.4.3 Loading NEXUS-ENABLE Instruction .......................................................927
38.5.4.4 Selecting a Nexus Client Register ................................................................928
38.5.5 Nexus JTAG Port Sharing ..............................................................................................929
38.5.6 MCKO and ipg_sync_mcko ...........................................................................................929
38.5.7 EVTO Sharing ................................................................................................................929
38.5.8 Nexus Reset Control .......................................................................................................929
Initialization/Application Information ..........................................................................................929
38.6.1 Accessing NPC tool-mapped registers ...........................................................................929
Chapter 39
Register Protection (REG_PROT)
39.1 Introduction ...................................................................................................................................931
39.1.1 Overview .........................................................................................................................931
39.1.2 Features ...........................................................................................................................931
39.1.3 Modes of Operation ........................................................................................................932
39.2 External Signal Description ..........................................................................................................932
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39.3 Memory Map and Register Definition ..........................................................................................932
39.3.1 Memory Map ..................................................................................................................933
39.3.2 Register Descriptions ......................................................................................................934
39.3.2.1 Module Registers (MR0-6143) .....................................................................934
39.3.2.2 Module Register and Set Soft Lock Bit (LMR0-6143) ................................934
39.3.2.3 Soft Lock Bit Register (SLBR0-1535) .........................................................934
39.3.2.4 Global Configuration Register (GCR) ..........................................................935
39.4 Functional Description ..................................................................................................................936
39.4.1 General ............................................................................................................................936
39.4.2 Change Lock Settings .....................................................................................................937
39.4.2.1 Change Lock Settings Directly Via Area #4 .................................................937
39.4.2.2 Enable Locking Via Mirror Module Space (Area #3) ..................................938
39.4.2.3 Write Protection for Locking Bits .................................................................939
39.4.3 Access Errors ..................................................................................................................940
39.5 Initialization/Application Information ..........................................................................................940
39.5.1 Reset ................................................................................................................................940
39.5.2 Writing C code using the register protection scheme .....................................................940
39.6 Registers under protection .............................................................................................................942
Chapter 40
Temperature Sensor (TSENS)
40.1
40.2
40.3
40.4
Introduction ...................................................................................................................................955
Features .........................................................................................................................................955
Signals ...........................................................................................................................................955
Memory Map and Register Description ........................................................................................956
40.4.1 Memory Map ..................................................................................................................956
40.5 Modes of operation ........................................................................................................................956
40.6 Obtaining the device temperature using TSENS ...........................................................................956
40.6.1 TSENS calibration constants ..........................................................................................956
40.6.2 Equations for converting TSENS voltage to device temperature ...................................957
Chapter 41
JTAG Controller (JTAGC)
41.1 Introduction ...................................................................................................................................959
41.1.1 Overview .........................................................................................................................959
41.1.2 Features ...........................................................................................................................960
41.1.3 Modes of Operation ........................................................................................................960
41.1.3.1 Reset ..............................................................................................................960
41.1.3.2 IEEE 1149.1-2001 Defined Test Modes .......................................................960
41.1.3.3 Bypass Mode .................................................................................................961
41.2 External Signal Description ..........................................................................................................961
41.2.1 Overview .........................................................................................................................961
41.2.2 Detailed Signal Descriptions ..........................................................................................961
41.2.2.1 TCK - Test Clock Input .................................................................................961
41.2.2.2 TDI - Test Data Input ....................................................................................961
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41.2.2.3 TDO - Test Data Output ................................................................................961
41.2.2.4 TMS - Test Mode Select ...............................................................................962
41.3 Register Definition ........................................................................................................................962
41.3.1 Register Descriptions ......................................................................................................962
41.3.1.1 Instruction Register .......................................................................................962
41.3.1.2 Bypass Register .............................................................................................962
41.3.1.3 Device Identification Register ......................................................................963
41.3.1.4 CENSOR_CTRL Register ............................................................................963
41.3.1.5 Boundary Scan Register ................................................................................964
41.4 Functional Description ..................................................................................................................964
41.4.1 JTAGC Reset Configuration ...........................................................................................964
41.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port ..................................................................964
41.4.3 TAP Controller State Machine ........................................................................................965
41.4.3.1 Enabling the TAP Controller ........................................................................967
41.4.3.2 Selecting an IEEE 1149.1-2001 Register ......................................................967
41.4.4 JTAGC Block Instructions ..............................................................................................967
41.4.4.1 IDCODE Instruction .....................................................................................968
41.4.4.2 SAMPLE/PRELOAD Instruction .................................................................968
41.4.4.3 SAMPLE Instruction ....................................................................................968
41.4.4.4 EXTEST — External Test Instruction ..........................................................968
41.4.4.5 ENABLE_CENSOR_CTRL Instruction ......................................................968
41.4.4.6 CLAMP Instruction ......................................................................................969
41.4.4.7 ACCESS_AUX_TAP_x Instructions ............................................................969
41.4.4.8 BYPASS Instruction .....................................................................................969
41.4.5 Boundary Scan ................................................................................................................969
41.5 Initialization/Application Information ..........................................................................................969
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About This Book
This reference manual describes the MPC5604E processor for software and hardware developers.
Information regarding bus timing, signal behavior, and AC, DC, and thermal characteristics are detailed
in the device data sheet (MPC5604E Microcontroller Data Sheet).
The information in this book is subject to change without notice, as described in the disclaimers on the title
page. As with any technical documentation, the reader needs to make sure to use the most recent version
of the documentation.
To locate any published errata or updates for this document, refer to the world-wide web at
http://www.freescale.com/powerpc.
Audience
This manual is intended for system software and hardware developers and applications programmers who
want to develop products with the MPC5604E processor. It is assumed that the reader understands
operating systems, microprocessor system design, basic principles of software and hardware, and basic
details of the PowerPC® architecture.
Chapter Organization and Device-Specific Information
This document includes chapters that describe:
• The device as a whole
• The functionality of the individual modules on the device
In the latter, any device-specific information is presented in the section “Information Specific to This
Device” at the beginning of the chapter, where the chapter may describe a superset of features.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about PowerPC architecture.
General Information
Useful information about the PowerPC architecture and computer architecture in general:
• Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture
(MPCFPE32B)
• Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross
Bannatyne, Joseph D. Greenfield
• Computer Architecture: A Quantitative Approach, Second Edition, by John L. Hennessy and David
A. Patterson.
• Computer Organization and Design: The Hardware/Software Interface, Second Edition, David A.
Patterson and John L. Hennessy.
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
1
PowerArchitecture Documentation
Power Architecture documentation is available from the sources listed on the back cover of this manual,
as well as our web site, http://www.freescale.com/powerpc.
• Reference manuals (formerly called user’s manuals)—These books provide details about
individual PowerPC implementations and are intended to be used in conjunction with the PowerPC
Programmers Reference Manual.
• Addenda/errata to reference manuals—Because some processors have follow-on parts, an
addendum is provided that describes the additional features and functionality changes. Also, if
mistakes are found within a reference manual, an errata document may be issued before the next
published release of the reference manual. These addenda/errata are intended for use with the
corresponding reference manuals.
• Data sheets—Data sheets provide specific information regarding pin-out diagrams, bus timing,
signal behavior, and AC, DC, and thermal characteristics, as well as other design considerations.
• Product briefs—Each device has a product brief that provides an overview of its features. This
document is roughly equivalent to the overview (Chapter 1) of a device’s reference manual.
• Application notes—These short documents address specific design issues useful to programmers
and engineers working with Freescale Semiconductor processors.
Additional literature is published as new processors become available. For a current list of PowerPC
documentation, refer to http://www.freescale.com/powerpc.
Conventions
This document uses the following notational conventions:
cleared/set
When a bit takes the value zero, it is said to be cleared; when it takes a value of
one, it is said to be set.
reserved
When a bit or address is reserved, it should not be written. If read, its value cannot
be not guaranteed. Reading or writing to reserved bits or addresses may cause
unexpected results.
MNEMONICS
In text, instruction mnemonics are shown in uppercase.
mnemonics
In code and tables, instruction mnemonics are shown in lowercase.
italics
Italics indicate variable command parameters.
Book titles in text are set in italics.
0x0
Prefix to denote hexadecimal number
0b0
Prefix to denote binary number
REG[FIELD]
Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges
appear in brackets. For example, RAMBAR[BA] identifies the base address field
in the RAM base address register.
nibble
byte
halfword
A 4-bit data unit
An 8-bit data unit
A 16-bit data unit1
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word
doubleword
x
~
&
|
A 32-bit data unit
A 64-bit data unit
In some contexts, such as signal encodings, x (without italics) indicates a “don’t
care” condition.
With italics, used to express an undefined alphanumeric value (e.g., a variable in
an equation); or a variable alphabetic character in a bit, register, or module name
(e.g., DSPI_x could refer to DSPI_A or DSPI_B).
Used to express an undefined numerical value; or a variable numeric character in
a bit, register, or module name (e.g., EIFn could refer to EIF1 or EIF0).
NOT logical operator
AND logical operator
OR logical operator
||
OVERBAR
Field concatenation operator
An overbar indicates that a signal is active-low.
x
n
Register Figure Conventions
This document uses the following conventions for the register reset values:
w1c
Write 1 to clear the bit to 0.
—
Undefined at reset or “not applicable.”
U
Bit value is uninitialized upon reset.
u
Bit value is unchanged upon reset.
[signal_name]
Reset value is determined by the polarity of the indicated signal.
The following register fields are used:
R
0
Indicates a reserved bit field in a memory-mapped register. These bits are always read as zeros.
1
Indicates a reserved bit field in a memory-mapped register. These bits are always read as ones.
W
R
W
R FIELDNAME
Indicates a read/write bit.
W
R FIELDNAME
Indicates a read-only bit field in a memory-mapped register.
W
1The
only exceptions to this appear in the discussion of serial communication modules that support variable-length data
transmission units. To simplify the discussion these units are referred to as words regardless of length.
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3
R
Indicates a write-only bit field in a memory-mapped register.
W FIELDNAME
R FIELDNAME
W
w1c
R
0
Write 1 to clear: indicates that writing a 1 to this bit field clears it.
Indicates a self-clearing bit.
W FIELDNAME
Acronyms and Abbreviations
Table i lists acronyms and abbreviations used in this document.
Table i. Acronyms and Abbreviated Terms
Term
Meaning
ADC
Analog-to-digital conversion
ALU
Arithmetic logic unit
BDM
Background debug mode
BIST
Built-in self test
BSDL
Boundary-scan description language
CODEC
Code/decode
DAC
Digital-to-analog conversion
DMA
Direct memory access
DSP
Digital signal processing
EA
Effective address
FIFO
First-in, first-out
GPIO
General-purpose I/O
IEEE
Institute for Electrical and Electronics Engineers
IFP
Instruction fetch pipeline
IPL
Interrupt priority level
JEDEC
Joint Electron Device Engineering Council
JTAG
Joint Test Action Group
LIFO
Last-in, first-out
LRU
Least recently used
LSB
Least-significant byte
lsb
Least-significant bit
MAC
Multiply accumulate unit, also Media access controller
MSB
Most-significant byte
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Table i. Acronyms and Abbreviated Terms (continued)
Term
Meaning
msb
Most-significant bit
Mux
Multiplex
NC
No connection
NOP
No operation
OEP
Operand execution pipeline
PC
Program counter
PLIC
Physical layer interface controller
PLL
Phase-locked loop
PIN
Referring to an external pin or ball (i.e. external signal)
POR
Power-on reset
RISC
Reduced instruction set computing
Rx
Receive
SOF
Start of frame
STAC
Shared Time and Counter
TAP
Test access port
TTL
Transistor transistor logic
Tx
UART
USB
Transmit
Universal asynchronous/synchronous receiver transmitter
Universal serial bus
Terminology Conventions
Table ii shows terminology conventions used throughout this document.
Table ii. Notational Conventions
Instruction
Operand Syntax
Opcode Wildcard
cc
Logical condition (example: NE for not equal)
Register Specifications
An
Ay,Ax
Any address register n (example: A3 is address register 3)
Source and destination address registers, respectively
Dn
Any data register n (example: D5 is data register 5)
Dy,Dx
Source and destination data registers, respectively
Rc
Any control register (example VBR is the vector base register)
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Table ii. Notational Conventions (continued)
Instruction
Operand Syntax
Rm
MAC registers (ACC, MAC, MASK)
Rn
Any address or data register
Rw
Destination register w (used for MAC instructions only)
Ry,Rx
Xi
Any source and destination registers, respectively
Index register i (can be an address or data register: Ai, Di)
Miscellaneous Operands
#<data>
<ea>
<ea>y,<ea>x
<label>
Immediate data following the 16-bit operation word of the instruction
Effective address
Source and destination effective addresses, respectively
Assembly language program label
<list>
List of registers for MOVEM instruction (example: D3–D0)
<shift>
Shift operation: shift left (<<), shift right (>>)
<size>
Operand data size: byte (B), word (W), longword (L)
bc
Instruction and data caches
dc
Data cache
ic
Instruction cache
# <vector>
<>
<xxx>
Identifies the 4-bit vector number for trap instructions
identifies an indirect data address referencing memory
identifies an absolute address referencing memory
dn
Signal displacement value, n bits wide (example: d16 is a 16-bit displacement)
SF
Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations)
Operations
+
Arithmetic addition or postincrement indicator
–
Arithmetic subtraction or predecrement indicator
x
Arithmetic multiplication
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Table ii. Notational Conventions (continued)
Instruction
Operand Syntax
/
Arithmetic division
~
Invert; operand is logically complemented
&
Logical AND
|
Logical OR
^
Logical exclusive OR
<<
Shift left (example: D0 << 3 is shift D0 left 3 bits)
>>
Shift right (example: D0 >> 3 is shift D0 right 3 bits)
→
Source operand is moved to destination operand
←→
Two operands are exchanged
sign-extended
All bits of the upper portion are made equal to the high-order bit of the lower portion
If <condition>
then
<operations>
else
<operations>
Test the condition. If true, the operations after then are performed. If the condition is false and the
optional else clause is present, the operations after else are performed. If the condition is false and
else is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an
example.
Subfields and Qualifiers
{}
Optional operation
()
Identifies an indirect address
dn
Displacement value, n-bits wide (example: d16 is a 16-bit displacement)
Address
Calculated effective address (pointer)
Bit
Bit selection (example: Bit 3 of D0)
lsb
Least significant bit (example: lsb of D0)
LSB
Least significant byte
LSW
Least significant word
msb
Most significant bit
MSB
Most significant byte
MSW
Most significant word
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Chapter 1
Overview
1.1
Chipset overview
The MPC5604E microcontroller is a gateway system designed to move data from different sources via
Ethernet to a receiving system and vice versa. The supported data sources and sinks are:
• Video data (with 8/10/12 bits per data word)
• Audio data (6× stereo channels)
• RADAR data (2 × 12 bit with <1μs per sample, digitized externally and read in via SPI)
• Other serial communication interfaces including CAN, LIN, and SPI
The Ethernet module has a bandwidth of 10/100 Mbits/sec and supports precision time stamps
(IEEE1588). Unshielded twisted pair cables are used to transfer data (via Ethernet) in the car, resulting in
a significant reduction of wiring costs by providing inexpensive high bandwidth data links.
The core selected for the device is the Harvard bus interface version of the e200z0 to cover the low-end
chassis application space.
The e200 processor family is a set of CPU cores that implement low-cost versions of the Power
Architecture Book E architecture. The e200 processors are designed for deeply embedded control
applications that require low cost solutions rather than maximum performance. The e200z0 processor
integrates an integer execution unit, branch control unit, instruction fetch and load/store units, and a
multi-ported register file capable to sustaining three read and two write operations per clock. Most integer
instructions execute in a single clock cycle. Branch target prefetching is performed by branch unit to allow
single-cycle branches in some cases. The e200z0 core is a single-issue, 32-bit Power Architecture Book E
VLE only design with 32-bit general purpose registers (GPRs). All arithmetic instructions that execute in
the core operate on data in the general purpose registers (GPRs). Instead of the base Power Architecture
Book E instruction set support, the e200z0 core only implements the VLE (variable length encoding) APU,
providing improved code density.
The MPC5604E has a single level of memory hierarchy consisting of 96 KB on-chip SRAM and 578 KB
(512 KB code + 64 KB data) of on-chip flash memory. Both the SRAM and the flash memory can hold
instructions and data.
Multimedia support is provided by a video encoder module and a 6× stereo audio (SAI) module.
The timer functions of MPC5604E are performed by the eTimer Modular Timer System and Peripheral
Interrupt Timer (PIT) modules. The eTimer module implements enhanced timer features (six channels)
including dedicated motor control quadrature decode functionality and DMA support. The PIT module
includes four general purpose interrupt timers (32-bit counters) with DMA support for each channel.
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Overview
Off-chip communication is performed by a suite of serial protocols including CANs, ethernet, enhanced
SPIs (DSPI), and SCIs (LINFlex).
The System Integration Unit Lite (SIUL) performs several chip-wide configuration functions. Pad
configuration and general-purpose input/output (GPIO) are controlled from the SIUL. External interrupts
are also found in the SIUL.
As the MPC5604E is built on a wider legacy of Power Architecture-based devices, when applicable and
possible, reusing or enhancement of existing IP, design and concepts is adopted.
1.2
Target applications
This device is a gateway system to move data from different sources via Ethernet to a receiving system
and vice versa. The supported data sources/sinks combined with the Ethernet are:
• Video data (with 8/10/12 bits per data word)
• Audio data (6x stereo channels)
• RADAR data (2x 12 bit with <1us per sample, digitized externally and read in via SPI)
• Other Serial communication interfaces like CAN, LIN, and SPI
The Ethernet has a bandwidth of 10/100 Mbits/sec supporting precision time stamps (IEEE1588).
Unshielded twisted pair cables are then used to transfer information (via Ethernet) in the car. Thus, a
significant reduction of wiring costs in the car can be achieved by providing high bandwidth data links.
The Ethernet AVB is an upcoming high-bandwidth communication standard in the automotive area
competing with established protocols like LVDS, MOST, and FlexRay (to a sudden extend for some
chassis applications).
1.3
Features
The table provides a summary of the features of the MPC5604E.
Table 1. Device summary
MPC5604E
Feature
100-pin LQFP1
CPU
64-pin LQFP
e200z0h, 64 MHz, VLE only, no SPE
Flash with ECC
CFlash: 512 KB (LC) DFlash: 64 KB (LC, area optimized)
RAM with ECC
96 KB
DMA
16 channels
PIT
yes
SWT
yes
FCU
yes
Ethernet
Video Encoder
100 Mbits MII
100 Mbits MII-Lite
8bpp/12bpp
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Overview
Table 1. Device summary (continued)
MPC5604E
Feature
100-pin LQFP1
Audio Interface
6x Stereo (4x synchronous + 2x synchronous/asynchronous)
1× 4 channels + VDD_IO + VDDCore + TSens
ADC (10-bit)
1×6 channels
Timer I/O (eTimer)
2×
SCI (LINFlex)
SPI (DSPI)
DSPI_0: 2 chip selects
DSPI_1: 2 chip selects
DSPI_2: 4 chip selects
CAN (FlexCAN)
1×
IIC
2×
Supply
3.3 V IO
1.2V Core with dedicated ballast source pin in two modes:
• internal ballast or
• external supply (using power on reset pin)
1× FMPLL
Phase Lock Loop (PLL)
Internal RC Oscillator
16 MHz
External crystal
Oscillator
4 MHz - 40 MHz
CRC
Debug
yes
JTAG, Nexus2+
Ambient Temperature
1
1.4
64-pin LQFP
JTAG
–40 to 125 °C
The 100-pin package is not a production package. It is used for software development only.
Block diagram
Figure 1 shows a top-level block diagram of the MPC5604E microcontroller.
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Overview
Internal and
External Ballast
e200z0 Core
32-bit
General
Purpose
Registers
Integer
Execution
Unit
Special
Purpose
Registers
Exception
Handler
Instruction
Unit
Variable
Length
Encoded
Instructions
Branch
Prediction
Unit
Load/Store
Unit
1.2 V Regulator
Control
XOSC
16 MHz
RC Oscillator
FMPLL
(System)
JTAG
Nexus2+
JTAG Port
Nexus2+
eDMA
16 channels
Instruction Bus
(32-bit)
Master
Interrupt
Controller
Data Bus
(32-bit)
Master
FEC
Master
PTP
MII
Master
96 KB
SRAM
(ECC)
PDI
TSENS
ME
PCU
video_clk
Slave
MJPEG
64 KB
Data
Flash
(ECC)
Slave
Output
Buffer
512 KB
Code
Flash
(ECC)
Slave
RGM
Slave
CGM
Crossbar Switch (XBAR, AMBA 2.0 v6 AHB)
ADC
BAM
CRC
DSPI
eDMA
eTimer
FCD
FCU
FEC
FlexCAN
FMPLL
I2C
SAI
LINFlex
ME
Analog-to-Digital Converter
Boot Assist Module
Cylic Redundancy Check
Deserial Serial Peripheral Interface
Enhanced Direct Memory Access
Enhanced Timer
Fractional Clock Divider
Fault Collection Unit
Fast Ethernet Controller
Flexible Controller Area Network
Frequency-Modulated Phase-Locked Loop
Inter-Integrated Circuit serial interface
Serial Audio Interface 6xStereo
Serial Communication Interface (LIN support)
Mode Entry Module
CGM
PCU
RGM
TSENS
MJPEG
PDI
PIT
PTP
SIUL
SRAM
SSCM
STM
SWT
FCU
SIUL
BAM
SWT
STM
PIT
SSCM
FCD
3 x SAI
3 x I2C
CRC
FlexCAN
3 x DSPI
2 x LINFlex
ADC
10-bit
4+3 channels
eTimer
Peripheral Bridge
Clock Generation Module
Power Control Unit
Reset Generation Module
Temperature sensor
12-bit Motion JPEG Encoder
Parallel Data Interface (image sensor)
Periodic Interrupt Timer
IEEE 1588 Precision Time Stamps
System Integration Unit
Static Random-Access Memory
System Status and Configuration Module
System Timer Module
Software Watchdog Timer
Figure 1. MPC5604E block diagram
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Overview
1.5
Application examples
The following sections contain examples of applications for the MPC5604E microcontroller.
1.5.1
CMOS vision sensor gateway
The active safety and advanced driver assistance systems (ADAS) support Panorama View Park-Assist
providing a high quality view of the vehicle’s surroundings (typically a bird's eye view).
For this, up to 5 CMOS cameras with wide-angle lenses attached to the car. A typical installation has one
camera at each corner of the front bumper, one in each side mirror and one in the rear. The front-viewing
sensors cannot be combined with the front-viewing camera sensor used for active safety applications due
to completely different optical requirements. All sensors are connected to a central fusion Electronic
Control Unit (ECU) that performs enhancement and image generation.
First, the fusion unit corrects the wide-angle distortion in each image, if not done optically. Alternatively,
there is an inexpensive optical solution (2nd inverting lens) on the market.
The next step is the stitching of the images—similar to the feature found on many of today’s digital
cameras. There is a broad range of algorithm complexity depending on the required quality. In principle,
similarities in adjacent images need to identified, e.g., by running matching filters. After identifying how
the images fit geometrically together, there is some post-processing necessary for a smooth appearance
within the overlapping areas.
Finally, the stitched images are rendered on a 3D grid model representing the chosen perspective to
generate the final image.
The interconnect between the remote cameras and central fusion unit is done in a point-to-point manner
with a switch located in the central ECU. The switch combines the Ethernet AVB streams and sends them,
e.g., via GigE, to the central processing unit. Future systems with more ADAS nodes (e.g., cameras and
RADARs in the bumper) might have two dedicated ADAS switches.
Figure 2 illustrates a multi-camera system based on the MPC5604E.
Video
MPC5604E Gateway
.
.
.
100 Mb/s
Control
Switch
3–5 Sensor Units
1 Gb/s
Fusion
Unit
Video
MPC5604E Gateway
Control
100 Mb/s
Figure 2. Multi-camera system level diagram
Each camera in Figure 2 is connected to one MPC5604E gateway via a parallel digital interface as shown
in Figure 3. The raw data is buffered and the color component is vertically sub-sampled from YUV4:2:2
to YUV4:2:0. A low latency video encoder compresses the image data by a factor of 1:5/1:10 or higher
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Overview
into a bit stream. This compression is not lossless, thus, the quality of the image is degraded with higher
compression ratios. The video bitstream is then buffered in the MPC5604E (dedicated video bit stream
buffer) and transmitted via the Ethernet AVB link.
6V
3.3 V /
1.5 V
clk
XTAL
MPC5604E
ctrl
image
Imager
sync
3.3 V
Vreg
I2C or DSPI
PDI
MII
Ethernet
PHY
Ethernet
Transformer
Nexus
debugging
Workstation
Figure 3. MPC5604E interfacing for CMOS sensor gateway
Figure 4 illustrates the processing flow of video data within the MPC5604E.
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Overview
Internal
Ballast
e200z0 Core @ 64MHz
32-bit
General Purpose
Registers
16MHz
RC Oscillator
JTAG Port
Nexus2+
JTAG
Nexus2+
FMPLL
(System)
eDMA
16 Channels
Instruction
Bus
(32-bit)
Special Purpose
Registers
Exception
Handler
Instruction
Unit
Variable Length
Encoded
Instructions
Branch
Prediction
Unit
Load/Store
Unit
Interrupt
Controller
Data
Bus
(32-bit)
PTP +
CE_RTC
FEC
Master
Master
Master
Master
Cross Bar Switch (XBAR, AMBA 2.0v6 AHB)
Output Buffer
96kB
SRAM
(ECC)
PCU
64kB
Data Flash
(ECC)
Slave
ME
512kB
Code Flash
(ECC)
video_clk1
Slave
CGM
Slave
RGM
Slave
MII
PDI
Integer
Execution
Unit
XOSC
MJPEG
1.2V
Regulator
Control
System
Integration
Unit
Boot Assist
Module
SWT
STM
PIT
SSCM
3x FCD
3xI2S/I2 ST DM
2x IIC
CRC
FlexCAN
3x DSPI
2x LinFlex
eTimer
ADC
10-bit
4+3 Channels
Peripheral Bridge
Camera
(1280x800@30fps,
10-bits/pix)
1. video_clk frequency can be 120/128 MHz depending on the system_clk (60/64 MHz).
Video Encoding:
Video data is captured by the camera, and streamed via the PDI to the Video Encoder (MJPEG). The MJPEG offers the encoded
data via an output buffer memory to the FEC (Ethernet).
Besides the video data, also histograms (for exposure control) are streamed to the PDI. The PDI separates these data that are
moved via DMA to the SRAM. The CPU processes the information and set up the exposure/white balance via the IIC in the camera.
Figure 4. MPC5604E video data path
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Overview
1.6
Audio source gateway
The MPC5604E can be effectively used as an audio source gateway. Figure 5 shows the data flow for this
application. Six stereo input audio channels at 44.1 KHz or 48 KHz are provided via I2S by an external
audio source (radio, CD/DVD player, etc.). The external device provides the clock for its data (master).
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Overview
Internal
Ballast
e200z0 Core @ 64MHz
32-bit
General Purpose
Registers
16MHz
RC Oscillator
JTAG Port
Nexus2+
JTAG
Nexus2+
FMPLL
(System)
eDMA
16 Channels
Instruction
Bus
(32-bit)
Special Purpose
Registers
Exception
Handler
Instruction
Unit
Variable Length
Encoded
Instructions
Branch
Prediction
Unit
Load/Store
Unit
Interrupt
Controller
Data
Bus
(32-bit)
Master
Master
Master
Master
Cross Bar Switch (XBAR, AMBA 2.0v6 AHB)
Output Buffer
video_clk1
Slave
96KB
SRAM
(ECC)
PCU
64KB
Data Flash
(ECC)
ME
512KB
Code Flash
(ECC)
Slave
CGM
Slave
RGM
Slave
MII
PTP +
CE_RTC
FEC
PDI
Integer
Execution
Unit
XOSC
MJPEG
1.2V
Regulator
Control
System
Integration
Unit
Boot Assist
Module
SWT
STM
PIT
SSCM
3x FCD
3xI2S/I2 ST DM
2x IIC
CRC
FlexCAN
3x DSPI
2x LinFlex
eTimer
ADC
10-bit
4+3 Channels
Peripheral Bridge
Not
used
Audio Source
with 11.29MHz
Audio Clock
1. video_clk frequency can be 120/128 MHz depending on the system_clk (60/64 MHz).
Audio In:
Data is sampled based on the input signals SAI_BCLK (11.29MHz) and SAI_SYNC. The I2S module (SAI) buffers the
input data (6 channels) and signals the availability of data to the DMA module (in 64MHz domain). The DMA module
moves the data to the SRAM. From here the FEC can move the data via the MII interface to a receiver.
Figure 5. Audio to ethernet data path
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Overview
1.7
Critical performance parameters
MPC5604E is running under the following critical performance corner points:
• Maximum CPU frequency: 64 MHz
• Junction temperature range: –40 °C to 150 °C1
• Nominal power dissipation: Less than 1.5 W
• Supply voltages:
— VDD_HV_IO = 3.3V
— VDD_HV_ADC = 3.3V
— VDD_LV_CORE= 1.2 V (with internal ballast or external supply)
1.8
Chip-level features
On-chip modules available within the family include the following features:
•
•
•
•
•
•
•
32-bit Power Architecture® embedded CPU (e200z0h) with single issue and Harvard architecture
Memory
— 512 KB on-chip Code Flash with ECC and erase/program controller
— additional 64 (4 × 16) KB on-chip Data Flash with ECC for EEPROM emulation
— 96 KB on-chip SRAM with ECC
Fail-safe protection
— Programmable watchdog timer
— Non-maskable interrupt
— Fault collection unit
Nexus 2+ interface
Interrupts and events
— 16-channel eDMA controller
— 16 priority level controller
— Up to 25 external interrupts
— PIT implements four 32-bit timers
— 120 interrupts are routed via INTC
General purpose I/Os
— Individually programmable as input, output or special function
— 39 on LQFP64
— 71 on LQFP1002
1 general purpose eTimer unit
— 6 timers each with up/down capabilities
1.Ambient temperature is 125 °C, for the video use case with internal core voltage supply the ambient temperature is
105 °C.
2.The 100-pin package is not a production package. It is used for software development only.
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Overview
•
•
•
•
•
•
•
•
— 16-bit resolution, cascadeable counters
— Quadrature decode with rotation direction flag
— Double buffer input capture and output compare
Communications interfaces
— 2 LINFlex channels (1 × Master/Slave, 1 × Master Only)
— 3 DSPI channels with automatic chip select generation (up to 2/2/4 chip selects)
— 1 FlexCAN interface (2.0B Active) with 32 message buffers
One 10-bit analog-to-digital converter (ADC)
— 7 input channels: 4 channels routed to the pins, 3 internal connections (Temperature sensor,
Core voltage, IO voltage)
— Conversion time < 1 μs including sampling time at full precision
— 4 analog watchdogs with interrupt capability
On-chip CAN/UART bootstrap loader with Boot Assist Module (BAM)
100 MBit Fast Ethernet Controller (FEC)
— Supports precision timestamps
— MII on 100-pin1 LQFP package
— MII-lite on 64-pin LQFP package
Video encoder
6x stereo audio interface
I2C controller module
CRC module
Module features
1.8.1
High performance e200z0 core CPU
The e200z0 Power Architecture core provides the following features:
• High performance e200z0 core processor for managing peripherals and interrupts
• Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU
• Harvard architecture
• Variable length encoding (VLE), allowing mixed 16-bit and 32-bit instructions
• Results in smaller code size footprint
• Minimizes impact on performance
• Branch processing acceleration using lookahead instruction buffer
• Load/store unit
• 1-cycle load latency
• Misaligned access support
1. The 100-pin package is not a production package. It is used for software development only.
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Overview
•
•
•
•
•
•
•
•
1.8.2
No load-to-use pipeline bubbles
Thirty-two 32-bit general purpose registers (GPRs)
Separate instruction bus and load/store bus Harvard architecture
Hardware vectored interrupt support
Reservation instructions for implementing read-modify-write constructs
Long cycle time instructions, except for guarded loads, do not increase interrupt latency
Extensive system development support through Nexus debug port
Non Maskable Interrupt support
Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and
four slave ports. The crossbar supports a 32-bit address bus width and a 32-bit data bus width.
The crossbar allows for concurrent transactions to occur from any master port to any slave port. If a slave
port is simultaneously requested by more than one master port, arbitration logic will select the higher
priority master and grant it ownership of the slave port. All other masters requesting that slave port will be
stalled until the higher priority master completes its transactions. The default priority scheme is fixed
priority based on the master ID. Besides this, the software can select a round robin arbitration.
The crossbar provides the following features:
• Four master ports
— e200z0 core complex Instruction port
— e200z0 core complex Load/Store Data port
— eDMA
— Ethernet
• Four slave ports
— Flash memory (code flash and data flash) controller
— SRAM controller
— Video encoder output buffer
— Peripheral bridge
• 32-bit internal address, 32-bit internal data paths
• Fixed Priority Arbitration based on port master
• Temporary dynamic priority elevation of masters
1.8.3
System clocks and clock generation
The following list summarizes the system clock and clock generation on the MPC5604E:
• Lock detect circuitry continuously monitors lock status
• Loss of clock (LOC) detection for PLL outputs
• Programmable output clock divider (÷1, ÷2, ÷4, ÷8)
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Overview
•
•
•
•
•
1.8.4
Fractional clock divider clock for close loop controlled clocks
— Provides audio clock in medium quality mode (approximately 11.29 MHz)
— Provides camera input clock (25–30 MHz)
On-chip oscillator with automatic level control
Internal 16 MHz RC oscillator for rapid start-up and safe mode
— Supports frequency trimming by user application
Ethernet TX clock as input for the PLL (via OSC input pin)
Up to 64 MHz for system clock; up to 128 MHz for video encoder clock
Frequency Modulated Phase Lock Loop (FMPLL)
The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 40 MHz input clock.
Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL
multiplication factor, output clock divider ratio are all software configurable.
The PLL has the following major features:
• Input clock frequency from 4 MHz to 40 MHz
• Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz
• Reduced frequency divider (RFD) for reduced frequency operation without forcing the PLL to
re-lock
• Frequency modulated PLL
• Modulation enabled/disabled through software
• Triangle wave modulation
• Programmable modulation depth (±0.25% to ±2% deviation from center frequency)
• Programmable modulation frequency dependent on reference frequency
• Self-clocked mode (SCM) operation
1.8.5
Main oscillator
The main oscillator provides these features:
• Input frequency range 4 MHz to 40 MHz
• Crystal input mode or Oscillator input mode
• PLL reference
1.8.6
Internal RC oscillator
This device has an RC ladder phase-shift oscillator. The architecture uses constant current charging of a
capacitor. The voltage at the capacitor is compared by the stable bandgap reference voltage.
The RC Oscillator provides these features:
• Nominal frequency 16 MHz
• ±5% variation over voltage and temperature after process trim
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Overview
•
•
1.8.7
Clock output of the RC oscillator serves as system clock source in case loss of lock or loss of clock
is detected by the PLL
RC oscillator is used as the default system clock during startup
Voltage regulator (VREG)
The on-chip voltage regulator module provides the following features:
• Available in two modes
— Using internal PMOS ballast transistor to regulate external 3.3 V down to 1.2 V for the core
logic
— Disabled for using external supply for core logic
• Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V
1.8.8
System Integration Unit (SIU-Lite)
The MPC5604E SIU-Lite controls MCU pad configuration, external interrupt, general purpose I/O
(GPIO), and internal peripheral multiplexing.
The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block
provides uniform and discrete input/output control of the I/O pins of the MCU.
The SIU provides the following features:
• Centralized general purpose input output (GPIO) control
— 71 GPIO pads (bonding to pins is package dependent)
• As many as four internal output functions can be multiplexed onto one pin
• All GPIO pins can be independently configured to support pull-up, pull down, or no pull
• Reading and writing to GPIO supported both as individual pins and 16-bit wide ports
• All peripheral pins can be alternatively configured as both general purpose input or output pins
• Direct readback of the pin value is supported on all pins through the SIU supporting 4 external
interrupts based on general purpose input pins
• Supports 4 external interrupts based on general purpose input pins (8 pads per interrupt)
• Configurable digital input filter that can be applied to general purpose input pins with interrupt
functions for noise elimination
1.8.9
Boot Assist Module (BAM)
The BAM is a block of read-only one-time programmed memory and is identical for all MPC56XX
devices that are based on the e200z0h core. The BAM program is executed every time the device is
powered-on if the alternate boot mode has been selected by the user.
The BAM provides the following features:
•
Boot from Internal Code Flash
— Selected as default (using internal pull down on FAB pin).
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Overview
•
— Censorship mode to protect the content of the flash memory.
Alternate serial boot-loading via FlexCAN, LINFlex
— BAM accepts a password via the used serial communication channel to grant the legitimate
user access to the non-volatile memory.
1.8.10
Junction temperature sensor
The MPC5604E has a junction temperature sensor to enable measurement of the temperature of the silicon
via the ADC.
The junction temperature sensor has these key parameters:
• Nominal temperature range from –40 °C to 150 °C
• Calibrated sensor accuracy:
— ±10 °C, –40 to 25 °C ambient
— ±7 °C, 25 to 125 °C ambient
1.8.11
JTAG controller (JTAGC)
The JTAG controller (JTAGC) block provides the means to test chip functionality and connectivity while
remaining transparent to system logic when not in test mode. All data input to and output from the JTAGC
block is communicated in serial format. The JTAGC block is compliant with the IEEE standard.
The JTAG controller provides the following features:
• IEEE Test Access Port (TAP) interface with four pins (TDI, TMS, TCK, TDO)
• Selectable modes of operation include JTAGC/debug or normal system operation.
• A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:
— BYPASS
— IDCODE
— EXTEST
— SAMPLE
— SAMPLE/PRELOAD
• A 5-bit instruction register that supports the additional following public instructions:
— ACCESS_AUX_TAP_NPC
— ACCESS_AUX_TAP_ONCE
• Three test data registers: a bypass register, a boundary scan register, and a device identification
register.
• A TAP controller state machine that controls the operation of the data registers, instruction register
and associated circuitry.
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Overview
1.8.12
Nexus Debug Interface (NDI)
The NDI (Nexus Debug Interface) block provides real-time development support capabilities for the
device Power Architecture based MCU in compliance with the IEEEISTO 5001-2003 standard. This
development support is supplied for MCUs without requiring external address and data pins for internal
visibility. The NDI block is an integration of several individual Nexus blocks that are selected to provide
the development support interface for this device. The NDI block interfaces to the host processor and
internal busses to provide development support as per the IEEE-ISTO 5001-2003 Class 2+ standard. The
development support provided includes access to the MCUs internal memory map and access to the
processors internal registers during run time.
The Nexus Interface provides the following features:
• Configured via the IEEE 1149.1
• All Nexus port pins operate at VDDIO (no dedicated power supply)
• Nexus 2+ features supported
• Static debug
• Watchpoint messaging
• Ownership trace messaging
• Program trace messaging
• Real time read/write of any internally memory mapped resources through JTAG pins
• Overrun control, which selects whether to stall before Nexus overruns or keep executing and allow
overwrite of information
• Watchpoint triggering for program tracing
• Auxiliary Output Port
• Four MDO (Message Data Out) pins in full port mode
• MCKO (Message Clock Out) pin
• Two MSEO (Message Start/End Out) pins
• EVTO (Event Out) pin
• Auxiliary Input Port
• EVTI (Event In) pin
1.8.13
DMA controller
The enhanced direct memory access (eDMA) controller is a second-generation module capable of
performing complex data movements via 16 programmable channels, with minimal intervention from the
host processor. The hardware micro architecture includes a DMA engine which performs source and
destination address calculations, and the actual data movement operations, along with an SRAM-based
memory containing the transfer control descriptors (TCD) for the channels. This implementation is utilized
to minimize the overall block size.
The eDMA module provides the following features:
• 16 channels support independent 8-, 16-, or 32-bit single value or block transfers
MPC5604E Reference Manual, Rev. 5
1-24
Freescale Semiconductor
Overview
•
•
•
•
•
•
•
Supports variable sized queues and circular queues
Source and destination address registers are independently configured to post-increment or remain
constant
Each transfer is initiated by a peripheral, CPU, or eDMA channel request
Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single
value or block transfer
DMA transfers possible between system memories, DSPIs, ADC, eTimer, audio interface, and
video bit stream output buffer
Programmable DMA channel mux allows assignment of any DMA source to any available DMA
channel with as many as 30 potential request sources.
eDMA abort operation through software
1.8.14
•
•
DMA channel multiplexer (DMA_MUX)
32 independently selectable DMA channel routers
Each channel router is assigned to one of the following sources:
— One of the peripheral DMA sources
— The always enabled source
1.8.15
Software Watchdog Timer (SWT)
The SWT on the MPC5604E is configured as the SWT found on MPC5604P devices. This includes, e.g.,
the reset values for the timer clock selection.
The SWT has the following features:
• 32-bit time-out register to set the time-out period
• Timer running on IRC clock for increased functional safety
• Programmable selection of window mode or regular servicing
• Programmable selection of reset or interrupt on an initial time-out
• Master access protection
• Hard and soft configuration lock bits
• Reset configuration inputs allow timer to be enabled out of reset
1.8.16
System Timer Module (STM)
The STM module implements these features:
• 32-bit up counter with 8-bit pre-scaler
• Four 32-bit compare channels
• Independent interrupt source for each channel
• Counter can be stopped in debug mode
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
1-25
Overview
1.8.17
Periodic Interrupt Timers (PIT)
The PIT module implements these features:
• As many as four general purpose interrupt timers
• 32-bit counter resolution
• Clocked by system clock frequency
• Each channel can be used as trigger for a DMA request
1.8.18
FlexCAN module
The MPC5604E MCU contains one controller area network (FlexCAN) module. This module is a
communication controller implementing the CAN protocol according to Bosch Specification version 2.0B.
The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific
requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle,
cost-effectiveness and required bandwidth. The FlexCAN module contains 32 message buffers.
The FlexCAN module provides the following features:
• Supports the full implementation of the CAN Specification Version 2.0, Part B
— Standard data and remote frames (up to 109 bits long)
— Extended data and remote frames (up to 127 bits long)
— 0 to 8 bytes data length
— Programmable bit rate up to 1 Mbit/s
— Content-related addressing
• 32 message buffers of 0 to 8 bytes data length
• Each message buffer configurable as RX or TX, all supporting standard and extended messages
• Listen-only mode capability
• Individual mask registers for each message buffer
• Programmable transmit-first scheme: lowest ID or lowest buffer number
• Timestamp based on 16-bit free-running timer
• Global network time, synchronized by a specific message
• Programmable loop-back mode supporting self-test operation
• Maskable interrupts
• Independent of the transmission medium (an external transceiver is assumed)
• High immunity to EMI
• Short latency time due to an arbitration scheme for high-priority messages
• Wake-up when activity on the RX pin
— Requires an external glitch filter at the pad (2750 ns of 0-input)
— Wake-up via CAN interrupt
• Transmit features
— Supports configuration of multiple mailboxes to form message queues of scalable depth
MPC5604E Reference Manual, Rev. 5
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Freescale Semiconductor
Overview
•
•
— Arbitration scheme according to message ID or message buffer number
— Internal arbitration to guarantee no inner or outer priority inversion
Receive features
— Individual programmable filters for each mailbox
— Eight mailboxes configurable as a six-entry receive FIFO
— Eight programmable acceptance filters for receive FIFO
Programmable clock source
— System clock
— Direct oscillator clock to avoid PLL jitter
1.8.19
Deserial Serial Peripheral Interface (DSPI)
The deserial serial peripheral interface (DSPI) module provides a synchronous serial interface for
communication between the MPC5604E MCU and external devices (e.g., sensors).
The DSPI modules provide these features:
• Full duplex, three-wire synchronous transfers
• Master or slave operation
• Programmable master bit rates
• Programmable clock polarity and phase
• End-of-transmission interrupt flag
• Programmable transfer baud rate
• Programmable data frames from 4 to 16 bits
• As many as four chip select lines available per DSPI module, depending on package and pin
multiplexing, enable 12 external devices to be selected using external multiplexing from a single
DSPI
• Eight clock and transfer attributes registers
• Chip select strobe available as alternate function on one of the chip select pins for de-glitching
• FIFOs for buffering as many as five transfers on the transmit and receive side
• Queueing operation possible through use of the eDMA
• TX and RX FIFOs can be disabled individually for low-latency updates to SPI queues
• Visibility into TX and RX FIFOs for ease of debugging
• Programmable transfer attributes on a per-frame basis
• Modified SPI transfer formats for communication with slower peripheral devices
1.8.20
Serial communication interface module (LINFlex)
The LINFlex on the MPC5604E features the following:
• Supports LIN Master mode, LIN Slave mode and UART mode
• LIN state machine compliant to LIN1.3, 2.0, and 2.1 Specifications
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
1-27
Overview
•
•
•
•
Handles LIN frame transmission and reception without CPU intervention
LIN features
— Autonomous LIN frame handling
— LIN0 supports master and slave mode with 16 identifier filters
— LIN1 supports master mode only (no identifier filters required)
— Message buffer to store Identifier and as much as 8 data bytes
— Supports message length as long as 64 bytes
— Detection and flagging of LIN errors: Sync field; Delimiter; ID parity; Bit; Framing; Checksum
and Time-out errors
— Classic or extended checksum calculation
— Configurable Break duration as long as 36-bit times
— Programmable Baud rate pre-scalers (13-bit mantissa, 4-bit fractional)
— Diagnostic features: Loop back; Self Test; LIN bus stuck dominant detection
— Interrupt-driven operation with 16 interrupt sources
LIN slave mode features
— Autonomous LIN header handling
— Autonomous LIN response handling
UART mode
— Full-duplex operation
— Standard non return-to-zero (NRZ) mark/space format
— Data buffers with 4-byte receive, 4-byte transmit
— Configurable word length (8-bit or 9-bit words)
— Error detection and flagging
— Parity, Noise and Framing errors
— Interrupt-driven operation with four interrupt sources
— Separate transmitter and receiver CPU interrupt sources
— 16-bit programmable baud-rate modulus counter and 16-bit fractional
— Two receiver wake-up methods
1.8.21
eTimer
The eTimer module provides six 16-bit general purpose up/down timer/counter.
The following features are implemented:
• Individual channel capability
— Input capture trigger
— Output compare
— Double buffer (to capture rising edge and falling edge)
— Separate pre-scaler for each counter
MPC5604E Reference Manual, Rev. 5
1-28
Freescale Semiconductor
Overview
•
•
•
•
•
•
•
— Selectable clock source
— 0% to 100% pulse measurement
— Rotation direction flag (Quad decoder mode)
Maximum count rate
Counters are cascadeable
Programmable count modulo
Quadrature decode capabilities
Counters can share available input pins
Count once or repeatedly
Counters are pre-loadable
1.8.22
Successive approximation Analog-to-Digital Converter (ADC)
The ADC module provides the following features:
• Analog part:
— One on-chip AD converter
— 10-bit AD resolution
— Conversion time, including sampling time, less than 1 μs (at full precision)
— Typical sampling time is 150 ns min. (at full precision)
— Differential non-linearity error (DNL) ±1 LSB
— Integral non-linearity error (INL) ±1.5 LSB
— TUE < 3 LSB
— Single-ended input signal range from 0 to VDD_HV_ADC
— The ADC supply can be equal to VDD_HV_IO (VDD_HV_ADC = 3.3 V)
— The ADC supply and the ADC reference are not independent from each other (they are
internally bonded to the same pad)
— Sample times of 2 (default), 8, 64, or 128 ADC clock cycles
• Digital part:
— 8 input channels
– 4 channels routed to the pins
– 3 internal connections: 1× temperature sensor, 1× core voltage, 1× IO voltage
— Four analog watchdogs comparing ADC results against predefined levels (low, high, range)
before results are stored in the appropriate ADC result location,
— Register-based interface with the CPU: control register, status register, and one result register
per channel
— ADC state machine managing 3 request flows: regular command, hardware injected command
through eTimer and software injected command
— DMA compatible interface
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
1-29
Overview
1.8.23
Fault Collection Unit (FCU)
The FCU provides an independent fault reporting mechanism even when the CPU is not performing
properly.
The FCU module includes following features:
• Collection of critical faults (all of these must be glitch free)
• Reporting of selected critical faults to external
• Fault flag status kept over non-destructive reset for later analysis (in a "Freeze" register)
• Continous and synchronous latch of MC state
• MC state kept over non-destructive reset for later analysis (in a "Freeze" register)
• 4 states finite state machine (Init, Normal, Alarm, Fault)
• Different actions can be taken depending on fault type.
• Selectable protocols for fault signal indication in Fault state (dual-rail, time-switching, bi-stable)
• Programmable clock prescaler for time-switching output signal generation
• Protection mechanism to avoid un-wanted clearing of fault flags
• Internal logic testing, by using a fake fault generator during initialization phase
1.8.24
Cyclic Redundancy Check (CRC)
The CRC has the following major features:
• 2 contexts (static parameter) for the concurrent CRC computation
• Separate CRC engine for each context
• 0-wait states during the CRC computation (pipeline scheme)
• 3 hardwired polynomials (CRC-8, CRC-16-CCITT, CRC-32)
• Support for byte/half-word/word width of the input data stream
1.8.25
•
•
•
•
•
•
•
Image resolution up to 1280×800 at 30 fps
Low latency compression with MJPEG format
Color sub-sampling from YUV4:2:2 to YUV4:2:0
8 bits per pixel component
12 bits per pixel component
Support compression ratio from 1:20 to 1:5
Support for the Ethernet Controller DMA via CPU Interrupt
1.8.26
•
•
Video encoder
Serial Audio Interface (SAI)
Supports up to 6 (stereo) audio channels
Transmitter with independent Bit Clock and Frame Sync supporting 4 data channels
MPC5604E Reference Manual, Rev. 5
1-30
Freescale Semiconductor
Overview
•
•
•
•
•
Receiver with independent Bit Clock and Frame Sync supporting 4 data channels
Maximum Frame Size of 16 Words
Word size of between 8-bits and 32-bits Word size configured separately for first word and
remaining words in frame
Asynchronous 8 × 32-bit FIFO for each Transmit and Receive Channel
Restarts after FIFO Error
1.8.27
Ethernet AVB (FEC + PTP + RTC)
The Ethernet modules provide 100 MBits/s data communication for all use cases. To support Ethernet
AVB (Audio Video Bridging), this module group consists of following modules:
• FEC (Ethernet base module)
• PTP (IEEE 1588 precision time protocol)
• RTC (Real time clock required for precision time protocol)
MPC5604E does not integrate the PHY components of the Ethernet, thus, the FEC connects via the
MII-Lite interface (14 pins) to the external PHY. In addition to the MII-Lite interface, the RTC provides a
single timer pin that is directly linked to the precision time.
Support for different Ethernet MAC-PHY interfaces:
• 100 Mbits/s IEEE 802.3 MII-Lite 1
• 10 Mbits/s IEEE 802.3 MII-Lite
• IEEE 802.3 full duplex flow control and half duplex flow
• Programmable max frame length
• Address recognition
• Word size configured separately for first word and remaining words in frame
• Asynchronous 4 x 32-bit FIFO for each Transmit and Receive Channel
• Graceful restart after FIFO Error:
— Frames with broadcast address may be always accepted or always rejected
— Exact match for single 48-bit individual (unicast) address
— Asynchronous 4 x 32-bit FIFO for each Transmit and Receive Channel
— Hash (64-bit hash) check of individual (unicast) address
— Hash (64-bit hash) check of group (multicast) address
— Promiscuous mode
• Internal loop-back
1.8.27.1
Precision Time Protocol
Hardware assistance for IEEE1588 Precision Time Protocol v1.0
• Supports user configured values for PTP header fields
• Support timestamp overrun report for TX and RX
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
1-31
Overview
•
•
Supports interrupts notification due to following: RX PTP frame detection, TX
PTP frame transmission which was marked by the Software as a PTP frame, RX and TX timestamp
overrun error
1.8.27.2
RTC
Support single IEEE1588 RTC
• Support timer frequency compensation
• Support timer offset update
• One 64-bit FIPER start register. Used to define the starting time of PPS signals generation
• Support timer frequency compensation
• Separate maskable timer interrupt event register
• Phase aligned adjustable (divide by N) clock output
The MPC5604E MCU tools and third-party developers are similar to those used for the Freescale
MPC5500 product family, offering a widespread, established network of tool and software vendors. The
device also features a high-performance Nexus debug interface.
MPC5604E Reference Manual, Rev. 5
1-32
Freescale Semiconductor
Chapter 2
Memory Map
Table 2 shows the memory map for the MPC5604E device. All addresses on the MPC5604E, including
those that are reserved, are identified in the table. The addresses represent the physical addresses assigned
to each IP block.
Table 2. System memory map
Start
Address
End
Address
Size
(KB)
Description
On-Chip Flash Memory (Code Flash)
0x0000_0000
0x0000_3FFF
16
0x0000_4000
0x0000_7FFF
16
0x0000_8000
0x0000_FFFF
32
0x0001_0000
0x0000_17FF
32
0x0001_8000
0x0001_BFFF
16
0x0001_C000
0x0001_FFFF
16
0x0002_0000
0x0002_FFFF
64
0x0003_0000
0x0003_FFFF
64
0x0004_0000
0x0005_FFFF
128
0x0006_0000
0x0007_FFFF
128
0x0008_0000
0x001F_FFFF
1536
Code Flash Array 0
Reserved
On-Chip Flash Memory (Shadow for Code Flash)
0x0020_0000
0x0020_3FFF
16
Code Flash Array 0 Shadow Sector
0x0020_4000
0x003F_FFFF
2032
Reserved
On-Chip Flash Memory (Test Sector for Code Flash)
0x0040_0000
0x0040_3FFF
16
Code Flash Array 0 Test Sector
0x0040_4000
0x005F_FFFF
2032
Reserved
On-Chip Flash Memory (Data Flash)
0x0080_0000
0x0080_3FFF
16
Data Flash Array 0
0x0080_4000
0x0080_7FFF
16
Data Flash Array 0
0x0080_8000
0x0080_BFFF
16
Data Flash Array 0
0x0080_C000
0x0080_FFFF
16
Data Flash Array 0
MPC5604E Reference Manual Rev. 5
Freescale Semiconductor
2-33
Memory Map
Table 2. System memory map (continued)
Start
Address
0x0081_0000
End
Address
0x009F_FFFF
Size
(KB)
1984
Description
Reserved
On-Chip Flash Memory (Shadow Sector for Data Flash)
0x00A0_0000
0x00BF_FFFF
2048
Reserved
On-Chip Flash Memory (Test Sector for Data Flash)
0x00C0_0000
0x00C0_1FFF
8
Reserved
0x00C0_2000
0x00C0_3FFF
8
Data Flash Test Sector
0x00C0_4000
0x00FF_FFFF
4080
Reserved
Emulation Mapping
0x0100_0000
0x01FF_FFFF
524288
Reserved
SRAM
0x4000_0000
0x4000_9FFF
40
SRAM
0x4000_A000
0x4000_FFFF
24
SRAM
0x4001_0000
0x4001_7FFF
32
SRAM
0x4001_8000
0x4FFF_FFFF
262048
Reserved
0x5000_0000
0x5000_1FFF
8
Video Output Buffer
0x5000_2000
0x5000_3FFF
8
Mirrored Video Output Buffer (from 0x50000000)
0x5000_4000
0x5FFF_FFFF
262128
Reserved
0x6000_0000
0x7FFF_FFFF
524288
Reserved
Table 3. Peripheral memory map
Start
Address
Size
(KB)
End
Address
ME_PCTL
Description
0xC3F8_0000
0xC3F8_7FFF
32
—
Reserved
0xC3F8_8000
0xC3F8_BFFF
16
—
Code Flash Configuration 0 (CFLASH0)
0xC3F8_C000
0xC3F8_FFFF
16
—
Data Flash Configuration (DFLASH0)
0xC3F9_0000
0xC3F9_3FFF
16
—
System Integration Unit Lite (SIUL)
0xC3F9_4000
0xC3F9_7FFF
16
—
WakeUP Unit (WKUP)
0xC3F9_8000
0xC3FD_7FFF
256
—
Reserved
0xC3FD_8000
0xC3FD_BFFF
16
—
System Status and Configuration Module (SSCM)
0xC3FD_C000
0xC3FD_FFFF
16
—
Mode Entry (MC_ME)
MPC5604E Reference Manual, Rev. 5
2-34
Freescale Semiconductor
Memory Map
Table 3. Peripheral memory map
Start
Address
Size
(KB)
End
Address
ME_PCTL
Description
0xC3FE_0000
0xC3FE_3FFF
16
—
Clock related modules
Note: Refer to Table 7 for details.
0xC3FE_4000
0xC3FE_7FFF
16
—
Reset Generation Module (MC_RGM)
0xC3FE_8000
0xC3FE_BFFF
16
—
Power Control Unit (MC_PCU)
0xC3FE_C000
0xC3FE_FFFF
16
—
Reserved
0xC3FF_0000
0xC3FF_3FFF
16
92
Periodic Interrupt Timer (PTI)
0xC3FF_4000
0xC3FF_FFFF
48
—
Reserved
AIPS(0) - Off Platform Peripherals
0xFFE0_0000
0xFFE0_3FFF
16
32
Analog to Digital Converter 0 (ADC0)
0xFFE0_4000
0xFFE1_7FFF
80
—
Reserved
0xFFE1_8000
0xFFE1_BFFF
16
38
eTimer 0
0xFFE1_C000
0xFFE2_FFFF
80
—
Reserved
0xFFE3_0000
0xFFE3_3FFF
16
44
Inter IC Bus Interface Controller 0 (I2C0)
0xFFE3_4000
0xFFE3_7FFF
16
45
Inter IC Bus Interface Controller 1 (I2C1)
0xFFE3_8000
0xFFE3_FFFF
32
—
Reserved
0xFFE4_0000
0xFFE4_3FFF
16
48
LinFlex 0
0xFFE4_4000
0xFFE4_7FFF
16
49
LinFlex 1
0xFFE4_8000
0xFFE6_7FFF
128
—
Reserved
0xFFE6_8000
0xFFE6_BFFF
16
58
Cyclic Redundany Checker (CRC)
0xFFE6_C000
0xFFE6_FFFF
16
—
Fault Collection Unit (FCU)
0xFFE7_0000
0xFFE7_3FFF
16
—
Reserved
0xFFE7_4000
0xFFE7_7FFF
16
61
Precision Time Stamps (PTP)
0xFFE7_8000
0xFFE7_BFFF
16
62
Real-Time Counter (CE_RTC)
0xFFE7_C000
0xFFE7_FFFF
80
—
Reserved
AIPS(0) - Off Platform Peripherals (mirrored from AIPS(1) range 0xC3F80000 - 0xC3FFFFFF)
0xFFE8_0000
0xFFEF_FFFF
512
—
Mirrored
AIPS(0) - On Platform Peripherals
0xFFF0_0000
0xFFF3_7FFF
224
—
Reserved
0xFFF3_8000
0xFFF3_BFFF
16
—
Software Watchdog Timer 0 (SWT0)
0xFFF3_C000
0xFFF3_FFFF
16
—
System Timer Module 0 (STM0)
0xFFF4_0000
0xFFF4_3FFF
16
—
Miscellaneous Control Module (MCM)
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
2-35
Memory Map
Table 3. Peripheral memory map
Start
Address
Size
(KB)
End
Address
ME_PCTL
Description
0xFFF4_4000
0xFFF4_7FFF
16
—
Direct Memory Access Controller 0 (DMA2x)
0xFFF4_8000
0xFFF4_BFFF
16
—
Interrupt Controller (INTC)
AIPS(0) - Off Platform Peripherals
0xFFF4_C000
0xFFF4_FFFF
16
—
Ethernet (FEC)
0xFFF5_0000
0xFFF7_FFFF
192
—
Reserved
0xFFF8_0000
0xFFF8_FFFF
64
—
Reserved
0xFFF9_0000
0xFFF9_3FFF
16
4
DSPI 0
0xFFF9_4000
0xFFF9_7FFF
16
5
DSPI 1
0xFFF9_8000
0xFFF9_BFFF
16
6
DSPI 2
0xFFF9_C000
0xFFFB_FFFF
144
—
Reserved
0xFFFC_0000
0xFFFC_3FFF
16
16
FlexCan 0 (CAN0)
0xFFFC_4000
0xFFFD_7FFF
80
—
Reserved
0xFFFD_8000
0xFFFD_BFFF
16
22
SAI 0
0xFFFD_C000
0xFFFD_FFFF
16
23
DMA Channel Multiplexer (DMA_CH_MUX)
0xFFFE0000
0xFFFE_FFFF
64
—
Reserved
0xFFFF0000
0xFFFF_3FFF
16
28
SAI 1
0xFFFF4000
0xFFFF_7FFF
16
29
SAI 2
0xFFFF8000
0xFFFF_BFFF
16
30
Video Data Path/Parallel Digital Interface (PDI)
0xFFFFC000
0xFFFF_FFFF
16
—
Boot Assist Module (BAM)
MPC5604E Reference Manual, Rev. 5
2-36
Freescale Semiconductor
Chapter 3
Signal Description
3.1
Introduction
This chapter describes signals that connect off-chip. It includes a signal properties summary, power and
ground segmentation summary, package pinouts, and detailed descriptions of signals. Because the
MPC5604E comes in multiple packages, some signals may not be available on every package. Refer to the
MPC5604E Microcontroller Data Sheet for electrical characteristics.
3.2
Signal Properties Summary
Table 4 shows the signals properties for each pin on MPC5604E. For all port pins that have an associated
SIU_PCRn register to control pin properties, the supported functions column lists the functions associated
with the programming of the SIU_PCRn[PA] bit in the order: general-purpose input/output (GPIO),
function 1, function 2, and function 3. When an alternate function is not implemented for a value of
SIU_PCRn[PA], a dash is shown in the Description column and the respective value in the PA bitfield is
reserved.
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
3-37
Signal Description
Table 4. Pin muxing
Port
pin
PCR
register
Alternate
function1,2,8
Functions
3
Peripheral
I/O
direction4
Pad speed5
SRC = 0
Pin6
SRC = 1
64-pin
100-pin7
Port A (16-bit)
A[0]
PCR[0]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[0]
D[0]
—
—
D[11]
SIN
EIRQ[0]
SIUL
SAI0
—
—
VID
DSPI 1
SIUL
I/O
I/O
—
—
I
I
I
Slow
Medium
2
2
A[1]
PCR[1]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[1]
D[1]
SOUT
—
D[10]
EIRQ[1]
SIUL
SAI0
DSPI1
—
VID
SIUL
I/O
I/O
O
—
I
I
Slow
Medium
3
4
A[2]
PCR[2]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[2]
D[2]
SCK
D[0]
D[9]
ETC[5]
EIRQ[2]
SIUL
SAI0
DSPI1
SAI1
VID
ETIMER0
SIUL
I/O
I/O
I/O
I/O
I
I
I
Slow
Medium
4
6
A[3]
PCR[3]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[3]
D[3]
—
D[0]
D[8]
SIN
EIRQ[3]
SIUL
SAI0
—
SAI2
VID
DSPI2
SIUL
I/O
I/O
—
I/O
I
I
I
Slow
Medium
5
8
A[4]
PCR[4]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[4]
SYNC
SOUT
—
D[7]
ETC[3]
EIRQ[4]
SIUL
SAI0
DSPI2
—
VID
ETIMER0
SIUL
I/O
I/O
O
—
I
I
I
Slow
Medium
8
15
A[5]
PCR[5]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[5]
SYNC
SCK
D[0]
CLK
ETC[4]
EIRQ[5]
SIUL
SAI1
DSPI2
SAI1
VID
ETIMER0
SIUL
I/O
I/O
I/O
I/O
I
I
I
Medium
Fast
9
16
MPC5604E Reference Manual, Rev. 5
3-38
Freescale Semiconductor
Signal Description
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2,8
Functions
3
Peripheral
I/O
direction4
Pad speed5
SRC = 0
SRC = 1
Pin6
64-pin
100-pin7
A[6]
PCR[6]
ALT0
ALT1
ALT2
ALT3
—
—
—
—
GPIO[6]
SYNC
CS0
—
VSYNC
D[0]
ETC[1]
EIRQ[6]
SIUL
SAI2
DSPI2
—
VID
VID
ETIMER0
SIUL
I/O
I/O
I/O
—
I
I
I
I
Slow
Medium
10
17
A[7]
PCR[7]
ALT0
ALT1
ALT2
ALT3
—
—
—
—
GPIO[7]
BCLK
CS1
—
HREF
D[1]
ETC[2]
EIRQ[7]
SIUL
SAI0
DSPI2
—
VID
VID
ETIMER0
SIUL
I/O
I/O
I/O
—
I
I
I
I
Slow
Medium
16
23
A[8]
PCR[8]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[8]
BCLK
CS0
D[0]
D[6]
RX
EIRQ[8]
SIUL
SAI1
DSPI1
SAI2
VID
LIN1
SIUL
I/O
I/O
I/O
I/O
I
I
I
Slow
Medium
24
37
A[9]
PCR[9]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[9]
BCLK
CS1
TX
D[5]
EIRQ[9]
SIUL
SAI2
DSPI1
LIN1
VID
SIUL
I/O
I/O
I/O
O
I
I
Slow
Medium
25
38
A[10]
PCR[10]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[10]
MCLK
ETC[5]
—
D[4]
SIN
EIRQ[10]
SIUL
SAI2
ETIMER0
—
VID
DSPI0
SIUL
I/O
I/O
I/O
—
I
I
I
Slow
Medium
26
39
A[11]
PCR[11]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[11]
TX
CS1
CS0
D[3]
RX
RX
SIUL
CAN0
DSPI0
DSPI1
VID
LIN0
LIN1
I/O
O
O
I/O
I
I
I
Slow
Medium
27
40
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
3-39
Signal Description
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2,8
Functions
3
Peripheral
I/O
direction4
Pad speed5
SRC = 0
Pin6
SRC = 1
64-pin
100-pin7
A[12]
PCR[12]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[12]
TX
CS0
TX
D[2]
RX
EIRQ[11]
SIUL
LIN0
DSPI0
LIN1
VID
CAN0
SIUL
I/O
O
I/O
O
I
I
I
Slow
Medium
28
41
A[13]
PCR[13]
ALT0
ALT1
ALT2
ALT3
—
GPIO[13]
CLK
F[0]
CS0
EIRQ[12]
SIUL
IIC1
FCU0
DSPI0
SIUL
I/O
I/O
O
I/O
I
Slow
Medium
29
42
A[14]
PCR[14]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[14]
DATA
F[1]
CS1
SIN
EIRQ[13]
SIUL
IIC1
FCU0
DSPI0
DSPI0
SIUL
I/O
I/O
O
O
I
I
Slow
Medium
30
43
A[15]
PCR[15]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[15]
SCK
PPS3
MCLK
SCK
ETC[0]
EIRQ[18]
SIUL
DSPI0
CE_RTC
SAI1
DSPI1
ETIMER0
SIUL
I/O
I/O
O
I/O
I
I
I
Slow
Medium
61
95
Port B (16-bit)
B[0]
PCR[16]
ALT0
ALT1
ALT2
ALT3
—
GPIO[16]
TX
ALARM2
BCLK
AN[0]
SIUL
CAN0
CE_RTC
SAI1
ADC08
I/O
O
O
I/O
I
Slow
Medium
17
26
B[1]
PCR[17]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[17]
—
—
D[0]
AN[1]
RX
TRIGGER2
SIUL
—
—
SAI1
ADC08
CAN0
CE_RTC
I/O
—
—
I/O
I
I
I
Slow
Medium
18
27
B[2]
PCR[18]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[18]
TX
PPS2
ALARM1
AN[2]
TRIGGER1
SIUL
LIN0
CE_RTC
CE_RTC
ADC08
CE_RTC
I/O
O
O
O
I
I
Slow
Medium
19
28
MPC5604E Reference Manual, Rev. 5
3-40
Freescale Semiconductor
Signal Description
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2,8
Functions
3
Peripheral
I/O
direction4
Pad speed5
SRC = 0
SRC = 1
Pin6
64-pin
100-pin7
B[3]
PCR[19]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[19]
ETC[2]
SOUT
PPS1
AN[3]
RX
EIRQ[14]
SIUL
ETIMER0
DSPI0
CE_RTC
ADC08
LIN0
SIUL
I/O
I/O
I/O
O
I
I
I
Slow
Medium
20
29
B[4]
PCR[20]
ALT0
ALT1
ALT2
ALT3
—
GPI[20]
—
—
—
RX_DV
SIUL
—
—
—
FEC
I
—
—
—
I
Slow
Medium
32
50
B[5]
PCR[21]
ALT0
ALT1
ALT2
ALT3
GPIO[21]
TX_D0
DEBUG[0]
—
SIUL
FEC
SSCM
—
I/O
O
I/O
—
Slow
Medium
33
55
B[6]
PCR[22]
ALT0
ALT1
ALT2
ALT3
GPIO[22]
TX_D1
DEBUG[1]
—
SIUL
FEC
SSCM
—
I/O
O
I/O
—
Slow
Medium
34
56
B[7]
PCR[23]
ALT0
ALT1
ALT2
ALT3
GPIO[23]
TX_D2
DEBUG[2]
—
SIUL
FEC
SSCM
—
I/O
O
I/O
—
Slow
Medium
39
62
B[8]
PCR[24]
ALT0
ALT1
ALT2
ALT3
GPIO[24]
TX_D3
DEBUG[3]
—
SIUL
FEC
SSCM
—
I/O
O
I/O
—
Slow
Medium
44
67
B[9]
PCR[25]
ALT0
ALT1
ALT2
ALT3
GPIO[25]
TX_EN
DEBUG[4]
—
SIUL
FEC
SSCM
—
I/O
O
I/O
—
Slow
Medium
45
70
B[10]
PCR[26]
ALT0
ALT1
ALT2
ALT3
GPIO[26]
MDC
DEBUG[5]
—
SIUL
FEC
SSCM
—
I/O
O
I/O
—
Slow
Medium
46
73
B[11]
PCR[27]
ALT0
ALT1
ALT2
ALT3
GPIO[27]
MDIO
DEBUG[6]
—
SIUL
FEC
SSCM
—
I/O
I/O
I/O
—
Slow
Medium
48
75
B[12]
PCR[28]
ALT0
ALT1
ALT2
ALT3
—
GPIO[28]
—
DEBUG[7]
—
TX_CLK
SIUL
—
SSCM
—
FEC
I/O
—
I/O
—
I
Slow
Medium
49
76
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
3-41
Signal Description
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2,8
Functions
3
Peripheral
Pad speed5
I/O
direction4
SRC = 0
Pin6
SRC = 1
64-pin
100-pin7
B[13]
PCR[29]
ALT0
ALT1
ALT2
ALT3
—
GPI[29]
—
—
—
RX_D0
SIUL
—
—
—
FEC
I
—
—
—
I
Slow
Medium
50
77
B[14]
PCR[30]
ALT0
ALT1
ALT2
ALT3
—
GPI[30]
—
—
—
RX_D1
SIUL
—
—
—
FEC
I
—
—
—
I
Slow
Medium
51
79
B[15]
PCR[31]
ALT0
ALT1
ALT2
ALT3
—
GPI[31]
—
—
—
RX_D2
SIUL
—
—
—
FEC
I
—
—
—
I
Slow
Medium
52
81
Port C (64-pin: 7-bit; 100-pin: 16-bit)
C[0]
PCR[32]
ALT0
ALT1
ALT2
ALT3
—
GPI[32]
—
—
—
RX_D3
SIUL
—
—
—
FEC
I
—
—
—
I
Slow
Medium
53
82
C[1]
PCR[33]
ALT0
ALT1
ALT2
ALT3
—
—
GPI[33]
—
—
—
RX_CLK
EIRQ[15]
SIUL
—
—
—
FEC
SIUL
I
—
—
—
I
I
Slow
Medium
54
83
C[2]
PCR[34]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[34]
ETC[0]
TX
PPS1
D[0]
RX
EIRQ[16]
SIUL
ETIMER0
CAN0
CE_RTC
VID
LIN0
SIUL
I/O
I/O
O
O
I
I
I
Slow
Medium
57
91
C[3]
PCR[35]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[35]
ETC[1]
TX
SYNC
D[1]
RX
EIRQ[17]
SIUL
ETIMER0
LIN0
SAI1
VID
CAN0
SIUL
I/O
I/O
O
I/O
I
I
I
Slow
Medium
60
94
MPC5604E Reference Manual, Rev. 5
3-42
Freescale Semiconductor
Signal Description
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2,8
Functions
3
Peripheral
I/O
direction4
Pad speed5
SRC = 0
SRC = 1
Pin6
64-pin
100-pin7
C[4]
PCR[36]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[36]
CLK_OUT
ETC[4]
MCLK
TRIGGER1
ABS[0]
EIRQ[19]
SIUL
MC_CGL
ETIMER0
SAI0
CE_RTC
MC_RGM
SIUL
I/O
O
I/O
I/O
I
I
I
Medium
Fast
62
96
C[5]
PCR[37]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[37]
CLK
ETC[3]
CS2
ABS[2]
EIRQ[20]
SIUL
IIC0
ETIMER0
DSPI2
MC_RGM
SIUL
I/O
—
I/O
O
I
I
Slow
Medium
63
99
C[6]
PCR[38]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[38]
DATA
CS0
CS3
FAB
EIRQ[21]
SIUL
IIC0
DSPI1
DSPI2
MC_RGM
SIUL
I/O
—
I/O
O
I
I
Slow
Medium
64
100
C[7]
PCR[39]
ALT0
ALT1
ALT2
ALT3
—
GPIO[39]
TXD
—
—
RXD
SIUL
LIN0
—
—
LIN1
I/O
O
—
—
I
Slow
Medium
—
3
C[8]
PCR[40]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[40]
TXD
—
—
RXD
EIRQ[22]
SIUL
LIN1
—
—
LIN0
SIUL
I/O
O
—
—
I
I
Slow
Medium
—
5
C[9]
PCR[41]
ALT0
ALT1
ALT2
ALT3
—
—
GPI[41]
—
—
—
SIN
EIRQ[23]
SIUL
—
—
—
DSPI0
SIUL
I
—
—
—
I
I
Slow
Medium
—
7
C[10]
PCR[42]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[42]
ETC[5]
ETC[4]
—
SIN
EIRQ[24]
SIUL
ETIMER0
ETIMER0
—
DSPI1
SIUL
I/O
I/O
I/O
—
I
I
Slow
Medium
—
24
C[11]
PCR[43]
ALT0
ALT1
ALT2
ALT3
GPIO[43]
ETC[2]
ETC[1]
ETC[3]
SIUL
ETIMER0
ETIMER0
ETIMER0
I/O
I/O
I/O
I/O
Slow
Medium
—
25
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
3-43
Signal Description
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2,8
Functions
3
Peripheral
I/O
direction4
Pad speed5
SRC = 0
Pin6
SRC = 1
64-pin
100-pin7
C[12]
PCR[44]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[44]
PPS1
PPS2
ALARM1
TRIGGER1
TRIGGER2
EIRQ[25]
SIUL
CE_RTC
CE_RTC
CE_RTC
CE_RTC
CE_RTC
SIUL
I/O
O
O
O
I
I
I
Slow
Medium
—
44
C[13]
PCR[45]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[45]
—
—
—
D[1]
EIRQ[26]
SIUL
—
—
—
VID
SIUL
I/O
—
—
—
I
I
Slow
Medium
—
46
C[14]
PCR[46]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[46]
—
—
—
D[0]
EIRQ[27]
SIUL
—
—
—
VID
SIUL
I/O
—
—
—
I
I
Slow
Medium
—
47
C[15]
PCR[47]
ALT0
ALT1
ALT2
ALT3
—
GPI[47]
—
—
—
COL
SIUL
—
—
—
FEC
I
—
—
—
I
Slow
Medium
—
48
Port D (100-pin package: 16-bit)
D[0]
PCR[48]
ALT0
ALT1
ALT2
ALT3
GPIO[48]
MDO0
—
—
SIUL
NEXUS
—
—
I/O
O
—
—
Slow
Medium
—
9
D[1]
PCR[49]
ALT0
ALT1
ALT2
ALT3
GPIO[49]
MCK0
—
—
SIUL
NEXUS
—
—
I/O
O
—
—
Slow
Medium
—
14
D[2]
PCR[50]
ALT0
ALT1
ALT2
ALT3
GPIO[50]
EVTO
—
—
SIUL
NEXUS
—
—
I/O
O
—
—
Slow
Medium
—
13
D[3]
PCR[51]
ALT0
ALT1
ALT2
ALT3
GPIO[51]
MSEO1
—
—
SIUL
NEXUS
—
—
I/O
O
—
—
Slow
Medium
—
72
D[4]
PCR[52]
ALT0
ALT1
ALT2
ALT3
GPIO[52]
MSEO0
—
—
SIUL
NEXUS
—
—
I/O
O
—
—
Slow
Medium
—
78
MPC5604E Reference Manual, Rev. 5
3-44
Freescale Semiconductor
Signal Description
Table 4. Pin muxing (continued)
Port
pin
PCR
register
Alternate
function1,2,8
Functions
3
Peripheral
I/O
direction4
Pad speed5
SRC = 0
SRC = 1
Pin6
64-pin
100-pin7
D[5]
PCR[53]
ALT0
ALT1
ALT2
ALT3
GPIO[53]
MDO3
—
—
SIUL
NEXUS
—
—
I/O
O
—
—
Slow
Medium
—
80
D[6]
PCR[54]
ALT0
ALT1
ALT2
ALT3
GPIO[54]
MDO2
—
—
SIUL
NEXUS
—
—
I/O
O
—
—
Slow
Medium
—
84
D[7]
PCR[55]
ALT0
ALT1
ALT2
ALT3
GPIO[55]
MDO1
—
—
SIUL
NEXUS
—
—
I/O
—
—
—
Slow
Medium
—
98
D[8]
PCR[56]
ALT0
ALT1
ALT2
ALT3
—
GPI[56]
—
—
—
EVTI
SIUL
—
—
—
NEXUS
I
—
—
—
I
Slow
Medium
—
10
D[9]
PCR[57]
ALT0
ALT1
ALT2
ALT3
—
—
GPIO[57]
ETC[3]
ETC[2]
—
RXD
EIRQ[28]
SIUL
ETIMER0
ETIMER0
—
CAN0
SIUL
I/O
I/O
I/O
—
I
I
Slow
Medium
—
49
D[10]
PCR[58]
ALT0
ALT1
ALT2
ALT3
GPIO[58]
TXD
—
—
SIUL
CAN0
—
—
I/O
O
—
—
Slow
Medium
—
51
D[11]
PCR[59]
ALT0
ALT1
ALT2
ALT3
GPIO[59]
ETC[0]
ETC[5]
ETC[4]
SIUL
ETIMER0
ETIMER0
ETIMER0
I/O
I/O
I/O
I/O
Slow
Medium
—
52
D[12]
PCR[60]
ALT0
ALT1
ALT2
ALT3
—
GPIO[60]
ETC[1]
ETC[0]
—
SIN
SIUL
ETIMER0
ETIMER0
—
DSPI0
I/O
I/O
I/O
—
I
Slow
Medium
—
53
D[13]
PCR[61]
ALT0
ALT1
ALT2
ALT3
—
—
GPI[61]
—
—
—
CRS
EIRQ[29]
SIUL
—
—
—
FEC
SIUL
I
—
—
—
I
I
Slow
Medium
—
54
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
3-45
Signal Description
Table 4. Pin muxing (continued)
Port
pin
D[14]
D[15]
PCR
register
PCR[62]
PCR[63]
Alternate
function1,2,8
Functions
ALT0
ALT1
ALT2
ALT3
—
—
GPI[62]
—
—
—
ALT0
ALT1
ALT2
ALT3
3
Peripheral
I/O
direction4
Pad speed5
SRC = 0
Pin6
SRC = 1
64-pin
100-pin7
I
—
—
—
I
I
Slow
Medium
—
57
EIRQ[30]
SIUL
—
—
—
FEC
SIUL
GPIO[63]
F[0]
—
—
SIUL
FCU0
—
—
I/O
O
—
—
Slow
Medium
—
69
RX_ER
Port E (100-pin package: 7-bit)
E[0]
PCR[64]
ALT0
ALT1
ALT2
ALT3
GPIO[64]
F[1]
—
—
SIUL
FCU0
—
—
I/O
O
—
—
Slow
Medium
—
68
E[1]
PCR[65]
ALT0
ALT1
ALT2
ALT3
GPIO[65]
TX_ER
—
—
SIUL
FEC
—
—
I/O
O
—
—
Slow
Medium
—
71
E[2]
PCR[66]
ALT0
ALT1
ALT2
ALT3
—
—
GPI[66]
—
—
—
I
—
—
—
I
I
Slow
Medium
—
85
EIRQ[31]
SIUL
—
—
—
LIN1
SIUL
RXD
E[3]
PCR[67]
ALT0
ALT1
ALT2
ALT3
GPIO[67]
TXD
—
—
SIUL
LIN1
—
—
I/O
O
—
—
Slow
Medium
—
86
E[4]
PCR[68]
ALT0
ALT1
ALT2
ALT3
GPIO[68]
CS0
CS0
CS0
SIUL
DSPI0
DSPI1
DSPI2
I/O
I/O
I/O
I/O
Slow
Medium
—
89
E[5]
PCR[69]
ALT0
ALT1
ALT2
ALT3
GPIO[69]
SCK
SCK
SCK
SIUL
DSPI0
DSPI1
DSPI2
I/O
I/O
I/O
I/O
Slow
Medium
—
90
E[6]
PCR[70]
ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[70]
SOUT
SOUT
SOUT
SIN
SIN
SIN
SIUL
DSPI0
DSPI1
DSPI2
DSPI0
DSPI2
DSPI2
I/O
O
O
O
I
I
I
Slow
Medium
—
97
MPC5604E Reference Manual, Rev. 5
3-46
Freescale Semiconductor
Signal Description
1
2
3
4
5
6
7
8
ALT0 is the primary (default) function for each port after reset.
Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIU module. PCR.PA = 00 → ALT0;
PCR.PA = 01 → ALT1; PCR.PA = 10 → ALT2; PCR.PA = 11 → ALT3. This is intended to select the output functions; to use
one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA bitfields.
For this reason, the value corresponding to an input only function is reported as “—”.
Module included on the MCU.
Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the
values of the PSMIO.PADSELx bitfields inside the SIUL module.
Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register.
Additional board pull resistors are recommended when JTAG pins are not being used on the board or application.
The 100-pin package is not a production package. It is used for software development only.
Do not use ALT multiplexing when ADC channels are used.
3.3
Supply pins
Table 5 lists the supply pins for the MPC5604E.
Table 5. Supply pins
Supply
Port Pin
Multi-bonded Power
Supplies/Ground
Pin
Description
64-pin
100-pin1
VREG control and power supply pins. Pins available on 64-pin and 100-pin package.
VDD_HV_S_BALLAST
VDD_HV_S_BALLAST0
Ballast Source/Supply Voltage
VDD_HV_S_BALLAST1
Ballast Source/Supply Voltage
23
34
ADC0 reference and supply voltage. Pins available on 64-pin and 100-pin package.
VDD_HV_ADC0
ADC0 supply voltage with respect to
ground (VSS_HV_ADC)
VDD_HV_ADC0
ADC0 high reference voltage with respect
to ground (VSS_HV_ADC)
VSS_HV_ADC0
ADC0 ground voltage with respect to
ground
VSS_HV_ADC0
ADC0 low reference voltage with respect to
ground
VDD_HV_ADC
VSS_HV_ADC
21
30
22
31
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
3-47
Signal Description
Table 5. Supply pins (continued)
Supply
Port Pin
Multi-bonded Power
Supplies/Ground
Pin
Description
64-pin
100-pin1
11
18
38
61
55
87
-
36
12
19
37
60
Power supply pins (3.3 V). Pins available on 64-pin and 100-pin package.
VDD_HV
VDD_HV_IO0_0
Input/output ground voltage
VDD_HV_OSC0
Crystal oscillator amplifier supply voltage
VDD_HV_IO0_2
3.3 V Input/Output Supply Voltage (supply)
VDD_HV_FLA1
Code and data flash supply voltage
VDD_HV_IO0_3
3.3 V Input/Output Supply Voltage (supply)
VDD_HV_FLA0
Code and data flash supply voltage
VDD_HV
VSS_HV
HV Supply
VSS_HV_IO0_0
Input/output ground voltage
VSS_HV_OSC0
Crystal oscillator amplifier ground
VSS_HV_IO0_2
Input/output ground voltage
Vss_HV_FLA1
Code and data flash supply ground
Vss_IO0_4
Vss_HV_FLA0
VSS_HV
Input/output ground voltage
35
56
Code and data flash supply voltage
HV Ground
88
47
74
7
12
58
92
35
58
-
33
Power supply pins (1.2 V). Pins available on 64-pin and 100-pin package.
VDD_LV_COR0_3
VDD_LV_PLL0
VDD_LV
VDD_LV_COR0_2
VDD_LV_FLA0
VDD_LV_COR0_1
VDD_LV_FLA1
VDD_LV
1.2 V supply pins for core logic and code
Flash. Decoupling capacitor must be
connected between these pins and the
nearest VSS_LV_COR0_3 pin.
1.2 V PLL supply voltage
1.2 V supply pins for core logic and code
Flash. Decoupling capacitor must be
connected between these pins and the
nearest VSS_LV_COR0_2 pin.
Code and data flash supply voltage
1.2 V supply pins for core logic and code
Flash. Decoupling capacitor must be
connected between these pins and the
nearest VSS_LV_COR0_1 pin.
Code and data flash supply voltage
Core supply
MPC5604E Reference Manual, Rev. 5
3-48
Freescale Semiconductor
Signal Description
Table 5. Supply pins (continued)
Supply
Port Pin
Multi-bonded Power
Supplies/Ground
VSS_LV_COR0_3
VSS_LV_PLL0
VSS_LV_COR0_2
VSS_LV
VSS_LV_FLA0
VSS_LV_COR0_1
VSS_LV_FLA1
VSS_LV
1
3.4
Pin
Description
64-pin
100-pin1
6
11
59
93
36
59
-
32
1.2 V supply pins for core logic and code
Flash. Decoupling capacitor must be
connected betwee.n these pins and the
nearest VDD_LV_COR0_3 pin.
PLL supply ground
1.2 V supply pins for core logic and code
Flash. Decoupling capacitor must be
connected betwee.n these pins and the
nearest VDD_LV_COR0_2 pin.
Code and data flash supply ground
1.2 V supply pins for core logic and data
Flash. Decoupling capacitor must be
connected between these pins and the
nearest VDD_LV_COR0_1 pin.
Code and data flash supply ground
Core ground
The 100-pin package is not a production package. It is used for software development only.
System pins
Table 6 lists the system pins for the MPC5604E.
Table 6. System pins
Pad speed1
Symbol
Description
Pin
Direction
SRC = 0 SRC = 1
64-pin
100-pin
2
Dedicated pins
NMI
Non-maskable Interrupt
Input only
Slow
—
1
1
XTAL
Oscillator amplifier output
Output only
—
—
13
20
Input for oscillator amplifier circuit and
internal clock generator
Input only
—
—
14
21
TDI3
JTAG test data input
Input only
Slow
Medium
40
63
TMS3
JTAG state machine control
Input only
Slow
Medium
41
64
EXTAL
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
3-49
Signal Description
Table 6. System pins (continued)
Pad speed1
Symbol
Description
Direction
SRC = 0 SRC = 1
TCK3
TDO
3
JTAG clock
JTAG test data output
Pin
64-pin
100-pin
2
Input only
Slow
—
42
65
Output only
Slow
Medium
43
66
Bidirectional
Medium
—
15
22
Input only
—
—
31
45
Reset pin
RESET
Bidirectional reset with Schmitt trigger
characteristics and noise filter
POR_B
Power-on reset
1
SRC values refer to the value assigned to the Slew Rate Control bits of the pad configuration register.
The 100-pin package is not a production package. It is used for software development only.
3 Additional board pull resistors are recommended when JTAG pins are not being used on the board or application.
2
3.5
Pinouts
Figure 6 shows the 64-pin LQFP pin assignments. Figure 7 shows the 100-pin LQFP1 pin assignments.
For more information, see the MPC5604E Microcontroller Data Sheet.
1. The 100LQFP package is not available in production quantity—it is for development only.
MPC5604E Reference Manual, Rev. 5
3-50
Freescale Semiconductor
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
C[6]
C[5]
C[4]
A[15]
C[3]
VSS_LV
VDD_LV
C[2]
VSS_HV
VDD_HV
C[1]
C[0]
B[15]
B[14]
B[13]
B[12]
Signal Description
NMI
A[0]
A[1]
A[2]
A[3]
64 LQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
B[11]
VSS_HV
B[10]
B[9]
B[8]
TDO
TCK
TMS
TDI
B[7]
VDD_HV
VSS_HV
VSS_LV
VDD_LV
B[6]
B[5]
VDD_HV_ADC
VSS_HV_ADC
VDD_HV_S_BALLAST
A[8]
A[9]
A[10]
A[11]
A[12]
A[13]
A[14]
POR_B
B[4]
B[0]
B[1]
B[2]
B[3]
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS_LV
VDD_LV
A[4]
A[5]
A[6]
VDD_HV
VSS_HV
XTAL
EXTAL
RESET
A[7]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Note:
1. All VDD_HV and VSS_HV pins must be shorted on the board. The ADC supply
(VDD_HV_ADC) and ground (VSS_HV_ADC) should be managed independently from other
high-voltage supplies, (it may still be supplied from the same high-voltage source, but caution
must be taken while routing it on the board.)
2. All VDD_LV and VSS_LV pins must be shorted on the board.
Figure 6. 64-pin LQFP pinout (top view)
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
3-51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
C[6]
C[5]
D[7]
E[6]
C[4]
A[15]
C[3]
VSS_LV
VDD_LV
C[2]
E[5]
E[4]/
VSS_HV
VDD_HV
E[3]
E[2]
D[6]
C[1]
C[0]
B[15]
D[5]
B[14]
D[4]
B[13]
B[12]
Signal Description
NMI
A[0]
C[7]
A[1]
C[8]
A[2]
C[9]
A[3]
D[0]
D[8]
100 LQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
B[11]
VSS_HV
B[10]
D[3]
E[1]
B[9]
D[15]
E[0]
B[8]
TDO
TCK
TMS
TDI
B[7]
VDD_HV
VSS_HV
VSS_LV
VDD_LV
D[14]
B[6]
B[5]
D[13]
D[12]
D[11]
D[10]
VDD_HV_S_BALLAST
VSS_HV
VDD_HV
A[8]
A[9]
A[10]
A[11]
A[12]
A[13]
A[14]
C[12]
POR_B
C[13]
C[14]
C[15]
D[9]
B[4]
VDD_HV_ADC
VSS_HV_ADC
VSS_LV
VDD_LV
B[0]
B[1]
B[2]
B[3]
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS_LV
VDD_LV
D[2]
D[1]
A[4]
A[5]
A[6]
VDD_HV
VSS_HV
XTAL
EXTAL
RESET
A[7]
C[10]
C[11]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1. All VDD_HV and VSS_HV pins must be shorted on the board. The ADC supply
(VDD_HV_ADC) and ground (VSS_HV_ADC) should be managed independently from other
high-voltage supplies, (it may still be supplied from the same high-voltage source, but caution
must be taken while routing it on the board.)
2. All VDD_LV and VSS_LV pins must be shorted on the board.
Figure 7. 100-pin LQFP pinout (top view)1
1. The 100-pin package is not a production package. It is used for software development only.
MPC5604E Reference Manual, Rev. 5
3-52
Freescale Semiconductor
Chapter 4
Clock Architecture
The goal of this section is to provide designers and users with documentation to help them understand the
programming model of the IC clock distribution. The following information is included:
• Clock sources
• Clock selection architecture
• Clock distribution
• Power modes
4.1
Clock related modules
The following clock related modules are instantiated on MPC5604E devices.
• 1 x Clock, Reset and Mode Handling (MagicCarpet)
• 1 x High Frequency Oscillator (XOSC)
• 1 x High Frequency RC-Oscillator (IRCOSC)
• 1 x Frequency Modulated Phase Lock Loop (FMPLL_0)
• 1 x Clock Monitoring Unit (CMU_0)
• 3 x Fractional Clock Dividers (wrapped to include AUX Clock Selectors)
• 4 x Integer Clock Dividers
4.2
High-level block diagrams
This section shows the block diagrams for the clock selection, Figure 8, and for the clock distribution,
Figure 9, and Figure 10.
MPC5604E Reference Manual Rev. 5
Freescale Semiconductor
4-53
Clock Architecture
IRCOSC_Clk
16 MHz
Vid_Clk
120/128 MHz
RC-Oscillator
(IRC) 16 MHz
4-40 MHz
Oscillator
(XOSC)
FMPLL_0
. –.. 2
–.. 1,
FMPLL_CLK_DIV
0
4
System
5
Clk Sel 0
2
8
120 MHz
Reset: 1
–.. 1,–.. 2
Reset: 2
Run: SW
sel. typical 2
0
1
2 Clk Out
3 Sel 0
4
5
16 MHz
SYS_CLK_DIV
–.. 1, –.. 2, –.. 4, –.. 8
Sys_Clk
60/64 MHz
RTC_Clk1
30 MHz
.–. 1,–.. 2
RTC_CLK_DIV
Clk_Out
~30 MHz
CMU_0
0
1 FCD: 9b/12b2
2
3
240 MHz
All dividers are SW
programmable
–.. 2
A_Clk[0]
22,5792 MHz
MCLK[0]
0
1 FCD: 9b/12b2
2
3
A_Clk[1]
22,5792 MHz
MCLK[1]
0
1 FCD: 9b/12b2
2
3
A_Clk[2]
30 MHz/
22,5792 MHz
MCLK[2]
Note: The maximum frequency supported by clk_out pad is 32 MHz.
RTC_Clk divider is SW programmable. Reset value of this divider is 2.
It is requirement in RTC that ipg_clk should be half of ipg_ce_clk.
So, the SW should never program this divider = 1.
2 For details, refer to MCLK Divide Register (I2S_MDR) of the Integrated Interchip
Sound (I2S) / Synchronous Audio Interface (SAI) chapter.
1.
Figure 8. MPC5604E Clock Selection
MPC5604E Reference Manual, Rev. 5
4-54
Freescale Semiconductor
Clock Architecture
The block shows a set of clock selectors and their possible inputs sources. The internal RC-Oscillator is a
reliable clock source, that run independently from any other components. It is the main clock source during
boot or in case of lock loss in the PLL. During Run-Mode the PLL is assumed to be used as main clock
source allowing to operate the system at high frequencies. The PLL clock is derived from the Oscillator
(XOSC) output. The XOSC module requires an external oscillator source, either a crystal or an external
clock generator.
The main clock is the system clock Sys_Clk. It drives the CPU core, the crossbar, and the IPS peripheral
bus including all peripheral interfaces of the IP blocks. A typical frequency would be 60MHz or 64MHz.
To support the external clock frequency required for the MIILite interface of the Ethernet module (FEC)
the system clock needs to higher than 50MHz. The system clock is furthermore divided by 2 and provided
as possible clock for the real-time counter used to for precision timestamps (RTC_Clk).
The MPC5604E allows to supply for different use cases closed loop controlled clocks. For this purpose,
the MPC5604E instantiates Fractional Clock Dividers (FCD), for which the frequency can be adjusted
with fine granularity. To achieve a minimum clock jitter, the input frequency shall be selected as high as
possible, up to the maximum input frequency the FCDs can work on. To create a closed loop control, the
real clock frequency can be measured using an eTimer input, by counting the clock edges (up to
Sys_Clk/2). Thus, low long term drift can be achieved. The FCD clocks can be provided to:
• Clk_Out (to a pin, e.g., used as camera clock)
• A0_Clk - A2_Clk (audio bit clocks)
For further information about FCD input clock selection, see Section 23.1.3.1, “SAI/I2S Clock Selection”
of Chapter 23, "SAI Instantiation".
The MPC5604E allows to clock external components, e.g., the camera sensor. For this purpose the
MPC5604E has an output pin (Clk_Out). The clock source for this pin can be selected using the
Clk_Out_Sel_0 selector. If this clock needs to have a low long term drift, it can be selected from the
A0/1/2_Clk.
The Vid_Clk drives the video encoder module. This frequency needs to be higher than the pixel clock
provided by the camera sensor. The camera provides a pixel clock up to 80MHz or 100MHz, thus, typically
the Vid_Clk will be configured to 120MHz.
The external audio interfaces run also on dedicated frequencies that is different from the system clock. This
clock can be supplied either from external or from internal. In both cases the frequency of the audio bit
clock need to be closed loop controlled to remove long term drift and to prevent buffer overflows or
underruns. In case the audio bit clock is provided from internal, the fractional clock divider clock needs to
be used. However, this is an easy solution, the fractional clock divider implies a peak jitter from 1/2 x input
clock (e.g., 120MHz). Thus, the input clock for the FCD is preferably selected with a frequency as high as
possible. Thus, the input selector can also select from the PLL output directly, which is running at 4x
Sys_Clk. Because the system clock shall not below 50MHz (due to the FEC minimum clock) the FCD
should operate at input frequencies of 200MHz and above. The FCD clocks can be used for low cost audio.
For high quality audio an external audio clock should be used with a jitter about 100ps RMS.
Figure 9 shows how the clocks from the clock selectors are connected to the system components. All BIU
(bus interface units to the IPS peripheral bus) are running on system clock. The IPS clock running on
Sys_Clk is only active on active bus cycles.
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
4-55
Clock Architecture
Thus, all modules also have a module clock that is typically a gated (per module) version of the system
clock Sys_Clk. Besides this, the software watchdog timer SWT uses the more reliable internal RC
oscillator clock IRCOSC_CLK. This clock is almost always on and thus well apt for safety functions.
The IRCOSC_Clk is also used for safety relevant functions in the Fault Collection Unit (FCU).
Furthermore, this clock is used for the digital filters to detect external interrupt events. Thus, the system
can resume from STOP mode, while the system clock is gated off and only the IRCOSC_Clk is running.
Sys_Clk
IPS@Sys_Clk
PIT
Module Clock
BIU
INTC
Module Clock
STM
BIU
Module Clock
BIU
IRCOSC_Clk
SSCM
Module Clock
Protocol Clock
BIU
SWT
Module Clock
Timeout
BIU
WK_UP
PFlash CTR
Code Flash
Module Clock
BIU
IRCOSC_Clk
Data Flash
FCU
Module Clock
Safety Logging
BIU
Module Clock
BIU
MC
Module Clock
BIU
ME
PMU
CGM
FMPLL
RGM
RCOSC
PCU
OSC
SRAM
Module Clock
IRCOSC_Clk
SIUL
Module Clock
IRQ Filter Clk
BIU
eDMA
CRC
Module Clock
BIU
Module Clock
BIU
DMA_Mux
Module Clock
BIU
Figure 9. MPC5604E Clock Distribution Part A
MPC5604E Reference Manual, Rev. 5
4-56
Freescale Semiconductor
Clock Architecture
Figure 10 shows how the clocks are connected to the remaining system components and to the functional
IP modules. Again, all BIUs (bus interface units) are running on system clock that is gated on only during
active IPS bus cycles.
Furthermore, the functional clocks RTC_Clk, Vid_Clk, and A0/1/2_Clk are routed to the corresponding
IP modules. The RTC_Clk can be selected as time base for the precision time stamps of the PTP. The
A0/1/2_Clk clocks provide the protocol clock for the audio interfaces. The Vid_Clk drives the logic of the
video encoder and its input- and output buffers.
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
4-57
Clock Architecture
Sys_Clk
IPS@Sys_Clk
LinFlex_0
Module Clock
BIU
IIC_0
Module Clock
BIU
IF
Clk
LinFlex_1
Module Clock
BIU
IIC_1
Module Clock
BIU
IF
Clk
FlexCAN_0
Module Clock
Protocol Clock
BIU
ADC_0
Vid_Clk
A-Clk[0:2]
Module Clock
BIU
DSPI_0
Video_0
Module Clock
BIU
Pix_Clk
Module Clock
BIU
SAI_0
Module Clock
Audio Clock
BIU
SAI_1
Module Clock
Audio Clock
BIU
SAI_2
Module Clock
Audio Clock
BIU
IF
SClk
IF
DSPI_1
Module Clock
BIU
IF
IF
SClk
BClk
DSPI_2
Module Clock
BIU
IF
SClk
BClk
RTC_Clk
IF
IF
BClk
PTP + RTC
cemx_clk
ipg_clk
ipg_ce_clk
BIU
TX_Clk
IF
RX_Clk
FEC
Module Clock
BIU
With DMA support
BIU = Bus Interface Unit
(e.g., IPS bus)
eTimer_0
Module Clock
BIU
Figure 10. MPC5604E Clock Distribution Part B
MPC5604E Reference Manual, Rev. 5
4-58
Freescale Semiconductor
Clock Architecture
NOTE
Disabling of peripherals and clock sources:
Software should take care that the clock sources (system clocks and protocol
clocks) clock sources selected for a peripheral are not disabled during any
mode transition preceding a mode transition to disable the peripheral.
For example: In FLEXCAN, when FXOSC is selected for the CAN Engine
clock source (FLEXCAN_CTRL[CLK_SRC]), before disabling
FLEXCAN peripheral clock, the user must ensure that FXOSC is enabled
in the current mode prior to the target mode transition that will disable the
FLEXCAN.
FXOSC is enabled in the current mode prior to the target mode transition
that will disable the FLEXCAN.
Enabling of peripherals and clock sources:
Software should take care that the clock sources (system clocks and protocol
clocks) are enabled for the target mode, before initiating the target mode
transition to enable the peripheral.
4.3
Memory Map
This section provides the memory map of the registers that correspond to clock related modules.
Table 7. Memory Map
Address
Name
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0xC3FE
_0000
…
0xC3FE
_001C
XOSC registers
0xC3FE
_0020
…
0xC3FE
_005C
reserved
0xC3FE
_0060
…
0xC3FE
_007C
IRC registers
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
4-59
Clock Architecture
Table 7. Memory Map
Address
Name
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
reserved
0xC3FE
_00A0
…
0xC3FE
_00BC
FMPLL_0 registers
0xC3FE
_00C0
...
0xC3FE
_00FC
reserved
0xC3FE
_0100
…
0xC3FE
_011C
CMU0 registers
0xC3FE PLL_CLK_DI
_0120 V
R
0
0
0
0
0
0
0
CLK_DIV
0xC3FE
_0080
…
0xC3FE
_009C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
0xC3FE
_0124
…
0xC3FE
_013C
R
0
0
0
0
0
0
0
CLK_DIV
0xC3FE SYSTEM_CL
_0140 K_DIV
reserved
0
0
0
0
0
0
0
0
0
0
W
R
W
0xC3FE
_0144
…
0xC3FE
_015C
reserved
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Clock Architecture
Address
Name
0xC3FE RTC_CLK_DI
_0160 V
R
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
CLK_DIV
Table 7. Memory Map
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
0xC3FE
_0164
…
0xC3FE
_036C
reserved
0xC3FE CGM_OC_EN R
_0370 1
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EN
W
0xC3FE CGM_OCDS_ R
_0374 SC1
W
0
0
R
0
0
0
0
0
0
0
0
0
0
0
0
SELDIV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SELCTL
0
0
0
0
W
0xC3FE CGM_SC_SS
_0378 1
R
SELSTAT
W
R
0
0
0
0
W
1
4.4
4.4.1
For details, refer to the chapter Clock Generation Module (MC_CGM).
Internal RC oscillator (IRC) digital interface
Introduction
The IRC digital interface controls the 16 MHz fast internal RC oscillator (IRC). It holds control and status
registers accessible for application.
4.4.2
Functional description
The IRC provides a high frequency clock of 16 MHz. This clock can be used to accelerate the exit from
reset and wakeup sequence from low power modes of the system. It is controlled by the MC_ME module
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Clock Architecture
based on the current device mode. The clock source status is updated in ME_GS[S_RC]. Please refer to
the MC_ME chapter for further details.
The IRC can be further divided by a configurable division factor in the range from 1 to 32 to generate the
divided clock to match system requirements. This division factor is specified by RC_CTL[RCDIV] bits.
The IRC output frequency can be trimmed by RC_CTL[IRCTRIM] bits. These bits can be programmed
to modify internal capacitor/resistor values. After power on reset, the trimming bits are provided by the
flash options. Only after a first write access to RC_CTL will the value specified by bits IRCTRIM control
the trimming.
In this oscillator, two's complement trimming method is implemented. So the trimming code increases
from -32 to 31. As the trimming code increases, the internal time constant increases and frequency reduces.
Please refer to device datasheet for average frequency variation of the trimming step.
4.4.3
Register description
Address offset: 0x0000
0
1
Base Address: 0xC3FE_0060
2
3
4
6
7
8
9
10
11
12
13
Reserved
IRCTRIM[5:0]
—
rw
Access
Reset
5
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
Reserved
Access
Reset
—
0
0
rw
0
0
0
0
—
0
0
0
0
rw
0
0
0
0
Figure 11. IRC Oscillator Control Register (IRC_CTL)
Table 8. RC Oscillator Control Register (IRC_CTL) field descriptions
Field
Description
IRCTRIM[5:0]
IRC trimming bits
Note: All configurations cannot be used. Please refer to data sheet.
NOTE
The IRC is trimmed during reset using a factory programmed value stored
in flash. After reset, this trim value is not visible at IRC_CTL[TRIM].
Therefore, any read-write operation on the 32-bit register will potentially set
the IRC to an unoptimised trim value.
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Clock Architecture
Bus access errors are generated in only half of the non-implemented address
space of Oscillator External Interface (Crystal XOSC) and RCOSC Digital
Interface (16MHz Internal RC oscillator [IRC]). Do not access
unimplemented address space for XOSC and RCOSC register areas OR
write software that is not dependent on receiving an error when access to
unimplemented XOSC and RCOSC space occurs.
4.5
External crystal oscillator (XOSC) digital interface
The XOSC digital interface controls the operation of the 4– MHz fast external crystal oscillator (XOSC).
It holds control and status registers accessible for application.
4.5.1
•
•
•
•
4.5.2
Main features
Oscillator powerdown control and status reporting through MC_ME block
Oscillator clock available interrupt
Oscillator bypass mode
Output clock division factors ranging from 1, 2, 3....32
Functional description
The XOSC circuit includes an internal oscillator driver and an external crystal circuitry. It provides an
output clock that can be provided to the FMPLL or used as a reference clock to specific modules depending
on system needs.
The XOSC can be controlled by the MC_ME module. The ME_xxx_MC[XOSCON] bit controls the
powerdown of the oscillator based on the current device mode while ME_GS[S_XOSC] register provides
the oscillator clock available status.
After system reset, the oscillator is put into powerdown state and software has to switch on when required.
Whenever the crystal oscillator is switched on from the off state, the OSCCNT counter starts and when it
reaches the value EOCV[7:0]×512, the oscillator clock is made available to the system. Also, an interrupt
pending XOSC_CTL[I_OSC] bit is set. An interrupt is generated if the interrupt mask bit M_OSC is set.
The oscillator circuit can be bypassed by setting XOSC_CTL[OSCBYP]. This bit can only be set by
software. A system reset is needed to reset this bit. In this bypass mode, the output clock has the same
polarity as the external clock applied on the EXTAL pin and the oscillator status is forced to ‘1’. The
bypass configuration is independent of the powerdown mode of the oscillator.
Table 9 shows the truth table of different oscillator configurations.
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Clock Architecture
Table 9. Truth table of crystal oscillator
ME_xxx_MC[FXOSCON] FXOSC_CTL[OSCBYP]
XTAL
EXTAL
FXOSC
Oscillator MODE
0
0
No crystal,
High Z
No crystal,
High Z
0
Powerdown
x
1
x
Ext clock
EXTAL
Bypass, OSC disabled
1
0
Crystal
Crystal
EXTAL
Normal, OSC enabled
Gnd
Ext clock
EXTAL
Normal, OSC enabled
The XOSC clock can be further divided by a configurable factor in the range 1 to 32 to generate the divided
clock to match system requirements. This division factor is specified by XOSC_CTL[OSCDIV] field.
4.5.3
Register description
Address offset: 0x0000
1
2
3
OSCBYP
0
Base Address: 0xC3FE0000
4
5
6
7
8
9
10
11
12
Reserved
EOCV[7:0]
—
rw
13
14
15
rs
Reset
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
M_OSC
Access
Access
rw
Reset
0
Reserved
—
0
rw
0
0
0
0
0
0
I_OSC
Reserved
rc
—
0
0
0
0
0
Figure 12. External Crystal Oscillator Control Register (XOSC_CTL)
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Clock Architecture
Table 10. External Crystal Oscillator Control Register (XOSC_CTL) field descriptions
Field
Description
OSCBYP
Crystal Oscillator bypass
This bit specifies whether the oscillator should be bypassed or not. Only software can set this bit.
System reset is needed to clear this bit.
0: Oscillator output is used as root clock
1: EXTAL is used as root clock
EOCV[7:0]
End of Count Value
These bits specify the end of count value to be used for comparison by the oscillator stabilization
counter OSCCNT after reset or whenever it is switched on from the off state (OSCCNT runs on the
FXOSC). This counting period ensures that external oscillator clock signal is stable before it can be
selected by the system. When oscillator counter reaches the value EOCV[7:0] × 512, the crystal
oscillator clock interrupt (I_OSC) request is generated. The OSCCNT counter will be kept under
reset if oscillator bypass mode is selected.
M_OSC
Crystal oscillator clock interrupt mask
0: Crystal oscillator clock interrupt is masked
1: Crystal oscillator clock interrupt is enabled
I_OSC
Crystal oscillator clock interrupt
This bit is set by hardware when OSCCNT counter reaches the count value EOCV[7:0]×512. It is
cleared by software by writing ‘1’.
0: No oscillator clock interrupt occurred
1: Oscillator clock interrupt pending
NOTE
Bus access errors are generated in only half of the non-implemented address
space of Oscillator External Interface (Crystal XOSC) and RCOSC Digital
Interface (16MHz Internal RC oscillator [IRC]). Do not access
unimplemented address space for XOSC and RCOSC register areas OR
write software that is not dependent on receiving an error when access to
unimplemented XOSC and RCOSC space occurs."
4.6
4.6.1
Frequency-modulated phase-locked loop (FMPLL)
Introduction
This section describes the features and functions of the FMPLL module implemented in the device.
4.6.2
Overview
The FMPLL enables the generation of high speed system clocks from a common 4–40 MHz input clock.
Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL
multiplication factor and output clock divider ratio are all software configurable.
MPC5604E has one FMPLL that can generate the system clock and takes advantage of the FM mode.
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Clock Architecture
NOTE
The user must take care not to program device with a frequency higher than
allowed (no hardware check).
The FMPLL block diagram is shown in Figure 13.
Phase
clkin
IDF
Frequency
Detector
(PFD)
Charge
Pump
Low Pass
Filter
PHI
VCO
ODF
NDIV
Loop
Frequency
Divider
Figure 13. FMPLL block diagram
4.6.3
Features
The FMPLL has the following major features:
• Input clock frequency 4 MHz – 40 MHz
• PFD input clock frequency range in normal mode is 4–16 MHz
• Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz
• Frequency divider (FD) for reduced frequency operation without forcing the FMPLL to relock
• Frequency modulated FMPLL
— Modulation enabled/disabled through software
— Triangle wave modulation
• Programmable modulation depth
— ±0.25% to ±4% deviation from center spread frequency1
— −0.5% to +8% deviation from down spread frequency
— Programmable modulation frequency dependent on reference frequency
• Self-clocked mode (SCM) operation
• 4 available modes
— Normal mode
— Progressive clock switching
— Normal mode with frequency modulation
— Powerdown mode
4.6.4
Memory map2
Table 11 shows the memory map of the FMPLL. The FMPLL_0 base address is 0xC3FE_00A0.
1. Spread spectrum should be programmed in line with maximum datasheet frequency figures.
2. FMPLL_x are mapped through the MC_CGM register slot
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Clock Architecture
Table 11. FMPLL memory map
Base address: 0xC3FE00A0 (FMPLL_0)
Address offset
Register
Access
Location
0x0
Control Register (CR)
R/W (write
access in
supervisor mode
only)
on page 67
0x4
Modulation Register (MR)
R/W (write
access in
supervisor mode
only)
on page 69
Table 12. FMPLL memory map
Address offset
Register
Location
0x0
Control Register (CR)
on page 67
0x4
Modulation Register (MR)
on page 69
4.6.5
Register description
The FMPLL operation is controlled by two registers. Those registers can be accessed and written in
supervisor mode only.
4.6.5.1
Control Register (CR)
Table 13. CR field descriptions
Field
Description
IDF
The value of this field sets the FMPLL input division factor as described in Table 14.
ODF
The value of this field sets the FMPLL output division factor as described in Table 15.
NDIV
The value of this field sets the FMPLL loop division factor as described in Table 16.
EN_PLL_SW
This bit is used to enable progressive clock switching. After the PLL locks, the PLL output initially
is divided by 8, and then progressively decreases until it reaches divide-by-1.
0 Progressive clock switching disabled.
1 Progressive clock switching enabled.
Note: Progressive clock switching should not be used if a non-changing clock is needed, such
as for serial communications, until the division has finished.
I_LOCK
This bit is set by hardware whenever there is a lock/unlock event.
S_LOCK
This bit is an indication of whether the FMPLL has acquired lock.
0: FMPLL unlocked
1: FMPLL locked
Note: S_LOCK =1 signals coarse lock. The system clock should not be changed to PLL output
for at least 200 µs after S_LOCK is set.
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Clock Architecture
Table 13. CR field descriptions (continued)
Field
Description
PLL_FAIL_MASK This bit is used to mask the pll_fail output.
0 pll_fail not masked.
1 pll_fail masked.
PLL_FAIL_FLAG This bit is asynchronously set by hardware whenever a loss of lock event occurs while FMPLL
is switched on. It is cleared by software writing ‘1’.
Table 14. Input divide ratios
IDF[3:0]
Input divide ratios
0000
Divide by 1
0001
Divide by 2
0010
Divide by 3
0011
Divide by 4
0100
Divide by 5
0101
Divide by 6
0110
Divide by 7
0111
Divide by 8
1000
Divide by 9
1001
Divide by 10
1010
Divide by 11
1011
Divide by 12
1100
Divide by 13
1101
Divide by 14
1110
Divide by 15
1111
Clock Inhibit
Table 15. Output divide ratios
ODF[1:0]
Output divide ratios
00
Divide by 2
01
Divide by 4
10
Divide by 8
11
Divide by 16
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Clock Architecture
Table 16. Loop divide ratios
4.6.5.2
NDIV[6:0]
Loop divide ratios
0000000–0011111
—
0100000
Divide by 32
0100001
Divide by 33
0100010
Divide by 34
...
...
1011111
Divide by 95
1100000
Divide by 96
1100001–1111111
—
Modulation Register (MR)
Offset: 0x4
RESET:
R
W
RESET:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
SPRD_SEL
STRB_BYPASS
W
0
MOD_PERIOD
FM_EN
R
Access: Supervisor read/write
0
INC_STEP
0
0
0
0
0
0
0
0
Figure 14. Modulation Register (MR)
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Clock Architecture
Table 17. MR field descriptions
Field
Description
STRB_BYPASS Strobe bypass.
The STRB_BYPASS signal is used to bypass the strobe signal used inside FMPLL to latch the
correct values for control bits (INC_STEP, MOD_PERIOD and SPRD_SEL).
0 Strobe is used to latch FMPLL modulation control bits
1 Strobe is bypassed. In this case control bits need to be static. The control bits must be changed
only when FMPLL is in powerdown mode.
SPRD_SEL
Spread type selection.
The SPRD_SEL controls the spread type in Frequency Modulation mode.
0 Center SPREAD
1 Down SPREAD
MOD_PERIOD Modulation period.
The MOD_PERIOD field is the binary equivalent of the value modperiod derived from following
formula:
f ref
modperiod = -------------------4 × f mod
where:
fref: represents the frequency of the feedback divider
fmod: represents the modulation frequency
FM_EN
INC_STEP
Frequency Modulation Enable. The FM_EN enables the frequency modulation.
0 Frequency modulation disabled
1 Frequency modulation enabled
Increment step.
The INC_STEP field is the binary equivalent of the value incstep derived from following formula:
15
( 2 – 1 ) × md × MDF
incstep = round ---------------------------------------------------------------
100 × 5 × MODPERIOD
where:
md: represents the peak modulation depth in percentage (Center spread -- pk-pk=+/-md,
Downspread -- pk-pk=-2×md)
MDF: represents the nominal value of loop divider (CR[NDIV])
4.6.6
4.6.6.1
Functional description
Normal mode
In Normal Mode the FMPLL inputs are driven by the CR. This means that, when the FMPLL is in lock
state, the FMPLL output clock (PHI) is derived by the reference clock (CLKIN) through this relation:
clkin ⋅ NDIV
phi = ---------------------------------IDF ⋅ ODF
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Clock Architecture
where the value of IDF, NDIV and ODF are set in the CR and can be derived from Table 14, Table 15 and
Table 16.
4.6.6.2
Progressive clock switching
Progressive clock switching allows to switch the system clock to FMPLL output clock stepping through
different division factors. This means that the current consumption gradually increases and, in turn, voltage
regulator response is improved.
This feature can be enabled by programming CR[EN_PLL_SW] bit. When enabled, the system clock is
switched to divided PHI. The FMPLL_clk divider is then progressively decreased to the target divider as
shown in Table 18.
Table 18. Progressive clock switching on pll_select rising edge
Number of FMPLL output clock cycles
FMPLL_clk frequency
(FMPLL output clock frequency)
8
(FMPLL output clock frequency)/8
16
(FMPLL output clock frequency)/4
32
(FMPLL output clock frequency)/2
onward
FMPLL output clock frequency
FMPLL output clock
Division factors of 8, 4, 2 or 1
FMPLL_clk
Figure 15. FMPLL output clock division flow during progressive switching
4.6.6.3
Normal mode with frequency modulation
The FMPLL default mode is without frequency modulation enabled. When frequency modulation is
enabled, however, two parameters must be set to generate the desired level of modulation: the PERIOD,
and the STEP. The modulation waveform is always a triangle wave and its shape is not programmable.
FM mode is activated in two steps:
1. Configure the FM mode characteristics: MOD_PERIOD, INC_STEP.
2. Enable the FM mode by programming bit FM_EN of the MR to ‘1’. FM mode can only be enabled
when FMPLL is in lock state.
There are two ways to latch these values inside the FMPLL, depending on the value of bit STRB_BYPASS
in the MR.
If STRB_BYPASS is low, the modulation parameters are latched in the FMPLL only when the strobe
signal goes high for at least two cycles of CLKIN clock. The strobe signal is automatically generated in
the FMPLL digital interface when the modulation is enabled (FM_EN goes high) if the FMPLL is locked
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Clock Architecture
(S_LOCK = 1) or when the modulation has been enabled (FM_EN = 1) and FMPLL enters lock state
(S_LOCK goes high).
If STRB_BYPASS is high, the strobe signal is bypassed. In this case, control bits (MOD_PERIOD[12:0],
INC_STEP[14:0], SPREAD_CONTROL) need to be static or hardwired to constant values. The control
bits must be changed only when the FMPLL is in powerdown mode.
The modulation depth in % is
100 × 5 × INCSTEPxMODPERIOD
ModulationDepth = -------------------------------------------------------------------------------------------15
( 2 – 1 ) × MDF
NOTE
The user must ensure that the product of INCTEP and MODPERIOD is less
than (215-1).
Figure 16. Frequency modulation
4.6.6.4
Powerdown mode
To reduce consumption, the FMPLL can be switched off when not required by programming the registers
ME_x_MC on the MC_ME module.
4.6.7
Recommendations
To avoid any unpredictable behavior of the FMPLL clock, it is recommended to follow these guidelines:
• The FMPLL VCO frequency should reside in the range 256 MHz to 512 MHz. Care is required
when programming the multiplication and division factors to respect this requirement.
• The user must change the multiplication, division factors only when the FMPLL output clock is
not selected as system clock. Use progressive clock switching if system clock changes are required
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Clock Architecture
•
•
•
4.7
4.7.1
while the PLL is being used as the system clock source. MOD_PERIOD, INC_STEP,
SPREAD_SEL bits should be modified before activating the FM mode. Then strobe has to be
generated to enable the new settings. If STRB_BYP is set to ‘1’ then MOD_PERIOD, INC_STEP
and SPREAD_SEL can be modified only when FMPLL is in powerdown mode.
FMPLL must be powered down before changing the values of NDIV and IDF and then powered
up with the new settings. If the power up and power down is not performed, the NDIV and IDF
will reflect new configuration values but the PLL frequency will be as per the old configuration.
Use progressive clock switching (FMPLL output clock can be changed when it is the system clock,
but only when using progressive clock switching).
Before enabling FMPLL, ensure that the input clock to FMPLL is stable.
Clock Monitor Unit (CMU)
Overview
The Clock Monitor Unit (CMU) serves three purposes:
• FMPLL clock monitoring: detect if FMPLL leaves an upper or lower frequency boundary
• Crystal clock monitoring: monitor the external crystal oscillator clock, which must be greater than
the internal RC clock divided by a division factor given by CMU_CSR[RCDIV]
• Frequency meter: measure the frequency of RCOSC versus a known reference clock XOSC
CMU forwards these kind of events to the MC_CGM, MC_ME, and FCU. These in turn can then switch
to a safe mode, generate a reset, or generate or an interrupt.
Table 19. CMU module summary
Module
CMU_0
4.7.2
•
•
•
•
4.7.3
Monitored clocks
PLL divider clock
Main features
RC oscillator frequency measurement
External oscillator clock monitoring with respect to CK_IRC÷n clock
FMPLL clock frequency monitoring with respect to CK_IRC÷4 clock
Event generation for various failures detected inside monitoring unit
Functional description
The names of the clocks involved in this block have the following meaning:
• CK_XOSC: clock coming from the external crystal oscillator
• CK_IRC: clock coming from the low frequency internal RC oscillator
• CK_PLL: clock coming from the FMPLL
• FOSC: frequency of external crystal oscillator clock
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Clock Architecture
•
•
FRC: frequency of low frequency internal RC oscillator
FPLL: frequency of FMPLL divider clock
4.7.4
Crystal clock monitor
If FOSC is smaller than FRC divided by 2RCDIV bits of CMU_0_CSR and the CK_XOSC is ‘ON’ and stable
as signaled by the MC_ME, then:
• CMU_ISR[OLRI] is set.
NOTE
OSC and FMPLL monitor may produce false events when OSC/FMPLL
frequency is less than 2×RC/2RCDIV frequency due to the limitation on to
compare two clocks accurately.
4.7.4.1
FMPLL clock monitor
The FMPLL clock CK_PLL frequency can be monitored by programming CME bit of CMU_CSR register
to 1. CK_PLL monitor starts as soon as CME bit is set. This monitor can be disabled at any time by writing
CME bit to 0.
If CK_PLL frequency (FPLL) is greater than a reference value determined by the HFREF[11:0] bits of
CMU_HFREFR and the CK_PLL is ‘ON’ and the FMPLL locked as signaled by the MC_ME then
• An event pending bit FHHI in CMU_ISR is set
If FPLL is less than a reference clock frequency (FRC/4) and the CK_PLL is ‘ON’ and the FMPLL locked
as signaled by the MC_ME, then:
• An event pending bit FLCI in CMU_ISR is set
If FPLL is less than a reference value determined by the LFREF[11:0] bits of CMU_LFREFR and the
CK_PLL is ‘ON’ and the FMPLL locked as signaled by the MC_ME, then:
• An event pending bit FLLI in CMU_ISR is set
• A failure event is signaled to the MC_RGM and Fault Collection Unit, which in turn can generate
an interrupt
NOTE
OSC and FMPLL monitor may produce false events when OSC/FMPLL
frequency is less than 2×RC/2RCDIV frequency due to the limitation on to
compare two clocks accurately.
4.7.4.2
Frequency meter
The frequency meter calibrates the internal RC oscillator (CK_IRC) using a known frequency.
NOTE
This value can then be stored in the flash memory so that application
software can reuse it later on.
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Clock Architecture
The reference clock is always the XOSC. A simple frequency meter returns a draft value of CK_IRC. The
measure starts when CMU_CSR[SFM] is set. The measurement duration is given by the CMU_MDR
register in terms of IRC clock cycles with a width of 20 bits. The SFM bit is cleared by the hardware after
the frequency measurement is done and the count is loaded in the CMU_FDR.The frequency FRC can be
derived from the value loaded in the CMU_FDR register as follows:
FRC = (FOSC × MD) / n
Eqn. 1
where n is the value in CMU_FDR register and MD is the value in CMU_MDR.
NOTE
When FXOSC > FIRC and MDR=0xFFFFF, it will cause overflow of FDR
register and the value stored cannot be relied upon. When FXOSC > FIRC,
application need to ensure that value of MDR is chosen such that n does not
overflow where n is number of XOSC clock edges in duration of MDR IRC
clock edges.
4.7.5
Memory map and register description
The CMU registers are mapped through the MC_CGM (see the memory map in Chapter 5, Clock
Generation Module (MC_CGM)). The base address for CMU is shown in Table 20.
Table 20. CMU base address
Module
Base address
CMU_0
0xC3FE_0100
The memory map of CMU is shown in Table 21.
Table 21. CMU memory map
Address offset
Register
Location
0x00
Control status register (CMU_CSR)
on page 76
0x04
Frequency display register (CMU_FDISP)
on page 77
0x08
High-frequency reference register A (CMU_HFREFR_A)
on page 77
0x0C
Low-frequency reference register A (CMU_LFREFR_A)
on page 78
0x10
Interrupt status register (CMU_ISR)
on page 78
0x14
0x18
Reserved
Measurement duration register (CMU_MDR)
on page 79
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Freescale Semiconductor
4-75
Clock Architecture
4.7.5.1
Control status register (CMU_CSR)
Address: Base + 0x00
R
Access: User read/write
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
CKSEL1
0
0
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
24
25
26
27
28
29
30
0
0
0
0
0
0
0
0
0
0
SFM
RCDIV
1
1
31
CME
_A
0
Figure 17. Control status register (CMU_CSR)
Table 22. CMU_0_CSR field descriptions
Field
SFM
Description
Start frequency measure
Set this bit to start a clock frequency measure. The bit is cleared by hardware when the measure is
ready in the CMU_FDR register. Software cannot clear this bit.
0 Frequency measurement is completed or not yet started.
1 Frequency measurement is started.
CKSEL1
Clock selection
This field selects the clock to be measured by the frequency meter. Selects IRC 16 MHz as reference
clock. This field must not be programmed with value 2.
RCDIV
RC clock division factor
These bits specify the RC clock division factor. The output clock is CK_IRC fast (16 MHz) divided by the
factor 2RCDIV. This output clock is compared with CK_XOSC for crystal clock monitor feature.The clock
division coding is as follows.
00 Clock divided by 1 (No division).
01 Clock divided by 2.
10 Clock divided by 4.
11 Clock divided by 8.
CME_A
Clock monitor enable
0 Monitor is disabled.
1 Monitor is enabled.
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Freescale Semiconductor
Clock Architecture
4.7.5.2
Frequency display register (CMU_FDR)
Address: Base + 0x04
R
Access: User read-only
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
FD[19:16]
W
Reset
R
FD[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
Figure 18. Frequency display Register (CMU_FDR)
Table 23. CMU_FDR field descriptions
Field
Description
FD
Measured frequency bits
This register displays the measured frequency fRC with respect to fOSC. The measured value is given
by the following formula:
fRC = (fOSC × MD) / n
where n is the value in CMU_FDR register
4.7.5.3
High-frequency reference register A (CMU_HFREFR_A)
Address: Base + 0x08
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
1
1
1
1
1
W
Reset
R
HFREF_A
W
Reset
1
1
1
1
1
1
1
Figure 19. High-frequency reference register A (CMU_HFREFR_A)
Table 24. CMU_HFREFR_A field descriptions
Field
Description
HFREF_A High-frequency reference value
These bits determine the high reference value for the FMPLL clock. The reference value is given by:
(HFREF_A/16) × (fRC/4).
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Freescale Semiconductor
4-77
Clock Architecture
4.7.5.4
Low-frequency reference register A (CMU_LFREFR_A)
Address: Base + 0x0C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
Reset
R
LFREF_A
W
Reset
0
0
0
0
0
0
0
Figure 20. Low-frequency reference register A (CMU_LFREFR_A)
Table 25. CMU_LFREFR_A fields descriptions
Field
Description
LFREF_A
4.7.5.5
Low-frequency reference value
These bits determine the low reference value for the FMPLL clock. The reference value is given by:
(LFREF_A/16) × (fRC/4).
Interrupt status register (CMU_ISR)
Address: Base + 0x10
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
OLRI
W
FLLI_A
R
FHHI_A
Reset
FLCI_A
W
w1c
w1c
w1c
w1c
0
0
0
0
Figure 21. Interrupt status register (CMU_ISR)
Table 26. CMU_ISR field descriptions
Field
FLCI_A
Description
FMPLL clock frequency less than reference clock interrupt
This bit is set by hardware when both of the following are true:
• The FMPLL frequency becomes lower than reference clock frequency (FRC/4) value
• CK_FMPLL is ‘ON’ and the FMPLL locked as signaled by the MC_ME.
It can be cleared by software by writing 1.
0 No FLC event.
1 FLC event is pending.
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Freescale Semiconductor
Clock Architecture
Table 26. CMU_ISR field descriptions (continued)
FHHI_A
FMPLL_0 Clock frequency higher than high reference interrupt
This bit is set by hardware when both of the following are true:
• The FMPLL frequency becomes higher than HFREF_A value
• CK_FMPLL is ‘ON’ and the FMPLL locked as signaled by the MC_ME.
It can be cleared by software by writing 1.
0 No FHH event.
1 FHH event is pending.
FLLI_A
FMPLL_0 Clock frequency less than low reference event
This bit is set by hardware when both of the following are true:
• The FMPLL frequency becomes lower than LFREF_A value
• CK_FMPLL is ‘ON’ and the FMPLL locked as signaled by the MC_ME.
It can be cleared by software by writing 1.
0 No FLL event.
1 FLL event is pending.
OLRI
Oscillator frequency less than RC frequency event
This bit is set by hardware when both of the following are true:
• The frequency of CK_XOSC is less than CK_IRCfast/2RCDIV frequency
• CK_XOSC is ‘ON’ and stable as signaled by the MC_ME.
It can be cleared by software by writing 1.
0 No OLR event.
1 OLR event is pending.
4.7.5.6
Measurement duration register (CMU_MDR)
Address: Base + 0x18
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
0
0
0
0
0
0
0
0
0
0
0
0
12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
15
MD[15:0]
W
Reset
14
MD[19:16]
W
Reset
13
0
0
0
0
0
0
0
0
0
Figure 22. Measurement duration register (CMU_MDR)
Table 27. CMU_MDR field descriptions
4.8
Field
Description
MD
Measurement duration bits
This register displays the measured duration in term of IRC clock cycles. This value is loaded in the
frequency meter down-counter. When CMU_CSR[SFM] = 1, the down-counter starts counting.
Boot and power management concept
At boot time, the MPC5604E is using the IRCOSC_Clk to start. At this time (after reset), the system clock
divider is set to a value of "1", thus, the system clock is 16MHz. Then, the MPC5604E can configure the
module to connect the external oscillator (XOSC) and the PLL. Once the PLL is locked, the SW can
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
4-79
Clock Architecture
change the system clock divider to "2" and switch the system clock selector to be driven by the PLL. One
output of the PLL can be reconfigured without producing glitches on the clock signal. This clock is used
to drive the system clock (Sys_Clk).
The other output clock of the PLL is used to drive all the other clocks. Because this port cannot be
reconfigured free of glitches, all attached IP modules need to be gated off before changing the clock
frequency.
The other clock selectors (Clk Out Sel and the FCDs) do not allow glitch-less clock selection. Thus, SW
need to gate off all attached IP modules before changing the clock source.
In case the PLL lock gets lost during operation, the MPC5604E switches to safe mode and automatically
selects the IRCOSC_Clk as input at the system clock selector so that the system clock runs now at 8MHz.
In safe mode, the SW can switch the divider value again to "1" thus, the system clock is 16MHz. The loss
of lock event also creates an entry in the Fault Collection Unit (FCU).
The MPC5604E also supports two low power modes, the STOP mode and the HALT mode. These modes
distinguish between different clock and clock gating settings. In both modes the clocks need to be
configured to allow a resume to the RUN mode. Figure 23 shows which modules need to use the reliable
IRCOSC_Clk that remains active during STOP mode. These are the safety relevant functions in
• FCU
• SWT
and the functions need for wake-up, which are
• digital input filters for external interrupt detection (part of the SIUL).
The non maskable interrupt (NMI) is driven via an input pin. This signal is routed purely in a combinatorial
way through the system. This allows to wake-up as long as only the Mode Entry (ME) unit is clocked.
MPC5604E Reference Manual, Rev. 5
4-80
Freescale Semiconductor
Clock Architecture
MagicCarpet
CGL
IRCOSC_CLK
SYS_CLK_G#1
System
Clock
Selector 0
XOSC_CLK
FMPLL_0_CLK
SYS_CLK
Clock
Gates
•
•
•
SYS_CLK_G#n
IRCOSC_CLK
SYS_CLK_G#z
Platform
IRCOSC_CLK
SIU-Lite
SWT
Filter
(digital)
IRQ #n
IRQ #m
INTC
Pad
(external IRQ
capable)
•
•
•
4
IRQ #p
Filter
(digital)
IRQ #q
•
•
•
Pad
(external IRQ
capable)
mcp
nmi
Core
SYS_CLK_G#x
PIT
crifint
STOP/HALT
mode
request
•
•
•
STOP/HALT
mode
ack
SYS_CLK_G#y
Any
peripheral
MC_CGL
WakeUp
wakeup
MagicCarpet ME
SYS_CLK
PLL ON
Filter
(analog)
FMPLL_0
Pad
(NMI)
FMPLL_0_CLK
XOSC_CLK
Legend:
Combinatorial
Available in STOP mode
Available in HALT mode
Figure 23. MPC5604E Clock Selection for Power Modes
4.9
Safety concept
This section gives a brief overview on the safety aspects of the clock architecture. This includes two items:
• reliable clock for safety modules
• clock frequency monitoring
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
4-81
Clock Architecture
A safety relevant unit of the MPC5604E is the Software Watchdog Timer (SWT). To ensure that this
modules operates also in case of failure of the system clock, the watchdog counter decrements every cycle
of the IRCOSC_Clk. This clock is more robust against failure compared to the PLL clock because it does
not depend on other components. In case of the PLL clock, proper performance also depends on the
external crystal or clock generator, the XOSC and loss of clock lock.
Besides the loss of PLL lock detection, the MPC5604E also has a Clock Monitoring Unit (CMU). Its main
features are:
• RC oscillator (IRCOSC_Clk) frequency measurement
• External oscillator clock monitoring with respect to IRCOSC_Clk/n clock (turned off at reset)
• PLL clock frequency monitoring with respect to IRCOSC_Clk/4 clock (turned off at reset)
• Event generation for various failures detected inside monitoring unit
Figure 24 shows how the clock monitoring unit is integrated into the MPC5604E clocking system.
XOSC valid (on AND stable)/off
CMU_0
FMPLL_0 valid (on AND locked)/off
IRCOSC_CLK
CK 1
16MHz
CK 0(reference)
XOSC_CLK
4-40MHz
FMPLL_0
120/128 MHZ
CK XOSC
CK PLL
Loss of crystal
OLR
FHH
MagicCarpet
FMPLL_0 frequency out of range
FLL
Logical OR
FCU
Figure 24. MPC5604E Clock Monitoring Unit Integration
In case of clock monitoring event, the CMU signals the Clock Generation Module, Reset Generation
Module, and Mode Entry Module, which might take appropriate actions (e.g., switching the system clock
to the IRCOSC_Clk), and to the fault collection unit (FCU) to keep record of the event.
MPC5604E Reference Manual, Rev. 5
4-82
Freescale Semiconductor
Chapter 5
Clock Generation Module (MC_CGM)
5.1
5.1.1
Introduction
Overview
The clock generation module (MC_CGM) generates reference clocks for all the chip blocks. The
MC_CGM selects one of the system clock sources to supply the system clock. The MC_ME controls the
system clock selection (see the MC_ME chapter for more details). The memory spaces of system and
peripheral clock sources which have addressable memory spaces are accessed through the MC_CGM
memory space. The MC_CGM also selects and generates an output clock.
Figure 25 shows the MC_CGM block diagram.
MPC5604E Reference Manual Rev. 5
Freescale Semiconductor
5-83
Clock Generation Module (MC_CGM)
IRC
MC_CGM
MC_ME
XOSC
Registers
Register Interface
MC_RGM
FMPLL_0
System Clock
Multiplexer
peripherals
CLKOUT
core
Mapped Modules Interface
Output Clock
Selector/Divider
mapped
peripherals
Figure 25. MC_CGM block diagram
5.1.2
Features
The MC_CGM includes the following features:
• generates system and peripheral clocks
• selects and enables/disables the system clock supply from system clock sources according to
MC_ME control
MPC5604E Reference Manual, Rev. 5
5-84
Freescale Semiconductor
Clock Generation Module (MC_CGM)
•
•
•
•
supports multiple clock sources and maps their address spaces to its memory map
generates an output clock
guarantees glitch-less clock transitions when changing the system clock selection
supports 8, 16, and 32-bit wide read/write accesses
5.2
External Signal Description
The MC_CGM delivers an output clock to the CLKOUT pin for off-chip use and/or observation.
5.3
Memory Map and Register Definition
Table 28. MC_CGM Register Description
Access
Address
Name
Description
Size
Location
User
Supervisor
Test
0xC3FE PLL_DIVIDER
_0120
PLL Clock Divider
byte
read
read/write
read/write
on page 86
0xC3FE SYSTEM_CLK_DIVI
_0140 DER
System Clock Divider
byte
read
read/write
read/write
on page 86
0xC3FE RTC_CLK_DIVIDER RTC Clock Divider
_0160
byte
read
read/write
read/write
on page 87
0xC3FE CGM_OC_EN
_0370
Output Clock Enable
word
read
read/write
read/write
on page 87
0xC3FE CGM_OCDS_SC
_0374
Output Clock Division
Select
byte
read
read/write
read/write
on page 88
0xC3FE CGM_SC_SS
_0378
System Clock Select
Status
byte
read
read
read
on page 89
NOTE
Any access to unused registers as well as write accesses to read-only
registers will:
•
•
5.3.1
not change register content
cause a transfer error
Register Descriptions
All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered
according to big endian. For example, the CGM_OC_EN register may be accessed as a word at address
0xC3FE_0370, as a half-word at address 0xC3FE_0372, or as a byte at address 0xC3FE_0373.
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
5-85
Clock Generation Module (MC_CGM)
5.3.1.1
PLL Clock Divider Register (PLL_CLK_DIV)
Address 0xC3FE_0120
R
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
7
CLK_DIV
0
Figure 26. PLL Clock Divider Register (PLL_CLK_DIV)
This register sets the FMPLL_0 PCS clock division factor.
Table 29. PLL Clock Divider Register (PLL_CLK_DIV) Field Descriptions
Field
Description
CLK_DIV
5.3.1.2
Clock Divider Enable
0 FMPLL_0 PCS clock to system clock selector is divided by 1 (no division)
1 FMPLL_0 PCS clock to system clock selector is divided by 2
System Clock Divider Register (SYSTEM_CLK_DIV)
Address 0xC3FE_0140
R
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
7
CLK_DIV
0
Figure 27. System Clock Divider Register (SYSTEM_CLK_DIV)
This register sets the system clock division factor.
Table 30. System Clock Divider Register (SYSTEM_CLK_DIV) Field Descriptions
Field
CLK_DIV
Description
Clock Divider Enable
0 system clock is divided by 1 (no division)
1 system clock is divided by 2
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5-86
Freescale Semiconductor
Clock Generation Module (MC_CGM)
5.3.1.3
RTC Clock Divider Register (RTC_CLK_DIV)
Address 0xC3FE_0160
R
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
CLK_DIV
W
Reset
0
Figure 28. RTC Clock Divider Register (RTC_CLK_DIV)
This register sets the RTC clock division factor.
Table 31. RTC Clock Divider Register (RTC_CLK_DIV) Field Descriptions
Field
Description
CLK_DIV
5.3.1.4
Clock Divider Enable
0 RTC clock is divided by 1 (no division)
1 RTC clock is divided by 2
Output Clock Enable Register (CGM_OC_EN)
Address 0xC3FE_0370
R
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
EN
0
Figure 29. Output Clock Enable Register (CGM_OC_EN)
This register is used to enable and disable the output clock.
Table 32. Output Clock Enable Register (CGM_OC_EN) Field Descriptions
Field
EN
Description
Output Clock Enable control
0 Output Clock is disabled
1 Output Clock is enabled
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
5-87
Clock Generation Module (MC_CGM)
5.3.1.5
Output Clock Division Select Register (CGM_OCDS_SC)
Address 0xC3FE_0374
R
Access: User read, Supervisor read/write, Test read/write
0
1
0
0
0
0
2
4
5
SELDIV
W
Reset
3
0
6
7
0
0
SELCTL
0
0
0
Figure 30. Output Clock Division Select Register (CGM_OCDS_SC)
This register is used to select the current output clock source and by which factor it is divided before being
delivered at the output clock.
Table 33. Output Clock Enable Register (CGM_OC_EN) Field Descriptions
Field
Description
SELDIV Output Clock Division Select
00 output selected Output Clock without division
01 output selected Output Clock divided by 2
10 output selected Output Clock divided by 4
11 output selected Output Clock divided by 8
SELCTL Output Clock Source Selection Control — This value selects the current source for the output clock.
0000 IRC
0001 XOSC
0010 FMPLL_0
0011 FCD0 A0_CLK
0100 FCD1 A1_CLK
0101 FCD2 A2_CLK
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 reserved
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5-88
Freescale Semiconductor
Clock Generation Module (MC_CGM)
5.3.1.6
System Clock Select Status Register (CGM_SC_SS)
Address 0xC3FE_0378
R
Access: User read, Supervisor read, Test read
0
1
2
3
4
5
6
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
0
0
0
0
0
0
0
0
0
0
0
0
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SELSTAT
W
Reset
R
W
Reset
Figure 31. System Clock Select Status Register (CGM_SC_SS)
This register provides the current system clock source selection.
Table 34. System Clock Select Status Register (CGM_SC_SS) Field Descriptions
Field
Description
SELSTAT
System Clock Source Selection Status — This value indicates the current source for the system clock.
0000 IRC
0001 reserved
0010 XOSC
0011 reserved
0100 FMPLL_0 PCS
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 system clock is disabled
5.4
5.4.1
Functional Description
System Clock Generation
Figure 32 shows the block diagram of the system clock generation logic. The MC_ME provides the system
clock select and switch mask (see MC_ME chapter for more details), and the MC_RGM provides the safe
clock request (see MC_RGM chapter for more details). The safe clock request forces the selector to select
the IRC as the system clock and to ignore the system clock select.
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
5-89
Clock Generation Module (MC_CGM)
IRC
0
XOSC
2
FMPLL_0 PCS
clock
divider
system clock is disabled if
ME_<current mode>_MC.SYSCLK = “1111”
4
’
video clock
PLL_CLK_DIV Register
SYSTEM_CLK_DIV
Register
clock
divider
system clock
MC_RGM SAFE mode request
clock
divider
“000
1
ME_<current mode>
_MC.SYSCLK
0
RTC clock
RTC_CLK_DIV
Register
CGM_SC_SS Register
Figure 32. MC_CGM System Clock Generation Overview
5.4.1.1
System Clock Source Selection
During normal operation, the system clock selection is controlled
• on a SAFE mode or reset event, by the MC_RGM
• otherwise, by the MC_ME
5.4.1.2
System Clock Disable
During the TEST mode, the system clock can be disabled by the MC_ME.
5.4.2
Output Clock Multiplexing
The MC_CGM contains a multiplexing function for a number of clock sources which can then be used as
output clock sources. The selection is done via the CGM_OCDS_SC register.
MPC5604E Reference Manual, Rev. 5
5-90
Freescale Semiconductor
Clock Generation Module (MC_CGM)
5.4.3
Output Clock Division Selection
IRC
XOSC
FMPLL_0
FCD0 A0_CLK
FCD1 A1_CLK
FCD2 A2_CLK
0
1
2
3
4
5
CGM_OC_EN Register
3
2
1
’
CLKOUT
0
CGM_OCDS_SC.SELCTL
Register
CGM_OCDS_SC.SELDIV
Register
Figure 33. MC_CGM Output Clock Multiplexer and CLKOUT Generation
The MC_CGM provides the following output signal for the output clock generation:
• CLKOUT (see Figure 33). This signal is generated by using one of the 3-stage ripple counter
outputs or the selected signal without division. The non-divided signal is not guaranteed to be 50%
duty cycle by the MC_CGM.
The MC_CGM also has an output clock enable register (see Section 5.3.1.4, “Output Clock Enable
Register (CGM_OC_EN)”) that contains the output clock enable/disable control bit.
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
5-91
Clock Generation Module (MC_CGM)
THIS PAGE IS INTENTIONALLY LEFT BLANK
MPC5604E Reference Manual, Rev. 5
5-92
Freescale Semiconductor
Chapter 6
Mode Entry Module (MC_ME)
6.1
6.1.1
Introduction
Overview
The MC_ME controls the chip mode and mode transition sequences in all functional states. It also contains
configuration, control and status registers accessible for the application.
Figure 34 shows the MC_ME block diagram.
MPC5604E Reference Manual Rev. 5
Freescale Semiconductor
6-93
Mode Entry Module (MC_ME)
VREG
Flashes
MC_ME
Registers
Register Interface
MC_RGM
IRC
MC_CGM
XOSC
FMPLL_0
core
Chip
Mode
State
Machine
peripherals
WKPU
Figure 34. MC_ME Block Diagram
MPC5604E Reference Manual, Rev. 5
6-94
Freescale Semiconductor
Mode Entry Module (MC_ME)
6.1.2
Features
The MC_ME includes the following features:
• control of the available modes by the ME_ME register
• definition of various chip mode configurations by the ME_<mode>_MC registers
• control of the actual chip mode by the ME_MCTL register
• capture of the current mode and various resource status within the contents of the ME_GS register
• optional generation of various mode transition interrupts
• status bits for each cause of invalid mode transitions
• peripheral clock gating control based on the ME_RUN_PC0…7, ME_LP_PC0…7, and
ME_PCTLn registers
• capture of current peripheral clock gated/enabled status
6.1.3
Modes of Operation
The MC_ME is based on several chip modes corresponding to different usage models of the chip. Each
mode is configurable and can define a policy for energy and processing power management to fit particular
system requirements. An application can easily switch from one mode to another depending on the current
needs of the system. The operating modes controlled by the MC_ME are divided into system and user
modes. The system modes are modes such as RESET, DRUN, SAFE, and TEST. These modes aim to
ease the configuration and monitoring of the system. The user modes are modes such as RUN0…3,
HALT0, and STOP0 which can be configured to meet the application requirements in terms of energy
management and available processing power. The modes DRUN, SAFE, TEST, and RUN0…3 are the
chip software running modes.
Table 35 describes the MC_ME modes.
Table 35. MC_ME Mode Descriptions
Name
Description
Entry
Exit
RESET
This is a chip-wide virtual mode during which the
system reset
application is not active. The system remains in this mode assertion from
until all resources are available for the embedded software MC_RGM
to take control of the chip. It manages hardware
initialization of chip configuration, voltage regulators, clock
sources, and flash modules.
system reset
deassertion from
MC_RGM
DRUN
This is the entry mode for the embedded software. It
provides full accessibility to the system and enables the
configuration of the system at startup. It provides the
unique gate to enter user modes. BAM when present is
executed in DRUN mode.
system reset
deassertion from
MC_RGM,
software request
from SAFE, TEST
and RUN0…3
system reset
assertion,
RUN0…3, TEST
via software,
SAFE via software
or hardware
failure.
SAFE
This is a chip-wide service mode which may be entered on
the detection of a recoverable error. It forces the system
into a pre-defined safe configuration from which the system
may try to recover.
hardware failure,
software request
from DRUN, and
RUN0…3
system reset
assertion, DRUN
via software
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
6-95
Mode Entry Module (MC_ME)
Table 35. MC_ME Mode Descriptions (continued)
Name
6.2
Description
Entry
Exit
TEST
This is a chip-wide service mode which is intended to
provide a control environment for chip software testing.
software request
from DRUN
system reset
assertion, DRUN
via software
RUN0…3
These are software running modes where most processing
activity is done. These various run modes allow to enable
different clock & power configurations of the system with
respect to each other.
software request
from DRUN or
other RUN0…3,
interrupt event
from HALT0,
interrupt or
wakeup event from
STOP0
system reset
assertion, SAFE
via software or
hardware failure,
other RUN0…3
modes, HALT0,
STOP0 via
software
HALT0
This is a reduced-activity low-power mode during which the software request
clock to the core is disabled. It can be configured to switch from RUN0…3
off analog peripherals like clock sources, flash, main
regulator, etc. for efficient power management at the cost of
higher wakeup latency.
system reset
assertion, SAFE
on recoverable
hardware failure,
RUN0…3 on
off-platform
interrupt event
STOP0
software request
This is an advanced low-power mode during which the
clock to the core is disabled. It may be configured to switch from RUN0…3
off most of the peripherals including clock sources for
efficient power management at the cost of higher wakeup
latency.
system reset
assertion, SAFE
on recoverable
hardware failure,
RUN0…3 on
interrupt event or
wakeup event
External Signal Description
The MC_ME has no connections to any external pins.
6.3
Memory Map and Register Definition
The MC_ME contains registers for:
• mode selection and status reporting
• mode configuration
• mode transition interrupts status and mask control
• scalable number of peripheral sub-mode selection and status reporting
MPC5604E Reference Manual, Rev. 5
6-96
Freescale Semiconductor
Mode Entry Module (MC_ME)
6.3.1
Memory Map
Table 36. MC_ME Register Description
Access
Address
Name
Description
Size
Location
User
Supervisor
Test
read
0xC3FD ME_GS
_C000
Global Status
word
read
read
on page 105
0xC3FD ME_MCTL
_C004
Mode Control
word
read
read/write
read/write on page 107
0xC3FD ME_ME
_C008
Mode Enable
word
read
read/write
read/write on page 108
0xC3FD ME_IS
_C00C
Interrupt Status
word
read
read/write
read/write on page 110
0xC3FD ME_IM
_C010
Interrupt Mask
word
read
read/write
read/write on page 111
0xC3FD ME_IMTS
_C014
Invalid Mode Transition
Status
word
read
read/write
read/write on page 112
0xC3FD ME_DMTS
_C018
Debug Mode Transition
Status
word
read
read
read
on page 113
0xC3FD ME_RESET_MC
_C020
RESET Mode
Configuration
word
read
read
read
on page 116
0xC3FD ME_TEST_MC
_C024
TEST Mode
Configuration
word
read
read/write
read/write on page 116
0xC3FD ME_SAFE_MC
_C028
SAFE Mode
Configuration
word
read
read/write
read/write on page 117
0xC3FD ME_DRUN_MC
_C02C
DRUN Mode
Configuration
word
read
read/write
read/write on page 117
0xC3FD ME_RUN0_MC
_C030
RUN0 Mode
Configuration
word
read
read/write
read/write on page 118
0xC3FD ME_RUN1_MC
_C034
RUN1 Mode
Configuration
word
read
read/write
read/write on page 118
0xC3FD ME_RUN2_MC
_C038
RUN2 Mode
Configuration
word
read
read/write
read/write on page 118
0xC3FD ME_RUN3_MC
_C03C
RUN3 Mode
Configuration
word
read
read/write
read/write on page 118
0xC3FD ME_HALT0_MC
_C040
HALT0 Mode
Configuration
word
read
read/write
read/write on page 118
0xC3FD ME_STOP0_MC
_C048
STOP0 Mode
Configuration
word
read
read/write
read/write on page 119
0xC3FD ME_PS0
_C060
Peripheral Status 0
word
read
read
read
on page 121
0xC3FD ME_PS1
_C064
Peripheral Status 1
word
read
read
read
on page 121
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
6-97
Mode Entry Module (MC_ME)
Table 36. MC_ME Register Description (continued)
Access
Address
Name
Description
Size
Location
User
Supervisor
Test
0xC3FD ME_PS2
_C068
Peripheral Status 2
word
read
read
read
on page 122
0xC3FD ME_PS3
_C06C
Peripheral Status 3
word
read
read
read
on page 122
0xC3FD ME_RUN_PC0
_C080
Run Peripheral
Configuration 0
word
read
read/write
read/write on page 123
0xC3FD ME_RUN_PC1
_C084
Run Peripheral
Configuration 1
word
read
read/write
read/write on page 123
…
0xC3FD ME_RUN_PC7
_C09C
Run Peripheral
Configuration 7
word
read
read/write
read/write on page 123
0xC3FD ME_LP_PC0
_C0A0
Low-Power Peripheral
Configuration 0
word
read
read/write
read/write on page 124
0xC3FD ME_LP_PC1
_C0A4
Low-Power Peripheral
Configuration 1
word
read
read/write
read/write on page 124
…
0xC3FD ME_LP_PC7
_C0BC
Low-Power Peripheral
Configuration 7
word
read
read/write
read/write on page 124
0xC3FD ME_PCTL4
_C0C4
DSPI0 Control
byte
read
read/write
read/write on page 124
0xC3FD ME_PCTL5
_C0C5
DSPI1 Control
byte
read
read/write
read/write on page 124
0xC3FD ME_PCTL6
_C0C6
DSPI2 Control
byte
read
read/write
read/write on page 124
0xC3FD ME_PCTL16
_C0D0
FlexCAN0 Control
byte
read
read/write
read/write on page 124
0xC3FD ME_PCTL22
_C0D6
SAI0 Control
byte
read
read/write
read/write on page 124
0xC3FD ME_PCTL23
_C0D7
DMA_CH_MUX Control
byte
read
read/write
read/write on page 124
0xC3FD ME_PCTL28
_C0DC
SAI1 Control
byte
read
read/write
read/write on page 124
0xC3FD ME_PCTL29
_C0DD
SAI2 Control
byte
read
read/write
read/write on page 124
0xC3FD ME_PCTL30
_C0DE
Video Control
byte
read
read/write
read/write on page 124
0xC3FD ME_PCTL32
_C0E0
ADC0 Control
byte
read
read/write
read/write on page 124
MPC5604E Reference Manual, Rev. 5
6-98
Freescale Semiconductor
Mode Entry Module (MC_ME)
Table 36. MC_ME Register Description (continued)
Access
Address
Name
Description
Size
Location
User
Supervisor
Test
0xC3FD ME_PCTL38
_C0E6
eTimer0 Control
byte
read
read/write
read/write on page 124
0xC3FD ME_PCTL44
_C0EC
I2C_DMA0 Control
byte
read
read/write
read/write on page 124
0xC3FD ME_PCTL45
_C0ED
I2C_DMA1 Control
byte
read
read/write
read/write on page 124
0xC3FD ME_PCTL48
_C0F0
LIN_FLEX0 Control
byte
read
read/write
read/write on page 124
0xC3FD ME_PCTL49
_C0F1
LIN_FLEX1 Control
byte
read
read/write
read/write on page 124
0xC3FD ME_PCTL58
_C0FA
CRC Control
byte
read
read/write
read/write on page 124
0xC3FD ME_PCTL61
_C0FD
PTP Control
byte
read
read/write
read/write on page 124
0xC3FD ME_PCTL62
_C0FE
CE_RTC Control
byte
read
read/write
read/write on page 124
0xC3FD ME_PCTL92
_C11C
PIT_RTI Control
byte
read
read/write
read/write on page 124
0xC3FD ME_PCTL104
_C128
CMU0 Control
byte
read
read/write
read/write on page 124
NOTE
Any access to unused registers as well as write accesses to read-only
registers will:
•
•
not change register content
cause a transfer error
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
6-99
Mode Entry Module (MC_ME)
0xC3FD ME_GS
_C000
0
1
2
3
27
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
0
0
0
0
S_MVR
Name
S_PDO
Address
S_MTRANS
Table 37. MC_ME Memory Map
S_DFLA
R S_CURRENT_MODE
S_CFLA
S_FMPLL_0
S_XOSC
S_IRC
W
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
R
S_SYSCLK
W
R
TARGET_MODE
W
R
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RUN3
RUN2
RUN1
R
HALT0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRUN
SAFE
TEST
RESET_FUNC
0
0
0
0
0
I_IMODE
I_SAFE
I_MTC
R
I_ICONF
W
RUN0
0xC3FD ME_ME
_C008
KEY
STOP0
W
I_ICONF_CU
0xC3FD ME_MCTL
_C004
W
R
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
M_MTC
R
M_ICONF
0xC3FD ME_IM
_C010
w1c w1c w1c w1c w1c
M_ICONF_CU
W
M_SAFE
R
M_IMODE
0xC3FD ME_IS
_C00C
W
R
W
MPC5604E Reference Manual, Rev. 5
6-100
Freescale Semiconductor
Mode Entry Module (MC_ME)
2
3
27
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S_NMA
R
1
0
0
0
CDP_PRPH_64_95
0
0
DFLAON
0
SMR
0
CORE_DBG
CFLASH_SC
0
0
CDP_PRPH_96_127
0
PMC_PROG
0
MVRON
0
MPH_BUSY
0
DFLASH_SC
PREVIOUS_MODE
SYSCLK_SW
R
SCSRC_SC
0xC3FD ME_DMTS
_C018
CDP_PRPH_0_143
w1c w1c w1c w1c w1c
PDO
W
CDP_PRPH_0_31
R
S_SEA
W
CDP_PRPH_32_63
0xC3FD ME_IMTS
_C014
0
S_DMA
Name
S_MTI
Address
S_MRI
Table 37. MC_ME Memory Map (continued)
IRC_SC
0
CSRC_CSRC_SC
R
VREG_CSRC_SC
W
W
0xC3FD
_C01C
0xC3FD ME_RESET_
_C020 MC
reserved
R
0
0
0
0
0
0
0
CFLAON
FMPLL_0ON
XOSCON
IRCON
PDO
0
0
MVRON
0
FMPLL_0ON
W
R
SYSCLK
W
0xC3FD ME_TEST_M
_C024 C
R
0
0
0
0
0
0
0
0
DFLAON
CFLAON
0
0
0
0
0
0
0
0
W
IRCON
R
XOSCON
W
SYSCLK
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
6-101
Mode Entry Module (MC_ME)
2
3
27
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
MVRON
IRCON
R
1
0
0
MVRON
0xC3FD ME_SAFE_M
_C028 C
0
XOSCON
Name
PDO
Address
FMPLL_0ON
Table 37. MC_ME Memory Map (continued)
DFLAON
CFLAON
W
R
SYSCLK
0xC3FD ME_DRUN_M
_C02C C
R
0
0
0
0
0
0
0
0
PDO
W
DFLAON
CFLAON
0
0
0
0xC3FD ME_RUN0…3
_C030 _MC
R
…
0xC3FD
W
_C03C
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PDO
W
0
0xC3FD ME_HALT0_
_C040 MC
R
0
0
0
0
0
0
0
0
PDO
W
0
0
0
0
IRCON
0
MVRON
0
IRCON
0
MVRON
0
XOSCON
0
XOSCON
0
FMPLL_0ON
R
FMPLL_0ON
W
SYSCLK
DFLAON
CFLAON
SYSCLK
DFLAON
CFLAON
0
0
0
0
0
0
0
0
W
0xC3FD
_C044
IRCON
0
XOSCON
R
FMPLL_0ON
W
SYSCLK
reserved
MPC5604E Reference Manual, Rev. 5
6-102
Freescale Semiconductor
Mode Entry Module (MC_ME)
Name
0xC3FD ME_STOP0_
_C048 MC
R
0
1
2
3
27
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
MVRON
Address
PDO
Table 37. MC_ME Memory Map (continued)
0
0
DFLAON
CFLAON
0
0
0
0
0
0
IRCON
0
S_DSPI0
0
XOSCON
R
S_DSPI1
W
SYSCLK
W
0xC3FD
_C04C
…
0xC3FD
_C05C
S_FlexCAN0
S_SAI0
S_DMA_CH_MUX
S_SAI1
R
S_SAI2
0xC3FD ME_PS0
_C060
S_Video
reserved
S_DSPI2
W
R
S_LIN_FLEX0
S_LIN_FLEX1
S_CRC
R
S_PTP
0xC3FD ME_PS1
_C064
S_CE_RTC
W
S_ADC0
S_eTimer0
S_I2C_DMA0
R
S_I2C_DMA1
W
W
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
6-103
Mode Entry Module (MC_ME)
Table 37. MC_ME Memory Map (continued)
Name
0xC3FD ME_PS2
_C068
0
1
2
3
27
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
S_PIT_RTI
Address
R
W
R
W
R
W
S_CMU0
0xC3FD ME_PS3
_C06C
R
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RUN0
DRUN
SAFE
TEST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0
RUN1
0xC3FD ME_RUN_PC R
_C080 0…7
W
…
0xC3FD
_C09C
R
RUN2
reserved
RUN3
0xC3FD
_C074
…
0xC3FD
_C07C
HALT0
reserved
STOP0
0xC3FD
_C070
W
0xC3FD ME_LP_PC0
_C0A0 …7
…
0xC3FD
_C0BC
R
W
R
W
MPC5604E Reference Manual, Rev. 5
6-104
Freescale Semiconductor
Mode Entry Module (MC_ME)
Name
0xC3FD ME_PCTL0… R
_C0C0 1431
W
…
0xC3FD
R
_C14C
W
0
1
2
3
27
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
DBG_F DBG_F
Address
DBG_F DBG_F
Table 37. MC_ME Memory Map (continued)
0
LP_CFG
RUN_CFG
LP_CFG
RUN_CFG
0
0xC3FD
_C150
…
0xC3FD
_FFFC
1
LP_CFG
RUN_CFG
LP_CFG
RUN_CFG
reserved
There is space in the register map for 144 peripherals. Please refer to Table 36 for the ME_PCTLn locations
actually occupied. The unoccupied locations contain a read-only byte value of 0x00.
6.3.2
Register Description
Unless otherwise noted, all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes.
The bytes are ordered according to big endian. For example, the ME_RUN_PC0 register may be accessed
as a word at address 0xC3FD_C080, as a half-word at address 0xC3FD_C082, or as a byte at address
0xC3FD_C083.
Some fields may be read-only, and their reset value of ‘1’ or ‘0’ and the corresponding behavior cannot be
changed.
6.3.2.1
Global Status Register (ME_GS)
3
4
5
6
7
8
9
10
11
12
S_CURRENT_MODE
1
0
0
S_PDO
0
0
S_MVR
S_DFLA
S_CFLA
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
S_FMPLL_0
S_XOSC
S_IRC
0
1
2
Access: User read, Supervisor read, Test read
S_MTRANS
Address 0xC3FD_C000
0
0
1
R
13
14
15
W
Reset
R
S_SYSCLK
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 35. Global Status Register (ME_GS)
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
6-105
Mode Entry Module (MC_ME)
This register contains global mode status.
Table 38. Global Status Register (ME_GS) Field Descriptions
Field
Description
S_CURREN Current chip mode status
T_MODE
0000 RESET
0001 TEST
0010 SAFE
0011 DRUN
0100 RUN0
0101 RUN1
0110 RUN2
0111 RUN3
1000 HALT0
1001 reserved
1010 STOP0
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 reserved
S_MTRANS Mode transition status
0 Mode transition process is not active
1 Mode transition is ongoing
S_PDO
Output power-down status — This bit specifies output power-down status of I/Os. This bit is asserted
whenever outputs of pads are forced to high impedance state or the pads power sequence driver is
switched off.
0 No automatic safe gating of I/Os used and pads power sequence driver is enabled
1 In SAFE/TEST modes, outputs of pads are forced to high impedance state and the pads power
sequence driver is disabled. The inputs are level unchanged. In STOP0 mode, only the pad power
sequence driver is disabled, but the state of the output remains functional.
S_MVR
Main voltage regulator status
0 Main voltage regulator is not ready
1 Main voltage regulator is ready for use
S_DFLA
Data flash availability status
00 Data flash is not available
01 Data flash is in power-down mode
10 Data flash is not available
11 Data flash is in normal mode and available for use
S_CFLA
Code flash availability status
00 Code flash is not available
01 Code flash is in power-down mode
10 Code flash is in low-power mode
11 Code flash is in normal mode and available for use
S_FMPLL_0 system PLL status
0 system PLL is not stable
1 system PLL is providing a stable clock
S_XOSC
external oscillator status
0 external oscillator is not stable
1 external oscillator is providing a stable clock
MPC5604E Reference Manual, Rev. 5
6-106
Freescale Semiconductor
Mode Entry Module (MC_ME)
Table 38. Global Status Register (ME_GS) Field Descriptions (continued)
Field
Description
S_IRC
internal RC oscillator status
0 internal RC oscillator is not stable
1 internal RC oscillator is providing a stable clock
S_SYSCLK
6.3.2.2
System clock switch status — These bits specify the system clock currently used by the system.
0000 IRC
0001 reserved
0010 XOSC
0011 reserved
0100 FMPLL_0 PCS
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 system clock is disabled
Mode Control Register (ME_MCTL)
Address 0xC3FD_C004
0
R
R
2
3
TARGET_MODE
W
Reset
1
Access: User read, Supervisor read/write, Test read/write
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
0
1
0
0
1
0
1
0
0
0
0
1
1
1
1
1
0
1
0
0
1
0
1
0
0
0
0
1
1
1
1
W
Reset
KEY
Figure 36. Mode Control Register (ME_MCTL)
This register is used to trigger software-controlled mode changes. Depending on the modes as enabled by
ME_ME register bits, configurations corresponding to unavailable modes are reserved and access to
ME_<mode>_MC registers must respect this for successful mode requests.
NOTE
Byte and half-word write accesses are not allowed for this register as a
predefined key is required to change its value.
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
6-107
Mode Entry Module (MC_ME)
Table 39. Mode Control Register (ME_MCTL) Field Descriptions
Field
Description
TARGET_M
ODE
Target chip mode — These bits provide the target chip mode to be entered by software
programming. The mechanism to enter into any mode by software requires the write operation twice:
first time with key, and second time with inverted key. These bits are automatically updated by
hardware while entering SAFE on hardware request. Also, while exiting from the HALT0 and STOP0
modes on hardware exit events, these are updated with the appropriate RUN0…3 mode value.
0000 RESET (triggers a ‘functional’ reset event)
0001 TEST
0010 SAFE
0011 DRUN
0100 RUN0
0101 RUN1
0110 RUN2
0111 RUN3
1000 HALT0
1001 reserved
1010 STOP0
1011 reserved
1100 reserved
1101 disabled
1110 reserved
1111 disabled
Note: 1101 and 1111 modes are permanently disabled. Setting these modes will set S_DMA bit in
ME_IMTS register.
KEY
6.3.2.3
Control key — These bits enable write access to this register. Any write access to the register
with a value different from the keys is ignored. Read access will always return inverted key.
KEY:0101101011110000 (0x5AF0)
INVERTED KEY:1010010100001111 (0xA50F)
Mode Enable Register (ME_ME)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
HALT0
RUN3
RUN2
RUN1
RUN0
DRUN
SAFE
R
Access: User read, Supervisor read/write, Test read/write
STOP0
Address 0xC3FD_C008
0
0
0
0
0
0
0
0
0
0
1
1
1
TEST
R
RESET_FUNC
W
Reset
W
Reset
0
0
01
Figure 37. Mode Enable Register (ME_ME)
MPC5604E Reference Manual, Rev. 5
6-108
Freescale Semiconductor
Mode Entry Module (MC_ME)
This register allows a way to disable the chip modes which are not required for a given chip. RESET,
SAFE, DRUN, and RUN0 modes are always enabled.
Table 40. Mode Enable Register (ME_ME) Field Descriptions
Field
Description
STOP0
STOP0 mode enable
0 STOP0 mode is disabled
1 STOP0 mode is enabled
HALT0
HALT0 mode enable
0 HALT0 mode is disabled
1 HALT0 mode is enabled
RUN3
RUN3 mode enable
0 RUN3 mode is disabled
1 RUN3 mode is enabled
RUN2
RUN2 mode enable
0 RUN2 mode is disabled
1 RUN2 mode is enabled
RUN1
RUN1 mode enable
0 RUN1 mode is disabled
1 RUN1 mode is enabled
RUN0
RUN0 mode enable
1 RUN0 mode is enabled
DRUN
DRUN mode enable
1 DRUN mode is enabled
SAFE
SAFE mode enable
1 SAFE mode is enabled
TEST
TEST mode enable
0 TEST mode is disabled
1 TEST mode is enabled
RESET_FUN ‘functional’ RESET mode enable
C
1 ‘functional’ RESET mode is enabled
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
6-109
Mode Entry Module (MC_ME)
6.3.2.4
Interrupt Status Register (ME_IS)
Address 0xC3FD_C00C
R
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
I_ICONF
I_IMODE
I_SAFE
I_MTC
Reset
I_ICONF_CU
W
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
Figure 38. Interrupt Status Register (ME_IS)
This register provides the current interrupt status.
Table 41. Interrupt Status Register (ME_IS) Field Descriptions
Field
Description
I_ICONF_CU Invalid mode configuration interrupt (Clock Usage) — This bit is set during a mode transition if a
clock which is required to be on by an enabled peripheral is configured to be turned off. It is cleared
by writing a ‘1’ to this bit.
0 No invalid mode configuration (clock usage) interrupt occurred
1 Invalid mode configuration (clock usage) interrupt is pending
I_ICONF
Invalid mode configuration interrupt — This bit is set whenever a write operation to
ME_<mode>_MC registers with invalid mode configuration is attempted. It is cleared by writing a ‘1’
to this bit.
0 No invalid mode configuration interrupt occurred
1 Invalid mode configuration interrupt is pending
I_IMODE
Invalid mode interrupt — This bit is set whenever an invalid mode transition is requested. It is
cleared by writing a ‘1’ to this bit.
0 No invalid mode interrupt occurred
1 Invalid mode interrupt is pending
I_SAFE
SAFE mode interrupt — This bit is set whenever the chip enters SAFE mode on hardware requests
generated in the system. It is cleared by writing a ‘1’ to this bit.
0 No SAFE mode interrupt occurred
1 SAFE mode interrupt is pending
I_MTC
Mode transition complete interrupt — This bit is set whenever the mode transition process
completes (S_MTRANS transits from 1 to 0). It is cleared by writing a ‘1’ to this bit. This mode
transition interrupt bit will not be set while entering low-power modes HALT0, or STOP0.
0 No mode transition complete interrupt occurred
1 Mode transition complete interrupt is pending
MPC5604E Reference Manual, Rev. 5
6-110
Freescale Semiconductor
Mode Entry Module (MC_ME)
6.3.2.5
Interrupt Mask Register (ME_IM)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
M_ICONF
M_IMODE
M_SAFE
M_MTC
R
Access: User read, Supervisor read/write, Test read/write
M_ICONF_CU
Address 0xC3FD_C010
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 39. Interrupt Mask Register (ME_IM)
This register controls whether an event generates an interrupt or not.
Table 42. Interrupt Mask Register (ME_IM) Field Descriptions
Field
Description
M_ICONF_C Invalid mode configuration (clock usage) interrupt mask
U
0 Invalid mode interrupt is masked
1 Invalid mode interrupt is enabled
M_ICONF
Invalid mode configuration interrupt mask
0 Invalid mode interrupt is masked
1 Invalid mode interrupt is enabled
M_IMODE
Invalid mode interrupt mask
0 Invalid mode interrupt is masked
1 Invalid mode interrupt is enabled
M_SAFE
SAFE mode interrupt mask
0 SAFE mode interrupt is masked
1 SAFE mode interrupt is enabled
M_MTC
Mode transition complete interrupt mask
0 Mode transition complete interrupt is masked
1 Mode transition complete interrupt is enabled
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
6-111
Mode Entry Module (MC_ME)
6.3.2.6
Invalid Mode Transition Status Register (ME_IMTS)
Address 0xC3FD_C014
R
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S_NMA
S_SEA
W
Reset
S_DMA
R
S_MRI
Reset
S_MTI
W
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
Figure 40. Invalid Mode Transition Status Register (ME_IMTS)
This register provides the status bits for the possible causes of an invalid mode interrupt.
Table 43. Invalid Mode Transition Status Register (ME_IMTS) Field Descriptions
Field
Description
S_MTI
Mode Transition Illegal status — This bit is set whenever a new mode is requested while some
other mode transition process is active (S_MTRANS is ‘1’). Please refer to Section 6.4.5, “Mode
Transition Interrupts” for the exceptions to this behavior. It is cleared by writing a ‘1’ to this bit.
0 Mode transition requested is not illegal
1 Mode transition requested is illegal
S_MRI
Mode Request Illegal status — This bit is set whenever the target mode requested is not a valid
mode with respect to current mode. It is cleared by writing a ‘1’ to this bit.
0 Target mode requested is not illegal with respect to current mode
1 Target mode requested is illegal with respect to current mode
S_DMA
Disabled Mode Access status — This bit is set whenever the target mode requested is one of those
disabled modes determined by ME_ME register. It is cleared by writing a ‘1’ to this bit.
0 Target mode requested is not a disabled mode
1 Target mode requested is a disabled mode
S_NMA
Non-existing Mode Access status — This bit is set whenever the target mode requested is one of
those non existing modes determined by ME_MCTL register. It is cleared by writing a ‘1’ to this bit.
0 Target mode requested is an existing mode
1 Target mode requested is a non-existing mode
S_SEA
SAFE Event Active status — This bit is set whenever the chip is in SAFE mode, SAFE event bit is
pending and a new mode requested other than RESET/SAFE modes. It is cleared by writing a ‘1’ to
this bit.
0 No new mode requested other than RESET/SAFE while SAFE event is pending
1 New mode requested other than RESET/SAFE while SAFE event is pending
MPC5604E Reference Manual, Rev. 5
6-112
Freescale Semiconductor
Mode Entry Module (MC_ME)
6.3.2.7
Debug Mode Transition Status Register (ME_DMTS)
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
CDP_PRPH_0_31
14
CDP_PRPH_32_63
13
CDP_PRPH_64_95
12
CORE_DBG
11
CDP_PRPH_96_127
10
PMC_PROG
9
MPH_BUSY
8
CDP_PRPH_0_143
7
CFLASH_SC
6
DFLASH_SC
5
SYSCLK_SW
4
SCSRC_SC
3
IRC_SC
2
CSRC_CSRC_SC
1
VREG_CSRC_SC
0
Access: User read, Supervisor read/write, Test read/write
SMR
Address 0xC3FD_C018
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
PREVIOUS_MODE
W
Reset
R
W
Reset
0
Figure 41. Debug Mode Transition Status Register (ME_DMTS)
This register provides the status of different factors which influence mode transitions. It is used to give an
indication of why a mode transition indicated by ME_GS.S_MTRANS may be taking longer than
expected.
NOTE
The ME_DMTS register does not indicate whether a mode transition is
ongoing. Therefore, some ME_DMTS bits may still be asserted after the
mode transition has completed.
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
6-113
Mode Entry Module (MC_ME)
Table 44. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions
Field
Description
PREVIOUS_ Previous chip mode — These bits show the mode in which the chip was prior to the latest change
MODE
to the current mode.
0000 RESET
0001 TEST
0010 SAFE
0011 DRUN
0100 RUN0
0101 RUN1
0110 RUN2
0111 RUN3
1000 HALT0
1001 reserved
1010 STOP0
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 reserved
MPH_BUSY MC_ME/MC_PCU Handshake Busy indicator — This bit is set if the MC_ME has requested a mode
change from the MC_PCU and the MC_PCU has not yet responded. It is cleared when the MC_PCU
has responded.
0 Handshake is not busy
1 Handshake is busy
PMC_PROG MC_PCU Mode Change in Progress indicator — This bit is set if the MC_PCU is in the process of
powering up or down power domains. It is cleared when all power-up/down processes have
completed.
0 Power-up/down transition is not in progress
1 Power-up/down transition is in progress
CORE_DBG Processor is in Debug mode indicator — This bit is set while the processor is in debug mode.
0 The processor is not in debug mode
1 The processor is in debug mode
SMR
SAFE mode request from MC_RGM is active indicator — This bit is set if a hardware SAFE mode
request has been triggered. It is cleared when the hardware SAFE mode request has been cleared.
0 A SAFE mode request is not active
1 A SAFE mode request is active
VREG_CSR Main VREG dependent Clock Source State Change during mode transition indicator — This bit is set
C_SC
when a clock source which depends on the main voltage regulator to be powered-up is requested to
change its power up/down state. It is cleared when the clock source has completed its state change.
0 No state change is taking place
1 A state change is taking place
CSRC_CSR (Other) Clock Source dependent Clock Source State Change during mode transition indicator — This
C_SC
bit is set when a clock source which depends on another clock source to be powered-up is requested
to change its power up/down state. It is cleared when the clock source has completed its state
change.
0 No state change is taking place
1 A state change is taking place
MPC5604E Reference Manual, Rev. 5
6-114
Freescale Semiconductor
Mode Entry Module (MC_ME)
Table 44. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions (continued)
Field
Description
IRC_SC
IRC State Change during mode transition indicator — This bit is set when the internal RC oscillator
is requested to change its power up/down state. It is cleared when the internal RC oscillator has
completed its state change.
0 No state change is taking place
1 A state change is taking place
SYSCLK_S
W
System Clock Switching pending status —
0 No system clock source switching is pending
1 A system clock source switching is pending
DFLASH_SC DFLASH State Change during mode transition indicator — This bit is set when the DFLASH is
requested to change its power up/down state. It is cleared when the DFLASH has completed its state
change.
0 No state change is taking place
1 A state change is taking place
CFLASH_SC CFLASH State Change during mode transition indicator — This bit is set when the CFLASH is
requested to change its power up/down state. It is cleared when the DFLASH has completed its state
change.
0 No state change is taking place
1 A state change is taking place
CDP_PRPH Clock Disable Process Pending status for Peripherals 0…1431 — This bit is set when any peripheral
has been requested to have its clock disabled. It is cleared when all the peripherals which have been
_0_143
requested to have their clocks disabled have entered the state in which their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
CDP_PRPH Clock Disable Process Pending status for Peripherals 96…1271— This bit is set when any peripheral
appearing in ME_PS3 has been requested to have its clock disabled. It is cleared when all these
_96_127
peripherals which have been requested to have their clocks disabled have entered the state in which
their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
CDP_PRPH Clock Disable Process Pending status for Peripherals 64…951 — This bit is set when any peripheral
appearing in ME_PS2 has been requested to have its clock disabled. It is cleared when all these
_64_95
peripherals which have been requested to have their clocks disabled have entered the state in which
their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
CDP_PRPH Clock Disable Process Pending status for Peripherals 32…631 — This bit is set when any peripheral
appearing in ME_PS1 has been requested to have its clock disabled. It is cleared when all these
_32_63
peripherals which have been requested to have their clocks disabled have entered the state in which
their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
CDP_PRPH Clock Disable Process Pending status for Peripherals 0…311 — This bit is set when any peripheral
appearing in ME_PS0 has been requested to have its clock disabled. It is cleared when all these
_0_31
peripherals which have been requested to have their clocks disabled have entered the state in which
their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
6-115
Mode Entry Module (MC_ME)
1
Peripheral n corresponds to the ME_PCTLn register. Please refer to Table 36 for the ME_PCTLn locations actually
occupied, which in turn indicates which peripherals are reported in the ME_DMTS register.
6.3.2.8
RESET Mode Configuration Register (ME_RESET_MC)
0
1
2
3
4
5
6
7
8
9
10
11
12
0
0
0
0
0
0
0
0
PDO
0
0
MVRON
DFLAON
CFLAON
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
XOSCON
IRCON
Access: User read, Supervisor read/write, Test read/write
FMPLL_0ON
Address 0xC3FD_C020
0
0
1
R
13
14
15
W
Reset
R
SYSCLK
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 42. RESET Mode Configuration Register (ME_RESET_MC)
This register configures system behavior during RESET mode. Please refer to Table 45 for details.
TEST Mode Configuration Register (ME_TEST_MC)
Address 0xC3FD_C024
Access: User read, Supervisor read/write, Test read/write
9
10
11
0
0
MVRON
6.3.2.9
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
0
0
0
0
0
0
0
8
0
0
0
23
24
25
0
0
14
15
DFLAON
CFLAON
1
1
1
1
1
26
27
28
29
30
31
IRCON
13
XOSCON
PDO
12
FMPLL_0ON
R
0
0
1
W
Reset
R
W
Reset
0
0
0
0
0
0
0
0
0
SYSCLK
0
0
0
0
Figure 43. TEST Mode Configuration Register (ME_TEST_MC)
This register configures system behavior during TEST mode. Please refer to Table 45 for details.
NOTE
Byte write accesses are not allowed to this register.
MPC5604E Reference Manual, Rev. 5
6-116
Freescale Semiconductor
Mode Entry Module (MC_ME)
SAFE Mode Configuration Register (ME_SAFE_MC)
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
9
10
11
12
0
0
MVRON
0
DFLAON
CFLAON
1
0
0
1
1
1
1
1
24
25
26
27
28
29
30
31
IRCON
Access: User read, Supervisor read/write, Test read/write
XOSCON
Address 0xC3FD_C028
FMPLL_0ON
6.3.2.10
8
0
0
1
R
PDO
13
14
15
W
Reset
R
SYSCLK
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 44. SAFE Mode Configuration Register (ME_SAFE_MC)
This register configures system behavior during SAFE mode. Please refer to Table 45 for details.
NOTE
Byte write accesses are not allowed to this register.
6.3.2.11
DRUN Mode Configuration Register (ME_DRUN_MC)
0
1
2
3
4
5
6
7
8
9
10
11
0
0
0
0
0
0
0
0
PDO
0
0
MVRON
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
0
0
0
0
0
0
0
0
0
XOSCON
Access: User read, Supervisor read/write, Test read/write
FMPLL_0ON
Address 0xC3FD_C02C
0
0
R
12
13
14
15
DFLAON
CFLAON
1
1
1
1
1
27
28
29
30
31
R
W
Reset
0
0
0
0
0
0
0
0
0
IRCON
W
Reset
1
SYSCLK
0
0
0
0
Figure 45. DRUN Mode Configuration Register (ME_DRUN_MC)
This register configures system behavior during DRUN mode. Please refer to Table 45 for details.
NOTE
Byte write accesses are not allowed to this register.
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
6-117
Mode Entry Module (MC_ME)
6.3.2.12
RUN0..3 Mode Configuration Register (ME_RUN0..3_MC)
0
1
2
3
4
5
6
7
8
9
10
11
0
0
0
0
0
0
0
0
PDO
0
0
MVRON
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
0
0
0
0
0
0
0
0
0
XOSCON
Access: User read, Supervisor read/write, Test read/write
FMPLL_0ON
Address 0xC3FD_C030 - 0xC3FD_C03C
0
0
R
12
13
14
15
DFLAON
CFLAON
1
1
1
1
1
27
28
29
30
31
Reset
R
W
Reset
0
0
0
0
0
0
0
0
0
IRCON
W
1
SYSCLK
0
0
0
0
Figure 46. RUN0…3 Mode Configuration Registers (ME_RUN0…3_MC)
This register configures system behavior during RUN0…3 modes. Please refer to Table 45 for details.
NOTE
Byte write accesses are not allowed to this register.
6.3.2.13
HALT0 Mode Configuration Register (ME_HALT0_MC)
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
8
9
10
11
0
0
0
0
0
0
0
0
PDO
0
0
MVRON
Address 0xC3FD_C040
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
0
0
0
0
0
0
0
0
0
14
15
DFLAON
CFLAON
1
1
1
1
1
26
27
28
29
30
31
IRCON
13
XOSCON
12
FMPLL_0ON
R
0
0
1
W
Reset
R
W
Reset
0
0
0
0
0
0
0
0
0
SYSCLK
0
0
0
0
Figure 47. HALT0 Mode Configuration Register (ME_HALT0_MC)
This register configures system behavior during HALT0 mode. Please refer to Table 45 for details.
NOTE
Byte write accesses are not allowed to this register.
MPC5604E Reference Manual, Rev. 5
6-118
Freescale Semiconductor
Mode Entry Module (MC_ME)
6.3.2.14
STOP0 Mode Configuration Register (ME_STOP0_MC)
Access: User read, Supervisor read/write, Test read/write
9
10
11
0
0
MVRON
Address 0xC3FD_C048
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
0
0
0
0
0
0
0
0
0
0
0
0
8
0
0
0
23
24
25
0
0
0
0
0
0
15
DFLAON
CFLAON
1
0
1
0
1
26
27
28
29
30
31
IRCON
14
XOSCON
PDO
13
FMPLL_0ON1
R
12
0
0
1
W
Reset
R
SYSCLK
W
Reset
0
0
0
0
Figure 48. STOP0 Mode Configuration Register (ME_STOP0_MC)
1
Invalid mode configuration interrupt (I_ICONF) is generated if software tries to set this bit.
This register configures system behavior during STOP0 mode. Please refer to Table 45 for details.
NOTE
Byte write accesses are not allowed to this register.
Table 45. Mode Configuration Registers (ME_<mode>_MC) Field Descriptions
Field
Description
PDO
I/O output power-down control — This bit controls the output power-down of I/Os.
0 No automatic safe gating of I/Os used and pads power sequence driver is enabled
1 In SAFE/TEST modes, outputs of pads are forced to high impedance state and pads power
sequence driver is disabled. The inputs are level unchanged. In STOP0 mode, only the pad power
sequence driver is disabled, but the state of the output remains functional.
MVRON
Main voltage regulator control — This bit specifies whether main voltage regulator is switched off or
not while entering this mode.
1 Main voltage regulator is switched on
DFLAON
Data flash power-down control — This bit specifies the operating mode of the data flash after entering
this mode.
00 reserved
01 reserved
10 reserved
11 Data flash is in normal mode
Note: Data flash should be kept in Normal mode in Stop and Halt mode.
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
6-119
Mode Entry Module (MC_ME)
Table 45. Mode Configuration Registers (ME_<mode>_MC) Field Descriptions (continued)
Field
CFLAON
Description
Code flash power-down control — This bit specifies the operating mode of the code flash after
entering this mode.
00 reserved
01 reserved
10 reserved
11 Code flash is in normal mode
Note: Code flash should be kept in Normal mode in Stop and Halt mode.
FMPLL_0ON System PLL control
0 system PLL is switched off
1 system PLL is switched on
XOSCON
IRCON
SYSCLK
external oscillator control
0 external oscillator is switched off
1 external oscillator is switched on
internal RC oscillator control
0 internal RC oscillator is switched off
1 internal RC oscillator is switched on
System clock switch control — These bits specify the system clock to be used by the system.
0000 IRC
0001 reserved
0010 XOSC
0011 reserved
0100 FMPLL_0 PCS
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 system clock is disabled in TEST mode, reserved in all other modes
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6-120
Freescale Semiconductor
Mode Entry Module (MC_ME)
Peripheral Status Register 0 (ME_PS0)
Address 0xC3FD_C060
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
S_DSPI0
7
S_DSPI1
6
S_SAI0
5
S_DSPI2
4
S_DMA_CH_MUX
3
S_SAI1
2
S_SAI2
1
S_Video
0
Access: User read, Supervisor read, Test read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
S_FlexCAN0
6.3.2.15
W
Reset
R
W
Reset
Figure 49. Peripheral Status Register 0 (ME_PS0)
This register provides the status of the peripherals. Please refer to Table 46 for details.
6.3.2.16
Peripheral Status Register 1 (ME_PS1)
Address 0xC3FD_C064
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
S_CRC
S_LIN_FLEX0
5
S_LIN_FLEX1
4
S_I2C_DMA0
3
S_PTP
2
S_I2C_DMA1
1
S_CE_RTC
0
Access: User read, Supervisor read, Test read
R
S_ADC0
Reset
S_eTimer0
W
W
Reset
0
0
Figure 50. Peripheral Status Register 1 (ME_PS1)
This register provides the status of the peripherals. Please refer to Table 46 for details.
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
6-121
Mode Entry Module (MC_ME)
6.3.2.17
Peripheral Status Register 2 (ME_PS2)
Address 0xC3FD_C068
1
2
0
0
0
16
17
0
0
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S_PIT_RTI
0
Access: User read, Supervisor read, Test read
R
W
Reset
R
W
Reset
Figure 51. Peripheral Status Register 2 (ME_PS2)
This register provides the status of the peripherals. Please refer to Table 46 for details.
6.3.2.18
Peripheral Status Register 3 (ME_PS3)
Address 0xC3FD_C06C
Access: User read, Supervisor read, Test read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
Reset
S_CMU0
W
R
W
Reset
0
Figure 52. Peripheral Status Register 3 (ME_PS3)
This register provides the status of the peripherals. Please refer to Table 46 for details.
Table 46. Peripheral Status Registers (ME_PSn) Field Descriptions
Field
Description
S_<periph>
Peripheral status — These bits specify the current status of each peripheral which is controlled by the
MC_ME.
0 Peripheral is frozen
1 Peripheral is active
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6-122
Freescale Semiconductor
Mode Entry Module (MC_ME)
6.3.2.19
Run Peripheral Configuration Registers (ME_RUN_PC0…7)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
RUN2
RUN1
RUN0
DRUN
SAFE
TEST
RESET
R
Access: User read, Supervisor read/write, Test read/write
RUN3
Address 0xC3FD_C080 - 0xC3FD_C09C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 53. Run Peripheral Configuration Registers (ME_RUN_PC0…7)
These registers configure eight different types of peripheral behavior during run modes.
Table 47. Run Peripheral Configuration Registers (ME_RUN_PC0…7) Field Descriptions
Field
Description
RUN3
Peripheral control during RUN3
0 Peripheral is frozen with clock gated
1 Peripheral is active
RUN2
Peripheral control during RUN2
0 Peripheral is frozen with clock gated
1 Peripheral is active
RUN1
Peripheral control during RUN1
0 Peripheral is frozen with clock gated
1 Peripheral is active
RUN0
Peripheral control during RUN0
0 Peripheral is frozen with clock gated
1 Peripheral is active
DRUN
Peripheral control during DRUN
0 Peripheral is frozen with clock gated
1 Peripheral is active
SAFE
Peripheral control during SAFE
0 Peripheral is frozen with clock gated
1 Peripheral is active
TEST
Peripheral control during TEST
0 Peripheral is frozen with clock gated
1 Peripheral is active
RESET
Peripheral control during RESET
0 Peripheral is frozen with clock gated
1 Peripheral is active
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
6-123
Mode Entry Module (MC_ME)
6.3.2.20
Low-Power Peripheral Configuration Registers (ME_LP_PC0…7)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
HALT0
R
Access: User read, Supervisor read/write, Test read/write
STOP0
Address 0xC3FD_C0A0 - 0xC3FD_C0BC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 54. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7)
These registers configure eight different types of peripheral behavior during non-run modes.
Table 48. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) Field Descriptions
Field
Description
STOP0
Peripheral control during STOP0
0 Peripheral is frozen with clock gated
1 Peripheral is active
HALT0
Peripheral control during HALT0
0 Peripheral is frozen with clock gated
1 Peripheral is active
6.3.2.21
Peripheral Control Registers (ME_PCTLn)
Address 0xC3FD_C0C0 - 0xC3FD_C14F
0
R
0
W
Reset
0
1
2
DBG_F
0
Access: User read, Supervisor read/write, Test read/write
3
4
5
LP_CFG
0
0
6
7
RUN_CFG
0
0
0
0
Figure 55. Peripheral Control Registers (ME_PCTLn)
These registers select the configurations during run and non-run modes for each peripheral. Please refer to
Table 36 for information on which ME_PCTLn locations are actually occupied. The unoccupied locations
contain a read-only byte value of 0x00.
MPC5604E Reference Manual, Rev. 5
6-124
Freescale Semiconductor
Mode Entry Module (MC_ME)
Table 49. Peripheral Control Registers (ME_PCTLn) Field Descriptions
Field
Description
DBG_F
Peripheral control in debug mode — This bit controls the state of the peripheral in debug mode
0 Peripheral state depends on RUN_CFG/LP_CFG bits and the chip mode
1 Peripheral is frozen if not already frozen in chip modes.
NOTE
This feature is useful to freeze the peripheral state
while entering debug. For example, this may be used
to prevent a reference timer from running while
making a debug accesses.
LP_CFG
Peripheral configuration select for non-run modes — These bits associate a configuration as defined
in the ME_LP_PC0…7 registers to the peripheral.
000 Selects ME_LP_PC0 configuration
001 Selects ME_LP_PC1 configuration
010 Selects ME_LP_PC2 configuration
011 Selects ME_LP_PC3 configuration
100 Selects ME_LP_PC4 configuration
101 Selects ME_LP_PC5 configuration
110 Selects ME_LP_PC6 configuration
111 Selects ME_LP_PC7 configuration
RUN_CFG
Peripheral configuration select for run modes — These bits associate a configuration as defined in
the ME_RUN_PC0…7 registers to the peripheral.
000 Selects ME_RUN_PC0 configuration
001 Selects ME_RUN_PC1 configuration
010 Selects ME_RUN_PC2 configuration
011 Selects ME_RUN_PC3 configuration
100 Selects ME_RUN_PC4 configuration
101 Selects ME_RUN_PC5 configuration
110 Selects ME_RUN_PC6 configuration
111 Selects ME_RUN_PC7 configuration
NOTE
After modifying any of the ME_RUN_PC0…7, ME_LP_PC0…7, and
ME_PCTLn registers, software must request a mode change and wait for
the mode change to be completed before entering debug mode in order to
have consistent behavior between the peripheral clock control process and
the clock status reporting in the ME_PSn registers.
6.4
6.4.1
Functional Description
Mode Transition Request
The transition from one mode to another mode is normally handled by software by accessing the mode
control register ME_MCTL. But in case of special events, the mode transition can be automatically
managed by hardware. In order to switch from one mode to another, the application should access the
ME_MCTL register twice by writing
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
6-125
Mode Entry Module (MC_ME)
•
•
the first time with the value of the key (0x5AF0) into the KEY bit field and the required target mode
into the TARGET_MODE bit field,
and the second time with the inverted value of the key (0xA50F) into the KEY bit field and the
required target mode into the TARGET_MODE bit field.
Once a valid mode transition request is detected, the target mode configuration information is loaded from
the corresponding ME_<mode>_MC register.The mode transition request may require a number of
cycles depending on the programmed configuration, and software should check the
S_CURRENT_MODE bit field and the S_MTRANS bit of the global status register ME_GS to verify
when the mode has been correctly entered and the transition process has completed. For a description of
valid mode requests, please refer to Section 6.4.5, “Mode Transition Interrupts”.
Any modification of the mode configuration register of the currently selected mode will not be taken into
account immediately but on the next request to enter this mode. This means that transition requests such
as RUN0…3 → RUN0…3, DRUN → DRUN, SAFE → SAFE, and TEST → TEST are considered
valid mode transition requests. As soon as the mode request is accepted as valid, the S_MTRANS bit is
set till the status in the ME_GS register matches the configuration programmed in the respective
ME_<mode>_MC register.
NOTE
It is recommended that software poll the S_MTRANS bit in the ME_GS
register after requesting a transition to HALT0 or STOP0 modes.
MPC5604E Reference Manual, Rev. 5
6-126
Freescale Semiconductor
Mode Entry Module (MC_ME)
SYSTEM MODES
recoverable
hardware failure
USER MODES
RUN0
software
request
SAFE
HALT0
RUN1
RESET
DRUN
RUN2
STOP0
RUN3
non-recoverable
failure
TEST
Figure 56. MC_ME Mode Diagram
6.4.2
6.4.2.1
Modes Details
RESET MODE
The chip enters this mode on the following events:
• from SAFE, DRUN, RUN0…3, or TEST mode when the TARGET_MODE bit field of the
ME_MCTL register is written with “0000” for a ‘functional’ reset
• from any mode due to a system reset by the MC_RGM because of some non-recoverable hardware
failure in the system (see the MC_RGM chapter for details)
Transition to this mode is instantaneous, and the system remains in this mode until the reset sequence is
finished. The mode configuration information for this mode is provided by the ME_RESET_MC register.
This mode has a pre-defined configuration, and the IRC is selected as the system clock.
6.4.2.2
DRUN Mode
The chip enters this mode on the following events:
• automatically from RESET mode after completion of the reset sequence
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Freescale Semiconductor
6-127
Mode Entry Module (MC_ME)
•
from RUN0…3, SAFE, or TEST mode when the TARGET_MODE bit field of the ME_MCTL
register is written with “0011”
As soon as any of the above events has occurred, a DRUN mode transition request is generated. The mode
configuration information for this mode is provided by the ME_DRUN_MC register. In this mode, the
flashes, all clock sources, and the system clock configuration can be controlled by software as required.
After system reset, the software execution starts with the default configuration selecting the IRC as the
system clock.
This mode is intended to be used by software
• to initialize all registers as per the system needs
NOTE
Software must ensure that the code executes from RAM before changing to
this mode if the flashes are configured to be in the low-power or
power-down state in this mode.
6.4.2.3
SAFE Mode
The chip enters this mode on the following events:
• from DRUN, RUN0…3 when the TARGET_MODE bit field of the ME_MCTL register is
written with “0010”
• from any mode except RESET due to a SAFE mode request generated by the MC_RGM because
of some potentially recoverable hardware failure in the system (see the MC_RGM chapter for
details)
NOTE
If a hardware SAFE mode request occurs during RESET, depending on the
timing of the SAFE mode request, SAFE mode may be entered
immediately after the normal completion of the reset sequence or several
system clock cycles after DRUN entry. The SAFE mode request does not
have any influence on the execution of the reset sequence itself.
As soon as any of the above events has occurred, a SAFE mode transition request is generated. The mode
configuration information for this mode is provided by the ME_SAFE_MC register. This mode has a
pre-defined configuration, and the IRC is selected as the system clock.
If the SAFE mode is requested by software while some other mode transition process is ongoing, the new
target mode becomes the SAFE mode regardless of other pending requests or new requests during the
mode transition. Any new mode request made during a transition to the SAFE mode will cause an invalid
mode interrupt.
NOTE
If software requests to change to the SAFE mode and then requests to
change back to the parent mode before the mode transition is completed, the
chip’s final mode after mode transition will be the SAFE mode.
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Freescale Semiconductor
Mode Entry Module (MC_ME)
As long as a SAFE event is active, the system remains in the SAFE mode, and any software mode request
during this time is ignored and lost.
This mode is intended to be used by software
• to assess the severity of the cause of failure and then to either
— re-initialize the chip via the DRUN mode, or
— completely reset the chip via the RESET mode.
If the outputs of the system I/Os need to be forced to a high impedance state upon entering this mode, the
PDO bit of the ME_SAFE_MC register should be set. The input levels remain unchanged.
6.4.2.4
Test Mode
The chip enters this mode on the following event:
• from the DRUN mode when the TARGET_MODE bit field of the ME_MCTL register is written
with “0001”
As soon as the above event has occurred, a TEST mode transition request is generated. The mode
configuration information for this mode is provided by the ME_TEST_MC register. Except for the main
voltage regulator, all resources of the system are configurable in this mode. The system clock to the whole
system can be stopped by programming the SYSCLK bit field to “1111”, and in this case, the only way to
exit this mode is via a chip reset.
This mode is intended to be used by software
• to execute software test routines
NOTE
Software must ensure that the code executes from RAM before changing to
this mode if the flashes are configured to be in the low-power or
power-down state in this mode.
6.4.2.5
RUN0..3 Modes
The chip enters one of these modes on the following events:
• from the DRUN, SAFE, or another RUN0…3 mode when the TARGET_MODE bit field of the
ME_MCTL register is written with “0100…0111”
• from the HALT0 mode due to an off-platform interrupt event
• from the STOP0 mode due to an interrupt or wakeup event
As soon as any of the above events has occurred, a RUN0…3 mode transition request is generated. The
mode configuration information for these modes is provided by the ME_RUN0…3_MC registers. In these
modes, the flashes, all clock sources, and the system clock configuration can be controlled by software as
required.
These modes are intended to be used by software
• to execute application routines
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NOTE
Software must ensure that the code executes from RAM before changing to
this mode if the flashes are configured to be in the low-power or
power-down state in this mode.
6.4.2.6
HALT0 Mode
The chip enters this mode on the following event:
• from one of the RUN0…3 modes when the TARGET_MODE bit field of the ME_MCTL register
is written with “1000”.
As soon as the above event has occurred, a HALT0 mode transition request is generated. The mode
configuration information for this mode is provided by ME_HALT0_MC register. This mode is quite
configurable, and the ME_HALT0_MC register should be programmed according to the system needs.
The flashes can be put in low-power or power-down mode as needed. If there is a HALT0 mode request
while an interrupt request is active, the transition to HALT0 is aborted with the resultant mode being the
current mode, SAFE (on SAFE mode request), or DRUN (on reset), and an invalid mode interrupt is not
generated.
This mode is intended as a first-level low-power mode with
• the core clock frozen
• only a few peripherals running
and to be used by software
• to wait until it is required to do something and then to react quickly (i.e., within a few system clock
cycles of an interrupt event)
NOTE
It is good practice for software to ensure that the S_MTRANS bit in the
ME_GS register has been cleared on HALT0 mode exit to ensure that the
previous RUN0…3 mode configuratoin has been fully restored before
executing critical code.
6.4.2.7
STOP0 Mode
The chip enters this mode on the following event:
• from one of the RUN0…3 modes when the TARGET_MODE bit field of the ME_MCTL register
is written with “1010”.
As soon as the above event has occurred, a STOP0 mode transition request is generated. The mode
configuration information for this mode is provided by the ME_STOP0_MC register. This mode is fully
configurable, and the ME_STOP0_MC register should be programmed according to the system needs.
The flashes can be put in power-down mode as needed. If there is a STOP0 mode request while any
interrupt or wakeup event is active, the transition to STOP0 is aborted with the resultant mode being the
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current mode, SAFE (on SAFE mode request), or DRUN (on reset), and an invalid mode interrupt is not
generated.
This can be used as an advanced low-power mode with the core clock frozen and almost all peripherals
stopped.
This mode is intended as an advanced low-power mode with
• the core clock frozen
• almost all peripherals stopped
and to be used by software
• to wait until it is required to do something with no need to react quickly (e.g., allow for system
clock source to be re-started)
This mode can be used to stop all clock sources and thus preserve the chip status. When exiting the STOP0
mode, the internal RC oscillator clock is selected as the system clock until the target clock is available.
NOTE
It is good practice for software to ensure that the S_MTRANS bit in the
ME_GS register has been cleared on STOP0 mode exit to ensure that the
previous RUN0…3 mode configuratoin has been fully restored before
executing critical code.
6.4.3
Mode Transition Process
The process of mode transition follows the following steps in a pre-defined manner depending on the
current chip mode and the requested target mode. In many cases of mode transition, not all steps need to
be executed based on the mode control information, and some steps may not be applicable according to
the mode definition itself.
6.4.3.1
Target Mode Request
The target mode is requested by accessing the ME_MCTL register with the required keys. This mode
transition request by software must be a valid request satisfying a set of pre-defined rules to initiate the
process. If the request fails to satisfy these rules, it is ignored, and the TARGET_MODE bit field is not
updated. An optional interrupt can be generated for invalid mode requests. Refer to Section 6.4.5, “Mode
Transition Interrupts” for details.
In the case of mode transitions occurring because of hardware events such as a reset, a SAFE mode
request, or interrupt requests and wakeup events to exit from low-power modes, the TARGET_MODE bit
field of the ME_MCTL register is automatically updated with the appropriate target mode. The mode
change process start is indicated by the setting of the mode transition status bit S_MTRANS of the
ME_GS register.
A RESET mode requested via the ME_MCTL register is passed to the MC_RGM, which generates a
global system reset and initiates the reset sequence. The RESET mode request has the highest priority,
and the MC_ME is kept in the RESET mode during the entire reset sequence.
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The SAFE mode request has the next highest priority after reset. It can be generated either by software via
the ME_MCTL register from all software running modes including DRUN, RUN0…3, and TEST or by
the MC_RGM after the detection of system hardware failures, which may occur in any mode.
6.4.3.2
Target Mode Configuration Loading
On completion of the Target Mode Request step, the target mode configuration from the
ME_<target mode>_MC register is loaded to start the resources (voltage sources, clock sources,
flashes, pads, etc.) control process.
An overview of resource control possibilities for each mode is shown in . A ‘√’ indicates that a given
resource is configurable for a given mode.
Table 50. MC_ME Resource Control Overview
Resourc
e
Mode
RESET
TEST
SAFE
DRUN
RUN0…3
√
IRC
on
on
on
√
XOSC
off
off
off
√
FMPLL_0
off
off
off
√
CFLASH
normal
normal
normal
√
DFLASH
normal
normal
normal
6.4.3.3
on
on
STOP0
√
√
on
on
on
on
√
√
√
√
off
on
off
off
√
√
√
off
on
off
off
√
√
√
√
normal
normal
normal
normal
√
√
√
√
normal
normal
normal
normal
√
√
on
on
MVREG
on
HALT0
on
on
Peripheral Clocks Disable
On completion of the Target Mode Request step, the MC_ME requests each peripheral to enter its stop
mode when:
• the peripheral is configured to be disabled via the target mode, the peripheral configuration
registers ME_RUN_PC0…7 and ME_LP_PC0…7, and the peripheral control registers
ME_PCTLn
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NOTE
The MC_ME automatically requests peripherals to enter their stop modes if
the power domains in which they are residing are to be turned off due to a
mode change. However, it is good practice for software to ensure that those
peripherals that are to be powered down are configured in the MC_ME to
be frozen.
Each peripheral acknowledges its stop mode request after closing its internal activity. The MC_ME then
disables the corresponding clock(s) to this peripheral.
In the case of a SAFE mode transition request, the MC_ME does not wait for the peripherals to
acknowledge the stop requests. The SAFE mode clock gating configuration is applied immediately
regardless of the status of the peripherals’ stop acknowledges.
Please refer to Section 6.4.6, “Peripheral Clock Gating” for more details.
Each peripheral that may block or disrupt a communication bus to which it is connected ensures that these
outputs are forced to a safe or recessive state when the chip enters the SAFE mode.
6.4.3.4
Processor Low-Power Mode Entry
If, on completion of the Peripheral Clocks Disable step, the mode transition is to the HALT0 mode, the
MC_ME requests the processor to enter its halted state. The processor acknowledges its halt state request
after completing all outstanding bus transactions.
If, on completion of the Peripheral Clocks Disable step, the mode transition is to the STOP0 mode, the
MC_ME requests the processor to enter its stopped state. The processor acknowledges its stop state request
after completing all outstanding bus transactions.
6.4.3.5
Processor and System Memory Clock Disable
If, on completion of the Processor Low-Power Mode Entry step, the mode transition is to the HALT0 or
STOP0 mode and the processor is in its appropriate halted or stopped state, the MC_ME disables the
processor and system memory clocks to achieve further power saving.
The clocks to the processor and system memory are unaffected while transitioning between software
running modes such as DRUN, RUN0…3, and SAFE.
WARNING
Clocks to the whole chip including the processor and system memory can
be disabled in TEST mode.
6.4.3.6
Clock Sources Switch-On
On completion of the Processor Low-Power Mode Entry step, the MC_ME switches on all clock sources
based on the <clock source>ON bits of the ME_<current mode>_MC and
ME_<target mode>_MC registers. The following clock sources are switched on at this step:
• the internal RC oscillator
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•
•
the external oscillator
the system PLL
The clock sources that are required by the target mode are switched on. The duration required for the
output clocks to be stable depends on the type of source, and all further steps of mode transition depending
on one or more of these clocks waits for the stable status of the respective clocks. The availability status
of these clocks is updated in the S_<clock source> bits of ME_GS register.
The clock sources which need to be switched off are unaffected during this process in order to not disturb
the system clock which might require one of these clocks before switching to a different target clock.
6.4.3.7
Flash Modules Switch-On
On completion of the step, if one or more of the flashes needs to be switched to normal mode from its
low-power or power-down mode based on the CFLAON and DFLAON bit fields of the
ME_<current mode>_MC and ME_<target mode>_MC registers, the MC_ME requests the flash to
exit from its low-power/power-down mode. When the flashes are available for access, the S_CFLA and
S_DFLA bit fields of the ME_GS register are updated to “11” by hardware.
WARNING
It is illegal to switch the CFLASH from low-power mode to power-down
mode and from power-down mode to low-power mode. The MC_ME,
however, does not prevent this nor does it flag it.
6.4.3.8
Pad Outputs-On
On completion of the step, if the PDO bit of the ME_<target mode>_MC register is cleared, then
• all pad outputs are enabled to return to their previous state
• the I/O pads power sequence driver is switched on
6.4.3.9
Peripheral Clocks Enable
Based on the current and target chip modes, the peripheral configuration registers ME_RUN_PC0…7,
ME_LP_PC0…7, and the peripheral control registers ME_PCTLn, the MC_ME enables the clocks for
selected modules as required. This step is executed only after the process is completed.
6.4.3.10
Processor and Memory Clock Enable
If the mode transition is from any of the low-power modes HALT0 or STOP0 to RUN0…3, the clocks
to the processor and system memory are enabled. The process of enabling these clocks is executed only
after the Flash Modules Switch-On process is completed.
6.4.3.11
Processor Low-Power Mode Exit
If the mode transition is from any of the low-power modes HALT0 orSTOP0 to RUN0…3, the MC_ME
requests the processor to exit from its halted or stopped state. This step is executed only after the Processor
and Memory Clock Enable process is completed.
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6.4.3.12
System Clock Switching
Based on the SYSCLK bit field of the ME_<current mode>_MC and ME_<target mode>_MC
registers, if the target and current system clock configurations differ, the following method is implemented
for clock switching.
• The target clock configuration for the IRC takes effect only after the S_IRC bit of the ME_GS
register is set by hardware (i.e., the internal RC oscillator has stabilized).
• The target clock configuration for the XOSC takes effect only after the S_XOSC bit of the
ME_GS register is set by hardware (i.e., the external oscillator has stabilized).
• The target clock configuration for the FMPLL_0 PCS takes effect only after the S_FMPLL_0 bit
of the ME_GS register is set by hardware (i.e., the system PLL has stabilized).
• If the clock is to be disabled, the SYSCLK bit field should be programmed with “1111”. This is
possible only in theTEST mode.
The current system clock configuration can be observed by reading the S_SYSCLK bit field of the
ME_GS register, which is updated after every system clock switching. Until the target clock is available,
the system uses the previous clock configuration.
System clock switching starts only after
• the Clock Sources Switch-On process has completed if the target system clock source is one of the
following:
— the internal RC oscillator
— the system PLL
• the Peripheral Clocks Disable process has completed in order not to change the system clock
frequency before peripherals close their internal activities
An overview of system clock source selection possibilities for each mode is shown in Table 51. A ‘√’
indicates that a given clock source is selectable for a given mode.
Table 51. MC_ME System Clock Selection Overview
System
Clock
Source
IRC
Mode
RESET
TEST
SAFE
DRUN
RUN0…3
HALT0
STOP0
√
(default)
√
(default)
√
(default)
√
(default)
√
(default)
√
(default)
√
(default)
√
XOSC
√
√
√
√
FMPLL_0
PCS
√
√
√
√
system
clock is
disabled
√1
1
disabling the system clock during TEST mode will require a reset in order to exit TEST mode
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6.4.3.13
Pad Switch-Off
If the PDO bit of the ME_<target mode>_MC register is ‘1’ then
• the outputs of the pads are forced to the high impedance state if the target mode is SAFE or TEST
This step is executed only after the Peripheral Clocks Disable process has completed.
6.4.3.14
Clock Sources (with no Dependencies) Switch-Off
Based on the chip mode and the <clock source>ON bits of the ME_<mode>_MC registers, if a given
clock source is to be switched off and no other clock source needs it to be on, the MC_ME requests the
clock source to power down and updates its availability status bit S_<clock source> of the ME_GS
register to ‘0’. The following clock sources switched off at this step:
• the system PLL
This step is executed only after the System Clock Switching process has completed.
6.4.3.15
Clock Sources (with Dependencies) Switch-Off
Based on the chip mode and the <clock source>ON bits of the ME_<mode>_MC registers, if a given
clock source is to be switched off and all clock sources which need this clock source to be on have been
switched off, the MC_ME requests the clock source to power down and updates its availability status bit
S_<clock source> of the ME_GS register to ‘0’. The following clock sources switched off at this step:
• the external oscillator
This step is executed only after
• the System Clock Switching process has completed in order not to lose the current system clock
during mode transition
• the Clock Sources (with no Dependencies) Switch-Off process has completed in order to, for
example, prevent unwanted lock transitions
6.4.3.16
Flash Switch-Off
Based on the CFLAON and DFLAON bit fields of the ME_<current mode>_MC and
ME_<target mode>_MC registers, if any of the flashes is to be put in its low-power or power-down
mode, the MC_ME requests the flash to enter the corresponding power mode and waits for the flash to
acknowledge. The exact power mode status of the flashes is updated in the S_CFLA and S_DFLA bit
fields of the ME_GS register. This step is executed only when the Processor and System Memory Clock
Disable process has completed.
6.4.3.17
Current Mode Update
The current mode status bit field S_CURRENT_MODE of the ME_GS register is updated with the target
mode bit field TARGET_MODE of the ME_MCTL register when :
• all the updated status bits in the ME_GS register match the configuration specified in the
ME_<target mode>_MC register
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•
•
•
power sequences are done
clock disable/enable process is finished
processor low-power mode (halt/stop) entry and exit processes are finished
NOTE
SAFE mode entry does not wait for the clock disable/enable process to
finish. It only waits for the ME_GS.S_RC bit to be set. This is to ensure
that the SAFE mode is entered as quickly as possible.
Software can monitor the mode transition status by reading the S_MTRANS bit of the ME_GS register.
The mode transition latency can differ from one mode to another depending on the resources’ availability
before the new mode request and the target mode’s requirements.
If a mode transition is taking longer to complete than is expected, the ME_DMTS register can indicate
which process is still in progress.
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Mode Entry Module (MC_ME)
Start
Write ME_MCTL register
SAFE mode request
interrupt/wakeup event
ANALOG ON
Clock Sources
Switch-On
Pad
Outputs On
FLASH
Switch-On
Peripheral Clocks
Disable
Processor &
Memory
Clock Enable
Processor
Low-Power
Entry
Processor &
Memory
Clock Disable
Peripheral Clocks
Enable
System Clock
Switching
Processor
Low-Power
Exit
DIGITAL CONTROL
S_MTRANS = ‘1’
Target Mode Request
FLASH
Switch-Off
PAD
Outputs Off
Current Mode Update
Clock Sources With
Dependencies Switch-Off
ANALOG OFF
Clock Sources Without
Dependencies Switch-Off
S_MTRANS = ‘0’
End
Figure 57. MC_ME Transition Diagram
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6.4.4
Protection of Mode Configuration Registers
While programming the mode configuration registers ME_<mode>_MC, the following rules must be
respected. Otherwise, the write operation is ignored and an invalid mode configuration interrupt may be
generated.
• If the IRC is selected as the system clock, IRC must be on.
• If the XOSC clock is selected as the system clock, OSC must be on.
• If the FMPLL_0 PCS clock is selected as the system clock, PLL must be on.
• If FMPLL_0 is on, XOSC must also be on.
NOTE
Software must ensure that clock sources with dependencies other than those
mentioned above are switched on as needed. There is no automatic
protection mechanism to check this in the MC_ME.
•
•
•
•
•
•
Configuration “00” for the CFLAON bit field is reserved.
Configuration “00” for the DFLAON bit field is reserved.
Configuration “10” for the DFLAON bit field is reserved.
Configuration "11" for the DFLAON bit field with "01" or "10" for the CFLAON bit field is
reserved.
System clock configurations marked as ‘reserved’ may not be selected.
Configuration “1111” for the SYSCLK bit field is allowed only for theTEST mode, and only in
this case may all system clock sources be turned off.
WARNING
If the system clock is stopped during TEST mode, the chip can exit only via
a system reset.
6.4.5
Mode Transition Interrupts
The MC_ME provides interrupts for incorrectly configuring a mode, requesting an invalid mode
transition, indicating a SAFE mode transition not due to a software request, and indicating when a mode
transition has completed.
6.4.5.1
Invalid Mode Configuration Interrupt
Whenever a write operation is attempted to the ME_<mode>_MC registers violating the protection rules
mentioned in the Section 6.4.4, “Protection of Mode Configuration Registers”, the interrupt pending bit
I_ICONF of the ME_IS register is set and an interrupt request is generated if the mask bit M_ICONF of
the ME_IM register is ‘1’.
In addition, during a mode transition, if a clock source has been configured in the
ME_<target mode>_MC register to be off and a peripheral requiring this clock source to be on has been
enabled via the ME_RUN_PC0…7/ME_LP_PC0…7 and ME_PCTLn registers, the interrupt pending
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bit I_ICONF_CU of the ME_IS register is set and an iterrupt request is generated if the mask bit
M_ICONF_CU of the ME_IM register is ‘1’.
6.4.5.2
Invalid Mode Transition Interrupt
The mode transition request is considered invalid under the following conditions:
• If the system is in the SAFE mode and the SAFE mode request from MC_RGM is active, and if
the target mode requested is other than RESET or SAFE, then this new mode request is considered
to be invalid, and the S_SEA bit of the ME_IMTS register is set.
• If the TARGET_MODE bit field of the ME_MCTL register is written with a value different from
the specified mode values (i.e., a non-existing mode), an invalid mode transition event is generated.
When such a non existing mode is requested, the S_NMA bit of the ME_IMTS register is set. This
condition is detected regardless of whether the proper key mechanism is followed while writing
the ME_MCTL register.
• If some of the chip modes are disabled as programmed in the ME_ME register, their respective
configurations are considered reserved, and any access to the ME_MCTL register with those
values results in an invalid mode transition request. When such a disabled mode is requested, the
S_DMA bit of the ME_IMTS register is set. This condition is detected regardless of whether the
proper key mechanism is followed while writing the ME_MCTL register.
• If the target mode is not a valid mode with respect to the current mode, the mode request illegal
status bit S_MRI of the ME_IMTS register is set. This condition is detected only when the proper
key mechanism is followed while writing the ME_MCTL register. Otherwise, the write operation
is ignored.
• If further new mode requests occur while a mode transition is in progress (the S_MTRANS bit of
the ME_GS register is ‘1’), the mode transition illegal status bit S_MTI of the ME_IMTS register
is set. This condition is detected only when the proper key mechanism is followed while writing
the ME_MCTL register. Otherwise, the write operation is ignored.
NOTE
As the causes of invalid mode transitions may overlap at the same time, the
priority implemented for invalid mode transition status bits of the
ME_IMTS register in the order from highest to lowest is S_SEA, S_NMA,
S_DMA, S_MRI, and S_MTI.
As an exception, the mode transition request is not considered as invalid under the following conditions:
• A new request is allowed to enter the RESET or SAFE mode irrespective of the mode transition
status.
• As the exit of HALT0 and STOP0 modes depends on the interrupts of the system which can occur
at any instant, these requests to return to RUN0…3 modes are always valid.
• In order to avoid any unwanted lockup of the chip modes, software can abort a mode transition by
requesting the parent mode if, for example, the mode transition has not completed after a software
determined ‘reasonable’ amount of time for whatever reason. The parent mode is the chip mode
before a valid mode request was made.
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•
Self-transition requests (e.g., RUN0 → RUN0) are not considered as invalid even when the mode
transition process is active (i.e., S_MTRANS is ‘1’). During the low-power mode exit process, if
the system is not able to enter the respective RUN0…3 mode properly (i.e., all status bits of the
ME_GS register match with configuration bits in the ME_<mode>_MC register), then software
can only request the SAFE or RESET mode. It is not possible to request any other mode or to go
back to the low-power mode again.
Whenever an invalid mode request is detected, the interrupt pending bit I_IMODE of the ME_IS register
is set, and an interrupt request is generated if the mask bit M_IMODE of the ME_IM register is ‘1’.
6.4.5.3
SAFE Mode Transition Interrupt
Whenever the system enters the SAFE mode as a result of a SAFE mode request from the MC_RGM due
to a hardware failure, the interrupt pending bit I_SAFE of the ME_IS register is set, and an interrupt is
generated if the mask bit M_SAFE of ME_IM register is ‘1’ .
The SAFE mode interrupt pending bit can be cleared only when the SAFE mode request is deasserted by
the MC_RGM (see the MC_RGM chapter for details on how to clear a SAFE mode request). If the system
is already in SAFE mode, any new SAFE mode request by the MC_RGM also sets the interrupt pending
bit I_SAFE. However, the SAFE mode interrupt pending bit is not set when the SAFE mode is entered
by a software request (i.e., programming of ME_MCTL register).
6.4.5.4
Mode Transition Complete interrupt
Whenever the system fully completes a mode transition (i.e., the S_MTRANS bit of ME_GS register
transits from ‘1’ to ‘0’), the interrupt pending bit I_MTC of the ME_IS register is set, and an interrupt
request is generated if the mask bit M_MTC of the ME_IM register is ‘1’. The interrupt bit I_MTC is not
set when entering low-power modes HALT0 and STOP0 in order to avoid the same event requesting the
immediate exit of these low-power modes.
6.4.6
Peripheral Clock Gating
During all chip modes, each peripheral can be associated with a particular clock gating policy determined
by two groups of peripheral configuration registers.
The run peripheral configuration registers ME_RUN_PC0…7 are chosen only during the software
running modes DRUN, TEST, SAFE, and RUN0…3. All configurations are programmable by software
according to the needs of the application. Each configuration register contains a mode bit which
determines whether or not a peripheral clock is to be gated. Run configuration selection for each peripheral
is done by the RUN_CFG bit field of the ME_PCTLn registers.
The low-power peripheral configuration registers ME_LP_PC0…7 are chosen only during the
low-power modes HALT0 and STOP0. All configurations are programmable by software according to
the needs of the application. Each configuration register contains a mode bit which determines whether or
not a peripheral clock is to be gated. Low-power configuration selection for each peripheral is done by the
LP_CFG bit field of the ME_PCTLn registers.
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Any modifications to the ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTLn registers do not
affect the clock gating behavior until a new mode transition request is generated.
Whenever the processor enters a debug session during any mode, the following occurs for each peripheral:
• The clock is gated if the DBG_F bit of the associated ME_PCTLn register is set. Otherwise, the
peripheral clock gating status depends on the RUN_CFG and LP_CFG bits. Any further
modifications of the ME_RUN_PC0…7, ME_LP_PC0…7, and ME_PCTLn registers during a
debug session will take affect immediately without requiring any new mode request.
6.4.7
Application Example
Figure 58 shows an example application flow for requesting a mode change and then waiting until the
mode transition has completed.
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Mode Entry Module (MC_ME)
START of mode change
N
config
for target mode
okay?
write ME_<target mode>_MC,
ME_RUN_PC0…7, ME_LP_PC0…7,
and ME_PCTLn registers
Y
write ME_MCTL with target mode
and key
write ME_MCTL with target mode
and inverted key
start timer
N
S_MTRANS
cleared?
Y
timer
expired?
N
stop timer
Y
mode change DONE
write ME_MCTL with current or
SAFE mode and key
write ME_MCTL with current or
SAFE mode and inverted key
Figure 58. MC_ME Application Example Flow Diagram
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Chapter 7
Reset Generation Module (MC_RGM)
7.1
7.1.1
Introduction
Overview
The reset generation module (MC_RGM) centralizes the different reset sources and manages the reset
sequence of the chip. It provides a register interface and the reset sequencer. Various registers are available
to monitor and control the chip reset sequence. The reset sequencer is a state machine which controls the
different phases (PHASE0, PHASE1, PHASE2, PHASE3, and IDLE) of the reset sequence and
controls the reset signals generated in the system.
Figure 59 shows the MC_RGM block diagram.
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Reset Generation Module (MC_RGM)
MC_RGM
power-on
MC_ME
1.2V low-voltage detected
software watchdog timer
2.7V low-voltage detected
(VREG)
Registers
Destructive
Reset Filter
Register Interface
FAB, ABS[1:0]
peripherals
Reset
State
Machine
RESET_B
core
Functional
Reset Filter
JTAG initiated reset
core reset
software reset
checkstop reset
FMPLL_0 fail
oscillator frequency lower than
reference
FMPLL_0 clock frequency higher/lower than reference
code or data flash fatal error
MC_CGM
Boot Mode
Capture
SSCM
Figure 59. MC_RGM Block Diagram
7.1.2
Features
The MC_RGM contains the functionality for the following features:
• ‘destructive’ resets management
• ‘functional’ resets management
• signalling of reset events after each reset sequence (reset status flags)
• conversion of reset events to SAFE mode or interrupt request events
• short reset sequence configuration
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Reset Generation Module (MC_RGM)
•
•
7.1.3
bidirectional reset behavior configuration
boot mode capture on RESET_B deassertion
Reset Sources
The different reset sources are organized into two families: ‘destructive’ and ‘functional’.
• A ‘destructive’ reset source is associated with an event related to a critical - usually hardware error or dysfunction. When a ‘destructive’ reset event occurs, the full reset sequence is applied to
the chip starting from PHASE0. This resets the full chip ensuring a safe start-up state for both
digital and analog modules, and the memory content must be considered to be unknown.
‘Destructive’ resets are
– power-on reset
– 1.2V low-voltage detected
– software watchdog timer
– 2.7V low-voltage detected (VREG)
• A ‘functional’ reset source is associated with an event related to a less-critical - usually
non-hardware - error or dysfunction. When a ‘functional’ reset event occurs, a partial reset
sequence is applied to the chip starting from PHASE1. In this case, most digital modules are reset
normally, while the state of analog modules or specific digital modules (e.g., debug modules, flash
modules) is preserved. ‘Functional’ resets are
– external reset
– JTAG initiated reset
– core reset
– software reset
– checkstop reset
– FMPLL_0 fail
– oscillator frequency lower than reference
– FMPLL_0 clock frequency higher/lower than reference
– code or data flash fatal error
When a reset is triggered, the MC_RGM state machine is activated and proceeds through the different
phases (i.e., PHASEn states). Each phase is associated with a particular chip reset being provided to the
system. A phase is completed when all corresponding phase completion gates from either the system or
internal to the MC_RGM are acknowledged. The chip reset associated with the phase is then released, and
the state machine proceeds to the next phase up to entering the IDLE phase. During this entire process, the
MC_ME state machine is held in RESET mode. Only at the end of the reset sequence, when the IDLE
phase is reached, does the MC_ME enter the DRUN mode.
Alternatively, it is possible for software to configure some reset source events to be converted from a reset
to either a SAFE mode request issued to the MC_ME or to an interrupt issued to the core (see
Section 7.3.1.3, “Functional Event Reset Disable Register (RGM_FERD)” and Section 7.3.1.4,
“Functional Event Alternate Request Register (RGM_FEAR)” for ‘functional’ resets).
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Reset Generation Module (MC_RGM)
7.2
External Signal Description
The MC_RGM interfaces to the bidirectional reset pin RESET_B and the boot mode pins FAB,
ABS[1:0].
7.3
Memory Map and Register Definition
Table 52. MC_RGM Register Description
Access
Address
1
2
Name
Description
Location
Size
User
Supervisor
Test
0xC3FE RGM_FES
_4000
Functional Event Status
half-word
read
read/write1 read/write1 on page 151
0xC3FE RGM_DES
_4002
Destructive Event Status
half-word
read
read/write1 read/write1 on page 152
0xC3FE RGM_FERD
_4004
Functional Event Reset
Disable
half-word
read
read/write2 read/write2 on page 153
0xC3FE RGM_FEAR
_4010
Functional Event Alternate half-word
Request
read
read/write
read/write
on page 155
0xC3FE RGM_FESS
_4018
Functional Event Short
Sequence
half-word
read
read/write
read/write
on page 156
0xC3FE RGM_FBRE
_401C
Functional Bidirectional
Reset Enable
half-word
read
read/write
read/write
on page 157
individual bits cleared on writing ‘1’
write once: ‘0’ = enable, ‘1’ = disable.
NOTE
Any access to unused registers as well as write accesses to read-only
registers will:
•
•
not change register content
cause a transfer error
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Reset Generation Module (MC_RGM)
3
27
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
F_PLL0
F_CHKSTOP
F_SOFT
F_CORE
F_LVD12
D_JTAG
0
AR_JTAG
0
D_CORE
0
AR_CORE
D_PLL0
AR_PLL0
F_SWT
D_CMU0_OLR
w1c
AR_CMU0_OLR
w1c
D_CMU0_FHL
w1c
AR_CMU0_FHL
R
D_EXR
0xC3FE RGM_
_4004 FERD
D_FLASH
W w1c
D_SOFT
F_POR
R
w1c w1c w1c w1c w1c w1c w1c
D_CHKSTOP
w1c
W w1c
F_JTAG
2
F_LVD27_VREG
R
1
F_CMU0_OLR
0xC3FE RGM_
_4000 FES /
RGM_
DES
0
F_FLASH
Name
F_EXR
Address
F_CMU0_FHL
Table 53. MC_RGM Memory Map
0
0
D_LVD12
0
D_SWT
R
D_LVD27_VREG
W
W
0xC3FE
_4008
…
0xC3FE
_400C
reserved
0xC3FE RGM_
_4010 FEAR
R
W
R
0
0
0
0
0
0
0
0
0
0
0
W
0xC3FE
_4014
reserved
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Reset Generation Module (MC_RGM)
Table 53. MC_RGM Memory Map (continued)
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
SS_JTAG
13
0
0
0
0
0
0
0
BE_JTAG
12
SS_CORE
11
BE_CORE
10
SS_SOFT
9
BE_SOFT
8
SS_CHKSTOP
7
BE_CHKSTOP
6
SS_PLL0
5
BE_PLL0
27
SS_CMU0_OLR
3
BE_CMU0_OLR
2
SS_CMU0_FHL
R
1
BE_CMU0_FHL
0xC3FE RGM_
_4018 FESS
0
SS_FLASH
Name
SS_EXR
Address
0
0
0
0
0
0
0
W
R
0
0
0
R
BE_EXR
0xC3FE RGM_
_401C FBRE
BE_FLASH
W
W
R
0
0
0
W
0xC3FE
_4020
…
0xC3FE
_7FFC
7.3.1
reserved
Register Descriptions
Unless otherwise noted, all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes.
The bytes are ordered according to big endian. For example, the RGM_DES[8:15] register bits may be
accessed as a word at address 0xC3FE_4000, as a half-word at address 0xC3FE_4002, or as a byte at
address 0xC3FE_4003.
Some fields may be read-only, and their reset value of ‘1’ or ‘0’ and the corresponding behavior cannot be
changed.
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Reset Generation Module (MC_RGM)
Functional Event Status Register (RGM_FES)
6
F_EXR
R
W w1c
POR
0
0
0
0
0
0
0
7
8
9
10
11
12
13
14
15
F_JTAG
5
F_CORE
4
F_SOFT
3
F_CHKSTOP
2
F_PLL0
1
F_CMU0_OLR
0
Access: User read, Supervisor read/write, Test read/write
F_CMU0_FHL
Address 0xC3FE_4000
F_FLASH
7.3.1.1
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
Figure 60. Functional Event Status Register (RGM_FES)
This register contains the status of the last asserted functional reset sources. It can be accessed in read/write
on either supervisor mode or test mode. It can be accessed in read only in user mode. Register bits are
cleared on write ‘1’ if the triggering event has already been cleared at the source.
NOTE
If a ‘functional’ reset source is configured to generate a SAFE mode request
or an interrupt request, software needs to clear the event in the source
module at least three system clock cycles before it clears the associated
RGM_FES status bit in order to avoid multiple SAFE mode requests or
interrupts for the same event. In order to avoid having to count cycles, it is
good practice for software to check whether the RGM_FES has been
properly cleared, and if not, clear it again.
Table 54. Functional Event Status Register (RGM_FES) Field Descriptions
Field
F_EXR
F_FLASH
Description
Flag for External Reset
0 No external reset event has occurred since either the last clear or the last destructive reset
assertion
1 An external reset event has occurred
Flag for code or data flash fatal error
0 No code or data flash fatal error event has occurred since either the last clear or the last destructive
reset assertion
1 A code or data flash fatal error event has occurred
F_CMU0_FH Flag for FMPLL_0 clock frequency higher/lower than reference
L
0 No FMPLL_0 clock frequency higher/lower than reference event has occurred since either the last
clear or the last destructive reset assertion
1 A FMPLL_0 clock frequency higher/lower than reference event has occurred
F_CMU0_OL Flag for oscillator frequency lower than reference
R
0 No oscillator frequency lower than reference event has occurred since either the last clear or the
last destructive reset assertion
1 A oscillator frequency lower than reference event has occurred
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Freescale Semiconductor
7-151
Reset Generation Module (MC_RGM)
Table 54. Functional Event Status Register (RGM_FES) Field Descriptions (continued)
Field
Description
F_PLL0
Flag for FMPLL_0 fail
0 No FMPLL_0 fail event has occurred since either the last clear or the last destructive reset
assertion
1 A FMPLL_0 fail event has occurred
F_CHKSTO Flag for checkstop reset
P
0 No checkstop reset event has occurred since either the last clear or the last destructive reset
assertion
1 A checkstop reset event has occurred
F_SOFT
Flag for software reset
0 No software reset event has occurred since either the last clear or the last destructive reset
assertion
1 A software reset event has occurred
F_CORE
Flag for core reset
0 No core reset event has occurred since either the last clear or the last destructive reset assertion
1 A core reset event has occurred
F_JTAG
Flag for JTAG initiated reset
0 No JTAG initiated reset event has occurred since either the last clear or the last destructive reset
assertion
1 A JTAG initiated reset event has occurred
Destructive Event Status Register (RGM_DES)
1
2
3
4
5
6
7
8
9
10
F_POR
R
W w1c
POR
1
0
0
0
0
0
0
0
0
0
0
11
12
13
14
15
F_LVD12
0
Access: User read, Supervisor read/write, Test read/write
F_SWT
Address 0xC3FE_4002
F_LVD27_VREG
7.3.1.2
w1c
w1c
w1c
0
0
0
0
0
Figure 61. Destructive Event Status Register (RGM_DES)
This register contains the status of the last asserted destructive reset sources. It can be accessed in
read/write on either supervisor mode or test mode. It can be accessed in read only in user mode. Register
bits are cleared on write ‘1’.
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Reset Generation Module (MC_RGM)
Table 55. Destructive Event Status Register (RGM_DES) Field Descriptions
Field
Description
F_POR
Flag for Power-On reset
0 No power-on event has occurred since the last clear
1 A power-on event has occurred
F_LVD27_V Flag for 2.7V low-voltage detected (VREG)
REG
0 No 2.7V low-voltage detected (VREG) event has occurred since either the last clear or the last
power-on reset assertion
1 A 2.7V low-voltage detected (VREG) event has occurred
F_SWT
F_LVD12
Flag for software watchdog timer
0 No software watchdog timer event has occurred since either the last clear or the last power-on
reset assertion
1 A software watchdog timer event has occurred
Flag for 1.2V low-voltage detected
0 No 1.2V low-voltage detected event has occurred since either the last clear or the last power-on
reset assertion
1 A 1.2V low-voltage detected event has occurred
NOTE
The F_POR flag is automatically cleared on a 1.2 V low-voltage detected
or a 2.7 V low-voltage detected. This means that if the power-up sequence
is not monotonic (i.e., the voltage rises and then drops enough to trigger a
low-voltage detection), the F_POR flag may not be set but instead the
F_LVD12 or F_LVD27_VREG flag is set on exiting the reset sequence.
Therefore, if the F_POR, F_LVD12 or F_LVD27_VREG flags are set on
reset exit, software should interpret the reset cause as power-on.
Functional Event Reset Disable Register (RGM_FERD)
5
6
0
0
0
0
0
0
7
8
D_FLASH
D_EXR
9
10
11
12
13
14
15
D_JTAG
4
D_CORE
3
D_SOFT
2
D_CHKSTOP
1
R
D_PLL0
0
Access: User read, Supervisor read/write, Test read/write
D_CMU0_OLR
Address 0xC3FE_4004
D_CMU0_FHL
7.3.1.3
0
0
0
0
0
0
0
W
POR
0
0
0
Figure 62. Functional Event Reset Disable Register (RGM_FERD)
This register provides dedicated bits to disable functional reset sources.When a functional reset source is
disabled, the associated functional event will trigger either a SAFE mode request or an interrupt request
(see Section 7.3.1.4, “Functional Event Alternate Request Register (RGM_FEAR)”). It can be accessed in
read/write in either supervisor mode or test mode. It can be accessed in read only in user mode. Each byte
can be written only once after power-on reset.
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Reset Generation Module (MC_RGM)
WARNING
It is important to clear the RGM_FES register before setting any of the bits
in the RGM_FERD register to ‘1’. Otherwise a redundant SAFE mode
request or interrupt request may occur.
Table 56. Functional Event Reset Disable Register (RGM_FERD) Field Descriptions
Field
D_EXR
D_FLASH
D_CMU0_F
HL
Description
Disable External Reset
0 An external reset event triggers a reset sequence
Disable code or data flash fatal error
0 A code or data flash fatal error event triggers a reset sequence
Disable FMPLL_0 clock frequency higher/lower than reference
0 A FMPLL_0 clock frequency higher/lower than reference event triggers a reset sequence
1 A FMPLL_0 clock frequency higher/lower than reference event generates either a SAFE mode or
an interrupt request depending on the value of RGM_FEAR.AR_CMU0_FHL
D_CMU0_O Disable oscillator frequency lower than reference
LR
0 A oscillator frequency lower than reference event triggers a reset sequence
1 A oscillator frequency lower than reference event generates either a SAFE mode or an interrupt
request depending on the value of RGM_FEAR.AR_CMU0_OLR
D_PLL0
Disable FMPLL_0 fail
0 A FMPLL_0 fail event triggers a reset sequence
1 A FMPLL_0 fail event generates either a SAFE mode or an interrupt request depending on the
value of RGM_FEAR.AR_PLL0
D_CHKSTO Disable checkstop reset
P
0 A checkstop reset event triggers a reset sequence
D_SOFT
Disable software reset
0 A software reset event triggers a reset sequence
D_CORE
Disable core reset
0 A core reset event triggers a reset sequence
1 A core reset event generates either a SAFE mode or an interrupt request depending on the value
of RGM_FEAR.AR_CORE
D_JTAG
Disable JTAG initiated reset
0 A JTAG initiated reset event triggers a reset sequence
1 A JTAG initiated reset event generates either a SAFE mode or an interrupt request depending on
the value of RGM_FEAR.AR_JTAG
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Reset Generation Module (MC_RGM)
Functional Event Alternate Request Register (RGM_FEAR)
2
3
4
5
6
7
8
0
0
0
0
0
0
0
0
0
R
9
10
11
0
0
0
12
13
0
0
14
15
AR_JTAG
1
AR_CORE
0
AR_PLL0
Access: User read, Supervisor read/write, Test read/write
AR_CMU0_OLR
Address 0xC3FE_4010
AR_CMU0_FHL
7.3.1.4
0
0
W
POR
Figure 63. Functional Event Alternate Request Register (RGM_FEAR)
This register defines an alternate request to be generated when a reset on a functional event has been
disabled. The alternate request can be either a SAFE mode request to MC_ME or an interrupt request to
the system. It can be accessed in read/write in either supervisor mode or test mode. It can be accessed in
read only in user mode.
Table 57. Functional Event Alternate Request Register (RGM_FEAR) Field Descriptions
Field
Description
AR_CMU0_F Alternate Request for FMPLL_0 clock frequency higher/lower than reference
HL
0 Generate a SAFE mode request on a FMPLL_0 clock frequency higher/lower than reference event
if the reset is disabled
1 Generate an interrupt request on a FMPLL_0 clock frequency higher/lower than reference event
if the reset is disabled
AR_CMU0_ Alternate Request for oscillator frequency lower than reference
OLR
0 Generate a SAFE mode request on a oscillator frequency lower than reference event if the reset
is disabled
1 Generate an interrupt request on a oscillator frequency lower than reference event if the reset is
disabled
AR_PLL0
Alternate Request for FMPLL_0 fail
0 Generate a SAFE mode request on a FMPLL_0 fail event if the reset is disabled
1 Generate an interrupt request on a FMPLL_0 fail event if the reset is disabled
AR_CORE
Alternate Request for core reset
0 Generate a SAFE mode request on a core reset event if the reset is disabled
1 Generate an interrupt request on a core reset event if the reset is disabled
AR_JTAG
Alternate Request for JTAG initiated reset
0 Generate a SAFE mode request on a JTAG initiated reset event if the reset is disabled
1 Generate an interrupt request on a JTAG initiated reset event if the reset is disabled
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Freescale Semiconductor
7-155
Reset Generation Module (MC_RGM)
Functional Event Short Sequence Register (RGM_FESS)
5
6
0
0
0
0
0
0
7
8
SS_EXR
SS_FLASH
R
9
10
11
0
0
0
12
13
14
15
SS_JTAG
4
SS_CORE
3
SS_SOFT
2
SS_CHKSTOP
1
SS_PLL0
0
Access: User read, Supervisor read/write, Test read/write
SS_CMU0_OLR
Address 0xC3FE_4018
SS_CMU0_FHL
7.3.1.5
0
0
W
POR
0
0
0
0
0
Figure 64. Functional Event Short Sequence Register (RGM_FESS)
This register defines which reset sequence will be done when a functional reset sequence is triggered. The
functional reset sequence can either start from PHASE1 or from PHASE3, skipping PHASE1 and
PHASE2.
NOTE
This could be useful for fast reset sequence, for example to skip flash reset.
It can be accessed in read/write in either supervisor mode or test mode. It can be accessed in read in user
mode.
Table 58. Functional Event Short Sequence Register (RGM_FESS) Field Descriptions
Field
SS_EXR
SS_FLASH
Description
Short Sequence for External Reset
0 The reset sequence triggered by an external reset event will start from PHASE1
Short Sequence for code or data flash fatal error
0 The reset sequence triggered by a code or data flash fatal error event will start from PHASE1
SS_CMU0_F Short Sequence for FMPLL_0 clock frequency higher/lower than reference
HL
0 The reset sequence triggered by a FMPLL_0 clock frequency higher/lower than reference event
will start from PHASE1
1 The reset sequence triggered by a FMPLL_0 clock frequency higher/lower than reference event
will start from PHASE3, skipping PHASE1 and PHASE2
SS_CMU0_
OLR
Short Sequence for oscillator frequency lower than reference
0 The reset sequence triggered by a oscillator frequency lower than reference event will start from
PHASE1
1 The reset sequence triggered by a oscillator frequency lower than reference event will start from
PHASE3, skipping PHASE1 and PHASE2
SS_PLL0
Short Sequence for FMPLL_0 fail
0 The reset sequence triggered by a FMPLL_0 fail event will start from PHASE1
1 The reset sequence triggered by a FMPLL_0 fail event will start from PHASE3, skipping PHASE1
and PHASE2
SS_CHKST
OP
Short Sequence for checkstop reset
0 The reset sequence triggered by a checkstop reset event will start from PHASE1
1 The reset sequence triggered by a checkstop reset event will start from PHASE3, skipping
PHASE1 and PHASE2
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Reset Generation Module (MC_RGM)
Table 58. Functional Event Short Sequence Register (RGM_FESS) Field Descriptions (continued)
Field
Description
SS_SOFT
Short Sequence for software reset
0 The reset sequence triggered by a software reset event will start from PHASE1
1 The reset sequence triggered by a software reset event will start from PHASE3, skipping PHASE1
and PHASE2
SS_CORE
Short Sequence for core reset
0 The reset sequence triggered by a core reset event will start from PHASE1
1 The reset sequence triggered by a core reset event will start from PHASE3, skipping PHASE1 and
PHASE2
SS_JTAG
Short Sequence for JTAG initiated reset
0 The reset sequence triggered by a JTAG initiated reset event will start from PHASE1
1 The reset sequence triggered by a JTAG initiated reset event will start from PHASE3, skipping
PHASE1 and PHASE2
NOTE
This register is reset on any enabled ‘destructive’ or ‘functional’ reset event.
Functional Bidirectional Reset Enable Register (RGM_FBRE)
5
6
0
0
0
0
0
0
7
8
BE_FLASH
BE_EXR
9
10
11
12
13
14
15
BE_JTAG
4
BE_CORE
3
BE_SOFT
2
BE_CHKSTOP
1
R
BE_PLL0
0
Access: User read, Supervisor read/write, Test read/write
BE_CMU0_OLR
Address 0xC3FE_401C
BE_CMU0_FHL
7.3.1.6
0
0
0
0
0
0
0
W
POR
0
0
0
Figure 65. Functional Bidirectional Reset Enable Register (RGM_FBRE)
This register enables the generation of an external reset on functional reset. It can be accessed in read/write
in either supervisor mode or test mode. It can be accessed in read in user mode.reset
Table 59. Functional Bidirectional Reset Enable Register (RGM_FBRE) Field Descriptions
Field
BE_EXR
BE_FLASH
Description
Bidirectional Reset Enable for External Reset
0 RESET_B is asserted on an external reset event if the reset is enabled
1 RESET_B is not asserted on an external reset event
Bidirectional Reset Enable for code or data flash fatal error
0 RESET_B is asserted on a code or data flash fatal error event if the reset is enabled
1 RESET_B is not asserted on a code or data flash fatal error event
BE_CMU0_F Bidirectional Reset Enable for FMPLL_0 clock frequency higher/lower than reference
HL
0 RESET_B is asserted on a FMPLL_0 clock frequency higher/lower than reference event if the
reset is enabled
1 RESET_B is not asserted on a FMPLL_0 clock frequency higher/lower than reference event
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Reset Generation Module (MC_RGM)
Table 59. Functional Bidirectional Reset Enable Register (RGM_FBRE) Field Descriptions (continued)
Field
Description
BE_CMU0_
OLR
Bidirectional Reset Enable for oscillator frequency lower than reference
0 RESET_B is asserted on a oscillator frequency lower than reference event if the reset is enabled
1 RESET_B is not asserted on a oscillator frequency lower than reference event
BE_PLL0
BE_CHKST
OP
Bidirectional Reset Enable for FMPLL_0 fail
0 RESET_B is asserted on a FMPLL_0 fail event if the reset is enabled
1 RESET_B is not asserted on a FMPLL_0 fail event
Bidirectional Reset Enable for checkstop reset
0 RESET_B is asserted on a checkstop reset event if the reset is enabled
1 RESET_B is not asserted on a checkstop reset event
BE_SOFT
Bidirectional Reset Enable for software reset
0 RESET_B is asserted on a software reset event if the reset is enabled
1 RESET_B is not asserted on a software reset event
BE_CORE
Bidirectional Reset Enable for core reset
0 RESET_B is asserted on a core reset event if the reset is enabled
1 RESET_B is not asserted on a core reset event
BE_JTAG
Bidirectional Reset Enable for JTAG initiated reset
0 RESET_B is asserted on a JTAG initiated reset event if the reset is enabled
1 RESET_B is not asserted on a JTAG initiated reset event
7.4
Functional Description
7.4.1
Reset State Machine
The main role of MC_RGM is the generation of the reset sequence which ensures that the correct parts of
the chip are reset based on the reset source event. This is summarized in Table 60.
Table 60. MC_RGM Reset Implications
Source
What Gets Reset
External Reset
Assertion1
Boot Mode
Capture
power-on reset
all
yes
yes
‘destructive’ resets
all except some clock/reset management
yes
yes
external reset
all except some clock/reset management and
debug
programmable2
yes
‘functional’ resets
all except some clock/reset management and
debug
programmable2 programmable3
shortened ‘functional’ resets4 flip-flops except some clock/reset management
programmable2 programmable3
1
‘external reset assertion’ means that the RESET_B pin is asserted by the MC_RGM until the end of reset PHASE3
the assertion of the external reset is controlled via the RGM_FBRE register
3 the boot mode is captured if the external reset is asserted
4 the short sequence is enabled via the RGM_FESS register
2
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Reset Generation Module (MC_RGM)
NOTE
JTAG logic has its own independent reset control and is not controlled by
the MC_RGM in any way.
The reset sequence is comprised of five phases managed by a state machine, which ensures that all phases
are correctly processed through waiting for a minimum duration and until all processes that need to occur
during that phase have been completed before proceeding to the next phase.
The state machine used to produce the reset sequence is shown in Figure 66.
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Reset Generation Module (MC_RGM)
power-on
or any other
‘destructive’
reset
PHASE0
duration ≥ 3 internal RC oscillator clock cycles
16 MHz IRC stable, VREG voltage okay done
enabled
non-shortened external or
‘functional’
PHASE1
duration ≥ 350 internal RC oscillator clock cycles
PHASE2
duration ≥ 8 internal RC oscillator clock cycles
code and data flash initialization done
PHASE3
enabled
shortened
external or
‘functional’
duration ≥ 40 internal RC oscillator clock cycles
RESET_B released
code and data flash initialization done
IDLE
Figure 66. MC_RGM State Machine
7.4.1.1
PHASE0 Phase
This phase is entered immediately from any phase on a power-on or any other ‘destructive’ reset event.
The reset state machine exits PHASE0 and enters PHASE1 on verification of the following:
• all enabled ‘destructive’ resets have been processed
• all processes that need to be done in PHASE0 are completed
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Reset Generation Module (MC_RGM)
•
— 16 MHz IRC stable, VREG voltage okay
a minimum of 3 internal RC oscillator clock cycles have elapsed since power-up completion and
the last enabled ‘destructive’ reset event
7.4.1.2
PHASE1 Phase
This phase is entered either on exit from PHASE0 or immediately from PHASE2, PHASE3, or IDLE
on a non-masked external or ‘functional’ reset event if it has not been configured to trigger a ‘short’
sequence. The reset state machine exits PHASE1 and enters PHASE2 on verification of the following:
• all enabled, non-shortened ‘functional’ resets have been processed
• a minimum of 350 internal RC oscillator clock cycles have elapsed since the last enabled external
or non-shortened ‘functional’ reset event
7.4.1.3
PHASE2 Phase
This phase is entered on exit from PHASE1. The reset state machine exits PHASE2 and enters PHASE3
on verification of the following:
• all processes that need to be done in PHASE2 are completed
— code and data flash initialization
• a minimum of 8 internal RC oscillator clock cycles have elapsed since entering PHASE2
7.4.1.4
PHASE3 Phase
This phase is a entered either on exit from PHASE2 or immediately from IDLE on an enabled, shortened
‘functional’ reset event. The reset state machine exits PHASE3 and enters IDLE on verification of the
following:
• all processes that need to be done in PHASE3 are completed
— code and data flash initialization
• a minimum of 40 internal RC oscillator clock cycles have elapsed since the last enabled, shortened
‘functional’ reset event
7.4.1.5
IDLE Phase
This is the final phase and is entered on exit from PHASE3. When this phase is reached, the MC_RGM
releases control of the chip to the core and waits for new reset events that can trigger a reset sequence.
7.4.2
Destructive Resets
A ‘destructive’ reset indicates that an event has occurred after which critical register or memory content
can no longer be guaranteed.
The status flag associated with a given ‘destructive’ reset event (RGM_DES.F_<destructive reset>
bit) is set when the ‘destructive’ reset is asserted and the power-on reset is not asserted. It is possible for
multiple status bits to be set simultaneously, and it is software’s responsibility to determine which reset
source is the most critical for the application.
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Reset Generation Module (MC_RGM)
The chip’s low-voltage detector threshold ensures that, when 1.2V low-voltage detected, the supply is
sufficient to have the destructive event correctly propagated through the digital logic. Therefore, if a given
‘destructive’ reset is asserted, the MC_RGM ensures that the associated reset event will be correctly
triggered to the full system. A destructive reset will trigger a reset sequence starting from the beginning of
PHASE0.
7.4.3
External Reset
The MC_RGM manages the external reset coming from RESET_B. The detection of a falling edge on
RESET_B will start the reset sequence from the beginning of PHASE1.
The status flag associated with the external reset falling edge event (RGM_FES.F_EXR bit) is set when
the external reset is asserted and the power-on reset is not asserted.
NOTE
The RGM_FERD register can be written only once between two power-on
reset events.
External reset will trigger a reset sequence starting from the beginning of PHASE1.
The MC_RGM may also assert the external reset if the reset sequence was triggered by one of the
following:
• a power-on reset
• a ‘destructive’ reset event
• an external reset event
• a ‘functional’ reset event configured via the RGM_FBRE register to assert the external reset
In this case, the external reset is asserted until the end of PHASE3.
7.4.4
Functional Resets
A ‘functional’ reset indicates that an event has occurred after which it can be guaranteed that critical
register and memory content is still intact.
The status flag associated with a given ‘functional’ reset event (RGM_FES.F_<functional reset> bit)
is set when the ‘functional’ reset is asserted and the power-on reset is not asserted. It is possible for
multiple status bits to be set simultaneously, and it is software’s responsibility to determine which reset
source is the most critical for the application.
The ‘functional’ reset can be optionally disabled by software writing bit
RGM_FERD.D_<functional reset>.
NOTE
The RGM_FERD register can be written only once between two power-on
reset events.
An enabled ‘functional’ reset will normally trigger a reset sequence starting from the beginning of
PHASE1. Nevertheless, the RGM_FESS register enables the further configuring of the reset sequence
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Reset Generation Module (MC_RGM)
triggered by a functional reset. When RGM_FESS.SS_<functional reset> is set, the associated
‘functional’ reset will trigger a reset sequence starting directly from the beginning of PHASE3, skipping
PHASE1 and PHASE2. This can be useful especially in case a functional reset should not reset the flash
module.
7.4.5
Alternate Event Generation
The MC_RGM provides alternative events to be generated on reset source assertion. When a reset source
is asserted, the MC_RGM normally enters the reset sequence. Alternatively, it is possible for some reset
source events to be converted from a reset to either a SAFE mode request issued to the MC_ME or to an
interrupt request issued to the core.
Alternate event selection for a given reset source is made via the RGM_FERD and RGM_FEAR registers
as shown in Table 61.
Table 61. MC_RGM Alternate Event Selection
RGM_FERD
Bit Value
RGM_FEAR
Bit Value
0
X
reset
1
0
SAFE mode request
1
1
interrupt request
Generated Event
The alternate event is cleared by deasserting the source of the request (i.e., at the reset source that caused
the alternate request) and also clearing the appropriate RGM_FES status bit.
NOTE
Alternate requests (SAFE mode as well as interrupt requests) are generated
regardless of whether the system clock is running.
NOTE
If a masked ‘functional’ reset event which is configured to generate a SAFE
mode/interrupt request occurs during PHASE1, it is ignored, and the
MC_RGM will not send any safe mode/interrupt request to the MC_ME.
7.4.6
Boot Mode Capturing
The MC_RGM samples FAB, ABS[1:0] whenever RESET_B is asserted until five internal RC oscillator
clock cycles before its deassertion edge. The result of the sampling is used at the beginning of reset
PHASE3 for boot mode selection and is retained after RESET_B has been deasserted for subsequent
boots after reset sequences during which RESET_B is not asserted.
NOTE
In order to ensure that the boot mode is correctly captured, the application
needs to apply the valid boot mode value the entire time that RESET_B is
asserted.
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Reset Generation Module (MC_RGM)
NOTE
RESET_B can be asserted as a consequence of the internal reset
generation. This will force re-sampling of the boot mode pins. (See Table 60
for details.)
fs
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Chapter 8
Power Control Unit (MC_PCU)
8.1
8.1.1
Introduction
Overview
The power control unit (MC_PCU) acts as a bridge for mapping the PMU peripheral to the MC_PCU
address space.
Figure 67 depicts the MC_PCU block diagram.
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Power Control Unit (MC_PCU)
MC_PCU
Registers
Register Interface
Mapped Module Interface
core
mapped
peripheral
Figure 67. MC_PCU Block Diagram
8.1.2
Features
The MC_PCU includes the following features:
• maps the PMU registers to the MC_PCU address space
8.2
External Signal Description
The MC_PCU has no connections to any external pins.
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Power Control Unit (MC_PCU)
8.3
Memory Map and Register Definition
8.3.1
Memory Map
Table 62. MC_PCU Register Description
Access
Address
Name
0xC3FE PCU_PSTAT
_8040
Description
Size
Power Domain Status
Register
Location
word
User
Supervisor
Test
read
read
read
on page 168
NOTE
Any access to unused registers as well as write accesses to read-only
registers will:
•
•
not change register content
cause a transfer error
Table 63. MC_PCU Memory Map
Address
Name
0
1
2
3
27
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0xC3FE
_80004
…
0xC3FE
_803C
R
0
0
0
0
0
0
0
W
PD0
0xC3FE PCU_PSTAT
_8040
reserved
R
W
0x044
…
0x07C
reserved
0xC3FE
_8080
…
0xC3FE
_80FC
PMU registers
0xC3FE
_8100
…
0xC3FE
_BFFC
reserved
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Power Control Unit (MC_PCU)
8.3.2
Register Descriptions
All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered
according to big endian. For example, the PD0 field of the PCU_PSTAT register may be accessed as a
word at address 0xC3FE_8040, as a half-word at address 0xC3FE_8042, or as a byte at address
0xC3FE_8043.
8.3.2.1
Power Domain Status Register (PCU_PSTAT)
Address 0xC3FE_8040
R
Access: User read, Supervisor read, Test read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
PD0
W
R
W
Reset
1
Figure 68. Power Domain Status Register (PCU_PSTAT)
This register reflects the power status of all available power domains.
Table 64. Power Domain Status Register (PCU_PSTAT) Field Descriptions
Field
PDn
Description
Power status for power domain #n
0 Power domain is inoperable
1 Power domain is operable
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Chapter 9
Power Management
9.1
Power management overview
The device supports the following power modes:
•
•
9.1.1
Internal voltage regulation mode
External voltage regulation mode
Internal voltage regulation mode
In this mode, the following supplies are involved:
• VDD_HV_IO (3.3V) — This is the main supply provided externally.
• VDD_LV_CORE (1.2 V) — This is the core logic supply. In the internal regulation mode, the core
supply is derived from the main supply via an on-chip linear regulator driving an internal PMOS
ballast transistor. The PMOS ballast transistors are located in the pad ring and their source
connectors are directly bonded to a dedicated pin. See Figure 69.
Pads Pins
Vss_HV_IO0_X
3.3V
Vdd_HV_IO0_X
Vdd_HV_S_Ballast0/1
Vreg
LVD
...
POR_B
1.2V
...
Vdd_LV_REGCOR0
Vdd_LV_COR0_X
(3 supply pairs)
Vss_LV_COR0_X
Figure 69. Internal Regulation Mode
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Power Management
The core supply can also be provided externally. Table 65 shows how to connect VDD_HV_S_BALLAST pin
for internal and external core supply mode.
Table 65. Core Supply Select
Mode
9.1.2
Vdd_S_Ballast
Internal supply mode (via internal PMOS ballast
transistors)
VDD_HV_IO (3.3V)
External supply mode (e.g., via external switched
regulator)
VDD_LV_CORE (1.2V)
External voltage regulation mode
In the external regulation mode, the core supply is provided externally using a switched regulator. This
saves on-chip power consumption by avoiding the voltage drop over the ballast transistor. The external
supply mode is selected via a board level supply change at the Vdd_HV_S_Ballast pin.
Pads Pins
Vss_HV_IO0_X
Vdd_HV_IO0_X
3.3V
Vdd_HV_S_Ballast0/1
1.2V
(1.15V-1.32V)
Vreg
relaxed
LVD
...
POR_B
Power
Supply, e.g.,
switched or
linear
1.2V
...
Vdd_LV_REGCOR0
Vdd_LV_COR0_X
(3 supply pairs)
Vss_LV_COR0_X
Figure 70. External Regulation Mode
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Power Management
9.1.3
Voltage Regulator Electrical Characteristics
\
CREG2 (LV_COR/LV_CFLA)
GND
600 nF
VDD_HV_IO
VDD_LV_COR0_2
VSS_LV_COR0_2
VDD_HV_S_BALLAST0
-
Voltage Regulator
I
VDD_HV_S_BALLAST1
CREG1 (LV_COR/LV_DFLA)
VDD_LV_COR0_0
CDEC1 (Ballast decoupling)
VREF
+
VDD_LV_COR0_3
DEVICE
VSS_HV_IO
GND
DEVICE
VSS_LV_COR0_0
VSS_LV_COR0_1
VSS_HV_IO
VDD_HV_IO
VDD_LV_COR0_1
600 nF
GND
GND
CREG3 (LV_COR/LV_PLL)
CDEC2 (supply/IO decoupling)
Figure 71. Voltage regulator capacitance connection
9.2
Power sequencing
As shown in Figure 72 the MPC5604E includes on-chip diodes for ESD protection.
VDD_HV_IO (3.3 V)
VDD_HV_CORE (1.2 V)
VDD_HV_S_BALLAST
(3.3 V/1.2 V)
VDD_HV_ADC
(3.3 V)
Figure 72. Internal diodes between supply pads
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Power Management
For both internal and external core voltage supply modes the following conditions must be guaranteed at
power up and power down:
• VDD_HV_IO >= VDD_LV_CORE
• VDD_HV_IO >= VDD_HV_S_BALLAST
• VDD_HV_IO>= VDD_HV_ADC
9.3
Power Management Unit (PMU)
The primary function of the MPC5604E’s power management unit (PMU) is to generate the 1.2 V core
logic supply from the 3.3 V main supply. To allow an easy integration into a system The PMU includes an
internal PMOS ballast transistor.
In addition the PMU monitors the operation voltages using a set of supervisory circuits: the LVDs (Low
Voltage Detectors). Furthermore, the Power On Reset (POR) circuit monitors VddREG, the voltage used
internally by the PMU. When VddREG is below the POR threshold voltage, the POR output is asserted,
otherwise it is deasserted.
The purpose of the POR circuit is to keep the MPC5604E in the reset state as long as the supply voltage
to the LVD circuits is below their minimum operating voltage. By the time the POR output deasserts, the
LVDs are operating and able to assert their outputs properly.
In summary the PMU has the following features:
• Internal PMOS ballast transistor
• Power On Reset (POR)
• Low voltage detection
• Internal power on reset (POR) circuit to detect minimal voltage to operate voltage regulator.
• LVD27 for VddIO. The minimum threshold value must not be below 2.60V to guarantee correct
flash memory read operations.
• LVD12 for VddCore (trimmed during testing)
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Chapter 10
Interrupt Controller (INTC)
10.1
Introduction
The INTC provides priority-based preemptive scheduling of interrupt service requests (ISRs). This
scheduling scheme is suitable for statically scheduled hard real-time systems. The INTC supports 106
interrupt requests. It is targeted to work with Power Architecture technology and automotive applications
where the ISRs nest to multiple levels, but it also can be used with other processors and applications.
For high-priority interrupt requests in these target applications, the time from the assertion of the
peripheral’s interrupt request to when the processor is performing useful work to service the interrupt
request needs to be minimized. The INTC supports this goal by providing a unique vector for each
interrupt request source. It also provides 16 priorities so that lower priority ISRs do not delay the execution
of higher priority ISRs. Because each individual application will have different priorities for each source
of interrupt request, the priority of each interrupt request is configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC
supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the
priority can be raised temporarily so that tasks sharing the resource will not preempt each other.
Multiple processors can assert interrupt requests to each other through software configurable interrupt
requests. These software configurable interrupt requests can also be used to separate the work involved in
servicing an interrupt request into a high-priority portion and a low-priority portion. The high-priority
portion is initiated by a peripheral interrupt request, but then the ISR can assert a software configurable
interrupt request to finish the servicing in a lower priority ISR. Therefore these software configurable
interrupt requests can be used instead of the peripheral ISR scheduling a task through the RTOS.
10.2
•
•
•
•
Features
Supports 106 peripheral interrupts and 8 software-configurable interrupt request sources
Unique 9-bit vector per interrupt source
Each interrupt source programmable to one of 16 priorities
Preemption
— Preemptive prioritized interrupt requests to processor
— ISR at a higher priority preempts ISRs or tasks at lower priorities
— Automatic pushing or popping of preempted priority to or from a LIFO
— Ability to modify the ISR or task priority; modifying the priority can be used to implement the
priority ceiling protocol for accessing shared resources.
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Interrupt Controller (INTC)
•
Low latency—3 clock cycles from receipt of interrupt request from peripheral to interrupt request
to processor
Table 66. Interrupt sources available
10.3
Interrupt sources (106)
Number available
Software
8
eDMA2x
17
SWT
1
STM
4
SIUL
4
MC_ME
4
MC_RGM
1
MCM
3
I2C
2
Video Encoder
6
Fast Ethernet Controller (FEC)
3
CE_RTC
1
XOSC
1
PTP
1
SAI
6
PIT
4
ADC
3
FlexCAN
8
eTimer
8
DSPI
15
LINFlex
6
Block diagram
Figure 73 shows a block diagram of the interrupt controller (INTC).
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Interrupt Controller (INTC)
Software
Set/Clear
Interrupt
Registers
n1
Flag Bits
Peripheral
Interrupt
Requests
x
4-bits
8
n1
Priority
Arbitrator
4
Popped
Priority
4
Highest
Priority
Interrupt
Requests
n1
Request
Selector
Lowest
Vector
Interrupt
Request
n1
End of
Interrupt
Register
Vector
Encoder
Processor 0
Current
Priority
Register
Interrupt
Vector
9
Processor 0
Interrupt
Acknowledge
Register
Highest Priority
Update Interrupt Vector
Current
Priority
4
Hardware
Vector Enable
1
Vector Table
Entry Size 1
New
Priority
4
Pushed
Priority
4
Processor 0
Priority
LIFO
Module
Configuration
Register
Priority
Select
Registers
Interrupt
Vector
9
Interrupt
Request to
Processor
1
Priority
Comparator
1
Interrupt Acknowledge
1
Push/Update/Acknowledge
1
Pop
1
Slave
Interface
for Reads
& Writes
Peripheral
Memory Mapped Registers
Non-Memory Mapped Logic
1
The total number of available interrupt sources is 106, which includes 8 software sources.
Figure 73. INTC block diagram
10.4
Modes of operation
10.4.1
Normal mode
In normal mode, the INTC has two handshaking modes with the processor: software vector mode and
hardware vector mode.
NOTE
To correctly configure the interrupts in both software and hardware vector
mode, the user must also configure the IVPR. The core register IVPR
contains the base address for the interrupt handlers. Please refer to the core
reference manual for more information.
10.4.1.1
Software vector mode
In software vector mode, the interrupt exception handler software must read a register in the INTC to
obtain the vector associated with the interrupt request to the processor. The INTC will use software vector
mode for a given processor when its associated HVEN bit in INTC_MCR is negated. The hardware vector
enable signal to processor 0 or processor 1 is driven as negated when its associated HVEN bit is negated.
The vector is read from INC_IACKR. Reading the INTC_IACKR negates the interrupt request to the
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Interrupt Controller (INTC)
associated processor. Even if a higher priority interrupt request arrived while waiting for this interrupt
acknowledge, the interrupt request to the processor will negate for at least one clock. The reading also
pushes the PRI value in INTC_CPR onto the associated LIFO and updates PRI in the associated
INTC_CPR with the new priority.
Furthermore, the interrupt vector to the processor is driven as all 0s. The interrupt acknowledge signal
from the associated processor is ignored.
10.4.1.2
Hardware vector mode
In hardware vector mode, the hardware signals the interrupt vector from the INTC in conjunction with a
processor that can use that vector. This hardware causes the first instruction to be executed in handling the
interrupt request to the processor to be specific to that vector. Therefore, the interrupt exception handler is
specific to a peripheral or software configurable interrupt request rather than being common to all of them.
The INTC uses hardware vector mode for a given processor when the associated HVEN bit in the
INTC_MCR is asserted. The hardware vector enable signal to the associated processor is driven as
asserted. When the interrupt request to the associated processor asserts, the interrupt vector signal is
updated. The value of that interrupt vector is the unique vector associated with the preempting peripheral
or software configurable interrupt request. The vector value matches the value of the INTVEC field in the
INTC_IACKR field in the INTC_IACKR, depending on which processor was assigned to handle a given
interrupt source.
The processor negates the interrupt request to the processor driven by the INTC by asserting the interrupt
acknowledge signal for one clock. Even if a higher priority interrupt request arrived while waiting for the
interrupt acknowledge, the interrupt request to the processor will negate for at least one clock.
The assertion of the interrupt acknowledge signal for a given processor pushes the associated PRI value in
the associated INTC_CPR register onto the associated LIFO and updates the associated PRI in the
associated INTC_CPR register with the new priority. This pushing of the PRI value onto the associated
LIFO and updating PRI in the associated INTC_CPR does not occur when the associated interrupt
acknowledge signal asserts and INTC_SSCIR0_3–INTC_SSCIR4_7 is written at a time such that the PRI
value in the associated INTC_CPR register would need to be pushed and the previously last pushed PRI
value would need to be popped simultaneously. In this case, PRI in the associated INTC_CPR is updated
with the new priority, and the associated LIFO is neither pushed or popped.
10.4.1.3
Debug mode
The INTC operation in debug mode is identical to its operation in normal mode.
10.4.1.4
Stop mode
The INTC supports stop mode. The INTC can have its clock input disabled at any time by the clock driver
on the device. While its clocks are disabled, the INTC registers are not accessible.
The INTC requires clocking in order for a peripheral interrupt request to generate an interrupt request to
the processor.
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Interrupt Controller (INTC)
10.5
10.5.1
Memory map and registers description
Module memory map
Table 67 shows the INTC memory map.
Table 67. INTC memory map
Offset from
INTC_BASE
(0xFFF4_8000)
Register
0x0000
INTC Module Configuration Register (INTC_MCR)
0x0004
Reserved
0x0008
INTC Current Priority Register for Processor
(INTC_CPR)
0x000C
Reserved
0x0010
INTC Interrupt Acknowledge Register (INTC_IACKR)
0x0014
Reserved
0x0018
INTC End-of-Interrupt Register (INTC_EOIR)
0x001C
Reserved
Access
0x0020–0x0027 INTC Software Set/Clear Interrupt Registers
(INTC_SSCIR0_3–INTC_SSCIR4_7)
Reset value
Location
R/W
0x0000_0000 on page 178
R/W
0x0000_000F on page 178
R1/W
0x0000_0000 on page 180
W
0x0000_0000 on page 180
R/W
0x0000_0000 on page 181
R/W
0x0000_0000 on page 182
0x0028– 0x003C Reserved
0x0040–0x011C INTC Priority Select Registers
(INTC_PSR0_3–INTC_PSR220_221)2
0x0120–0x3FFF
Reserved
1
When the HVEN bit in the INTC module configuration register (INTC_MCR) is asserted, a read of the INTC_IACKR
has no side effects.
2 The PRI fields are “reserved” for peripheral interrupt requests whose vectors are labeled as Reserved in Table 74.
10.5.2
Registers description
With exception of the INTC_SSCIn and INTC_PSRn, all registers are 32 bits in width. Any combination
of accessing the four bytes of a register with a single access is supported, provided that the access does not
cross a register boundary. These supported accesses include types and sizes of 8 bits, aligned 16 bits,
misaligned 16 bits to the middle 2 bytes, and aligned 32 bits.
Although INTC_SSCIn and INTC_PSRn are 8 bits wide, they can be accessed with a single 16-bit or
32-bit access, provided that the access does not cross a 32-bit boundary.
In software vector mode, the side effects of a read of INTC_IACKR are the same regardless of the size of
the read. In either software or hardware vector mode, the size of a write to either
INTC_SSCIR0_3–INTC_SSCIR4_7 or INTC_EOIR does not affect the operation of the write.
INTC registers are accessible only when the core is in supervisor mode.
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
10-177
Interrupt Controller (INTC)
10.5.2.1
INTC Module Configuration Register (INTC_MCR)
The module configuration register configures options of the INTC.
Address: Base + 0x0000
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
VTES
0
HVEN
0
Figure 74. INTC Module Configuration Register (INTC_MCR)
Table 68. INTC_MCR field descriptions
Field
Description
26
VTES
Vector table entry size
Controls the number of 0s to the right of INTVEC in Section 10.5.2.3, “INTC Interrupt Acknowledge
Register (INTC_IACKR)”. If the contents of INTC_IACKR are used as an address of an entry in a vector
table as in software vector mode, then the number of right most 0s will determine the size of each
vector table entry. VTES impacts software vector mode operation but also affects
INTC_IACKR[INTVEC] position in both hardware vector mode and software vector mode.
0 4 bytes
1 8 bytes
31
HVEN
Hardware vector enable
Controls whether the INTC is in hardware vector mode or software vector mode. Refer to Section 10.4,
“Modes of operation”, for the details of the handshaking with the processor in each mode.
0 Software vector mode
1 Hardware vector mode
10.5.2.2
INTC Current Priority Register for Processor (INTC_CPR)
Address: Base + 0x0008
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
W
Reset
R
PRI
W
Reset
1
1
Figure 75. INTC Current Priority Register (INTC_CPR)
MPC5604E Reference Manual, Rev. 5
10-178
Freescale Semiconductor
Interrupt Controller (INTC)
Table 69. INTC_CPR field descriptions
Field
28–31
PRI[]
Description
Priority
PRI is the priority of the currently executing ISR according to the following:
1111 Priority 15—highest priority
1110 Priority 14
1101 Priority 13
1100 Priority 12
1011 Priority 11
1010 Priority 10
1001 Priority 9
1000 Priority 8
0111 Priority 7
0110 Priority 6
0101 Priority 5
0100 Priority 4
0011 Priority 3
0010 Priority 2
0001 Priority 1
0000 Priority 0—lowest priority
The INTC_CPR masks any peripheral or software settable interrupt request set at the same or lower
priority as the current value of the INTC_CPR[PRI] field from generating an interrupt request to the
processor. When the INTC interrupt acknowledge register (INTC_IACKR) is read in software vector
mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode, the
value of PRI is pushed onto the LIFO, and PRI is updated with the priority of the preempting interrupt
request. When the INTC end-of-interrupt register (INTC_EOIR) is written, the LIFO is popped into the
INTC_CPR’s PRI field.
The masking priority can be raised or lowered by writing to the PRI field, supporting the PCP. Refer to
Section 10.7.5, “Priority ceiling protocol”.
NOTE
A store to modify the PRI field that closely precedes or follows an access to
a shared resource can result in a non-coherent access to the resource. Refer
to Section 10.7.5.2, “Ensuring coherency”, for example code to ensure
coherency.
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
10-179
Interrupt Controller (INTC)
10.5.2.3
INTC Interrupt Acknowledge Register (INTC_IACKR)
Address Base + 0x0010
0
1
Access: User read/write
2
3
4
5
R
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
25
26
27
28
29
30
31
0
0
0
0
VTBA (most significant 16 bits)
W
Reset
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
R
INTVEC1
VTBA
(least significant 5 bits)
W
Reset
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
When the VTES bit in INTC_MCR is asserted, INTVEC is shifted to the left one bit. Bit is read as a ‘0’.
VTBA is narrowed to 20 bits in width.
Figure 76. INTC Interrupt Acknowledge Register (INTC_IACKR)
Table 70. INTC_IACKR field descriptions
Field
Description
0–20
or
0–19
VTBA
Vector Table Base Address
Can be the base address of a vector table of addresses of ISRs. The VTBA only uses the leftmost
20 bits when the VTES bit in INTC_MCR is asserted.
21–29
or
20–28
INTVEC
Interrupt Vector
It is the vector of the peripheral or software configurable interrupt request that caused the interrupt
request to the processor. When the interrupt request to the processor asserts, the INTVEC is
updated, whether the INTC is in software or hardware vector mode.
Note: If INTC_MCR[VTES] = 1, then the INTVEC field is shifted left one position to bits 20–28.
VTBA is then shortened by one bit to bits 0–19.
The interrupt acknowledge register provides a value that can be used to load the address of an ISR from a
vector table. The vector table can be composed of addresses of the ISRs specific to their respective
interrupt vectors.
In software vector mode, the INTC_IACKR has side effects from reads. Therefore, it must not be
speculatively read while in this mode. The side effects are the same regardless of the size of the read.
Reading the INTC_IACKR does not have side effects in hardware vector mode.
10.5.2.4
INTC End-of-Interrupt Register (INTC_EOIR)
Writing to the end-of-interrupt register signals the end of the servicing of the interrupt request. When the
INTC_EOIR is written, the priority last pushed on the LIFO is popped into INTC_CPR. An exception to
this behavior is described in Section 10.4.1.2, “Hardware vector mode”. The values and size of data
written to the INTC_EOIR are ignored. The values and sizes written to this register neither update the
INTC_EOIR contents or affect whether the LIFO pops. For possible future compatibility, write four bytes
of all 0s to the INTC_EOIR.
Reading the INTC_EOIR has no effect on the LIFO.
MPC5604E Reference Manual, Rev. 5
10-180
Freescale Semiconductor
Interrupt Controller (INTC)
Offsets:
Base + 0x0018 (IINTC_EOIR)
R
Access: User write-only
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
EOI[31:16]
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
EOI[15:0]
Reset
0
0
0
0
0
0
0
0
0
Figure 77. INTC End of Interrupt Register for Processor (INTC_EOIR)
Table 71. INTC_EOIR field descriptions
Field
Description
EOI
10.5.2.5
End of Interrupt. Write four all-zero bytes to this field to signal the end of the servicing of an
interrupt request.
INTC Software Set/Clear Interrupt Registers
(INTC_SSCIR0_3–INTC_SSCIR4_7)
Access: User read/write
Address Base + 0x0020
R
0
1
2
3
4
5
6
0
0
0
0
0
0
0
W
Reset
R
8
9
10
11
12
13
14
15
0
0
0
0
0
0
SET0
CLR
0
0
SET1
CLR
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
7
CLR
SET2 2
0
0
CLR
SET3 3
0
0
Figure 78. INTC Software Set/Clear Interrupt Register 0–3 (INTC_SSCIR[0:3])
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
10-181
Interrupt Controller (INTC)
Address Base + 0x0024
R
Access: User read/write
0
1
2
3
4
5
6
0
0
0
0
0
0
0
W
Reset
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
SET4
CLR
4
0
SET5
CLR
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
CLR
SET6 6
W
Reset
0
0
CLR
SET7 7
0
0
Figure 79. INTC Software Set/Clear Interrupt Register 4–7 (INTC_SSCIR[4:7])
Table 72. INTC_SSCIR[0:7] field descriptions
Field
Description
6, 14, 22, 30
SET[0:7]
Set Flag Bits
Writing a ‘1’ sets the corresponding CLRx bit. Writing a ‘0’ has no effect. Each SETx always will
be read as a ‘0’.
7, 15, 23, 31
CLR[0:7]
Clear Flag Bits
CLRx is the flag bit. Writing a ‘1’ to CLRx clears it provided that a ‘1’ is not written simultaneously
to its corresponding SETx bit. Writing a ‘0’ to CLRx has no effect.
0 Interrupt request not pending within INTC
1 Interrupt request pending within INTC
The software set/clear interrupt registers support the setting or clearing of software configurable interrupt
request. These registers contain eight independent sets of bits to set and clear a corresponding flag bit by
software. Excepting being set by software, this flag bit behaves the same as a flag bit set within a
peripheral. This flag bit generates an interrupt request within the INTC like a peripheral interrupt request.
Writing a ‘1’ to SETx will leave SETx unchanged at 0 but sets CLRx. Writing a ‘0’ to SETx has no effect.
CLRx is the flag bit. Writing a ‘1’ to CLRx clears it. Writing a ‘0’ to CLRx has no effect. If a ‘1’ is written
simultaneously to a pair of SETx and CLRx bits, CLRx will be asserted, regardless of whether CLRx was
asserted before the write.
10.5.2.6
INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR220_221)
Address Base + 0x0040
R
Access: User read/write
0
1
2
3
4
5
0
0
0
0
0
0
0
0
0
0
0
R
16
17
18
19
20
21
22
0
0
0
0
0
0
0
0
8
9
10
11
0
0
0
0
0
0
0
0
0
0
0
0
0
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
PRI2
W
Reset
7
PRI0
W
Reset
6
0
0
0
0
12
13
14
15
PRI1
PRI3
0
0
0
0
Figure 80. INTC Priority Select Register 0–3 (INTC_PSR[0:3])
MPC5604E Reference Manual, Rev. 5
10-182
Freescale Semiconductor
Interrupt Controller (INTC)
Address Base + 0x011C
R
Access: User read/write
0
1
2
3
0
0
0
0
4
R
6
0
0
0
0
0
0
0
16
17
18
19
20
21
0
0
0
0
0
0
0
0
0
0
0
0
7
8
9
10
11
0
0
0
0
0
0
0
0
0
0
0
0
0
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PRI220
W
Reset
5
12
13
14
15
PRI221
W
Reset
Figure 81. INTC Priority Select Register220–221 (INTC_PSR[220:221])
Table 73. INTC_PSR0_3–INTC_PSR220–221 field descriptions
Field
Description
4–7, 12–15,
20–23, 28–31
PRI[]–
PRI220:221
Priority Select
PRIx selects the priority for interrupt requests. Refer to Section 10.6, “Functional description”.
Table 74. INTC Priority Select Register address offsets
INTC_PSRx_x
Offset Address
INTC_PSRx_x
Offset Address
INTC_PSR0_3
0x0040
INTC_PSR112_115
0x00B0
INTC_PSR4_7
0x0044
INTC_PSR116_119
0x00B4
INTC_PSR8_11
0x0048
INTC_PSR120_123
0x00B8
INTC_PSR12_15
0x004C
INTC_PSR124_127
0x00BC
INTC_PSR16_19
0x0050
INTC_PSR128_131
0x00C0
INTC_PSR20_23
0x0054
INTC_PSR132_135
0x00C4
INTC_PSR24_27
0x0058
INTC_PSR136_139
0x00C8
INTC_PSR28_31
0x005C
INTC_PSR140_143
0x00CC
INTC_PSR32_35
0x0060
INTC_PSR144_147
0x00D0
INTC_PSR36_39
0x0064
INTC_PSR148_151
0x00D4
INTC_PSR40_43
0x0068
INTC_PSR152_155
0x00D8
INTC_PSR44_47
0x006C
INTC_PSR156_159
0x00DC
INTC_PSR48_51
0x0070
INTC_PSR160_163
0x00E0
INTC_PSR52_55
0x0074
INTC_PSR164_167
0x00E4
INTC_PSR56_59
0x0078
INTC_PSR168_171
0x00E8
INTC_PSR60_63
0x007C
INTC_PSR172_175
0x00EC
INTC_PSR64_67
0x0080
INTC_PSR176_179
0x00F0
INTC_PSR68_71
0x0084
INTC_PSR180_183
0x00F4
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
10-183
Interrupt Controller (INTC)
Table 74. INTC Priority Select Register address offsets (continued)
10.6
INTC_PSRx_x
Offset Address
INTC_PSRx_x
Offset Address
INTC_PSR72_75
0x0088
INTC_PSR184_187
0x00F8
INTC_PSR76_79
0x008C
INTC_PSR188_191
0x00FC
INTC_PSR80_83
0x0090
INTC_PSR192_195
0x0100
INTC_PSR84_87
0x0094
INTC_PSR196_199
0x0104
INTC_PSR88_91
0x0098
INTC_PSR200_203
0x0108
INTC_PSR92_95
0x009C
INTC_PSR204_207
0x010C
INTC_PSR96_99
0x00A0
INTC_PSR208_211
0x0110
INTC_PSR100_103
0x00A4
INTC_PSR212_215
0x0114
INTC_PSR104_107
0x00A8
INTC_PSR216_219
0x0118
INTC_PSR108_111
0x00AC
INTC_PSR220_221
0x011C
Functional description
The functional description involves the areas of interrupt request sources, priority management, and
handshaking with the processor.
NOTE
The INTC has no spurious vector support. Therefore, if an asserted
peripheral or software settable interrupt request, whose PRIn value in
INTC_PSR0–INTC_PSR221 is higher than the PRI value in INTC_CPR,
negates before the interrupt request to the processor for that peripheral or
software settable interrupt request is acknowledged, the interrupt request to
the processor still can assert or will remain asserted for that peripheral or
software settable interrupt request. In this case, the interrupt vector will
correspond to that peripheral or software settable interrupt request. Also, the
PRI value in the INTC_CPR will be updated with the corresponding PRIn
value in INTC_PSRn. Furthermore, clearing the peripheral interrupt
request’s enable bit in the peripheral or, alternatively, setting its mask bit has
the same consequences as clearing its flag bit. Setting its enable bit or
clearing its mask bit while its flag bit is asserted has the same effect on the
INTC as an interrupt event setting the flag bit.
Table 75. Interrupt vectors
IRQ#
Offset
Size
[Bytes]
Resource
Interrupt
Module
Core Interrupts
—
0x0000
16
—
Critical Input (INTC software vector
mode) / NMI
Core
—
0x0010
16
—
Machine check / NMI
Core
MPC5604E Reference Manual, Rev. 5
10-184
Freescale Semiconductor
Interrupt Controller (INTC)
Table 75. Interrupt vectors (continued)
IRQ#
Offset
Size
[Bytes]
Resource
Interrupt
Module
—
0x0020
16
—
Data Storage
Core
—
0x0030
16
—
Instruction Storage
Core
—
0x0040
16
—
External Input
(INTC software vector mode)
Core
—
0x0050
16
—
Alignment
Core
—
0x0060
16
—
Program
Core
—
0x0070
16
—
Reserved
Core
—
0x0080
16
—
System call
Core
—
0x0090
96
—
Unused
Core
—
0x00F0
16
—
Debug
Core
—
0x0100
1792
—
Unused
Core
On-Platform Peripheral Interrupts
0
0x0800
4
—
Software setable flag 0
Software
1
0x0804
4
—
Software setable flag 1
Software
2
0x0808
4
—
Software setable flag 2
Software
3
0x080C
4
—
Software setable flag 3
Software
4
0x0810
4
—
Software setable flag 4
Software
5
0x0814
4
—
Software setable flag 5
Software
6
0x0818
4
—
Software setable flag 6
Software
7
0x081C
4
—
Software setable flag 7
Software
8
0x0820
4
9
0x0824
4
—
Platform Flash Bank 0 Abort |
Platform Flash Bank 0 Stall |
Platform Flash Bank 1 Abort |
Platform Flash Bank 1 Stall |
Platform Flash Bank 2 Abort |
Platform Flash Bank 2 Stall |
Platform Flash Bank 3 Abort |
Platform Flash Bank 3 Stall
MCM
10
0x0828
4
—
Combined Error
DMA2x
11
0x082C
4
—
Channel 0
DMA2x
12
0x0830
4
—
Channel 1
DMA2x
13
0x0834
4
—
Channel 2
DMA2x
14
0x0838
4
—
Channel 3
DMA2x
15
0x083C
4
—
Channel 4
DMA2x
Reserved
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
10-185
Interrupt Controller (INTC)
Table 75. Interrupt vectors (continued)
IRQ#
Offset
Size
[Bytes]
Resource
Interrupt
Module
16
0x0840
4
—
Channel 5
DMA2x
17
0x0844
4
—
Channel 6
DMA2x
18
0x0848
4
—
Channel 7
DMA2x
19
0x084C
4
—
Channel 8
DMA2x
20
0x0850
4
—
Channel 9
DMA2x
21
0x0854
4
—
Channel 10
DMA2x
22
0x0858
4
—
Channel 11
DMA2x
23
0x085C
4
—
Channel 12
DMA2x
24
0x0860
4
—
Channel 13
DMA2x
25
0x0864
4
—
Channel 14
DMA2x
26
0x0868
4
—
Channel 15
DMA2x
27
0x086C
4
28
0x0870
4
29
0x0874
4
30
0x0878
4
—
Match on channel 0
STM
31
0x087C
4
—
Match on channel 1
STM
32
0x0880
4
—
Match on channel 2
STM
33
0x0884
4
—
Match on channel 3
STM
34
0x0888
4
35
0x088C
4
—
ECC_DBD_PlatformFlash |
ECC_DBD_PlatformRAM
MCM
36
0x0890
4
—
ECC_SBC_PlatformFlash |
ECC_SBC_PlatformRAM
MCM
37
0x0894
4
Reserved
—
Timeout
Software Watchdog (SWT)
Reserved
Reserved
Reserved
Common module interrupts
38
0x0898
4
Reserved
39
0x089C
4
Reserved
40
0x08A0
4
Reserved
41
0x08A4
4
GROUP_0
SIU External IRQ_0
System Integration Unit Lite
(SIUL)
42
0x08A8
4
GROUP_1
SIU External IRQ_1
System Integration Unit Lite
(SIUL)
43
0x08AC
4
GROUP_2
SIU External IRQ_2
System Integration Unit Lite
(SIUL)
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Interrupt Controller (INTC)
Table 75. Interrupt vectors (continued)
IRQ#
Offset
Size
[Bytes]
Resource
Interrupt
Module
GROUP_3
SIU External IRQ_3
System Integration Unit Lite
(SIUL)
44
0x08B0
4
45
0x08B4
4
Reserved
46
0x08B8
4
Reserved
47
0x08BC
4
Reserved
48
0x08C0
4
Reserved
49
0x08C4
4
Reserved
50
0x08C8
4
Reserved
51
0x08CC
4
ME_SAFE_MODE
Safe Mode Interrupt
MC_ME
52
0x08D0
4
ME_MODE_TRANS
Mode Transition Interrupt
MC_ME
53
0x08D4
4
ME_INVALID_MODE
Invalid Mode Interrupt
MC_ME
54
0x08D8
4
ME_INVALID_CONFIG
Invalid Mode Config
MC_ME
55
0x08DC
4
56
0x08E0
4
IRQ
Functional and destructive reset
alternate event interrupt (ipi_int)
MC_RGM
57
0x08E4
4
IRQ
XOSC counter expired (ipi_int_osc)
XOSC
58
0x08E8
4
59
0x08EC
4
PIT_0
PITimer Channel 0
Periodic Interrupt Timer (PIT)
60
0x08F0
4
PIT_1
PITimer Channel 1
Periodic Interrupt Timer (PIT)
61
0x08F4
4
PIT_2
PITimer Channel 2
Periodic Interrupt Timer (PIT)
62
0x08F8
4
all
ADC_EOC
Analog to Digital Converter 0
(ADC0)
63
0x08FC
4
wdg_high
ADC_ER
Analog to Digital Converter 0
(ADC0)
64
0x0900
4
wdg_low
ADC_WD
Analog to Digital Converter 0
(ADC0)
65
0x0904
4
CAN_ERROR
FLEXCAN_ESR[ERR_INT]
FlexCan 0 (CAN0)
66
0x0908
4
CAN_WARN
FLEXCAN_ESR_BOFF |
FLEXCAN_Transmit_Warning |
FLEXCAN_Receive_Warning
FlexCan 0 (CAN0)
67
0x090C
4
CAN_WAK
FLEXCAN_ESR_WAK
FlexCan 0 (CAN0)
68
0x0910
4
CAN_03_00
FLEXCAN_BUF_00_03
FlexCan 0 (CAN0)
69
0x0914
4
CAN_07_04
FLEXCAN_BUF_04_07
FlexCan 0 (CAN0)
70
0x0918
4
CAN_11_08
FLEXCAN_BUF_08_11
FlexCan 0 (CAN0)
71
0x091C
4
CAN_15_12
FLEXCAN_BUF_12_15
FlexCan 0 (CAN0)
Reserved
Reserved
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10-187
Interrupt Controller (INTC)
Table 75. Interrupt vectors (continued)
IRQ#
Offset
Size
[Bytes]
Resource
Interrupt
Module
CAN_31_16
FLEXCAN_BUF_16_31
FlexCan 0 (CAN0)
72
0x0920
4
73
0x0924
4
74
0x0928
4
DSPI_TFUF_OF
DSPI_SR[TFUF] DSPI_SR[RFOF]
DSPI_SR[SPEF]
DSPI 0
75
0x092C
4
DSPI_EOQF
DSPI_SR[EOQF]
DSPI 0
76
0x0930
4
DSPI_TFFF
DSPI_SR[TFFF]
DSPI 0
77
0x0934
4
DSPI_TCF
DSPI_SR[TCF]
DSPI 0
78
0x0938
4
DSPI_RFDF
DSPI_SR[RFDF]
DSPI 0
79
0x093C
4
LINFLEX_INT_RX
LINFlex_RXI
LIN FLEX 0
80
0x0940
4
LINFLEX_INT_TX
LINFlex_TXI
LIN FLEX 0
81
0x0944
4
LINFLEX_ERR
LINFlex_ERR
LIN FLEX 0
82
0x0948
4
Reserved
83
0x094C
4
Reserved
84
0x0950
4
Reserved
85
0x0954
4
Reserved
86
0x0958
4
Reserved
87
0x095C
4
Reserved
88
0x0960
4
Reserved
89
0x0964
4
Reserved
90
0x0968
4
Reserved
91
0x096C
4
Reserved
92
0x0970
4
Reserved
93
0x0974
4
Reserved
94
0x0978
4
DSPI_TFUF_OF
DSPI_SR[TFUF] DSPI_SR[RFOF]
DSPI_SR[SPEF]
DSPI 1
95
0x097C
4
DSPI_EOQF
DSPI_SR[EOQF]
DSPI 1
96
0x0980
4
DSPI_TFFF
DSPI_SR[TFFF]
DSPI 1
97
0x0984
4
DSPI_TCF
DSPI_SR[TCF]
DSPI 1
98
0x0988
4
DSPI_RFDF
DSPI_SR[RFDF]
DSPI 1
99
0x098C
4
LINFLEX_INT_RX
LINFlex_RXI
LIN FLEX 1
100
0x0990
4
LINFLEX_INT_TX
LINFlex_TXI
LIN FLEX 1
101
0x0994
4
LINFLEX_ERR
LINFlex_ERR
LIN FLEX 1
102
0x0998
4
Reserved
Reserved
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Interrupt Controller (INTC)
Table 75. Interrupt vectors (continued)
Size
[Bytes]
IRQ#
Offset
Resource
Interrupt
103-
0x099C
4
Reserved
104
0x09A0
4
Reserved
105
0x09A4
4
Reserved
106
0x09A8
4
Reserved
107
0x09AC
4
Reserved
108
0x09B0
4
Reserved
109
0x09B4
4
Reserved
110
0x09B8
4
Reserved
111
0x09BC
4
Reserved
112
0x09C0
4
Reserved
113
0x09C4
4
Reserved
114
0x09C8
4
DSPI_TFUF_OF
115
0x09CC
4
DSPI_EOQF
DSPI_SR[EOQF]
DSPI 2
116
0x09D0
4
DSPI_TFFF
DSPI_SR[TFFF]
DSPI 2
117
0x09D4
4
DSPI_TCF
DSPI_SR[TCF]
DSPI 2
118
0x09D8
4
DSPI_RFDF
DSPI_SR[RFDF]
DSPI 2
119
0x09DC
4
Reserved
120
0x09E0
4
Reserved
121
0x09E4
4
Reserved
122
0x09E8
4
Reserved
123
0x09EC
4
Reserved
124
0x09F0
4
Reserved
125
0x09F4
4
—
IBIF
Inter-IC Bus Interface
Controller 0 (I2C0)
126
0x09F8
4
—
IBIF
Inter-IC bus interface controller
1 (I2C1)
127
0x09FC
4
PIT_3
PITimer Channel 3
Periodic Interrupt Timer (PIT)
128
0x0A00
4
Reserved
129
0x0A04
4
Reserved
130
0x0A08
4
Reserved
131
0x0A0C
4
Reserved
132
0x0A10
4
Reserved
DSPI_SR[TFUF]
DSPI_SR[RFOF]
DSPI_SR[SPEF]
Module
DSPI 2
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10-189
Interrupt Controller (INTC)
Table 75. Interrupt vectors (continued)
IRQ#
Offset
Size
[Bytes]
Resource
Interrupt
133
0x0A14
4
Reserved
134
0x0A18
4
Reserved
135
0x0A1C
4
Reserved
136
0x0A20
4
Reserved
137
0x0A24
4
Reserved
138
0x0A28
4
Reserved
139
0x0A2C
4
Reserved
140
0x0A30
4
Reserved
141
0x0A34
4
Reserved
142
0x0A38
4
Reserved
143
0x0A3C
4
Reserved
144
0x0A40
4
Reserved
145
0x0A44
4
Reserved
146
0x0A48
4
Reserved
147
0x0A4C
4
Reserved
148
0x0A50
4
Reserved
149
0x0A54
4
Reserved
150
0x0A58
4
Reserved
151
0x0A5C
4
Reserved
152
0x0A60
4
Reserved
153
0x0A64
4
Reserved
154
0x0A68
4
Reserved
155
0x0A6C
4
Reserved
156
0x0A70
4
Reserved
Module
MPC5604E-specific interrupts
157
0x0A74
4
tmr0
TC0IR
eTimer_0
158
0x0A78
4
tmr1
TC1IR
eTimer_0
159
0x0A7C
4
tmr2
TC2IR
eTimer_0
160
0x0A80
4
tmr3
TC3IR
eTimer_0
161
0x0A84
4
tmr4
TC4IR
eTimer_0
162
0x0A8C
4
tmr5
TC5IR
eTimer_0
163
0x0A90
4
Reserved
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Interrupt Controller (INTC)
Table 75. Interrupt vectors (continued)
IRQ#
Offset
Size
[Bytes]
164
0x0A94
4
165
0x0A98
4
166
0x0A9C
4
167
0x0AA0
4
168
0x0AA4
4
Reserved
169
0x0AA8
4
Reserved
170
0x0AAC
4
Reserved
171
0x0AB0
4
Reserved
172
0x0AB4
4
Reserved
173
0x0AB8
4
Reserved
174
0x0ABC
4
Reserved
175
0x0AC0
4
Reserved
176
0x0AC4
4
Reserved
177
0x0AC8
4
Reserved
178
0x0ACC
4
Reserved
179
0x0AD0
4
encoder
VIS (Vertical Image Start)
VidEnc_0
180
0x0AD4
4
encoder
VIE (Vertical Image End)
VidEnc_0
181
0x0AD8
4
input buffer
SCR (Sub-Channel Ready)
VidEnc_0
182
0x0ADC
4
output buffer
PDR (Package Data Ready)
VidEnc_0
183
0x0AE0
4
all
INT1
VidEnc_0
VidEnc_0
Resource
Interrupt
Module
Reserved
wdog
WTIF
eTimer_0
Reserved
rcf
RCF
eTimer_0
184
0x0AE4
4
all
ERR2
185
0x0AE8
4
all
FEC
FEC_0
186
0x0AEC
4
tx
TX
FEC_0
187
0x0AF0
4
rx
RX
FEC_0
188
0x0AF4
4
cept
TIMESTAMP
PTP
189
0x0AF8
4
ce_rtc
TIMER
CE_RTC
190
0x0AFC
4
tx_fifo
TX
SAI_0
191
0x0B00
4
rx_fifo
RX
SAI_0
192
0x0B04
4
tx_fifo
TX
SAI_1
193
0x0B08
4
rx_fifo
RX
SAI_1
194
0x0B0C
4
tx_fifo
TX
SAI_2
195
0x0B10
4
rx_fifo
RX
SAI_2
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Interrupt Controller (INTC)
Table 75. Interrupt vectors (continued)
IRQ#
Offset
Size
[Bytes]
196
0x0B14
4
Reserved
197
0x0B18
4
Reserved
198
0x0B1C
4
Reserved
199
0x0B20
4
Reserved
200
0x0B24
4
Reserved
201
0x0B28
4
Reserved
202
0x0B30
4
Reserved
203
0x0B34
4
Reserved
204
0x0B38
4
Reserved
205
0x0B3C
4
Reserved
206
0x0B40
4
Reserved
207
0x0B44
4
Reserved
208
0x0B48
4
Reserved
209
0x0B4C
4
Reserved
210
0x0B50
4
Reserved
211
0x0B54
4
Reserved
212
0x0B58
4
Reserved
213
0x0B5C
4
Reserved
214
0x0B60
4
Reserved
215
0x0B64
4
Reserved
216
0x0B68
4
Reserved
217
0x0B6C
4
Reserved
218
0x0B70
4
Reserved
219
0x0B74
4
Reserved
220
0x0B78
4
Reserved
221
0x0B7C
4
Reserved
Resource
Interrupt
Module
1
183 is INT which is a single interrupt line ORing all the interrupts that are generated by the video encoder. This is an Active
Low Line.
2 184 is the interrupt for the errors i.e Length error and count error line.
Len_err_irq(Interrupt signalling mismatch between active line length and programmed line length).
count err irq(Interrupt signalling mismatch between active image height and programmed image height)
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Interrupt Controller (INTC)
10.6.1
Interrupt request sources
The INTC has two types of interrupt requests, peripheral and software configurable. These interrupt
requests can assert on any clock cycle.
10.6.1.1
Peripheral interrupt requests
An interrupt event in a peripheral’s hardware sets a flag bit that resides in the peripheral. The interrupt
request from the peripheral is driven by that flag bit.
The time from when the peripheral starts to drive its peripheral interrupt request to the INTC to the time
that the INTC starts to drive the interrupt request to the processor is three clocks.
External interrupts are handled by the SIU (see Section 13.6.3, “External interrupts”).
10.6.1.2
Software configurable interrupt requests
An interrupt request is triggered by software by writing a ‘1’ to a SETx bit in
INTC_SSCIR0_3–INTC_SSCIR4_7. This write sets the corresponding flag bit, CLRx, resulting in the
interrupt request. The interrupt request is cleared by writing a ‘1’ to the CLRx bit.
The time from the write to the SETx bit to the time that the INTC starts to drive the interrupt request to the
processor is four clocks.
10.6.1.3
Unique vector for each interrupt request source
Each peripheral and software configurable interrupt request is assigned a hardwired unique 9-bit vector.
Software configurable interrupts 0–7 are assigned vectors 0–7 respectively. The peripheral interrupt
requests are assigned vectors 8 to as high as needed to include all the peripheral interrupt requests. The
peripheral interrupt request input ports at the boundary of the INTC block are assigned specific hardwired
vectors within the INTC (see Table 66).
10.6.2
Priority management
The asserted interrupt requests are compared to each other based on their PRIx values set in
INTC_PSR0_3–INTC_PSR292_293. The result is compared to PRI in the associated INTC_CPR. The
results of those comparisons manage the priority of the ISR executed by the associated processor. The
associated LIFO also assists in managing that priority.
10.6.2.1
Current priority and preemption
The priority arbitrator, selector, encoder, and comparator subblocks shown in Figure 73 compare the priority of the asserted interrupt requests to the current priority. If the priority of any asserted peripheral or
software configurable interrupt request is higher than the current priority for a given processor, then the
interrupt request to the processor is asserted. Also, a unique vector for the preempting peripheral or software settable interrupt request is generated for INTC interrupt acknowledge register (INTC_IACKR), and
if in hardware vector mode, for the interrupt vector provided to the processor.
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Interrupt Controller (INTC)
10.6.2.1.1
Priority arbitrator subblock
The priority arbitrator subblock for each processor compares all the priorities of all of the asserted interrupt
requests assigned to that processor, both peripheral and software configurable. The output of the priority
arbitrator subblock is the highest of those priorities assigned to a given processor. Also, any interrupt
requests that have this highest priority are output as asserted interrupt requests to the associated request
selector subblock.
10.6.2.1.2
Request selector subblock
If only one interrupt request from the associated priority arbitrator subblock is asserted, then it is passed
as asserted to the associated vector encoder subblock. If multiple interrupt requests from the associated
priority arbitrator subblock are asserted, only the one with the lowest vector passes as asserted to the
associated vector encoder subblock. The lower vector is chosen regardless of the time order of the
assertions of the peripheral or software configurable interrupt requests.
10.6.2.1.3
Vector encoder subblock
The vector encoder subblock generates the unique 9-bit vector for the asserted interrupt request from the
request selector subblock for the associated processor.
10.6.2.1.4
Priority comparator subblock
The priority comparator submodule compares the highest priority output from the priority arbitrator submodule with PRI in INTC_CPR. If the priority comparator submodule detects that this highest priority is
higher than the current priority, then it asserts the interrupt request to the processor. This interrupt request
to the processor asserts whether this highest priority is raised above the value of PRI in INTC_CPR or the
PRI value in INTC_CPR is lowered below this highest priority. This highest priority then becomes the new
priority that will be written to PRI in INTC_CPR when the interrupt request to the processor is acknowledged. Interrupt requests whose PRIn in INTC_PSRn are zero will not cause a preemption because their
PRIn will not be higher than PRI in INTC_CPR.
10.6.2.2
Last-in first-out (LIFO)
The LIFO stores the preempted PRI values from the INTC_CPR. Therefore, because these priorities are
stacked within the INTC, if interrupts need to be enabled during the ISR, at the beginning of the interrupt
exception handler the PRI value in the INTC_CPR does not need to be loaded from the INTC_CPR and
stored onto the context stack. Likewise at the end of the interrupt exception handler, the priority does not
need to be loaded from the context stack and stored into the INTC_CPR.
The PRI value in the INTC_CPR is pushed onto the LIFO when the INTC_IACKR is read in software
vector mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode.
The priority is popped into PRI in the INTC_CPR whenever the INTC_EOIR is written.
Although the INTC supports 16 priorities, an ISR executing with PRI in the INTC_CPR equal to 15 will
not be preempted. Therefore, the LIFO supports the stacking of 15 priorities. However, the LIFO is only
14 entries deep. An entry for a priority of 0 is not needed because of how pushing onto a full LIFO and
popping an empty LIFO are treated. If the LIFO is pushed 15 or more times than it is popped, the priorities
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Interrupt Controller (INTC)
first pushed are overwritten. A priority of 0 would be an overwritten priority. However, the LIFO will pop
0s if it is popped more times than it is pushed. Therefore, although a priority of 0 was overwritten, it is
regenerated with the popping of an empty LIFO.
The LIFO is not memory mapped.
10.6.3
10.6.3.1
Handshaking with processor
Software vector mode handshaking
This section describes handshaking in software vector mode.
10.6.3.1.1
Acknowledging interrupt request to processor
A timing diagram of the interrupt request and acknowledge handshaking in software vector mode and the
handshake near the end of the interrupt exception handler, is shown in Figure 82. The INTC examines the
peripheral and software configurable interrupt requests. When it finds an asserted peripheral or software
configurable interrupt request with a higher priority than PRI in the associated INTC_CPR, it asserts the
interrupt request to the processor. The INTVEC field in the associated INTC_IACKR is updated with the
preempting interrupt request’s vector when the interrupt request to the processor is asserted. The INTVEC
field retains that value until the next time the interrupt request to the processor is asserted. The rest of
handshaking process is described in Section 10.4.1.1, “Software vector mode”.
10.6.3.1.2
End of interrupt exception handler
Before the interrupt exception handling completes, INTC end-of-interrupt register (INTC_EOIR) must be
written.When written, the associated LIFO is popped so the preempted priority is restored into PRI of the
INTC_CPR. Before it is written, the peripheral or software configurable flag bit must be cleared so that
the peripheral or software configurable interrupt request is negated.
NOTE
To ensure proper operation across all eSys MCUs, execute an MBAR or
MSYNC instruction between the access to clear the flag bit and the write to
the INTC_EOIR.
When returning from the preemption, the INTC does not search for the peripheral or software settable
interrupt request whose ISR was preempted. Depending on how much the ISR progressed, that interrupt
request may no longer even be asserted. When PRI in INTC_CPR is lowered to the priority of the
preempted ISR, the interrupt request for the preempted ISR or any other asserted peripheral or software
settable interrupt request at or below that priority will not cause a preemption. Instead, after the restoration
of the preempted context, the processor will return to the instruction address that it was to next execute
before it was preempted. This next instruction is part of the preempted ISR or the interrupt exception
handler’s prolog or epilog.
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Freescale Semiconductor
10-195
Interrupt Controller (INTC)
Clock
Interrupt request to processor
Hardware vector enable
Interrupt vector
0
Interrupt acknowledge
Read INTC_IACKR
Write INTC_EOIR
INTVEC in INTC_IACKR
0
PRI in INTC_CPR
0
108
1
0
Peripheral interrupt request 100
Figure 82. Software vector mode handshaking timing diagram
10.6.3.2
Hardware vector mode handshaking
A timing diagram of the interrupt request and acknowledge handshaking in hardware vector mode, along
with the handshaking near the end of the interrupt exception handler, is shown in Figure 83. As in software
vector mode, the INTC examines the peripheral and software settable interrupt requests, and when it finds
an asserted one with a higher priority than PRI in INTC_CPR, it asserts the interrupt request to the
processor. The INTVEC field in the INTC_IACKR is updated with the preempting peripheral or software
settable interrupt request’s vector when the interrupt request to the processor is asserted. The INTVEC
field retains that value until the next time the interrupt request to the processor is asserted. In addition, the
value of the interrupt vector to the processor matches the value of the INTVEC field in the INTC_IACKR.
The rest of the handshaking is described in” Section 10.4.1.2, “Hardware vector mode”.
The handshaking near the end of the interrupt exception handler, that is the writing to the INTC_EOIR, is
the same as in software vector mode. Refer to Section 10.6.3.1.2, “End of interrupt exception handler”.
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Freescale Semiconductor
Interrupt Controller (INTC)
Clock
Interrupt request to processor
Hardware vector enable
Interrupt vector
0
108
INTVEC in INTC_IACKR
0
108
PRI in INTC_CPR
0
Interrupt acknowledge
Read INTC_IACKR
Write INTC_EOIR
1
0
Peripheral interrupt request 100
Figure 83. Hardware vector mode handshaking timing diagram
10.7
Initialization/application information
10.7.1
Initialization flow
After exiting reset, all of the PRIn fields in INTC priority select registers (INTC_PSR0–INTC_PSR211)
will be zero, and PRI in INTC current priority register (INTC_CPR) will be 15. These reset values will
prevent the INTC from asserting the interrupt request to the processor. The enable or mask bits in the
peripherals are reset such that the peripheral interrupt requests are negated. An initialization sequence for
allowing the peripheral and software settable interrupt requests to cause an interrupt request to the
processor is: interrupt_request_initialization:
interrupt_request_initialization:
configure VTES and HVEN in INTC_MCR
configure VTBA in INTC_IACKR
raise the PRIn fields in INTC_PSRn
set the enable bits or clear the mask bits for the peripheral interrupt requests
lower PRI in INTC_CPR to zero
enable processor recognition of interrupts
10.7.2
Interrupt exception handler
These example interrupt exception handlers use Power Architecture assembly code.
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Interrupt Controller (INTC)
10.7.2.1
Software vector mode
interrupt_exception_handler:
code to create stack frame, save working register, and save SRR0 and SRR1
lis
r3,INTC_IACKR@ha
# form adjusted upper half of INTC_IACKR address
lwz
r3,INTC_IACKR@l(r3)
# load INTC_IACKR, which clears request to processor
lwz
r3,0x0(r3)
# load address of ISR from vector table
wrteei 1
# enable processor recognition of interrupts
code to save rest of context required by e500 EABI
mtlr
blrl
r3
# move INTC_IACKR contents into link register
# branch to ISR; link register updated with epilog
# address
epilog:
code to restore most of context required by e500 EABI
# Popping the LIFO after the restoration of most of the context and the disabling of processor
# recognition of interrupts eases the calculation of the maximum stack depth at the cost of
# postponing the servicing of the next interrupt request.
mbar
# ensure store to clear flag bit has completed
lis
r3,INTC_EOIR@ha
# form adjusted upper half of INTC_EOIR address
li
r4,0x0
# form 0 to write to INTC_EOIR
wrteei
0
# disable processor recognition of interrupts
stw
r4,INTC_EOIR@l(r3)
# store to INTC_EOIR, informing INTC to lower priority
code to restore SRR0 and SRR1, restore working registers, and delete stack frame
rfi
vector_table_base_address:
address of ISR for interrupt
address of ISR for interrupt
.
.
.
address of ISR for interrupt
address of ISR for interrupt
with vector 0
with vector 1
with vector 510
with vector 511
ISRx:
code to service the interrupt event
code to clear flag bit that drives interrupt request to INTC
blr # return to epilog
10.7.2.2
Hardware vector mode
This interrupt exception handler is useful with processor and system bus implementations that support a
hardware vector. This example assumes that each interrupt_exception_handlerx only has space for four
instructions, and therefore a branch to interrupt_exception_handler_continuedx is needed.
interrupt_exception_handlerx:
b interrupt_exception_handler_continuedx# 4 instructions available, branch to continue
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interrupt_exception_handler_continuedx:
code to create stack frame, save working register, and save SRR0 and SRR1
wrteei
1
# enable processor recognition of interrupts
code to save rest of context required by e500 EABI
bl
ISRx
# branch to ISR for interrupt with vector x
epilog:
code to restore most of context required by e500 EABI
# Popping the LIFO after the restoration of most of the context and the disabling of processor
# recognition of interrupts eases the calculation of the maximum stack depth at the cost of
# postponing the servicing of the next interrupt request.
mbar
# ensure store to clear flag bit has completed
lis
r3,INTC_EOIR@ha
# form adjusted upper half of INTC_EOIR address
li
r4,0x0
# form 0 to write to INTC_EOIR
wrteei
0
# disable processor recognition of interrupts
stw
r4,INTC_EOIR@l(r3) # store to INTC_EOIR, informing INTC to lower priority
code to restore SRR0 and SRR1, restore working registers, and delete stack frame
rfi
ISRx:
code to service the interrupt event
code to clear flag bit that drives interrupt request to INTC
blr
# branch to epilog
10.7.3
ISR, RTOS, and task hierarchy
The RTOS and all of the tasks under its control typically execute with PRI in INTC current priority register
(INTC_CPR) having a value of 0. The RTOS will execute the tasks according to whatever priority scheme
that it may have, but that priority scheme is independent and has a lower priority of execution than the
priority scheme of the INTC. In other words, the ISRs execute above INTC_CPR priority 0 and outside
the control of the RTOS, the RTOS executes at INTC_CPR priority 0, and while the tasks execute at
different priorities under the control of the RTOS, they also execute at INTC_CPR priority 0.
If a task shares a resource with an ISR and the PCP is being used to manage that shared resource, then the
task’s priority can be elevated in the INTC_CPR while the shared resource is being accessed.
An ISR whose PRIn in INTC priority select registers (INTC_PSR0–INTC_PSR211) has a value of 0 will
not cause an interrupt request to the processor, even if its peripheral or software settable interrupt request
is asserted. For a peripheral interrupt request, not setting its enable bit or disabling the mask bit will cause
it to remain negated, which consequently also will not cause an interrupt request to the processor. Since
the ISRs are outside the control of the RTOS, this ISR will not run unless called by another ISR or the
interrupt exception handler, perhaps after executing another ISR.
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10.7.4
Order of execution
An ISR with a higher priority can preempt an ISR with a lower priority, regardless of the unique vectors
associated with each of their peripheral or software configurable interrupt requests. However, if multiple
peripheral or software configurable interrupt requests are asserted, more than one has the highest priority,
and that priority is high enough to cause preemption, the INTC selects the one with the lowest unique
vector regardless of the order in time that they asserted. However, the ability to meet deadlines with this
scheduling scheme is no less than if the ISRs execute in the time order that their peripheral or software
configurable interrupt requests asserted.
The example in Table 76 shows the order of execution of both ISRs with different priorities and the same
priority
Table 76. Order of ISR execution example
Code Executing at End of Step
Step
#
Step Description
RTO
S
ISR108
1
ISR20
8
ISR30
8
PRI in
INTC_CPR
Interrupt
ISR40
at End of
Exception
8
Step
Handler
1
RTOS at priority 0 is executing.
X
0
2
Peripheral interrupt request 100 at
priority 1 asserts. Interrupt taken.
3
Peripheral interrupt request 400 at
priority 4 is asserts. Interrupt taken.
X
4
4
Peripheral interrupt request 300 at
priority 3 is asserts.
X
4
5
Peripheral interrupt request 200 at
priority 3 is asserts.
X
4
6
ISR408 completes. Interrupt
exception handler writes to
INTC_EOIR.
7
Interrupt taken. ISR208 starts to
execute, even though peripheral
interrupt request 300 asserted first.
8
ISR208 completes. Interrupt
exception handler writes to
INTC_EOIR.
9
Interrupt taken. ISR308 starts to
execute.
10
ISR308 completes. Interrupt
exception handler writes to
INTC_EOIR.
X
1
11
ISR108 completes. Interrupt
exception handler writes to
INTC_EOIR.
X
0
12
RTOS continues execution.
X
1
X
X
1
3
X
X
X
1
3
0
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1
ISR108 executes for peripheral interrupt request 100 because the first eight ISRs are for software configurable
interrupt requests.
10.7.5
10.7.5.1
Priority ceiling protocol
Elevating priority
The PRI field in INTC_CPR is elevated in the OSEK PCP to the ceiling of all of the priorities of the ISRs
that share a resource. This protocol allows coherent accesses of the ISRs to that shared resource.
For example, ISR1 has a priority of 1, ISR2 has a priority of 2, and ISR3 has a priority of 3. They share
the same resource. Before ISR1 or ISR2 can access that resource, they must raise the PRI value in
INTC_CPR to 3, the ceiling of all of the ISR priorities. After they release the resource, the PRI value in
INTC_CPR can be lowered. If they do not raise their priority, ISR2 can preempt ISR1, and ISR3 can
preempt ISR1 or ISR2, possibly corrupting the shared resource. Another possible failure mechanism is
deadlock if the higher priority ISR needs the lower priority ISR to release the resource before it can
continue, but the lower priority ISR cannot release the resource until the higher priority ISR completes and
execution returns to the lower priority ISR.
Using the PCP instead of disabling processor recognition of all interrupts eliminates the time when
accessing a shared resource that all higher priority interrupts are blocked. For example, while ISR3 cannot
preempt ISR1 while it is accessing the shared resource, all of the ISRs with a priority higher than 3 can
preempt ISR1.
10.7.5.2
Ensuring coherency
A scenario can cause non-coherent accesses to the shared resource. For example, ISR1 and ISR2 are both
running on the same core and both share a resource. ISR1 has a lower priority than ISR2. ISR1 is executing
and writes to the INTC_CPR. The instruction following this store is a store to a value in a shared coherent
data block. Either immediately before or at the same time as the first store, the INTC asserts the interrupt
request to the processor because the peripheral interrupt request for ISR2 has asserted. As the processor is
responding to the interrupt request from the INTC, and as it is aborting transactions and flushing its
pipeline, it is possible that both stores will be executed. ISR2 thereby thinks that it can access the data
block coherently, but the data block has been corrupted.
OSEK uses the GetResource and ReleaseResource system services to manage access to a shared resource.
To prevent corruption of a coherent data block, modifications to PRI in INTC_CPR can be made by those
system services with the code sequence:
disable processor recognition of interrupts
PRI modification
enable processor recognition of interrupts
10.7.6
Selecting priorities according to request rates and deadlines
The selection of the priorities for the ISRs can be made using rate monotonic scheduling (RMS) or a
superset of it, deadline monotonic scheduling (DMS). In RMS, the ISRs that have higher request rates have
higher priorities. In DMS, if the deadline is before the next time the ISR is requested, then the ISR is
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assigned a priority according to the time from the request for the ISR to the deadline, not from the time of
the request for the ISR to the next request for it.
For example, ISR1 executes every 100 µs, ISR2 executes every 200 µs, and ISR3 executes every 300 µs.
ISR1 has a higher priority than ISR2, which has a higher priority than ISR3; however, if ISR3 has a
deadline of 150 µs, then it has a higher priority than ISR2.
The INTC has 16 priorities, which may be less than the number of ISRs. In this case, the ISRs should be
grouped with other ISRs that have similar deadlines. For example, a priority could be allocated for every
time the request rate doubles. ISRs with request rates around 1 ms would share a priority, ISRs with request
rates around 500 µs would share a priority, ISRs with request rates around 250 µs would share a priority,
etc. With this approach, a range of ISR request rates of 216 could be included, regardless of the number of
ISRs.
Reducing the number of priorities reduces the processor’s ability to meet its deadlines. However, reducing
the number of priorities can reduce the size and latency through the interrupt controller. It also allows
easier management of ISRs with similar deadlines that share a resource. They do not need to use the PCP
to access the shared resource.
10.7.7
Software configurable interrupt requests
The software configurable interrupt requests can be used in two ways. They can be used to schedule a
lower priority portion of an ISR and they may also be used by processors to interrupt other processors in
a multiple processor system.
10.7.7.1
Scheduling a lower priority portion of an ISR
A portion of an ISR needs to be executed at the PRIx value in INTC_PSR0_3–INTC_PSR292_293, which
becomes the PRI value in INTC_CPR with the interrupt acknowledge. The ISR, however, can have a
portion that does not need to be executed at this higher priority. Therefore, executing the later portion that
does not need to be executed at this higher priority can prevent the execution of ISRs that do not have a
higher priority than the earlier portion of the ISR but do have a higher priority than what the later portion
of the ISR needs. This preemptive scheduling inefficiency reduces the processor’s ability to meet its
deadlines.
One option is for the ISR to complete the earlier higher priority portion, but then schedule through the
RTOS a task to execute the later lower priority portion. However, some RTOSs can require a large amount
of time for an ISR to schedule a task. Therefore, a second option is for the ISR, after completing the higher
priority portion, to set a SETx bit in INTC_SSCIR0_3–INTC_SSCIR4_7. Writing a ‘1’ to SETx causes a
software configurable interrupt request. This software configurable interrupt request will usually have a
lower PRIx value in the INTC_PSRx_x and will not cause preemptive scheduling inefficiencies. After
generating a software settable interrupt request, the higher priority ISR completes. The lower priority ISR
is scheduled according to its priority. Execution of the higher priority ISR is not resumed after the
completion of the lower priority ISR.
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10.7.7.2
Scheduling an ISR on another processor
Because the SETx bits in the INTC_SSCIRx_x are memory mapped, processors in multiple-processor
systems can schedule ISRs on the other processors. One application is that one processor wants to
command another processor to perform a piece of work and the initiating processor does not need to use
the results of that work. If the initiating processor is concerned that the processor executing the software
configurable ISR has not completed the work before asking it to again execute the ISR, it can check if the
corresponding CLRx bit in INTC_SSCIRx_x is asserted before again writing a ‘1’ to the SETx bit.
Another application is the sharing of a block of data. For example, a first processor has completed
accessing a block of data and wants a second processor to then access it. Furthermore, after the second
processor has completed accessing the block of data, the first processor again wants to access it. The
accesses to the block of data must be done coherently. To do this, the first processor writes a ‘1’ to a SETx
bit on the second processor. After accessing the block of data, the second processor clears the
corresponding CLRx bit and then writes 1 to a SETx bit on the first processor, informing it that it can now
access the block of data.
10.7.8
Lowering priority within an ISR
A common method for avoiding preemptive scheduling inefficiencies with an ISR whose work spans
multiple priorities (see Section 10.7.7.1, “Scheduling a lower priority portion of an ISR”) is to lower the
current priority. However, the INTC has a LIFO whose depth is determined by the number of priorities.
NOTE
Lowering the PRI value in INTC_CPR within an ISR to below the ISR’s
corresponding PRI value in INTC_PSR0_3–INTC_PSR292_293 allows
more preemptions than the LIFO depth can support.
Therefore, the INTC does not support lowering the current priority within an ISR as a way to avoid
preemptive scheduling inefficiencies.
10.7.9
10.7.9.1
Negating an interrupt request outside of its ISR
Negating an interrupt request as a side effect of an ISR
Some peripherals have flag bits that can be cleared as a side effect of servicing a peripheral interrupt
request. For example, reading a specific register can clear the flag bits and their corresponding interrupt
requests. This clearing as a side effect of servicing a peripheral interrupt request can cause the negation of
other peripheral interrupt requests besides the peripheral interrupt request whose ISR presently is
executing. This negating of a peripheral interrupt request outside of its ISR can be a desired effect.
10.7.9.2
Negating multiple interrupt requests in one ISR
An ISR can clear other flag bits besides its own. One reason that an ISR clears multiple flag bits is because
it serviced those flag bits, and therefore the ISRs for these flag bits do not need to be executed.
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10.7.9.3
Proper setting of interrupt request priority
Whether an interrupt request negates outside its own ISR due to the side effect of an ISR execution or the
intentional clearing a flag bit, the priorities of the peripheral or software configurable interrupt requests for
these other flag bits must be selected properly. Their PRIx values in INTC_PSR0_3–INTC_PSR292_293
must be selected to be at or lower than the priority of the ISR that cleared their flag bits. Otherwise, those
flag bits can cause the interrupt request to the processor to assert. Furthermore, the clearing of these other
flag bits also has the same timing relationship to the writing to INTC_SSCIR0_3–INTC_SSCIR4_7 as the
clearing of the flag bit that caused the present ISR to be executed (see Section 10.6.3.1.2, “End of interrupt
exception handler”).
A flag bit whose enable bit or mask bit negates its peripheral interrupt request can be cleared at any time,
regardless of the peripheral interrupt request’s PRIx value in INTC_PSRx_x.
10.7.10 Examining LIFO contents
In normal mode, the user does not need to know the contents of the LIFO. He may not even know how
deeply the LIFO is nested. However, if he wants to read the contents, such as in debug mode, they are not
memory mapped. The contents can be read by popping the LIFO and reading the PRI field in either
INTC_CPR. The code sequence is:
pop_lifo:
store to INTC_EOIR
load INTC_CPR, examine PRI, and store onto stack
if PRI is not zero or value when interrupts were enabled, branch to pop_lifo
When the examination is complete, the LIFO can be restored using this code sequence:
push_lifo:
load stacked PRI value and store to INTC_CPR
load INTC_IACKR
if stacked PRI values are not depleted, branch to push_lifo
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Chapter 11
Wakeup Unit (WKPU)
11.1
Introduction
11.1.1
Overview
The WKPU supports one external source that can cause non-maskable interrupt requests or wakeup events.
Figure 84 is a block diagram of the WKPU and its interfaces to other system components.
Wakeup Unit
Machine Check Request
NMI / Wakeup
- Configuration
Critical Interrupt
PLATFORM
Non-Maskable Interrupt
NMI enable
filter bypass
PBRIDGE
wakeup
NMI
filter
PADS
IOMUX
Mode /
Power Ctl
IPS
BUS
Figure 84. WKPU block diagram
11.1.2
Features
The WKPU supports:
• 1 NMI source
• 1 analog glitch filter
• Independent interrupt destination: non-maskable interrupt, critical interrupt, or machine check
request
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Wakeup Unit (WKPU)
•
•
Edge detection
Configurable system wakeup triggering from NMI sources
11.2
External signal description
The module has 1 signal input that can be used as a non-maskable interrupt source in normal run mode or
as system wakeup sources in certain power down modes.
11.3
Memory map and register description
This section provides a detailed description of all registers accessible in the WKPU module.
11.3.1
Memory map
Figure 77 gives an overview on the WKPU registers implemented.
Table 77. WKPU memory map
Address Offset
Use
Abbreviation
Size
Supported
Access Sizes
0x0000
NMI Status Flag Register
NSR
32
32/16/8
0x0004 - 0x0007
Reserved
0x0008
NMI Configuration Register
NCR
32
32/16/8
0x000C - 0x3FFF
Reserved
NOTE
Reserved registers will read as 0, writes will have no effect. If supported and
enabled by the SoC, a transfer error will be issued when trying to access
completely reserved register space.
11.3.2
Register descriptions
This section describes in address order all the WKPU registers. Each description includes a standard
register diagram with an associated figure number. Details of register bit and field function follow the
register diagrams, in bit order.
Figure 85. Key to Register Fields
Always
reads 1
11.3.2.1
1
Always
reads 0
0
R/W BIT Read- BIT WriteWrite 1 BIT Self-clear 0
bit
only bit
only bit BIT to clear w1c
bit BIT
N/A
NMI Status Flag Register (NSR)
This register holds the non-maskable interrupt status flags.
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Address 0x0000
:
Access: User read/write (write 1 to clear)
0
1
2
3
4
5
6
7
R
NIF0
NOVF0
0
0
0
0
0
0
W
w1c
w1c
0
0
0
0
0
0
0
0
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
R
W
Reset
R
W
Reset
R
W
Reset
Figure 86. NMI Status Flag Register (NSR)
Table 78. NSR Field Descriptions
Field
Description
NIF0
NMI Status Flag 0. This flag can be cleared only by writing a 1. Writing a 0 has no effect. If enabled
(NREE0 or NFEE0 set), NIF0 causes an interrupt request.
1 An event as defined by NREE0 and NFEE0 has occurred
0 No event has occurred on the pad
NOVF0
NMI Overrun Status Flag 0. This flag can be cleared only by writing a 1. Writing a 0 has no effect. It
will be a copy of the current NIF0 value whenever a NMI event occurs, thereby indicating to the
software that a NMI occurred while the last one was not yet serviced. If enabled (NREE0 or NFEE0
set), NOVF0 causes an interrupt request.
1 An overrun has occurred on NMI input 0
0 No overrun has occurred on NMI input 0
11.3.2.2
NMI Configuration Register (NCR)
This register holds the configuration bits for the non-maskable interrupt settings.
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Address: 0x0008
0
Access: User read/write
1
2
3
4
R
5
6
7
NREE0
NFEE0
NFE0
0
NLOCK0
NDSS0
NWRE0
W
Reset
R
0
0
0
0
0
0
0
0
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
R
W
Reset
Figure 87. NMI Configuration Register (NCR)
Table 79. NCR Field Descriptions
Field
Description
NLOCK0
NMI Configuration Lock Register 0. Writing a 1 to this bit locks the configuration for the NMI until it is
unlocked by a system reset. Writing a 0 has no effect.
NDSS0
NMI Destination Source Select 0.
00 non-maskable interrupt
01 critical interrupt
10 machine check request
11 reserved - no NMI, critical interrupt, or machine check request generated
NWRE0
NMI Wakeup Request Enable 0.
1 A set NIF0 bit or set NOVF0 bit causes a system wakeup request
0 System wakeup requests from the corresponding NIF0 bit are disabled
NREE0
NMI Rising-edge Events Enable 0.
1 Rising-edge event is enabled
0 Rising-edge event is disabled
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Table 79. NCR Field Descriptions (continued)
Field
NFEE0
NFE0
Description
NMI Falling-edge Events Enable 0.
1 Falling-edge event is enabled
0 Falling-edge event is disabled
NMI Filter Enable 0.
Enable analog glitch filter on the NMI pad input.
1 Filter is enabled
0 Filter is disabled
NOTE
Writing a ‘0’ to both NREE0 and NFEE0 disables the NMI functionality
completely (i.e. no system wakeup or interrupt will be generated on any pad
activity)!
11.4
11.4.1
Functional description
General
This section provides a complete functional description of the WKPU.
11.4.2
Non-Maskable Interrupts
The WKPU supports one non-maskable interrupt.
The WKPU supports the generation of 3 types of interrupts per NMI input to the SoC. The WKPU supports
the capturing of a second event per NMI input before the interrupt is cleared, thus reducing the chance of
losing an NMI event.
Each NMI passes through a bypassable analog glitch filter.
NOTE
Glitch filter control and pad configuration should be done while the NMI is
disabled in order to avoid erroneous triggering by glitches caused by the
configuration process itself.
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Wakeup Unit (WKPU)
Mode/
Pwr Ctl
machine check
critical IRQ
NMI
CPU
Destination
Wakeup Enable
Flag
Overrun
Edge Detect
NFE[0]
NFEE[0]
NREE[0]
NWRE[0]
NDSS[0]
Glitch Filter
NMI Configuration Register (NCR)
Figure 88. NMI pad diagram
11.4.2.1
NMI management
Each NMI can be enabled or disabled independently. This can be performed using the single NCR register
laid out to contain all configuration bits for a given NMI in a single byte (see Figure 87). A pad defined as
an NMI can be configured by the user to recognize interrupts with an active rising edge, an active falling
edge or both edges being active. A setting of having both edge events disabled results in no interrupt being
detected and should not be configured.
The active NMI edge is controlled by the user through the configuration of the NREE and NFEE bits.
NOTE
After reset, NREE and NFEE are set to ‘0’, therefore the NMI functionality
is disabled after reset and must be enabled explicitly by software.
Once a pad’s NMI functionality has been enabled, the pad cannot be reconfigured in the IOMUX to
override or disable the NMI.
The NMI destination interrupt is controlled by the user through the configuration of the NDSS bits. See
Table 79 for details.
Each NMI supports a status flag and an overrun flag which are located in the NSR register (see Figure 86).
This register is a clear-by-write-1 register type, preventing inadvertent overwriting of other flags in the
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same register. The status flag is set whenever an NMI event is detected. The overrun flag is set whenever
an NMI event is detected and the status flag is set (i.e. has not yet been cleared).
NOTE
The overrun flag is cleared by writing a ‘1’ to the appropriate overrun bit in
the NSR register. If the status bit is cleared and the overrun bit is still set, the
pending interrupt will not be cleared.
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Chapter 12
System Status and Configuration Module (SSCM)
12.1
12.1.1
Introduction
Overview
The System Status and Configuration Module (SSCM) provides central SOC functionality.
System Status and Configuration Module
RevID
Hardmacro
Core
Logic
Debug
Port
Bus
Interface
Peripheral
Bus
Interface
System
Status
Password
Comparator
Figure 89. System Status and Configuration Module Block Diagram
12.1.2
Features
The SSCM includes these distinctive features:
• System Configuration and Status
— Memory sizes/status
— Device Mode and Security Status
— Determine boot vector
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System Status and Configuration Module (SSCM)
•
•
•
— Search Code Flash for bootable sector
— DMA Status
Device identification information (MCU ID Registers)
Debug Status Port enable and selection
Bus and peripheral abort enable/disable
12.1.3
Modes of Operation
The SSCM operates identically in all system modes.
12.2
External Signal Description
The SSCM has no external pins.
12.3
Memory Map/Register Definition
This section provides a detailed description of all memory-mapped registers in the SSCM.
Table 80 shows the memory map for the SSCM. Note that all addresses are offsets; the absolute address
may be calculated by adding the specified offset to the base address of the SSCM.
Table 80. Module Memory Map
1
Address
Register
Size
Access
Mode1
Base + 0x0000
System Status (STATUS)
16 bits
R
A
Base + 0x0002
System Memory and ID (MEMCONFIG)
16 bits
R
A
Base + 0x0004
Reserved
16 bits
Reads/Writes have no effect.
A
Base + 0x0006
Error Configuration (ERROR)
16 bits
R/W
A
Base + 0x0008
Debug Status Port (DEBUGPORT)
16 bits
R/W
A
Base + 0x000A
Reserved
16 bits
Reads/Writes have no effect.
A
Base + 0x0014
to
Base + 0x001C
Reserved
32 bits
Reads/Writes have no effect.
A
Base + 0x0028
Primary Boot Address
32 bits
R
A
Base + 0x002C
Reserved
32 bits
Reads/Writes have no effect.
A
U = User Mode, S = Supervisor Mode, T = Test Mode, V = DFV Mode, A = All (No restrictions)
All registers are accessible via 8-bit, 16-bit or 32-bit accesses. However, 16-bit accesses must be aligned
to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example, the
STATUS register is accessible by a 16-bit READ/WRITE to address ’Base + 0x0002’, but performing a
16-bit access to ’Base + 0x0003’ is illegal.
12.3.1
Register Descriptions
The following registers are available in the SSCM. Those bits that are shaded out are reserved for future
use. To optimize future compatibility, these bits should be masked out during any read/write operations to
avoid conflict with future revisions.
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System Status and Configuration Module (SSCM)
12.3.1.1
System Status Register
The System Status register is a read-only register that reflects the current state of the system.
Address: Base + 0x0000
R
Access: Read / Write
0
1
2
3
0
0
0
0
4
5
NXEN PUB
6
7
SEC
0
8
9
10
BMODE
11
12
13
14
15
0
ABD
0
0
0
W
RESET:
1
= Reserved
Figure 90. Status (STATUS) Register
1
Reset values for this register depend on the associated option bits, or on the device status after leaving reset.
Table 81. STATUS Allowed Register Accesses
1
8-bit
16-bit
32-bit1
READ
Allowed
Allowed
Allowed
WRITE
Allowed
Allowed
Allowed
All 32-bit accesses must be aligned to 32-bit addresses (i.e. 0x0, 0x4, 0x8 or 0xC).
Table 82. STATUS Field Descriptions
Field
NXEN
Description
Nexus enabled.
PUB
Public Serial Access Status. This bit indicates whether serial boot mode with public password is allowed.
1 Serial boot mode with public password is allowed
0 Serial boot mode with private Flash password is allowed, provided the key hasn’t been swallowed
SEC
Security Status. This bit reflects the current security state of the Flash.
1 The Flash is secured
0 The Flash is not secured
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System Status and Configuration Module (SSCM)
Table 82. STATUS Field Descriptions (continued)
Field
Description
BMODE Device Boot Mode.
000 (reserved for FlexRay Boot Serial Boot Loader)
001 CAN Serial Boot Loader
010 SCI Serial Boot Loader
011 Single Chip
100 Expanded Chip
This field is only updated during reset. If the device goes into standby mode and wakes up from it again, the bits
retain their original value.
ABD
Autobaud. Indicates that autobaud detection is active when in SCI or CAN serial boot loader mode. No meaning in
other modes.
12.3.1.2
System Memory and ID Register
The System Memory Configuration register is a read-only register that reflects the memory configuration
of the system. It also contains the JTAG ID.
Address Base + 0x0002
R
0
1
Access: Read Only
2
3
4
R
5
6
7
8
9
JPIN
10
11
IVLD
12
13
14
MREV
15
DVLD
W
RESET:
1
1
0
0
1
0
0
0
0
0
1
0
0
0
0
1
= Reserved
Figure 91. System Memory and ID (MEMCONFIG) Register
Table 83. MEMCONFIG Field Descriptions
Field
Description
JPIN
JTAG Part ID Number
IVLD
Instruction Flash Valid. This bit identifies whether or not the on-chip Instruction Flash is accessible in the system
memory map. The Flash may not be accessible due to security limitations, or because there is no Flash in the
system.
1 Instruction Flash is accessible
0 Instruction Flash is not accessible
MREV
Minor Mask Revision
DVLD
Data Flash Valid. This bit identifies whether or not the on-chip Data Flash is visible in the system memory map. The
Flash may not be accessible due to security limitations, or because there is no Flash in the system.
1 Data Flash is visible
0 Data Flash is not visible
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System Status and Configuration Module (SSCM)
Table 84. MEMCONFIG Allowed Register Accesses
8-bit
16-bit
32-bit
READ
Allowed
Allowed
Allowed
(also reads STATUS register)
WRITE
Not Allowed
Not Allowed
Not Allowed
12.3.1.3
Error Configuration
The Error Configuration register is a read-write register that controls the error handling of the system.
Address : Base + 0x0006
R
Access: Read/Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PAE
RAE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
RESET:
= Reserved
Figure 92. Error Configuration (ERROR) Register
Table 85. ERROR Field Descriptions
Field
Description
PAE
Peripheral Bus Abort Enable. This bit enables bus aborts on any access to a peripheral slot that is not used on the
device. This feature is intended to aid in debugging when developing application code.
1 Illegal accesses to non-existing peripherals produce a Prefetch or Data Abort exception
0 Illegal accesses to non-existing peripherals do not produce a Prefetch or Data Abort exception
RAE
Register Bus Abort Enable. This bit enables bus aborts on illegal accesses to off-platform peripherals. Illegal
accesses are defined as reads or writes to reserved addresses within the address space for a particular peripheral.
This feature is intended to aid in debugging when developing application code.
1 Illegal accesses to peripherals produce a Prefetch or Data Abort exception
0 Illegal accesses to peripherals do not produce a Prefetch or Data Abort exception
Note: Transfers to Peripheral Bus resources may be aborted even before they reach the Peripheral Bus (i.e. at the
AIPS level). In this case, the PER_ABORT and REG_ABORT register bits will have no effect on the abort.
Table 86. ERROR Allowed Register Accesses
8-bit
16-bit
32-bit
READ
Allowed
Allowed
Allowed
WRITE
Allowed
Allowed
Not Allowed
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System Status and Configuration Module (SSCM)
12.3.1.4
Debug Status Port Register
The Debug Status Port register is used to (optionally) provide debug data on a set of pins. Consult the SOC
guide for this information.
Address: Base + 0x0008
R
Access: Read/Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
DEBUG_MODE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
RESET:
0
0
= Reserved for future use
Figure 93. Debug Status Port (DEBUGPORT) Register
Table 87. DEBUGPORT Field Descriptions
Field
Description
DEBUG_ Debug Status Port Mode. This field selects the alternate debug functionality for the Debug Status Port
MODE 000 undefined
001 Mode 1 Selected
010 Mode 2 Selected
011 Mode 3 Selected
100 Mode 4 Selected
101 Mode 5 Selected
110 Mode 6 Selected
111 Mode 7 Selected
Table 88 describes the functionality of the Debug Status Port in each mode.
Table 88. Debug Status Port Modes
Pin1
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
0
STATUS[0]
STATUS[8]
MEMCONFIG[0]
MEMCONFIG[8]
Reserved
Reserved
Reserved
1
STATUS[1]
STATUS[9]
MEMCONFIG[1]
MEMCONFIG[9]
Reserved
Reserved
Reserved
2
STATUS[2]
STATUS[10
]
MEMCONFIG[2]
MEMCONFIG[10]
Reserved
Reserved
Reserved
3
STATUS[3]
STATUS[11]
MEMCONFIG[3]
MEMCONFIG[11]
Reserved
Reserved
Reserved
4
STATUS[4]
STATUS[12
]
MEMCONFIG[4]
MEMCONFIG[12]
Reserved
Reserved
Reserved
5
STATUS[5]
STATUS[13
]
MEMCONFIG[5]
MEMCONFIG[13]
Reserved
Reserved
Reserved
6
STATUS[6]
STATUS[14
]
MEMCONFIG[6]
MEMCONFIG[14]
Reserved
Reserved
Reserved
7
STATUS[7]
STATUS[15
]
MEMCONFIG[7]
MEMCONFIG[15]
Reserved
Reserved
Reserved
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System Status and Configuration Module (SSCM)
1
All signals are active high, unless otherwise noted
Table 89. DEBUGPORT Allowed Register Accesses
1
8-bit
16-bit
32-bit1
READ
Allowed
Allowed
Not Allowed
WRITE
Allowed
Allowed
Not Allowed
All 32-bit accesses must be aligned to 32-bit addresses (i.e. 0x0, 0x4, 0x8 or 0xC).
Table 90. Debug Status Port Signals
Debug Status Port
Signals
sscm__ipg_debug_soc__wire
DS6
platform__zcor_pstat__wire[6:0]
video_wrap__valid_frame__wire
video_wrap__sub_start__wire
video_wrap__seq_luma__wire
video_wrap__seq_chroma__wire dflash0__f90_done__wire
DS7
cflash0__f90_done__wire
vreg_dig0__vreg_ok__wire
fmpll0__i_lock__wire
fmpll0__i_lock__wire
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System Status and Configuration Module (SSCM)
12.3.1.5
Primary Boot Address
Address: Base + 0x28
0
1
Access: Read/Write
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
SADR
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
SADR
W
RESET:
0
0
0
0
0
0
0
0
0
= Writes have no effect on this bit
Figure 94.
Table 91. PSA Field Descriptions
Field
SADR
12.4
Description
Start Address - the boot processor will start executing application code from this address
Functional Description
The primary purpose of the SSCM is to provide information about the current state and configuration of
the system that may be useful for configuring application software and for debug of the system.
12.5
12.5.1
Initialization/Application Information
Reset
The reset state of each individual bit is shown within the Register Description section (see Section 12.3.1,
“Register Descriptions”).
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Chapter 13
System Integration Unit Lite (SIUL)
13.1
Introduction
This chapter describes the System Integration Unit Lite (SIUL), which is used for the management of the
pads and their configuration. It controls the multiplexing of the alternate functions used on all pads as well
as being responsible for the management of the external interrupts to the device.
13.2
Overview
The System Integration Unit Lite (SIUL) controls the MCU pad configuration, ports, general-purpose
input and output (GPIO) signals and external interrupts with trigger event configuration. Figure 95
provides a block diagram of the SIUL and its interfaces to other system components.
The module provides dedicated general-purpose pads that can be configured as either inputs or outputs.
• When a pad is configured as an input, the state of the pad (logic high or low) is obtained by reading
an associated data input register.
• When a pad is configured as an output, the value driven onto the pad is determined by writing to
an associated data output register. Enabling the input buffers when a pad is configured as an output
allows the actual state of the pad to be read.
• To enable monitoring of an output pad value, the pad can be configured as both output and input
so the actual pad value can be read back and compared with the expected value.Rev. 5
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System Integration Unit Lite (SIUL)
SIUL Module
Pad Config (IOMUXC)
71
Pad Cfg (PCRs)
GPIO Functionality
71
Data
71
Pad Input
IO
MUX
7‘1
PADS
IPS
Master
Interrupt Functionality
32
Interrupt
- Configuration
- Glitch Filter
4
Interrupt
Controller
IPS
BUS
Figure 95. System Integration Unit Lite block diagram
13.3
Features
The System Integration Unit Lite supports these distinctive features:
The System Integration Unit Lite provides these features:
• GPIO
— GPIO function on up to 71 I/O pins
— Dedicated input and output registers for each GPIO pin
• External interrupts
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System Integration Unit Lite (SIUL)
— 4 system interrupt vectors for up to 32 interrupt sources
— 32 programmable digital glitch filters
— Independent interrupt mask
— Edge detection
System configuration
— Pad configuration control
•
13.4
External signal description
Most device pads support multiple device functions. Pad configuration registers are provided to enable
selection between GPIO and other signals. These other signals, also referred to as alternate functions, are
typically peripheral functions.
GPIO pads are grouped in “ports”, with each port containing up to 16 pads. With appropriate
configuration, all pins in a port can be read or written to in parallel with a single R/W access.
Table 92 lists the external pins used by the SIUL.
(
Table 92. SIUL signal properties
GPIO[0:198]
category
Name
System configuration
GPIO[0:70]
External interrupt
A0, A1, A2, A3, A4, A5, A6,
A7, A8, A9, A10, A12, A13,
A14, A15, B3, C1, C2, C3,
C4, C5, C6, C8, C9, C10,
C12, C13, C14, D9, D13,
D14, and E2
13.4.1
I/O
direction
I/O
Input
Function
General-purpose input/output
Pins with External Interrupt Request
functionality. Please refer to the signal
description chapter of this reference manual
for details.
Detailed signal descriptions
13.4.1.1
General-purpose I/O pins (GPIO[0:70])
The GPIO pins provide general-purpose input and output function. The GPIO pins are generally
multiplexed with other I/O pin functions. Each GPIO input and output is separately controlled by an input
(GPDIn_n) or output (GPDOn_n) register.
13.4.1.2
External interrupt request input pins (EIRQ[0:31])
The EIRQ[0:31] pins are connected to the SIUL inputs. Rising- or falling-edge events are enabled by
setting the corresponding bits in the SIUL_IREER or the SIUL_IFEER register.
13.5
Memory map and register description
This section provides a detailed description of all registers accessible in the SIUL module.
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System Integration Unit Lite (SIUL)
13.5.1
SIUL memory map
Table 93 gives an overview of the SIUL registers implemented.
Table 93. SIUL memory map
Register Offset
Register name
Location
0xC3F9_0000
Reserved
—
0x0004
MCU ID Register #1 (MIDR1)
on page 225
0x0008
MCU ID Register #2 (MIDR2)
on page 227
0x000C–0x0013
Reserved
0x0014
Interrupt Status Flag Register (ISR)
on page 228
0x0018
Interrupt Request Enable Register (IRER)
on page 228
0x001C–0x0027
Reserved
0x0028
Interrupt Rising-Edge Event Enable Register (IREER)
on page 229
0x002C
Interrupt Falling-Edge Event Enable Register (IFEER)
on page 229
0x0030
Interrupt Filter Enable Register (IFER)
on page 230
0x0034–0x003F
Reserved
0x0040–0x00CC
Pad Configuration Registers (PCR[0:70])
0x00CE–0x04FF
Reserved
0x500–0x519
Pad Selection for Multiplexed Inputs Registers
(PSMI0–PSMI25)
0x0520–0x05FF
Reserved
0x0600–0x0644
GPIO Pad Data Output Registers (GPDO0_3–GPDO68_71) on page 235
0x06C8–0x07FF
Reserved
0x0800–0x0844
GPIO Pad Data Input Registers (GPDI0_3–GPDI68_71)
0x08C8–0x0BFF
Reserved
0x0C00–0x0C08
Parallel GPIO Pad Data Out Registers (PGPDO0–PGPDO2) on page 237
0x0C0C–0x0C3F
Reserved
0x0C40–0x0C48
Parallel GPIO Pad Data In Register (PGPDI0–PGPDI2)
0x0C4C–0x0C7F
Reserved
0x0C80–0x0C90
Masked Parallel GPIO Pad Data Out Register
(MPGPDO0–MPGPDO4)
0x0C94–0x0FFF
Reserved
0x1000–0x107C
Interrupt Filter Maximum Counter Registers (IFMC0–IFMC31) on page 239
0x1080
Interrupt Filter Clock Prescaler Register (IFCPR)
0x1084–0x3FF
Reserved
—
—
—
on page 230
—
on page 232
—
—
on page 236
—
—
on page 237
—
on page 238
—
on page 241
—
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System Integration Unit Lite (SIUL)
NOTE
A transfer error will be issued when trying to access completely reserved
register space.
13.5.2
Register protection
Individual registers in System Integration Unit Lite can be protected from accidental writes using the
Register Protection module (Chapter 39, "Register Protection (REG_PROT)"). The following registers
can be protected:
• Interrupt Request Enable Register (IRER)
• Interrupt Rising-Edge Event Enable Register (IREER)
• Interrupt Falling-Edge Event Enable Register (IFEER)
• Interrupt Filter Enable Register (IFER)
• Interrupt Filter Enable Register (IFER)
• Pad Configuration Registers (PCR[0:70])
• Pad Selection for Multiplexed Inputs Registers (PSMI0–PSMI25)
• Interrupt Filter Maximum Counter Registers (IFMC0–IFMC31)
• Interrupt Filter Clock Prescaler Register (IFCPR)
Refer to Chapter 39, "Register Protection (REG_PROT)"for details.
13.5.3
Register description
This section describes in address order all the SIUL registers. Each description includes a standard register
diagram. Details of register bit and field function follow the register diagrams, in bit order. The numbering
convention of the registers is MSB = 0, however the numbering of the internal fields is LSB = 0, for
example, PARTNUM[5] = MIDR1[10].
Always
1
Always
0
Read-
R/W
BIT
Write-
Write 1 BIT
Self-
0
w1
c
clear
bit
BIT
BIT
reads 1
reads 0
bit
only bit
only bit BIT to clear
N/A
Figure 96. Key to register fields
13.5.3.1
MCU ID Register #1 (MIDR1)
This register contains the part number and the package ID of the device.
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System Integration Unit Lite (SIUL)
Address: Base + 0x0004
0
1
Access: User read-only
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
PARTNUM[15:0]
W
Reset
0
1
0
16
17
18
R CSP
1
0
1
1
0
0
0
0
0
0
1
0
0
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
MAJOR_MASK[3:0]1
MINOR_MASK[3:0]1
0
0
0
0
PKG[4:0]
W
Reset
0
0
0
0
0
1
0
0
0
0
0
0
Figure 97. MCU ID Register #1 (MIDR1)
1
See Table 94.
Table 94. MIDR1 field descriptions
Field
PARTNUM[15:0]
CSP
PKG[4:0]
Description
MCU Part Number
Device part number of the MCU.
0101_0110_0000_0010: 5602 (ENET)
0101_0110_0000_0011: 5603 (ENET, SAI)
0101_0110_0000_0100: 5604 (ENET, SAI, MPJPEG)
For the full part number this field needs to be combined with MIDR2.PARTNUM[23:16]
Always reads back 0
Package Settings
Can by read by software to determine the package type that is used for the particular device:
00001: 64-pin LQFP
MAJOR_MASK[3:0] Major Mask Revision
Counter starting at 0x0. Incremented each time a resynthesis is done.
0b0000
MINOR_MASK[3:0]
Minor Mask Revision
Counter starting at 0x0. Incremented each time a mask change is done.
0000: Silicon Cut 1.0
0001: Silicon Cut 1.1
0010: Silicon Cut 1.2
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System Integration Unit Lite (SIUL)
13.5.3.2
MCU ID Register #2 (MIDR2)
This register contains additional configuration information about the device.
Address: Base + 0x0008
0
R
1
SF
Access: User read-only
2
3
4
FLASH_SIZE[3:0]
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
21
22
23
24
25
26
27
28
29
30
31
0
0
0
EE
0
0
0
0
0
0
0
1
0
0
0
0
W
Reset
0
0
1
16
17
18
R
0
19
20
PARTNUM[23:16]
W
Reset
0
1
0
0
0
1
0
1
Figure 98. MCU ID Register #2 (MIDR2)
Table 95. MIDR2 field descriptions
Field
SF
Description
Manufacturer
0: Freescale
1: Reserved
FLASH_SIZE[3:0]
Coarse granularity for Flash memory size
0101: 512 KB
Other values are reserved.
PARTNUM[23:16]
ASCII character in MCU Part Number
0x45: ascii 'E' (MPC5604E)
EE
Data Flash present
0: No Data Flash present
1: Data Flash present
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System Integration Unit Lite (SIUL)
13.5.3.3
Interrupt Status Flag Register (ISR)
This register holds the interrupt flags.
Address: Base + 0x0014
0
1
Access: User read/write
2
3
4
5
6
7
8
R
EIF[31:16]
W
w1c
Reset
0
0
0
0
0
0
0
16
17
18
19
20
21
22
0
0
0
0
13
14
15
0
0
0
0
0
0
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
w1c
0
12
0
W
0
11
0
EIF[15:0]
0
10
0
R
Reset
9
0
0
Figure 99. Interrupt Status Flag Register (ISR)
Table 96. ISR field descriptions
Field
Description
EIFn
13.5.3.4
External Interrupt Status Flag n
This flag can be cleared only by writing a 1. Writing a 0 has no effect. If enabled (IRERn), EIFn
causes an interrupt request.
0: No interrupt event has occurred on the pad.
1: An interrupt event as defined by IREERn and IFEERn has occurred.
Interrupt Request Enable Register (IRER)
This register enables the interrupt messaging to the interrupt controller.
Address: Base + 0x0018
0
1
Access: User read/write
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
IRE[15:0]
W
Reset
8
IRE[31:16]
W
Reset
7
0
0
0
0
0
0
0
0
0
Figure 100. Interrupt Request Enable Register (IRER)
Table 97. IRER field descriptions
Field
IREn
Description
External Interrupt Request Enable n
0: Interrupt requests from the corresponding EIFn bit are disabled.
1: A set EIFn bit causes an interrupt request.
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System Integration Unit Lite (SIUL)
13.5.3.5
Interrupt Rising-Edge Event Enable Register (IREER)
This register allows rising-edge triggered events to be enabled on the corresponding interrupt pads.
Address: Base + 0x0028
0
Access: User read/write
1
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
IREE[31:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
IREE[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
Figure 101. Interrupt Rising-Edge Event Enable Register (IREER)
Table 98. IREER field descriptions
Field
Description
IREEn
13.5.3.6
Enable rising-edge events to cause the EIFn bit to be set.
0: Rising-edge event disabled
1: Rising-edge event enabled
Interrupt Falling-Edge Event Enable Register (IFEER)
This register allows falling-edge triggered events to be enabled on the corresponding interrupt pads.
Address: Base + 0x002C
0
1
Access: User read/write
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
IFEE[15:0]
W
Reset
8
IFEE[31:16]
W
Reset
7
0
0
0
0
0
0
0
0
0
Figure 102. Interrupt Falling-Edge Event Enable Register (IFEER)
Table 99. IFEER field descriptions
Field
IFEEn
Description
Enable falling-edge events to cause the EIFn bit to be set.
0: Falling-edge event disabled
1: Falling-edge event enabled
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System Integration Unit Lite (SIUL)
NOTE
If both the IREER.IREE and IFEER.IFEE bits are cleared for the same
interrupt source, the interrupt status flag for the corresponding external
interrupt will never be set.
13.5.3.7
Interrupt Filter Enable Register (IFER)
This register enables a digital filter counter on the corresponding interrupt pads to filter out glitches on the
inputs.
Address: Base + 0x0030
0
1
Access: User read/write
2
3
4
5
6
R
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
IFE[15:0]
W
Reset
8
IFE[31:16]
W
Reset
7
0
0
0
0
0
0
0
0
0
Figure 103. Interrupt Filter Enable Register (IFER)
Table 100. IFER field descriptions
Field
Description
IFEn
13.5.3.8
Enable digital glitch filter on the interrupt pad input.
0: Filter disabled
1: Filter enabled
Pad Configuration Registers (PCR[0:70])
The Pad Configuration Registers allow configuration of the static electrical and functional characteristics
associated with I/O pads. Each PCR controls the characteristics of a single pad.
Address: Base + 0x0040 (PCR0)
...
Base + 0x00CC (PCR70) 71 registers
0
R
0
W
Reset1
1
2
SMC APC
0
0
0
3
0
0
4
5
PA[1:0]
0
0
Access: User read/write
6
7
OBE
IBE
0
0
8
9
0
0
0
0
10
ODE
0
11
12
0
0
0
0
13
14
15
SRC WPE WPS
0
0
0
Figure 104. Pad Configuration Registers 0–70 (PCR[0:70])
1
See Table 102.
NOTE
16/32-bit access is supported for the PCR[0:70] registers.
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Table 101. PCR[0:70] field descriptions
Field
Description
SMC
Safe Mode Control
This bit supports the overriding of the automatic deactivation of the output buffer of the associated
pad upon entering Safe mode of the device.
0: In Safe mode, output buffer of the pad disabled
1: In Safe mode, output buffer remains functional
APC
Analog Pad Control
This bit enables the usage of the pad as analog input.
0: Analog input path from the pad is gated and cannot be used.
1: Analog input path switch can be enabled by the ADC.
PA[1:0]
Pad Output Assignment
This field selects the function that is allowed to drive the output of a multiplexed pad. The PA field
size can vary from 0 to 2 bits, depending on the number of output functions associated with this
pad.
00: Alternative mode 0: GPIO
01: Alternative mode 1 (see Signal Description)
10: Alternative mode 2 (see Signal Description)
11: Alternative mode 3 (see Signal Description)
Note: The number of bits in the PA bitfield depends of the number of actual alternate functions
provided for each pad. Please see the MPC5604E Microcontroller Data Sheetn
OBE
Output Buffer Enable
This bit enables the output buffer of the pad in case the pad is in GPIO mode.
0: Output buffer of the pad disabled when PA = 00
1: Output buffer of the pad enabled when PA = 00
IBE
Input Buffer Enable
This bit enables the input buffer of the pad.
0: Input buffer of the pad disabled
1: Input buffer of the pad enabled
ODE
Open Drain Output Enable
This bit controls output driver configuration for the pads connected to this signal. Either open drain
or push/pull driver configurations can be selected. This feature applies to output pads only.
0: Open drain enable signal negated for the pad
1: Open drain enable signal asserted for the pad
SRC
Slew Rate Control
0: Slowest configuration
1: Fastest configuration
WPE
Weak Pull Up/Down Enable
This bit controls whether the weak pull up/down devices are enabled/disabled for the pad
connected to this signal.
0: Weak pull device enable signal negated for the pad
1: Weak pull device enable signal asserted for the pad
WPS
Weak Pull Up/Down Select
This bit controls whether weak pull up or weak pull down devices are used for the pads connected
to this signal when weak pull up/down devices are enabled.
0: Pull down enabled
1: Pull up enabled
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Table 102. PCR[n] reset value exceptions
Field
Description
PCR[36]
PCR[37]
PCR[38]
These registers correspond to the ABS[0], ABS[2], and FAB boot pins, respectively. Their default
state is input, pull enabled. Their reset value is 0x0102.
This register corresponds to the TDO pin. Its default state is ALT1, slew rate = 1. Its reset value
is 0x0604.
This register corresponds to the TDI pin. Its default state is input, pull enabled, pull selected, slew
enabled. So its reset value is 0x0107.
PCR[n]
13.5.3.9
For other PCR[n] registers, the reset value is 0x0000.
Pad Selection for Multiplexed Inputs Registers (PSMI0–PSMI25)
Figure 105 is the generic figure for PSMI register set. To see actual implementation, refer to Table 104.
Via routing it is possible to define different pads to be possible inputs for a certain peripheral function.
Address: Base + SIUL address offset1
R
4
Access: User read/write
0
1
2
3
5
6
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
0
0
0
0
0
0
0
0
7
8
9
10
11
0
0
0
0
0
0
0
0
0
0
0
0
0
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
PADSEL0
12
13
14
15
PADSEL1
W
Reset
R
PADSEL2
PADSEL3
W
Reset
0
0
0
0
0
0
0
0
Figure 105. Pad Selection for Multiplexed Inputs Register (PSMI)
1
For SIUL address offset, refer to Table 104.
Table 103. PSMI field descriptions
Field
PADSEL0–3,
PADSEL4–7,
...
Description
Pad Selection Bits
Each PADSEL field selects the pad currently used for a certain input function. See Table 104.
In order to multiplex different pads to the same peripheral input, the SIUL provides a register that controls
the selection between the different sources.
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Table 104. Peripheral input pin selection
PSMI registers PADSEL fields SIUL address offset
PADSEL35
0x500
Function / Peripheral
Mapping1
CAN0RX
10: PCR[35]
PADSEL12
01: PCR[12]
PADSEL17
00: PCR[17]
PADSEL57
11: PCR[57]
PSMI0
PADSEL15
0x501
DSPI0
0: PCR[15]
PSMI1
PADSEL69
PADSEL10
PSMI2
000: PCR[10]
PADSEL 41
010: PCR[41]
PADSEL 60
011: PCR[60]
PADSEL 70
100: PCR[70]
0x503
DSPI 0
00: PCR[12]
PADSEL 13
01: PCR[13]
PADSEL 68
10: PCR[68]
0x504
DSPI 1
00: PCR[2]
PADSEL 69
01: PCR[69]
PADSEL 15
10: PCR[15]
PADSEL 0
PSMI5
DSPI 0
001: PCR[14]
PADSEL 2
PSMI4
0x502
PADSEL14
PADSEL12
PSMI3
1: PCR[69]
0x505
DSPI 1
00: PCR[0]
PADSEL 42
01: PCR[42]
PADSEL 70
10: PCR[70]
PADSEL 8
0x506
DSPI 1
00: PCR[8]
PADSEL 11
01: PCR[11]
PADSEL 38
10: PCR[38]
PADSEL 68
11: PCR[68]
PSMI6
PSMI7
PADSEL 5
0x507
DSPI 2
PADSEL 69
PSMI8
PADSEL 3
1: PCR[69]
0x508
DSPI 2
PADSEL 70
PSMI9
PADSEL 6
0: PCR[5]
0: PCR[3]
1: PCR[70]
0x509
DSPI 2
PADSEL 68
0: PCR[6]
1: PCR[68]
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Table 104. Peripheral input pin selection (continued)
PSMI registers PADSEL fields SIUL address offset
PADSEL 34
0x50A
Function / Peripheral
Mapping1
eTimer0
00: PCR[34]
PADSEL 59
01: PCR[59]
PADSEL 60
10: PCR[60]
PADSEL 15
11: PCR[15]
PSMI10
PADSEL 35
0x50B
eTimer0
00: PCR[35]
PADSEL 43
01: PCR[43]
PADSEL 60
10: PCR[60]
PADSEL 6
11: PCR[6]
PSMI11
PADSEL 19
0x50C
eTimer0
00: PCR[19]
PADSEL 43
01: PCR[43]
PADSEL 57
10: PCR[57]
PADSEL 7
11: PCR[7]
PSMI12
PADSEL 37
0x50D
eTimer0
00: PCR[37]
PADSEL 43
01: PCR[43]
PADSEL 57
10: PCR[57]
PADSEL 4
11: PCR[4]
PSMI13
PADSEL 36
0x50E
eTimer0
00: PCR[36]
PADSEL 42
01: PCR[42]
PADSEL 59
10: PCR[59]
PADSEL 5
11: PCR[5]
PSMI14
PADSEL 10
0x50F
eTimer0
00: PCR[10]
PADSEL 42
01: PCR[42]
PADSEL 59
10: PCR[59]
PADSEL 2
11: PCR[2]
PSMI15
PADSEL 34
0x510
LIN0
00: PCR[19]
PADSEL 11
01: PCR[11]
PADSEL 19
10: PCR[34]
PADSEL 40
11: PCR[40]
PSMI16
PADSEL 8
0x511
LIN1
00: PCR[8]
PADSEL 11
01: PCR[11]
PADSEL 39
10: PCR[39]
PADSEL 66
11: PCR[66]
PSMI17
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Table 104. Peripheral input pin selection (continued)
PSMI registers PADSEL fields SIUL address offset
PADSEL 18
PSMI18
PSMI19
0x512
Function / Peripheral
Mapping1
RTC
00: PCR[18]
PADSEL 36
01: PCR[36]
PADSEL 44
10: PCR[44]
PADSEL 17
0x513
RTC
PADSEL 44
PSMI20
PADSEL 8
1: PCR[44]
0x514
SAI1 BCLK
PADSEL 16
PADSEL 2
PSMI21
PSMI22
0x515
SAI1 RXDATA
01: PCR[5]
PADSEL 17
10: PCR[17]
PADSEL 5
PADSEL 3
PADSEL 6
0x516
SAI1
1
0: PCR[5]
1: PCR[35]
0x517
SAI2
0: PCR[3]
1: PCR[8]
0x518
Video
00: PCR[6]
PADSEL 34
01: PCR[34]
PADSEL 46
10: PCR[46]
PADSEL 7
PSMI25
00: PCR[2]
PADSEL 5
PADSEL 8
PSMI24
0: PCR[8]
1: PCR[16]
PADSEL 35
PSMI23
0: PCR[17]
0x519
Video
00: PCR[7]
PADSEL 35
01: PCR[35]
PADSEL 45
10: PCR[45]
See the signal description chapter of this reference manual for correspondence between PCR and
pinout
13.5.3.10 GPIO Pad Data Output Registers (GPDO0_3–GPDO68_71)
These registers are used to set or clear GPIO pads. Each pad data out bit can be controlled separately with
a byte access.
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System Integration Unit Lite (SIUL)
Address: Base + (0x0600–0x0644)
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
PDO
[0]
0
0
0
0
0
0
0
PDO
[1]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
PDO
[2]
0
0
0
0
0
0
0
PDO
[3]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 106. Port GPIO Pad Data Output Register 0–3 (GPDO0_3)
Table 105. GPDO0_3 field descriptions
Field
Description
PDO[x]
Pad Data Out
This bit stores the data to be driven out on the external GPIO pad controlled by this register.
0: Logic low value is driven on the corresponding GPIO pad when the pad is configured as an
output
1: Logic high value is driven on the corresponding GPIO pad when the pad is configured as an
output
13.5.3.11 GPIO Pad Data Input Registers (GPDI0_3–GPDI68_71)
These registers are used to read the GPIO pad data with a byte access.
Address: Base + (0x0800–0x0844)
R
Access: User read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
PDI
[0]
0
0
0
0
0
0
0
PDI
[1]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
PDI
[2]
0
0
0
0
0
0
0
PDI
[3]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 107. Port GPIO Pad Data Input Register 0–3 (GPDI0_3)
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Table 106. GPDO0_3 field descriptions
Field
PDI[x]
Description
Pad Data In
This bit stores the value of the external GPIO pad associated with this register.
0: Value of the data in signal for the corresponding GPIO pad is logic low
1: Value of the data in signal for the corresponding GPIO pad is logic high
13.5.3.12 Parallel GPIO Pad Data Out Registers (PGPDO0 – PGPDO2)
MPC5604E devices ports are constructed such that they contain 16 GPIO pins, for example PortA[0..15].
Parallel port registers for input (PGPDI) and output (PGPDO) are provided to allow a complete port to be
written or read in one operation, dependent on the individual pad configuration.
Writing a parallel PGPDO register directly sets the associated GPDO register bits. There is also a masked
parallel port output register allowing the user to determine which pins within a port are written.
While very convenient and fast, this approach does have implications regarding current consumption for
the device power segment containing the port GPIO pads. Toggling several GPIO pins simultaneously can
significantly increase current consumption.
WARNING
Caution must be taken to avoid exceeding maximum current thresholds
when toggling multiple GPIO pins simultaneously. Please refer to data
sheet.
Table 107 shows the locations and structure of the PGPDOx registers.
Table 107. PGPDO0 – PGPDO6 Register Map
Field
Register
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Offset1
0x0C00 PGPDO0
Port A
Port B
0x0C04 PGPDO1
Port C
Port D
0x0C08 PGPDO2
1
Port E
Reserved
SIU base address is 0xC3F9_0000. To calculate register address add offset to base address
It is important to note the bit ordering of the ports in the parallel port registers. The most significant bit of
the parallel port register corresponds to the least significant pin in the port.
For example in Table 107, the PGPDO0 register contains fields for Port A and Port B.
• Bit 0 is mapped to Port A[0], bit 1 is mapped to Port A[1] and so on, through bit 15, which is
mapped to Port A[15]
• Bit 16 is mapped to Port B[0], bit 17 is mapped to Port B[1] and so on, through bit 31, which is
mapped to Port B[15].
13.5.3.13 Parallel GPIO Pad Data In Register (PGPDI0 – PGPDI2)
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System Integration Unit Lite (SIUL)
The SIU_PGPDI registers are similar in operation to the PGPDIO registers, described in the previous
section (Section 13.5.3.12, “Parallel GPIO Pad Data Out Registers (PGPDO0 – PGPDO2)”) but they are
used to read port pins simultaneously.
NOTE
The port pins to be read need to be configured as inputs but even if a single
pin within a port has IBE set, then you can still read that pin using the
parallel port register. However, this does mean you need to be very careful.
Reads of PGPDI registers are equivalent to reading the corresponding GPDI registers but significantly
faster since as many as two ports can be read simultaneously with a single 32-bit read operation.
Table 108 shows the locations and structure of the PGPDIx registers. Each 32-bit PGPDIx register contains
two 16-bit fields, each field containing the values for a separate port.
Table 108. PGPDI0 – PGPDI6 Register Map
Field
Register
0x0C40
PGPDI0
Port A
Port B
0x0C44
PGPDI1
Port C
Port D
0x0C48
PGPDI2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Offset1
1
Port E
Reserved
SIU base address is 0xC3F9_0000. To calculate register address add offset to base address
It is important to note the bit ordering of the ports in the parallel port registers. The most significant bit of
the parallel port register corresponds to the least significant pin in the port.
For example in Table 108, the PGPDI0 register contains fields for Port A and Port B.
• Bit 0 is mapped to Port A[0], bit 1 is mapped to Port A[1] and so on, through bit 15, which is
mapped to Port A[15]
• Bit 16 is mapped to Port B[0], bit 17 is mapped to Port B[1] and so on, through bit 31, which is
mapped to Port B[15].
13.5.3.14 Masked Parallel GPIO Pad Data Out Register (MPGPDO0–MPGPDO4)
The MPGPDOx registers are similar in operation to the PGPDOx ports described in Section 13.5.3.12,
“Parallel GPIO Pad Data Out Registers (PGPDO0 – PGPDO2)”, but with two significant differences:
• The MPGPDOx registers support masked port-wide changes to the data out on the pads of the
respective port. Masking effectively allows selective bitwise writes to the full 16-bit port.
• Each 32-bit MPGPDOx register is associated to only one port.
NOTE
The MPGPDOx registers may only be accessed with 32-bit writes. 8-bit or
16-bit writes will not modify any bits in the register and will cause a transfer
error response by the module. Read accesses return ‘0’.
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System Integration Unit Lite (SIUL)
Table 109 shows the locations and structure of the MPGPDOx registers. Each 32-bit MPGPDOx register
contains two 16-bit fields (MASKx and MPPDOx). The MASK field is a bitwise mask for its associated
port. The MPPDO0 field contains the data to be written to the port.
Table 109. MPGPDO0 – MPGPDO4 Register Map
Field
Register
0x0C80
MPGPDO0
MASK0 (Port A)
MPPDO0 (Port A)
0x0C84
MPGPDO1
MASK1 (Port B)
MPPDO1 (Port B)
0x0C88
MPGPDO2
MASK2 (Port C)
MPPDO2 (Port C)
0x0C8C
MPGPDO3
MASK3 (Port D)
MPPDO3 (Port D)
0x0C90
MPGPDO4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Offset1
1
MASK4 (Port E)
Reserved
MPPDO4 (Port E)
SIU base address is 0xC3F9_0000. To calculate register address add offset to base address
It is important to note the bit ordering of the ports in the parallel port registers. The most significant bit of
the parallel port register corresponds to the least significant pin in the port.
For example in Table 109, the MPGPDO0 register contains field MASK0, which is the bitwise mask for
Port A and field MPPDO0, which contains data to be written to Port A.
• MPGPDO0[0] is the mask bit for Port A[0], MPGPDO0[1] is the mask bit for Port A[1] and so on,
through MPGPDO0[15], which is the mask bit for Port A[15]
• MPGPDO0[16] is the data bit mapped to Port A[0], MPGPDO0[17] is mapped to Port A[1] and so
on, through MPGPDO0[31], which is mapped to Port A[15].
Table 110. MPGPDO0..MPGPDO4 field descriptions
Field
MASKx
[15:0]
MPPDOx
[15:0]
Description
Mask Field
Each bit corresponds to one data bit in the MPPDOx register at the same bit location.
0: Associated bit value in the MPPDOxfield is ignored
1: Associated bit value in the MPPDOx field is written
Masked Parallel Pad Data Out
Write the data register that stores the value to be driven on the pad in output mode.
Accesses to this register location are coherent with accesses to the bitwise GPIO Pad Data Output
Registers (GPDO0_3–GPDO68_71).
The x and bit index define which MPPDO register bit is equivalent to which PDO register bit
according to the following equation:
MPPDO[x][y] = PDO[(x*16)+y]
13.5.3.15 Interrupt Filter Maximum Counter Registers (IFMC0–IFMC31)
These registers are used to configure the filter counter associated with each digital glitch filter.
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System Integration Unit Lite (SIUL)
NOTE
For the pad transition to trigger an interrupt it must be steady for at least the
filter period.
Address: Base + (0x1000–0x107C)
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
MAXCNTx[3:0]
W
Reset
0
0
0
0
Figure 108. Interrupt Filter Maximum Counter Registers (IFMC0–IFMC31)
Table 111. IFMC field descriptions
Field
MAXCNTx
Description
Maximum Interrupt Filter Counter setting.
Filter Period = T(CK)*3 (for 2 < MAXCNT < 6 )
Filter Period = T(CK)*MAXCNTx (for MAXCNT = 6,7,.... 15 )
For MAXCNT = 0, 1, 2 the filter behaves as ALL PASS filter.
MAXCNTx can be 0 to 15;
T(CK): Prescaled Filter Clock Period, which is IRC clock prescaled to IFCP value;
T(IRC): Basic Filter Clock Period: 62.5 ns (F = 16 MHz).
13.5.3.16 Interrupt Filter Clock Prescaler Register (IFCPR)
This register is used to configure a clock prescaler which is used to select the clock for all digital filter
counters in the SIUL.
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System Integration Unit Lite (SIUL)
Address: Base + 0x1080
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
IFCP[3:0]
W
Reset
0
0
0
0
Figure 109. Interrupt Filter Clock Prescaler Register (IFCPR)
Table 112. IFCPR field descriptions
Field
IFCP
13.6
13.6.1
Description
Interrupt Filter Clock Prescaler setting
Prescaled Filter Clock Period = T(FIRC) x (IFCP + 1)
T(FIRC) is the fast internal RC oscillator period.
IFCP can be 0 to 15.
Functional description
Pad control
The SIUL controls the configuration and electrical characteristic of the device pads. It provides a
consistent interface for all pads, both on a by-port and a by-bit basis. The pad configuration registers
(PCRn, see Section 13.5.3.8, “Pad Configuration Registers (PCR[0:70])”) allow software control of the
static electrical characteristics of external pins with a single write. These are used to configure the
following pad features:
• Open drain output enable
• Slew rate control
• Pull control
• Pad assignment
• Control of analog path switches
• Safe mode behavior configuration
13.6.2
General purpose input and output pads (GPIO)
The SIUL manages up to 199 GPIO pads organized as ports that can be accessed for data reads and writes
as 32, 16 or 8-bit.1
1. There are exceptions. Some pads, e.g., precision analog pads, are input only.
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System Integration Unit Lite (SIUL)
As shown in Figure 110, all port accesses are identical with each read or write being performed only at a
different location to access a different port width.
23
31
SIUL Base+ 0x0C00
SIUL Base+
0x0C02
SIUL Base+
0x0C03
15
7
7
0
15
7
16-bit Access (full port)
32-bit Access (2 ports)
7
16-bit Access (full port)
0
8-bit Access
(half port)
15
SIUL Base+
0x0C02
0
7
SIUL Base+
0x0C00
0
8-bit Access
(half port)
SIUL Base+
0x0C01
7
0
8-bit Access
(half port)
SIUL Base+
0x0C00
0
7
0
8-bit Access
(half port)
Figure 110. Data Port example arrangement showing configuration for different port width accesses
The SIUL has separate data input (GPDIn_n, see Section 13.5.3.11, “GPIO Pad Data Input Registers
(GPDI0_3–GPDI68_71)”) and data output (GPDOn_n, see Section 13.5.3.10, “GPIO Pad Data Output
Registers (GPDO0_3–GPDO68_71)”) registers for all pads, allowing the possibility of reading back an
input or output value of a pad directly. This supports the ability to validate what is present on the pad rather
than simply confirming the value that was written to the data register by accessing the data input registers.
Data output registers allow an output pad to be driven high or low (with the option of push-pull or open
drain drive). Input registers are read-only and reflect the respective pad value. When the pad is configured
to use one of its alternate functions, the data input value reflects the respective value of the pad. If a write
operation is performed to the data output register for a pad configured as an alternate function (non-GPIO),
this write will not be reflected by the pad value until reconfigured to GPIO.
The allocation of what input function is connected to the pin is defined by the PSMI registers (PCRn, see
Section 13.5.3.9, “Pad Selection for Multiplexed Inputs Registers (PSMI0–PSMI25)”)
13.6.3
External interrupts
The SIUL supports 24 external interrupts, EIRQ0–EIRQ23. In the signal description chapter of this
reference manual, mapping is shown for external interrupts to pads.
The SIUL supports three interrupt vectors to the interrupt controller. Each vector interrupt has eight
external interrupts combined together with the presence of flag generating an interrupt for that vector if
enabled. All of the external interrupt pads within a single group have equal priority.
Refer to Figure 111 for an overview of the external interrupt implementation.
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System Integration Unit Lite (SIUL)
Interrupt
Controller
Interrupt
Vectors
IRQ_23_16
IRQ_15_08
OR
IRQ_07_00
OR
OR
IRE[23:0](1)
Interrupt enable
Glitch filter Prescaler
EIF[23:16]
EIF[15:8]
EIF[7:0]
IFCP[3:0]
Glitch filter Counter_n
Edge Detection
MAXCOUNT[x]
IRQ Glitch Filter enable
IFE[23:0]
Glitch Filter
Interrupt Edge Enable
Rising
IREE[23:0](1)
Falling
IFEE[23:0](1)
Pads
Figure 111. External interrupt pad diagram
Each interrupt can be enabled or disabled independently. This can be performed using the Interrupt
Request Enable Register (IRER). A pad defined as an external interrupt can be configured to recognize
interrupts with an active rising edge, an active falling edge or both edges being active. A setting of having
both edge events disabled is reserved and should not be configured.
The active EIRQ edge is controlled through the configuration of the registers IREER and IFEER.
Each external interrupt supports an individual flag which is held in the Interrupt Status Flag Register (ISR).
This register is a clear-by-write-1 register type, preventing inadvertent overwriting of other flags in the
same register.
13.7
Pin muxing
For pin muxing, please refer to the signal description chapter of this reference manual.
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Chapter 14
e200z0h Core
14.1
Overview
The MPC5604E microcontroller implements the e200z0h core.
The e200 processor family is a set of CPU cores that implement low-cost versions of the Power
Architecture™ Book E architecture. e200 processors are designed for deeply embedded control
applications that require low cost solutions rather than maximum performance.
The e200z0h processors integrate an integer execution unit, branch control unit, instruction fetch and
load/store units, and a multi-ported register file capable of sustaining three read and two write operations
per clock. Most integer instructions execute in a single clock cycle. Branch target prefetching is performed
by the branch unit to allow single-cycle branches in some cases.
The e200z0 core is a single-issue, 32-bit Power Architecture Book E VLE-only design with 32-bit general
purpose registers (GPRs). All arithmetic instructions that execute in the core operate on data in the GPRs.
Instead of the base Power Architecture Book E instruction set support, the e200z0 core only implements
the VLE (variable-length encoding) APU, providing improved code density. The VLE APU is further
documented in the PowerPC™ VLE APU Definition, a separate document.
14.2
Features
The following is a list of some of the key features of the e200z0h core:
• High performance e200z0 core processor for managing peripherals and interrupts
• 32-bit Power Architecture Book E VLE-only programmer’s model
• Single issue, 32-bit CPU
• Implements the VLE APU for reduced code footprint
• In-order execution and retirement
• Precise exception handling
• Branch processing unit
— Dedicated branch address calculation adder
— Branch acceleration using Branch Target Buffer (e200z0h only)
• Supports independent instruction and data accesses to different memory subsystems, such as
SRAM and Flash memory via independent Instruction and Data bus interface units (BIUs)
• Load/store unit
— 1 cycle load latency
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e200z0h Core
•
•
— Fully pipelined
— Big-endian support only
— Misaligned access support
— Zero load-to-use pipeline bubbles for aligned transfers
Power management
— Low power design
— Dynamic power management of execution units
Testability
— Synthesizeable, full MuxD scan design
— ABIST/MBIST for optional memory arrays
14.2.1
Microarchitecture summary
The e200z0 processor utilizes a four stage pipeline for instruction execution. The Instruction Fetch (stage
1), Instruction Decode/Register file Read/Effective Address Calculation (stage 2), Execute/Memory
Access (stage 3), and Register Writeback (stage 4) stages operate in an overlapped fashion, allowing single
clock instruction execution for most instructions.
The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32-bit Barrel
shifter (Shifter), a Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a
Count-Leading-Zeros unit (CLZ), an 8 × 32 Hardware Multiplier array, result feed-forward hardware, and
a hardware divider.
Arithmetic and logical operations are executed in a single cycle with the exception of the divide and
multiply instructions. A Count-Leading-Zeros unit operates in a single clock cycle.
The Instruction Unit contains a PC incrementer and a dedicated Branch Address adder to minimize delays
during change of flow operations. Sequential prefetching is performed to ensure a supply of instructions
into the execution pipeline. Branch target prefetching from the BTB is performed to accelerate certain
taken branches. Prefetched instructions are placed into an instruction buffer with 4 entries, each capable
of holding a single 32-bit instruction or a pair of 16-bit instructions.
Conditional branches that are not taken execute in a single clock. Branches with successful target
prefetching have an effective execution time of one clock on e200z0h. All other taken branches have an
execution time of two clocks.
Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic
zero or sign extension of byte and halfword load data as well as optional byte reversal of data. These
instructions can be pipelined to allow effective single cycle throughput. Load and store multiple word
instructions allow low overhead context save and restore operations. The load/store unit contains a
dedicated effective address adder to allow effective address generation to be optimized. Also, a load-to-use
dependency does not incur any pipeline bubbles for most cases.
The Condition Register unit supports the condition register (CR) and condition register operations defined
by the Power Architecture architecture. The condition register consists of eight 4-bit fields that reflect the
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e200z0h Core
results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical
instructions, and provide a mechanism for testing and branching.
Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to
allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead.
14.2.1.1
Block diagram
OnCE/NEXUS
CPU
CONTROL LOGIC
CONTROL LOGIC
INSTRUCTION BUS INTERFACE UNIT
N
CONTROL
32
DATA
32
ADDRESS
NEXUS
DEBUG
UNIT
LR
SPR
CR
INTEGER
EXECUTION
UNIT
GPR
CTR
XER
MULTIPLY
UNIT
INSTRUCTION UNIT
INSTRUCTION BUFFER
CONTROL
EXTERNAL
SPR
INTERFACE
DATA
(MTSPR/MFSPR)
PC
UNIT
BRANCH
UNIT
LOAD/STORE
UNIT
DATA BUS INTERFACE UNIT
32
ADDRESS
32
DATA
N
CONTROL
Figure 112. e200z0h block diagram
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e200z0h Core
14.2.1.2
Instruction unit features
The features of the e200 Instruction unit are:
• 32-bit instruction fetch path supports fetching of one 32-bit instruction per clock, or as many as
two 16-bit VLE instructions per clock
• Instruction buffer with 4 entries in e200z0h, each holding a single 32-bit instruction, or a pair of
16-bit instructions
• Dedicated PC incrementer supporting instruction prefetches
• Branch unit with dedicated branch address adder supporting single cycle of execution of certain
branches, two cycles for all others
14.2.1.3
Integer unit features
The e200 integer unit supports single cycle execution of most integer instructions:
• 32-bit AU for arithmetic and comparison operations
• 32-bit LU for logical operations
• 32-bit priority encoder for count leading zero’s function
• 32-bit single cycle barrel shifter for shifts and rotates
• 32-bit mask unit for data masking and insertion
• Divider logic for signed and unsigned divide in 5 to 34 clocks with minimized execution timing
• 8 × 32 hardware multiplier array supports 1 to 4 cycle 32 × 32 → 32 multiply (early out)
14.2.1.4
Load/Store unit features
The e200 load/store unit supports load, store, and the load multiple / store multiple instructions:
• 32-bit effective address adder for data memory address calculations
• Pipelined operation supports throughput of one load or store operation per cycle
• 32-bit dedicated interface to memory
14.2.1.5
e200z0h system bus features
The features of the e200z0h System Bus interface are as follows:
• Independent Instruction and Data Buses
• AMBA AHB Lite Rev 2.0 Specification with support for ARM v6 AMBA Extensions
— Exclusive Access Monitor
— Byte Lane Strobes
— Cache Allocate Support
• 32-bit address bus plus attributes and control on each bus
• 32-bit read data bus for Instruction Interface
• Separate uni-directional 32-bit read data bus and 32-bit write data bus for Data Interface
• Overlapped, in-order accesses
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e200z0h Core
14.2.1.6
Nexus features
The Nexus 2+ module is compliant with Class 2 of the IEEE-ISTO 5001-2003 standard, with additional
Class 3 and Class 4 features available. The following features are implemented:
• Program Trace via Branch Trace Messaging (BTM). Branch trace messaging displays program
flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool
to interpolate what transpires between the discontinuities. Thus, static code may be traced.
• Ownership Trace via Ownership Trace Messaging (OTM). OTM facilitates ownership trace by
providing visibility of which process ID or operating system task is activated. An Ownership Trace
Message is transmitted when a new process/task is activated, allowing the development tool to
trace ownership flow.
• Run-time access to the processor memory map via the JTAG port. This allows for enhanced
download/upload capabilities.
• Watchpoint Messaging via the auxiliary interface
• Watchpoint Trigger enable of Program Trace Messaging
• Auxiliary interface for higher data input/output
— Configurable (min/max) Message Data Out pins (nex_mdo[n:0])
— One (1) or two (2) Message Start/End Out pins (nex_mseo_b[1:0])
— One (1) Read/Write Ready pin (nex_rdy_b) pin
— One (1) Watchpoint Event pin (nex_evto_b)
— One (1) Event In pin (nex_evti_b)
— One (1) MCKO (Message Clock Out) pin
• Registers for Program Trace, Ownership Trace and Watchpoint Trigger control
• All features controllable and configurable via the JTAG port
14.3
Core registers and programmer’s model
This section describes the registers implemented in the e200z0h core. It includes an overview of registers
defined by the Power Architecture Book E architecture, highlighting differences in how these registers are
implemented in the e200 core, and provides a detailed description of e200-specific registers. Full
descriptions of the architecture-defined register set are provided in Power Architecture Book E
Specification.
The Power Architecture Book E defines register-to-register operations for all computational instructions.
Source data for these instructions are accessed from the on-chip registers or are provided as immediate
values embedded in the opcode. The three-register instruction format allows specification of a target
register distinct from the two source registers, thus preserving the original data for use by other
instructions. Data is transferred between memory and registers with explicit load and store instructions
only.
Figure 113 and Figure 114 show the e200 register set, including the registers that are accessible while in
supervisor mode and the registers that are accessible in user mode. The number to the right of the
special-purpose registers (SPRs) is the decimal number used in the instruction syntax to access the register
(for example, the integer exception register (XER) is SPR 1).
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e200z0h Core
NOTE
e200z0h is a 32-bit implementation of the Power Architecture Book E
specification. In this document, register bits are sometimes numbered from
bit 0 (Most Significant Bit) to 31 (Least Significant Bit), rather than the
Book E numbering scheme of 32:63, thus register bit numbers for some
registers in Book E are 32 higher.
Where appropriate, the Book E defined bit numbers are shown in
parentheses.
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e200z0h Core
SUPERVISOR Mode Program Model
Exception Handling/Control Registers
General Registers
CR
GPR0
Count Register
CTR
Save and Restore
SPR General
General-Purpose
Registers
Condition Register
SPRG0
SPR 272
SPRG1
SPR 273
GPR1
SPR 9
Link Register
LR
SPR 8
GPR31
Interrupt Vector Prefix
SRR0
SPR 26
SRR1
SPR 27
CSRR0
SPR 58
IVPR
CSRR1
SPR 59
DSRR0
SPR 574
DSRR1
SPR 575
SPR 63
Exception Syndrome
XER
ESR
XER
SPR 1
Machine Check
Syndrome Register
MCSR
Processor Control Registers
Machine State
MSR
Processor Version
HID1
SPR 287
Processor ID
DEAR
SPR 61
SPR 1009
Memory Management Registers
Process ID
SPR 286
Debug Registers2
System Version1
SVR
SPR 572
Data Exception Address
Hardware Implementation
Dependent1
HID0
SPR 1008
PVR
PIR
SPR 62
SPR 1023
Debug Control
PID0
Instruction Address
Compare
DBCR0
SPR 308
IAC1
SPR 312
DBCR1
SPR 309
IAC2
SPR 313
DBCR2
SPR 310
IAC3
SPR 314
IAC4
SPR 315
Debug Status
DBSR
SPR 304
Data Address Compare
DAC1
SPR 316
DAC2
SPR 317
SPR 48
Configuration (Read-only)
MMUCFG
SPR
1015
Cache Registers
1 - These e200-specific registers may not be supported
by other Power Architecture processors
2 - Optional registers defined by the Power Architecture
Book E
3 - Read-only registers
Cache
Configuration
(Read-only)
L1CFG0
SPR 515
Figure 113. e200z0 Supervisor mode programmer’s model
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e200z0h Core
USER Mode Programmer Model
General Registers
General-Purpo
se
Condition
CR
GPR0
Count
CTR
SPR 9
GPR1
Link
Cache Registers
Cache
Configuration
(Read-only)
L1CFG0
LR
SPR 8
XER
SPR 1
SPR 515
GPR31
XER
Figure 114. e200 User mode program model
14.3.1
Unimplemented SPRs and read-only SPRs
e200 fully decodes the SPR field of the mfspr and mtspr instructions. If the SPR specified is undefined
and not privileged, an illegal instruction exception is generated. If the SPR specified is undefined and
privileged and the CPU is in user mode (MSR[PR=1]), a privileged instruction exception is generated. If
the SPR specified is undefined and privileged and the core is in supervisor mode (MSR[PR=0]), an illegal
instruction exception is generated.
For the mtspr instruction, if the SPR specified is read-only and not privileged, an illegal instruction
exception is generated. If the SPR specified is read-only and privileged and the core is in user mode
(MSR[PR=1]), a privileged instruction exception is generated. If the SPR specified is read-only and
privileged and the core is in supervisor mode (MSR[PR=0]), an illegal instruction exception is generated.
14.4
Instruction summary
The e200z0 core supports all VLE instructions described in the PowerPC™ VLE APU Definition version
1.2 together with the additional instructions for context save/restore.
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Chapter 15
Crossbar Switch (XBAR)
15.1
Introduction
This chapter describes the multi-port crossbar switch (XBAR), which supports simultaneous connections
between four master ports and four slave ports. XBAR supports a 32-bit address bus width and a 32-bit
data bus width at all master and slave ports.
15.2
Block diagram
Figure 115 shows a block diagram of the crossbar switch.
Master
Master
....
Master
Master modules
Crossbar Switch
Slave modules
Slave
Slave
....
Slave
Figure 115. XBAR block diagram
Table 113 gives the crossbar switch port for each master and slave, the assigned and fixed ID number for
each master and shows the master ID numbers as they relate to the master port numbers.
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Crossbar Switch (XBAR)
Table 113. Device XBAR switch ports
Port
Module
15.3
Logical
number
Physical master ID
Type
e200z0 core–CPU instructions
Master
0
0
e200z0 core—Data
Master
1
1
eDMA
Master
2
2
Ethernet
Master
Flash
Slave
0
—
Internal SRAM
Slave
2
—
Video encoder output buffer
Slave
Peripheral bridge
Slave
7
—
4
Overview
The XBAR allows for concurrent transactions to occur from any master port to any slave port. It is possible
for all master ports and slave ports to be in use at the same time as a result of independent master requests.
If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher
priority master and grants it ownership of the slave port. All other masters requesting that slave port are
stalled until the higher priority master completes its transactions.
Requesting masters are granted access based on a fixed priority.
15.4
•
•
•
•
•
Features
4 Master ports
— e200z0 core complex Instruction port
— e200z0 core complex Load/Store Data port
— eDMA
— Ethernet
4 Slave ports
— Flash memory (code flash and data flash) controller
— SRAM controller
— Video encoder output buffer
— Peripheral bridge
32-bit internal address, 32-bit internal data paths
Fully concurrent transfers between independent master and slave ports
Fixed priority scheme and fixed parking strategy
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Crossbar Switch (XBAR)
15.5
Modes of operation
15.5.1
Normal mode
In normal mode, the XBAR provides the register interface and logic that controls crossbar switch
configuration.
15.5.2
Debug mode
The XBAR operation in debug mode is identical to operation in normal mode.
15.6
Functional description
This section describes the functionality of the XBAR in more detail.
15.6.1
Overview
The main goal of the XBAR is to increase overall system performance by allowing multiple masters to
communicate concurrently with multiple slaves. To maximize data throughput, it is essential to keep
arbitration delays to a minimum.
This section examines data throughput from the point of view of masters and slaves, detailing when the
XBAR stalls masters, or inserts bubbles on the slave side.
15.6.2
General operation
When a master makes an access to the XBAR from an idle master state, the access is taken immediately
by the XBAR. If the targeted slave port of the access is available (that is, the requesting master is currently
granted ownership of the slave port), the access is immediately presented on the slave port. It is possible
to make single clock (zero wait state) accesses through the XBAR by a granted master. If the targeted slave
port of the access is busy or parked on a different master port, the requesting master receives wait states
until the targeted slave port can service the master request. The latency in servicing the request depends
on each master’s priority level and the responding slave’s access time.
Because the XBAR appears to be just another slave to the master device, the master device has no
indication that it owns the slave port it is targeting. While the master does not have control of the slave port
it is targeting, it is wait-stated.
A master is given control of a targeted slave port only after a previous access to a different slave port has
completed, regardless of its priority on the newly targeted slave port. This prevents deadlock from
occurring when a master has the following conditions:
•
•
•
Outstanding request to slave port A that has a long response time
Pending access to a different slave port B
Lower priority master also makes a request to the different slave port B.
In this case, the lower priority master is granted bus ownership of slave port B after a cycle of arbitration,
assuming the higher priority master slave port A access is not terminated.
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Crossbar Switch (XBAR)
After a master has control of the slave port it is targeting, the master remains in control of that slave port
until it gives up the slave port by running an IDLE cycle, leaves that slave port for its next access, or loses
control of the slave port to a higher priority master with a request to the same slave port. However, because
all masters run a fixed-length burst transfer to a slave port, it retains control of the slave port until that
transfer sequence is completed.
When a slave bus is idled by the XBAR, it is parked on the master that did the last transfer.
15.6.3
Master ports
A master access is taken if the slave port to which the access decodes is either currently servicing the
master or is parked on the master. In this case, the XBAR is completely transparent and the master access
is immediately transmitted on the slave bus and no arbitration delays are incurred. A master access stall if
the access decodes to a slave port that is busy serving another master, parked on another master.
If the slave port is currently parked on another master, and no other master is requesting access to the slave
port, then only one clock of arbitration is incurred. If the slave port is currently serving another master of
a lower priority and the master has a higher priority than all other requesting masters, then the master gains
control over the slave port as soon as the data phase of the current access is completed. If the slave port is
currently servicing another master of a higher priority, then the master gains control of the slave port after
the other master releases control of the slave port if no other higher priority master is also waiting for the
slave port.
A master access is responded to with an error if the access decodes to a location not occupied by a slave
port. This is the only time the XBAR directly responds with an error response. All other error responses
received by the master are the result of error responses on the slave ports being passed through the XBAR.
15.6.4
Slave ports
The goal of the XBAR with respect to the slave ports is to keep them 100% saturated when masters are
actively making requests. To do this the XBAR must not insert any bubbles onto the slave bus unless
absolutely necessary.
There is only one instance when the XBAR forces a bubble onto the slave bus when a master is actively
making a request. This occurs when a handoff of bus ownership occurs and there are no wait states from
the slave port. A requesting master that does not own the slave port is granted access after a one clock
delay.
15.6.5
Priority assignment
Each master port is assigned a fixed 3-bit priority level (hard-wired priority). Table 114 shows the priority
levels assigned to each master (the lowest has highest priority).
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Crossbar Switch (XBAR)
Table 114. Hardwired bus master priorities
Port
Module
15.6.6
Priority level
Type
Number
e200z0 core–CPU instructions
Master
0
7
e200z0 core—Data
Master
1
6
eDMA
Master
2
5
Ethernet
Master
Arbitration
XBAR supports only a fixed-priority comparison algorithm.
15.6.6.1
Fixed priority operation
When operating in fixed-priority arbitration mode, each master is assigned a unique priority level. If two
masters both request access to a slave port, the master with the highest priority in the selected priority
register gains control over the slave port.
Any time a master makes a request to a slave port, the slave port checks to see if the new requesting
master’s priority level is higher than that of the master that currently has control over the slave port (if any).
The slave port does an arbitration check at every clock edge to ensure that the proper master (if any) has
control of the slave port.
If the new requesting master’s priority level is higher than that of the master that currently has control of
the slave port, the higher priority master is granted control at the termination of any currently pending
access, assuming the pending transfer is not part of a burst transfer.
A new requesting master must wait until the end of the fixed-length burst transfer, before it is granted
control of the slave port. But if the new requesting master’s priority level is lower than that of the master
that currently has control of the slave port, the new requesting master is forced to wait until the master that
currently has control of the slave port is finished accessing the current slave port.
15.6.6.1.1
Parking
If no master is currently requesting the slave port, the slave port is parked. The slave port parks always to
the most recently requesting master (park-on-last). When parked on the last master, the slave port is
passing that master’s signals through to the slave bus. When the master accesses the slave port again, no
other arbitration penalties are incurred except that a one clock arbitration penalty is incurred for each
access request to the slave port made by another master port. All other masters pay a one clock penalty.
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Chapter 16
Miscellaneous Control Module (MCM)
16.1
Introduction
The Miscellaneous Control Module (MCM), provides miscellaneous control functions for the device
Standard Product Platform (SPP) including program-visible information about the platform configuration
and revision levels, a reset status register, a software watchdog timer, and wakeup control for exiting sleep
modes, and optional features such as an address map for the device’s crossbar switch, information on
memory errors reported by error-correcting codes and/or generic access error information for certain
processor cores. It also provides with register access protection for the following slave modules: INTC,
MCM, STM, and SWT.
16.2
Overview
The Miscellaneous Control Module is mapped into the IPS space and supports a number of miscellaneous
control functions for the platform device.
16.3
Features
The MCM includes these features:
• Program-visible information on the platform device configuration and revision
• egisters for capturing information on platform memory errors if error-correcting codes (ECC) are
implemented
• egisters to specify the generation of single- and double-bit memory data inversions for test
purposes if error-correcting codes are implemented
• ccess address information for faulted memory accesses for certain processor core
micro-architectures,
• AXBS_lite priority functions, including forcing round robin and high priority enabling.
• Capability to restrict register access to supervisor mode to selected on-platform slave devices:
INTC, MCM, STM, and SWT.
16.4
Memory Map and Registers Description
This section details the programming model for the Miscellaneous Control Module. This is an on-platform
128-byte space mapped to the region serviced by an IPS bus controller. Some of the control registers have
a 64-bit width. These 64-bit registers are implemented as two 32-bit registers, and include an “H” and “L”
suffixes, indicating the “high” and “low” portions of the control function.
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Miscellaneous Control Module (MCM)
The Miscellaneous Control Module does not include any logic which provides access control. Rather, this
function is supported using the standard access control logic provided by the IPS controller.
MCM registers are accessible only when the core is in supervisor mode (see Section 16.4.3,
“MCM_reg_protection”).
16.4.1
Memory Map
Table 115 is a 32-bit view of the MCM’s memory map.
Table 115. MCM 32-bit Memory Map
MCM Offset
0x0000
Register
Processor Core Type (PCT)
Revision (REV)
0x0008
IPS Module Configuration (IMC)
0x000c
Reserved
0x0014
Reserved
0x0018
Reserved
0x001c
Reserved
Misc Interrupt
(MIR)
0x0020
Reserved
0x0024
Miscellaneous User-Defined Control Register (MUDCR)
0x0028
Reserved
0x002c 0x003c
Reserved
0x0040
Reserved
ECC Configuration
(ECR)
0x0044
Reserved
ECC Status
(ESR)
Reserved
0x0048
ECC Error Generation (EEGR)
0x004c
Reserved
0x0050
Flash ECC Address (FEAR)
Reserved
0x0054
Flash ECC Master
(FEMR)
0x0058
Reserved
0x005c
Flash ECC Data (FEDR)
0x0060
RAM ECC Address (REAR)
0x0064
Reserved
RAM ECC Syndrome
(RESR)
RAM ECC Master
(REMR)
0x0068
Reserved
0x006c
RAM ECC Data (REDR)
Flash ECC Attributes
(FEAT)
RAM ECC Attributes
(REAT)
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Table 115. MCM 32-bit Memory Map (continued)
MCM Offset
Register
0x0070 0x007c
Reserved
16.4.2
Registers Description
Attempted accesses to reserved addresses result in an error termination, while attempted writes to
read-only registers are ignored and do not terminate with an error. Unless noted otherwise, writes to the
programming model must match the size of the register, e.g., an n-bit register only supports n-bit writes,
etc. Attempted writes of a different size than the register width produce an error termination of the bus
cycle and no change to the targeted register.
16.4.2.1
Processor Core Type (PCT) register
The PCT is a 16-bit read-only register specifying the architecture of the processor core in the device. The
state of this register is defined by a module input signal; it can only be read from the IPS programming
model. Any attempted write is ignored.
See Figure 116 and Table 116 for the Processor Core Type definition.
Register address: MCM Base + 0x0000
0
1
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
0
0
1
0
0
1
0
PCT[0:15]
W
RESET:
1
1
1
0
0
0
0
0
0
= Unimplemented
Figure 116. Processor Core Type (PCT) Register
16.4.2.2
Revision (REV) register
The REV is a 16-bit read-only register specifying a revision number. The state of this register is defined
by an input signal; it can only be read from the IPS programming model. Any attempted write is ignored.
See Figure 117 and Table 117 for the Revision definition.
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Register address: MCM Base + 0x0002
0
1
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
REV[0:15]
W
RESET:
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 117. Revision (REV) Register
Table 117. Revision (REV) Field Descriptions
Name
Description
0-15
REV[0:15]
Revision
The REV[0:15] field is specified by an input signal to define a software-visible revision number.
16.4.2.3
IPS Module Configuration (IMC) register
The IMC is a 32-bit read-only register identifying the presence/absence of the 32 low-order IPS peripheral
modules connected to the primary IPI SkyBlue bus controller. The state of this register is defined by a
module input signal; it can only be read from the IPS programming model. Any attempted write is ignored.
See Figure 118 and Table 118 for the IPS Module Configuration definition.
Register address: MCM Base + 0x0008
0
1
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
MC[0:15]
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
R
MC[16:31]
W
RESET:
1
1
1
1
0
0
0
0
0
= Unimplemented
Figure 118. IPS Module Configuration (IMC) Register
Table 118. IPS Module Configuration (IMC) Field Descriptions
Name
0-31
MC[0:31]
Description
IPS Module Configuration
MC[n] = 0 if an IPS module connection to decoded slot “n” is absent
MC[n] = 1 if an IPS module connection to decoded slot “n” is present
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16.4.2.4
Miscellaneous Interrupt Register (MIR)
All interrupt requests associated with MCM are collected in the MIR register. This includes the processor
core system bus fault interrupt.
During the appropriate interrupt service routine handling these requests, the interrupt source contained in
the MCMIR must be explicitly cleared. See Figure 119 and Table 119.
Register address: MCM Base + 0x001F
0
1
2
3
4
5
6
7
R
FB0AI
FB0SI
FB1AI
FB1SI
0
0
0
0
W
1
1
1
1
XXXXXXX
XXXXXXX
XXXXXXX
XXXXXXX
RESET:
0
0
0
0
0
0
0
0
XXXXXXX
= Unimplemented
Figure 119. Miscellaneous Interrupt (MIR) Register
Table 119. Miscellaneous Interrupt (MIR) Field Descriptions
Name
Description
0
FB0AI
Flash Bank 0 Abort Interrupt
0: A flash bank 0 abort has not occurred.
1: A flash bank 0 abort has occurred. The interrupt request is negated by writing a 1 to this bit. Writing a 0 has no
effect.
1
FB0SI
Flash Bank 0 Stall Interrupt
0: A flash bank 0 stall has not occurred.
1: A flash bank 0 stall has occurred. The interrupt request is negated by writing a 1 to this bit. Writing a 0 has no
effect.
2
FB1AI
Flash Bank 1 Abort Interrupt
0: A flash bank 1 abort has not occurred.
1: A flash bank 1 abort has occurred. The interrupt request is negated by writing a 1 to this bit. Writing a 0 has no
effect.
3
FB1SI
Flash Bank 1 Stall Interrupt
0: A flash bank 1 stall has not occurred.
1: A flash bank 1 stall has occurred. The interrupt request is negated by writing a 1 to this bit. Writing a 0 has no
effect.
16.4.2.5
Miscellaneous User-Defined Control Register (MUDCR)
The MUDCR provides a program-visible register for user-defined control functions. It typically is used as
configuration control for miscellaneous SoC-level modules. The contents of this register is simply output
from MCM to other modules where the user-defined control functions are implemented. See Figure 120
and Table 120 for the Miscellaneous User-Defined Control Register definition.
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Register address: MCM Base + 0x0024
RESET:
RESET:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 120. Miscellaneous User-Defined Control (MUDCR) Register
Table 120. Miscellaneous User-Defined Control Register (MUDCR) Field Descriptions
Name
Description
MUDCR
AXBS_lite force_round_robin bit (MUDCR[31])When the AXBS_lite is included on the platform, this bit is used to drive the force_round_robin bit of the
AXBS_lite. This will force the slaves into round robin mode of arbitration rather than fixed mode. Unless
a master is using priority elevation, which forces the design back into fixed mode regardless of this bit. By
defining the ‘define ENABLE_ROUND_ROBIN_RESET, this bit will reset to 1.
AXBS_lite is in round robin mode
AXBS_lite is in fixed priority mode
16.4.2.6
ECC registers
There are a number of program-visible registers for the sole purpose of reporting and logging of memory
failures. These registers include the following:
• ECC Configuration Register (ECR)
• ECC Status Register (ESR)
• ECC Error Generation Register (EEGR)
• Flash ECC Address Register (FEAR)
• Flash ECC Master Number Register (FEMR)
• Flash ECC Attributes Register (FEAT)
• Flash ECC Data Register (FEDR)
• RAM ECC Address Register (REAR)
• RAM ECC Syndrome Register (RESR)
• RAM ECC Master Number Register (REMR)
• RAM ECC Attributes Register (REAT)
• RAM ECC Data Register (REDR)
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Miscellaneous Control Module (MCM)
The details on the ECC registers are provided in the subsequent sections. If the design does not include
ECC on the memories, these addresses are reserved locations within the MCM’s programming model.
16.4.2.7
ECC Configuration Register (ECR)
The ECC Configuration Register is an 8-bit control register for specifying which types of memory errors
are reported. In all systems with ECC, the occurrence of a non-correctable error causes the current access
to be terminated with an error condition. In many cases, this error termination is reported directly by the
initiating bus master. However, there are certain situations where the occurrence of this type of
non-correctable error is not reported by the master. Examples include speculative instruction fetches which
are discarded due to a change-of-flow operation, and buffered operand writes. The ECC reporting logic in
the MCM provides an optional error interrupt mechanism to signal all non-correctable memory errors. In
addition to the interrupt generation, the MCM captures specific information (memory address, attributes
and data, bus master number, etc.) which may be useful for subsequent failure analysis.
The reporting of single-bit memory corrections can only be enabled via a an SoC-configurable module
input signal. While not directly accessible to a user, this capability is viewed as important for error logging
and failure analysis.
See Figure 121 and Table 121 for the ECC Configuration Register definition.
Register address: MCM Base + 0x0043
R
0
1
0
0
2
3
ER1BR
EF1BR
0
0
4
5
0
0
6
7
ERNCR
EFNCR
0
0
W
RESET:
0
0
0
0
= Unimplemented
Figure 121. ECC Configuration (ECR) Register
Table 121. ECC Configuration (ECR) Field Definitions
Name
2
ER1BR
Description
Enable RAM 1-bit Reporting
0 = Reporting of single-bit RAM corrections is disabled.
1 = Reporting of single-bit RAM corrections is enabled.
This bit can only be set if the SoC-configurable input enable signal is asserted. The occurrence of a single-bit RAM
correction generates a MCM ECC interrupt request as signalled by the assertion of ESR[R1BC]. The address,
attributes and data are also captured in the REAR, RESR, REMR, REAT and REDR registers.
3
EF1BR
Enable Flash 1-bit Reporting
0 = Reporting of single-bit flash corrections is disabled.
1 = Reporting of single-bit flash corrections is enabled.
This bit can only be set if the SoC-configurable input enable signal is asserted. The occurrence of a single-bit flash
correction generates a MCM ECC interrupt request as signalled by the assertion of ESR[F1BC]. The address,
attributes and data are also captured in the FEAR, FEMR, FEAT and FEDR registers.
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Miscellaneous Control Module (MCM)
Table 121. ECC Configuration (ECR) Field Definitions
Name
6
ERNCR
Description
Enable RAM Non-Correctable Reporting
0 = Reporting of non-correctable RAM errors is disabled.
1 = Reporting of non-correctable RAM errors is enabled.
The occurrence of a non-correctable multi-bit RAM error generates a MCM ECC interrupt request as signalled by
the assertion of ESR[RNCE]. The faulting address, attributes and data are also captured in the REAR, RESR,
REMR, REAT and REDR registers.
7
EFNCR
Enable Flash Non-Correctable Reporting
0 = Reporting of non-correctable flash errors is disabled.
1 = Reporting of non-correctable flash errors is enabled.
The occurrence of a non-correctable multi-bit flash error generates a MCM ECC interrupt request as signalled by
the assertion of ESR[FNCE]. The faulting address, attributes and data are also captured in the FEAR, FEMR, FEAT
and FEDR registers.
16.4.2.8
ECC Status Register (ESR)
The ECC Status Register is an 8-bit control register for signaling which types of properly-enabled ECC
events have been detected. The ESR signals the last, properly-enabled memory event to be detected. ECC
interrupt generation is separated into single-bit error detection/correction, uncorrectable error detection
and the combination of the two as defined by the following boolean equations:
MCM_ECC1BIT_IRQ
= ECR[ER1BR] & ESR[R1BC]
| ECR[EF1BR] & ESR[F1BC]
MCM_ECCRNCR_IRQ
= ECR[ERNCR] & ESR[RNCE]
MCM_ECCFNCR_IRQ
= ECR[EFNCR] & ESR[FNCE]
MCM_ECC2BIT_IRQ
= MCM_ECCRNCR_IRQ
| MCM_ECCFNCR_IRQ
MCM_ECC_IRQ
= MCM_ECC1BIT_IRQ
| MCM_ECC2BIT_IRQ
// ram, 1-bit correction
// flash, 1-bit correction
// ram, noncorrectable error
// flash, noncorrectable error
// ram, noncorrectable error
// flash, noncorrectable error
// 1-bit correction
// noncorrectable error
where the combination of a properly-enabled category in the ECR and the detection of the corresponding
condition in the ESR produces the interrupt request.
The MCM allows a maximum of one bit of the ESR to be asserted at any given time. This preserves the
association between the ESR and the corresponding address and attribute registers, which are loaded on
each occurrence of an properly-enabled ECC event. If there is a pending ECC interrupt and another
properly-enabled ECC event occurs, the MCM hardware automatically handles the ESR reporting,
clearing the previous data and loading the new state and thus guaranteeing that only a single flag is
asserted.
To maintain the coherent software view of the reported event, the following sequence in the MCM error
interrupt service routine is suggested:
1. Read the ESR and save it.
2. Read and save all the address and attribute reporting registers.
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3. Re-read the ESR and verify the current contents matches the original contents. If the two values
are different, go back to step 1 and repeat.
4. When the values are identical, write a 1 to the asserted ESR flag to negate the interrupt request.
See Figure 122 and Table 122 for the ECC Status Register definition.
Register address: MCM Base + 0x0047
R
0
1
2
3
4
5
6
7
0
0
R1BC
F1BC
0
0
RNCE
FNCE
0
0
0
0
0
0
0
0
W
RESET:
= Unimplemented
Figure 122. ECC Status (ESR) Register
Table 122. ECC Status (ESR) Field Definitions
Name
2
R1BC
Description
RAM 1-bit Correction
0 = No reportable single-bit RAM correction has been detected.
1 = A reportable single-bit RAM correction has been detected.
This bit can only be set if ECR[EPR1BR] is asserted. The occurrence of a properly-enabled single-bit RAM
correction generates a MCM ECC interrupt request. The address, attributes and data are also captured in the
REAR, RESR, REMR, REAT and REDR registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has
no effect.
3
F1BC
Flash 1-bit Correction
0 = No reportable single-bit flash correction has been detected.
1 = A reportable single-bit flash correction has been detected.
This bit can only be set if ECR[EPF1BR] is asserted. The occurrence of a properly-enabled single-bit flash
correction generates a MCM ECC interrupt request. The address, attributes and data are also captured in the
FEAR, FEMR, FEAT and FEDR registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect.
6
RNCE
RAM Non-Correctable Error
0 = No reportable non-correctable RAM error has been detected.
1 = A reportable non-correctable RAM error has been detected.
The occurrence of a properly-enabled non-correctable RAM error generates a MCM ECC interrupt request. The
faulting address, attributes and data are also captured in the REAR, RESR, REMR, REAT and REDR registers. To
clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect.
7
FNCE
Flash Non-Correctable Error
0 = No reportable non-correctable flash error has been detected.
1 = A reportable non-correctable flash error has been detected.
The occurrence of a properly-enabled non-correctable flash error generates a MCM ECC interrupt request. The
faulting address, attributes and data are also captured in the FEAR, FEMR, FEAT and FEDR registers. To clear
this interrupt flag, write a 1 to this bit. Writing a 0 has no effect.
In the event that multiple status flags are signaled simultaneously, MCM records the event with the R1BC
as highest priority, then F1BC, then RNCE, and finally FNCE.
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Miscellaneous Control Module (MCM)
16.4.2.9
ECC Error Generation Register (EEGR)
The ECC Error Generation Register is a 16-bit control register used to force the generation of single- and
double-bit data inversions in the memories with ECC, most notably the RAM. This capability is provided
for two purposes:
• It provides a software-controlled mechanism for “injecting” errors into the memories during data
writes to verify the integrity of the ECC logic.
• It provides a mechanism to allow testing of the software service routines associated with memory
error logging.
It should be noted that while the EEGR is associated with the RAM, similar capabilities exist for the flash,
i.e., the ability to program the non-volatile memory with single- or double-bit errors is supported for the
same two reasons previously identified.
For both types of memories (RAM and flash), the intent is to generate errors during data write cycles, such
that subsequent reads of the corrupted address locations generate ECC events, either single-bit corrections
or double-bit noncorrectable errors that are terminated with an error response.
The enabling of these error generation modes requires the same SoC-configurable input enable signal (as
that used to enable single-bit correction reporting) be asserted.
See Figure 123 and Table 123 for the ECC Configuration Register definition.
Register address: MCM Base + 0x004a
R
0
1
0
0
3
FRC1B FR11BI
4
5
6
7
8
0
0
FRCN
FR1
0
CI
NCI
0
0
I
W
RESET:
2
0
0
0
0
0
0
0
9
10
11
12
13
14
15
0
0
0
ERRBIT[0:6]
0
0
0
0
= Unimplemented
Figure 123. ECC Error Generation (EEGR) Register
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Table 123. ECC Error Generation (EEGR) Field Definitions
Name
Description
2
Force RAM Continuous 1-Bit Data Inversions
FRC1BI 0 = No RAM continuous 1-bit data inversions are generated.
1 = 1-bit data inversions in the RAM are continuously generated.
The assertion of this bit forces the RAM controller to create 1-bit data inversions, as defined by the bit position
specified in ERRBIT[0:6], continuously on every write operation.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position defined by
ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.
After this bit has been enabled to generate another continuous 1-bit data inversion, it must be cleared before being
set again to properly re-enable the error generation logic.
This bit can only be set if the same SoC configurable input enable signal (as that used to enable single-bit correction
reporting) is asserted.
3
FR11BI
Force RAM One 1-bit Data Inversion
0 = No RAM single 1-bit data inversion is generated.
1 = One 1-bit data inversion in the RAM is generated.
The assertion of this bit forces the RAM controller to create one 1-bit data inversion, as defined by the bit position
specified in ERRBIT[0:6], on the first write operation after this bit is set.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position defined by
ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.
After this bit has been enabled to generate a single 1-bit data inversion, it must be cleared before being set again to
properly re-enable the error generation logic.
This bit can only be set if the same SoC configurable input enable signal (as that used to enable single-bit correction
reporting) is asserted.
6
Force RAM Continuous Noncorrectable Data Inversions
FRCNCI 0 = No RAM continuous 2-bit data inversions are generated.
1 = 2-bit data inversions in the RAM are continuously generated.
The assertion of this bit forces the RAM controller to create 2-bit data inversions, as defined by the bit position
specified in ERRBIT[0:6] and the overall odd parity bit, continuously on every write operation.
After this bit has been enabled to generate another continuous noncorrectable data inversion, it must be cleared
before being set again to properly re-enable the error generation logic.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position defined by
ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.
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Table 123. ECC Error Generation (EEGR) Field Definitions (continued)
Name
Description
7
Force RAM One Noncorrectable Data Inversions
FR1NCI 0 = No RAM single 2-bit data inversions are generated.
1 = One 2-bit data inversion in the RAM is generated.
The assertion of this bit forces the RAM controller to create one 2-bit data inversion, as defined by the bit position
specified in ERRBIT[0:6] and the overall odd parity bit, on the first write operation after this bit is set.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position defined by
ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.
After this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again to properly
re-enable the error generation logic.
9-15
Error Bit Position
ERRBIT The vector defines the bit position which is complemented to create the data inversion on the write operation. For
[0:6]
the creation of 2-bit data inversions, the bit specified by this field plus the odd parity bit of the ECC code are inverted.
The RAM controller follows a vector bit ordering scheme where LSB=0. Errors in the ECC syndrome bits can be
generated by setting this field to a value greater than the RAM width. For example, consider a 32-bit RAM
implementation.
The 32-bit ECC approach requires 7 code bits for a 32-bit word. For PRAM data width of 32 bits, the actual SRAM
(32b data + 7b for ECC) = 39 bits. The following association between the ERRBIT field and the corrupted memory
bit is defined:
if ERRBIT = 0, then RAM[0] of the odd bank is inverted
if ERRBIT = 1, then RAM[1] of the odd bank is inverted
...
if ERRBIT = 31, then RAM[31] of the odd bank is inverted
if ERRBIT = 64, then ECC Parity[0] of the odd bank is inverted
if ERRBIT = 65, then ECC Parity[1] of the odd bank is inverted
...
if ERRBIT = 70, then ECC Parity[6] of the odd bank is inverted
For ERRBIT values of 32 to 63 and greater than 70, no bit position is inverted.
If an attempt to force a non-correctable inversion (by asserting EEGR[FRCNCI] or EEGR[FRC1NCI])
and EEGR[ERRBIT] equals 64, then no data inversion will be generated.
The only allowable values for the 4 control bit enables {FR11BI, FRC1BI, FRCNCI, FR1NCI} are
{0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. All other values result in undefined behavior.
16.4.2.10 Flash ECC Address Register (FEAR)
The FEAR is a 32-bit register for capturing the address of the last, properly-enabled ECC event in the flash
memory. Depending on the state of the ECC Configuration Register, an ECC event in the flash causes the
address, attributes and data associated with the access to be loaded into the FEAR, FEMR, FEAT and
FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 124 and Table 124 for the Flash ECC Address Register definition.
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Register address: MCM Base + 0x0050
0
1
2
3
4
5
6
7
R
8
9
10
11
12
13
14
15
FEAR[0:15]
W
RESET:
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
-
-
-
-
-
-
-
R
FEAR[16:31]
W
RESET:
-
-
-
-
-
-
-
-
-
= Unimplemented
Figure 124. Flash ECC Address (FEAR) Register
Table 124. Flash ECC Address (FEAR) Field Descriptions
Name
Description
0-31
FEAR[0:31]
Flash ECC Address Register
This 32-bit register contains the faulting access address of the last, properly-enabled flash ECC event.
16.4.2.11 Flash ECC Master Number Register (FEMR)
The FEMR is a 4-bit register for capturing the AXBS bus master number of the last, properly-enabled ECC
event in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event in
the flash causes the address, attributes and data associated with the access to be loaded into the FEAR,
FEMR, FEAT and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register
to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 125 and Table 125 for the Flash ECC Master Number Register definition.
Register address: MCM Base + 0x0056
R
0
1
2
3
0
0
0
0
0
0
0
0
4
5
6
7
-
-
FEMR[0:3]
W
RESET:
-
-
= Unimplemented
Figure 125. Flash ECC Master Number (FEMR) Register
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Miscellaneous Control Module (MCM)
Table 125. Flash ECC Master Number (FEMR) Field Descriptions
Name
Description
4-7
FEMR[0:3]
Flash ECC Master Number Register
This 4-bit register contains the AXBS bus master number of the faulting access of the last, properly-enabled
flash ECC event.
16.4.2.12 Flash ECC Attributes (FEAT) register
The FEAT is an 8-bit register for capturing the AXBS bus master attributes of the last, properly-enabled
ECC event in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event
in the flash causes the address, attributes and data associated with the access to be loaded into the FEAR,
FEMR, FEAT and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register
to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 126 and Table 126 for the Flash ECC Attributes Register definition.
Register address: MCM Base + 0x0057
0
R
1
Write
2
3
4
5
Size[0:2]
6
7
Protection[0:3]
W
RESET:
-
-
-
-
-
-
-
-
= Unimplemented
Figure 126. Flash ECC Attributes (FEAT) Register
Table 126. Flash ECC Attributes (FEAT) Field Descriptions
Name
0
Write
1-3
Size[0:2]
4-7
Protection[0:3]
Description
AMBA-AHB HWRITE
0 = AMBA-AHB read access
1 = AMBA-AHB write access
AMBA-AHB HSIZE[0:2]
0b000 = 8-bit AMBA-AHB access
0b001 = 16-bit AMBA-AHB access
0b010 = 32-bit AMBA-AHB access
0b1xx = Reserved
AMBA-AHB HPROT[0:3]
Protection[3]: Cacheable 0 = Non-cacheable,1 = Cacheable
Protection[2]: Bufferable0 = Non-bufferable,1 = Bufferable
Protection[1]: Mode 0 = User mode, 1 = Supervisor mode
Protection[0]: Type 0 = I-Fetch, 1 = Data
16.4.2.13 Flash ECC Data Register (FEDR)
The FEDR is a 32-bit register for capturing the data associated with the last, properly-enabled ECC event
in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event in the flash
causes the address, attributes and data associated with the access to be loaded into the FEAR, FEMR,
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FEAT and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register to be
asserted.
The data captured on a multi-bit non-correctable ECC error is undefined.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 127 and Table 127 for the Flash ECC Data Register definition.
Register address: MCM Base +0x005C
0
1
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
FEDR[0:15]
W
RESET:
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
-
-
-
-
-
-
-
R
FEDR[16:31]
W
RESET:
-
-
-
-
-
-
-
-
-
= Unimplemented
Figure 127. Flash ECC Data (FEDR) Register
Table 127. Flash ECC Data (FEDR) Field Descriptions
Name
0-31
FEDR[0:31]
Description
Flash ECC Data Register
This 32-bit register contains the data associated with the faulting access of the last, properly-enabled flash
ECC event. The register contains the data value taken directly from the data bus.
16.4.2.14 RAM ECC Address Register (REAR)
The REAR is a 32-bit register for capturing the address of the last, properly-enabled ECC event in the
RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the RAM
causes the address, attributes and data associated with the access to be loaded into the REAR, RESR,
REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register
to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 128 and Table 128 for the RAM ECC Address Register definition.
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Miscellaneous Control Module (MCM)
Register address: MCM Base + 0x0060
0
1
2
3
4
5
6
7
R
8
9
10
11
12
13
14
15
REAR[0:15]
W
RESET:
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
-
-
-
-
-
-
-
R
REAR[16:31]
W
RESET:
-
-
-
-
-
-
-
-
-
= Unimplemented
Figure 128. RAM ECC Address (REAR) Register
Table 128. RAM ECC Address (REAR) Field Descriptions
Name
Description
0-31
REAR[0:31]
RAM ECC Address Register
This 32-bit register contains the faulting access address of the last, properly-enabled RAM ECC event.
16.4.2.15 RAM ECC Syndrome Register (RESR)
The RESR is an 8-bit register for capturing the error syndrome of the last, properly-enabled ECC event in
the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the RAM
causes the address, attributes and data associated with the access to be loaded into the REAR, RESR,
REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register
to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 129 and Table 129 for the RAM ECC Syndrome Register definition.
Register address: MCM Base + 0x0065
0
1
2
3
R
4
5
6
7
-
-
-
-
RESR[0:7]
W
RESET:
-
-
-
-
= Unimplemented
Figure 129. RAM ECC Syndrome (RESR) Register
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Table 129. RAM ECC Syndrome (RESR) Field Descriptions
Name
Description
0-7
RESR[0:7]
RAM ECC Syndrome Register
This 8-bit syndrome field includes 6 bits of Hamming decoded parity plus an odd-parity bit for the entire 39-bit
(32-bit data + 7 ECC) code word. The upper 7 bits of the syndrome specify the exact bit position in error for
single-bit correctable codewords, and the combination of a non-zero 7-bit syndrome plus overall incorrect parity
bit signal a multi-bit, non-correctable error.
For correctable single-bit errors, the mapping shown in Table 129 associates the upper 7 bits of the syndrome
with the data bit in error.
Note: Table 129 associates the upper 7 bits of the ECC syndrome with the exact data bit in error for single-bit correctable
codewords. This table follows the bit vectoring notation where the LSB=0. Note that the syndrome value of 0x0001 implies
no error condition but this value is not readable when the PRESR is read for the no error case.
Table 130. RAM Syndrome Mapping for Single-Bit Correctable Errors
RESR[0:7]
Data Bit in Error
0x0000
ECC ODD[0]
0x0001
No Error
0x0002
ECC ODD[1]
0x0004
ECC ODD[2]
0x0006
DATA ODD BANK[31]
0x0008
ECC ODD[3]
0x000a
DATA ODD BANK[30]
0x000c
DATA ODD BANK[29]
0x000e
DATA ODD BANK[28]
0x0010
ECC ODD[4]
0x0012
DATA ODD BANK[27]
0x0014
DATA ODD BANK[26]
0x0016
DATA ODD BANK[25]
0x0018
DATA ODD BANK[24]
0x001a
DATA ODD BANK[23]
0x001c
DATA ODD BANK[22]
0x0050
DATA ODD BANK[21]
0x0020
ECC ODD[5]
0x0022
DATA ODD BANK[20]
0x0024
DATA ODD BANK[19]
0x0026
DATA ODD BANK[18]
0x0028
DATA ODD BANK[17]
0x002a
DATA ODD BANK[16]
0x002c
DATA ODD BANK[15]
0x0058
DATA ODD BANK[14]
0x0030
DATA ODD BANK[13]
0x0032
DATA ODD BANK[12]
0x0034
DATA ODD BANK[11]
0x0064
DATA ODD BANK[10]
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Miscellaneous Control Module (MCM)
Table 130. RAM Syndrome Mapping for Single-Bit Correctable Errors (continued)
RESR[0:7]
Data Bit in Error
0x0038
DATA ODD BANK[9]
0x0062
DATA ODD BANK[8]
0x0070
DATA ODD BANK[7]
0x0060
DATA ODD BANK[6]
0x0040
ECC ODD[6]
0x0042
DATA ODD BANK[5]
0x0044
DATA ODD BANK[4]
0x0046
DATA ODD BANK[3]
0x0048
DATA ODD BANK[2]
0x004a
DATA ODD BANK[1]
0x004c
DATA ODD BANK[0]
0x0003,0x0005........0x
004d
Multiple bit error
> 0x004d
Multiple bit error
16.4.2.16 RAM ECC Master Number Register (REMR)
The REMR is a 4-bit register for capturing the AXBS bus master number of the last, properly-enabled ECC
event in the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in
the RAM causes the address, attributes and data associated with the access to be loaded into the REAR,
RESR, REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status
Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 130 and Table 131 for the RAM ECC Master Number Register definition.
Register address: MCM Base + 0x0066
R
0
1
2
3
0
0
0
0
0
0
0
0
4
5
6
7
-
-
REMR[0:3]
W
RESET:
-
-
= Unimplemented
Figure 130. RAM ECC Master Number (REMR) Register
Table 131. RAM ECC Master Number (REMR) Field Descriptions
Name
Description
4-7
REMR[0:3]
RAM ECC Master Number Register
This 4-bit register contains the AXBS bus master number of the faulting access of the last, properly-enabled
RAM ECC event.
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16.4.2.17 RAM ECC Attributes (REAT) register
The REAT is an 8-bit register for capturing the AXBS bus master attributes of the last, properly-enabled
ECC event in the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event
in the RAM causes the address, attributes and data associated with the access to be loaded into the REAR,
RESR, REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status
Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 131 and Table 132 for the RAM ECC Attributes Register definition.
Register address: MCM Base + 0x0067
0
R
1
Write
2
3
4
5
Size[0:2]
6
7
Protection[0:3]
W
RESET:
-
-
-
-
-
-
-
-
= Unimplemented
Figure 131. RAM ECC Attributes (REAT) Register
Table 132. RAM ECC Attributes (REAT) Field Descriptions
Name
0
Write
1-3
Size[0:2]
4-7
Protection[0:3]
Description
AMBA-AHB HWRITE
0 = AMBA-AHB read access
1 = AMBA-AHB write access
AMBA-AHB HSIZE[0:2]
0b000 = 8-bit AMBA-AHB access
0b001 = 16-bit AMBA-AHB access
0b010 = 32-bit AMBA-AHB access
0b1xx = Reserved
AMBA-AHB HPROT[0:3]
Protection[3]: Cacheable 0 = Non-cacheable, 1 = Cacheable
Protection[2]: Bufferable 0 = Non-bufferable,1 = Bufferable
Protection[1]: Mode 0 = User mode, 1 = Supervisor mode
Protection[0]: Type 0 = I-Fetch, 1 = Data
16.4.2.18 RAM ECC Data Register (REDR)
The REDR is a 32-bit register for capturing the data associated with the last, properly-enabled ECC event
in the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the
RAM causes the address, attributes and data associated with the access to be loaded into the REAR, RESR,
REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register
to be asserted.
The data captured on a multi-bit non-correctable ECC error is undefined.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 132 and Table 133 for the RAM ECC Data Register definition.
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Miscellaneous Control Module (MCM)
Register address: MCM Base +0x006c
0
1
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
REDR[0:15]
W
RESET:
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
-
-
-
-
-
-
-
R
REDR[16:31]
W
RESET:
-
-
-
-
-
-
-
-
-
= Unimplemented
Figure 132. RAM ECC Data (REDR) Register
Table 133. RAM ECC Data (REDR) Field Descriptions
16.4.3
Name
Description
0-31
REDR[0:31]
RAM ECC Data Register
This 32-bit register contains the data associated with the faulting access of the last,
properly-enabled RAM ECC event. The register contains the data value taken directly from
the data bus.
MCM_reg_protection
The MCM_reg_protection logic provides hardware enforcement of supervisor mode access protection for
four on-platform IPS modules: INTC, MCM, STM, and SWT. This logic resides between the on-platform
bus sourced by the AIPS bus controller and the individual slave modules. It monitors the bus access type
(supervisor or user) and if a user access is attempted, the transfer is terminated with an error and inhibited
from reaching the slave module. Identical logic is replicated for each of the five, targeted slave modules.
A block diagram of the MCM_reg_protection module is shown in Figure 133.
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INTC
ips_supervisor_access
MCM
AIPS_LITE
MCM_REG_PROTECTION
STM
SWT
Figure 133. Spp_Ips_Reg_Protection block diagram
Attempted accesses to reserved addresses result in an error termination, while attempted writes to
read-only registers are ignored and do not terminate with an error. Unless noted otherwise, writes to the
programming model must match the size of the register; for example, an n-bit register only supports n-bit
writes, etc. Attempted writes of a different size than the register width produce an error termination of the
bus cycle and no change to the targeted register.
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Chapter 17
Internal Static RAM (SRAM)
17.1
Introduction
The general-purpose SRAM has a size of 96 KB.
The SRAM provides the following features:
• SRAM can be read/written from any bus master
• Byte, halfword, word and doubleword addressable
• Single-bit correction and double-bit error detection
17.2
SRAM operating mode
The SRAM has only one operating mode. No standby mode is available.
Table 134. SRAM operating modes
17.3
Mode
Configuration
Normal (functional)
Allows reads and writes of SRAM
Register memory map
The SRAM occupies 96 KB of memory starting at the base address as shown in Table 135.
Table 135. SRAM memory map
Address
Register name
Register description
Size
0x4000_0000 (Base)
—
—
96 KB
The internal SRAM has no registers. Registers for the SRAM ECC are located in the MCM .
17.4
SRAM ECC mechanism
The SRAM ECC detects the following conditions and produces the following results:
• Detects and corrects all 1-bit errors
• Detects and flags all 2-bit errors as non-correctable errors
• Detects 39-bit reads (32-bit data bus plus the 7-bit ECC) that return all zeros or all ones, asserts an
error indicator on the bus cycle, and sets the error flag
SRAM does not detect all errors greater than 2 bits.
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Internal Static RAM (SRAM)
Internal SRAM write operations are performed on the following byte boundaries:
• 1 byte (0:7 bits)
• 2 bytes (0:15 bits)
• 4 bytes or 1 word (0:31 bits)
If the entire 32 data bits are written to SRAM, no read operation is performed and the ECC is calculated
across the 32-bit data bus. The 8-bit ECC is appended to the data segment and written to SRAM.
If the write operation is less than the entire 32-bit data width (1 or 2-byte segment), the following occurs:
1. The ECC mechanism checks the entire 32-bit data bus for errors, detecting and either correcting or
flagging errors.
2. The write data bytes (1or 2-byte segment) are merged with the corrected 32 bits on the data bus.
3. The ECC is then calculated on the resulting 32 bits formed in the previous step.
4. The 7-bit ECC result is appended to the 32 bits from the data bus, and the 39-bit value is then
written to SRAM.
17.4.1
Access timing
The system bus is a two-stage pipelined bus that makes the timing of any access dependent on the access
during the previous clock. Table 136 lists the various combinations of read and write operations to SRAM
and the number of wait states used for the each operation. The table columns contain the following
information:
• Current operation—Lists the type of SRAM operation currently executing
• Previous operation—Lists the valid types of SRAM operations that can precede the current SRAM
operation (valid operation during the preceding clock)
• Wait states—Lists the number of wait states (bus clocks) the operation requires, which depends on
the combination of the current and previous operation
Table 136. Number of wait states required for SRAM operations
Operation type
Current operation
Previous operation
Number of wait states required
Read
Read
Idle
1
Pipelined read
8 , 16 or 32-bit write
0
(read from the same address)
1
(read from a different address)
Pipelined read
Read
0
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Internal Static RAM (SRAM)
Table 136. Number of wait states required for SRAM operations (continued)
Operation type
Current operation
Previous operation
Number of wait states required
Write
8 or 16-bit write
Idle
1
Read
Pipelined 8- or 16-bit write
2
32-bit write
8 or 16-bit write
0
(write to the same address)
Pipelined 8, 16 or 32-bit write
8 , 16 or 32-bit write
0
32-bit write
Idle
0
32-bit write
Read
17.4.2
Reset effects on SRAM accesses
Asynchronous reset will possibly corrupt RAM if it asserts during a read or write operation to SRAM. The
completion of that access depends on the cycle at which the reset occurs. If no access is occurring when
reset occurs, RAM corruption does not happen.
Instead synchronous reset (SW reset) should be used in controlled function (without RAM accesses) in
case initialization procedure is needed without RAM initialization.
17.5
Functional description
ECC checks are performed during the read portion of an SRAM ECC read/write (R/W) operation, and
ECC calculations are performed during the write portion of a R/W operation. Because the ECC bits can
contain random data after the device is powered on, the SRAM must be initialized by executing 32-bit
write operations prior any read accesses. This is also true for implicit read accesses caused by any write
accesses smaller than 32 bits as discussed in Section 17.4, “SRAM ECC mechanism”.
17.6
Initialization and application information
To use the SRAM, the ECC must check all bits that require initialization after power on. All writes must
specify an even number of registers performed on 32-bit word-aligned boundaries. If the write is not the
entire 32-bits (8 or 16 bits), a read/modify/write operation is generated that checks the ECC value upon
the read. Refer to Section 17.4, “SRAM ECC mechanism”.
NOTE
You must initialize SRAM, even if the application does not use ECC
reporting.
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Chapter 18
Flash Memory
18.1
Introduction
The flash memory comprises a platform flash controller interface and two flash memory arrays: one array
of KB for code (code flash) and one array of 64 KB for data (data flash). The flash architecture of the
MPC5604E device is illustrated in Figure 134.
AHB CROSSBAR SWITCH
AHB ports
32
4x128 Page Buffer
1x128 Page Buffer
PFlash Controller
512 KB
Code Flash
64 KB
Data Flash
Array 0
Array 1
Bank0 (code flash)
Bank1 (data flash)
Figure 134. MPC5604E flash memory architecture
MPC5604E flash memory is arranged as follows:
Array0 (code flash):
• 512 KB + 16 KB shadow block + 16 KB test block
• 8 small blocks organized as 16 KB, 16 KB, 32 KB, 32 KB, 16 KB, 16 KB, 64 KB and 64 KB
• 2 large blocks organized as 128 KB and 128 KB
• 1 Shadow block, 16 KB
• 1 Test block, 16 KB
Array1 (data flash):
• 64 KB + 8 KB test block
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Flash Memory
•
•
4 small blocks organized as 16 KB, 16 KB, 16 KB, 16 KB,
1 Test block, 8 KB
18.2
Platform flash controller
18.2.1
Introduction
This section provides an introduction of the platform flash controller, which acts as the interface between
the system bus and as many as two banks of flash memory arrays (program and data). It intelligently
converts the protocols between the system bus and the dedicated flash array interfaces. Several important
terms are used to describe the platform flash controller module and its connections. These terms are
defined here.
• Port—This term describes the AMBA-AHB connection(s) into the platform flash controller. From
an architectural and programming model viewpoint, the definition supports as many as two AHB
ports, even though this specific controller only supports a single AHB connection.
• Bank—This term describes the attached flash memories. From the platform flash controller’s
perspective, there may be one or two attached banks of flash memory. The code flash bank is
required and always attached to bank0. Additionally, there is a data flash attached to bank1. The
platform flash controller interface supports two separate connections, one to each memory bank.
On the MPC5604E device, bank0 and bank1 are internal to the device.
• Array—Each memory bank has one flash array instantiation.
• Page—This value defines the number of bits read from the flash array in a single access. For this
controller and memory, the page size is 128 bits (16 bytes).
The nomenclature “page buffers” and “line buffers” are used interchangeably.
18.2.1.1
Overview
The platform flash controller supports a 32-bit data bus width at the AHB port and connections to 128-bit
read data interfaces from two memory banks, where each bank contains one instantiation of the flash
memory array. One flash bank is connected to the code flash memory and the other bank is connected to
the data flash memory. The memory controller capabilities vary between the two banks with each bank’s
functionality optimized with the typical use cases associated with the attached flash memory. As an
example, the platform flash controller logic associated with the code flash bank contains a four-entry
“page” buffer, each entry containing 128 bits of data (1 flash page) plus an associated controller that
prefetches sequential lines of data from the flash array into the buffer, while the controller logic associated
with the data flash bank only supports a 128-bit register that serves as a temporary page holding register
and does not support any prefetching. Prefetch buffer hits from the code flash bank support 0-wait AHB
data phase responses. AHB read requests that miss the buffers generate the needed flash array access and
are forwarded to the AHB upon completion, typically incurring two wait states at an operating frequency
of 60 to 64 MHz.
This memory controller is optimized for applications where a cacheless processor core, for example the
Power e200z0h, is connected through the platform to on-chip memories, for example flash and RAM,
where the processor and platform operate at the same frequency. For these applications, the 2-stage
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pipeline AMBA-AHB system bus is effectively mapped directly into stages of the processor’s pipeline and
0 wait state responses for most memory accesses are critical for providing the required level of system
performance.
18.2.1.2
Features
The following list summarizes the key features of the platform flash controller:
• Single AHB port interface supports a 32-bit data bus. All AHB aligned and unaligned reads within
the 32-bit container are supported. Only aligned word writes are supported.
• Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each bank.
• Interface with code flash provides configurable read buffering and page prefetch support. Four
page read buffers (each 128 bits wide) and a prefetch controller support single-cycle read responses
(0 AHB data phase wait states) for hits in the buffers. The buffers implement a least-recently-used
replacement algorithm to maximize performance.
• Interface with data flash includes a 128-bit register to temporarily hold a single flash page. This
logic supports single-cycle read responses (0 AHB data phase wait states) for accesses that hit in
the holding register. There is no support for prefetching associated with bank1.
• Programmable response for read-while-write sequences including support for stall-while-write,
optional stall notification interrupt, optional flash operation termination, and optional termination
notification interrupt
• Separate and independent configurable access timing (on a per bank basis) to support use across a
wide range of platforms and frequencies
• Support of address-based read access timing for emulation of other memory types
• Support for reporting of single- and multi-bit flash ECC events
• Typical operating configuration loaded into programming model by system reset
18.2.2
Modes of operation
The platform flash controller module does not support any special modes of operation. Its operation is
driven from the AMBA-AHB memory references it receives from the platform’s bus masters. Its
configuration is defined by the setting of the programming model registers, physically located as part of
the flash array modules.
18.2.3
External signal descriptions
The platform flash controller does not directly interface with any external signals. Its primary internal
interfaces include a connection to an AMBA-AHB crossbar (or memory protection unit) slave port and
connections with as many as two banks (code and data) of flash memory, each containing one instantiation
of the flash array. Additionally, the operating configuration for the platform flash controller is defined by
the contents of certain code flash array0 registers that are inputs to the module.
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18.2.4
Memory map and registers description
Two memory maps are associated with the platform flash controller: one for the flash memory space and
another for the program-visible control and configuration registers. The flash memory space is accessed
via the AMBA-AHB port. The program-visible registers are accessed via the slave peripheral bus. Details
on both memory spaces are provided in Section 18.2.4.1, “Memory map”.
There are no program-visible registers that physically reside inside the platform flash controller. Rather,
the platform flash controller receives control and configuration information from the flash array
controller(s) to determine the operating configuration. These are part of the flash array’s configuration
registers mapped into its slave peripheral (IPS) address space but are described here.
18.2.4.1
Memory map
First, consider the flash memory space accessed via transactions from the platform flash controller’s AHB
port. To support the two separate flash memory banks, the platform flash controller uses address bit 23
(haddr[23]) to steer the access to the appropriate memory bank. In addition to the actual flash memory
regions, there are shadow and test sectors included in the system memory map. The program-visible
control and configuration registers associated with each memory array are included in the slave peripheral
address region. The system memory map defines one code flash array and one data flash array. See
Table 137.
Table 137. Flash-related regions in the system memory map
Start address
End address
Size
(KB)
Region
0x0000_0000
0x0000_3FFF
16
0x0000_4000
0x0000_7FFF
16
0x0000_8000
0x0000_FFFF
32
0x0001_0000
0x0000_17FF
32
0x0001_8000
0x0001_BFFF
16
0x0001_C000
0x0001_FFFF
16
0x0002_0000
0x0002_FFFF
64
0x0003_0000
0x0003_FFFF
64
0x0004_0000
0x0005_FFFF
128
0x0006_0000
0x0007_FFFF
128
0x0008_0000
0x001F_FFFF
1536
Reserved
0x0020_0000
0x0020_3FFF
16
Code Flash Array 0 Shadow Sector
0x0020_4000
0x003F_FFFF
2032
Reserved
0x0040_0000
0x0040_3FFF
16
Code Flash Array 0 Test Sector
0x0040_4000
0x005F_FFFF
2032
Reserved
0x0080_0000
0x0080_3FFF
16
Data Flash Array 0
Code Flash Array 0
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Table 137. Flash-related regions in the system memory map (continued)
Start address
Size
(KB)
End address
Region
0x0080_4000
0x0080_7FFF
16
Data Flash Array 0
0x0080_8000
0x0080_BFFF
16
Data Flash Array 0
0x0080_C000
0x0080_FFFF
16
Data Flash Array 0
0x0081_0000
0x009F_FFFF
1984
Reserved
0x00A0_0000
0x00BF_FFFF
2048
Reserved
0x00C0_0000
0x00C0_1FFF
8
Reserved
0x00C0_2000
0x00C0_3FFF
8
Data Flash Test Sector
0x00C0_4000
0x00FF_FFFF
4080
Reserved
For additional information on the address-based read access timing for emulation of other memory types,
see Section 18.2.17, “Wait state emulation”.
Next, consider the memory map associated with the control and configuration registers.
There are registers that control operation of the platform flash controller. Note the first two flash array
registers (PFCR0, PFCR1) are reset to a device-defined value, while the remaining register (PFAPR) is
loaded at reset from specific locations in the array’s shadow region.
Regardless of the number of populated banks or the number of flash arrays included in a given bank, the
configuration of the platform flash controller is wholly specified by the platform flash controller control
registers associated with code flash array0. The code array0 register settings define the operating behavior
of both flash banks. It is recommended to set the platform flash controller control registers for both arrays
to the array0 values.
NOTE
To perform program and erase operations, the control registers in the actual
referenced flash array must both be programmed, but the configuration of
the platform flash controller module is defined by the platform flash
controller control registers of code array0.
The 32-bit memory map for the platform flash controller control registers is shown in Table 138.
Table 138. Platform Flash Controller 32-bit memory map
Offset from
PFLASH_BASE
(0xFFE8_8000)
Register
Access
0x001C
Platform Flash Configuration Register 0 (PFCR0)
R/W
0x0020
Platform Flash Configuration Register 1 (PFCR1)
R/W
0x0024
Platform Flash Access Protection Register (PFAPR)
R/W
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18.2.4.2
Registers description
This section details the individual registers of the platform flash controller. The platform flash registers
control flash behavior globally.
18.2.4.2.1
Platform Flash Configuration Register 0 (PFCR0)
The Platform Flash Configuration Register 0 (PFCR0) defines the configuration associated with flash
memory bank0, which corresponds to the code flash. The register is described in Figure 135 and
Table 139.
NOTE
This register is not implemented on the data flash block.
PFCR0[BK0_APC] must equal to PFCR0[BK0_RWSC]. Refer datasheet
for correct setting of RWSC.
0
1
Access: User read/write
2
3
4
5
6
7
8
9
10
11
12
13
14
R
W
0
1
1
0
0
0
1
1
0
0
0
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
B0_P0_IPFE
1
0
0
0
0
0
0
0
1
0
1
Reset
1
1
1
B0_P0_BFE
B0_P0_PFLM
0
B0_P0_DPFE
W
0
B0_P0_BCFG
R
BK0_RWSC
BK0_RWWC
Reset
BK0_WWSC
BK0_RWWC
BK0_APC
15
BK0_RWWC
Address: Base + 0x001C
0
1
Figure 135. Platform Flash Configuration Register 0 (PFCR0)
Table 139. PFCR0 field descriptions
Field
BK0_APC
Description
Bank0 Address Pipelining Control
This field controls the number of cycles between flash array access requests. This field must be
set to a value appropriate to the operating frequency of the PFLASH. Higher operating frequencies
require non-zero settings for this field for proper flash operation. This field is set to 0b00010 by
hardware reset.
00000
00001
00010
...
11110
11111
Accesses may be initiated on consecutive (back-to-back) cycles.
Access requests require one additional hold cycle.
Access requests require two additional hold cycles.
Access requests require 30 additional hold cycles.
Access requests require 31 additional hold cycles.
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Table 139. PFCR0 field descriptions (continued)
Field
BK0_WWSC
Description
Bank0 Write Wait State Control
This field controls the number of wait states to be added to the flash array access time for writes.
This field must be set to a value appropriate to the operating frequency of the PFLASH. Higher
operating frequencies require non-zero settings for this field for proper flash operation. This field
is set to an appropriate value by hardware reset. This field is set to 0b00010 by hardware reset.
00000
00001
00010
...
111111
BK0_RWSC
No additional wait states are added.
1 additional wait state is added.
2 additional wait states are added.
31 additional wait states are added.
Bank0 Read Wait State Control
This field controls the number of wait states to be added to the flash array access time for reads.
This field must be set to a value corresponding to the operating frequency of the PFLASH and the
actual read access time of the PFLASH. Higher operating frequencies require non-zero settings
for this field for proper flash operation.
0 MHz, < 23 MHz
23 MHz, < 45 MHz
45 MHz, < 68 MHz
68 MHz, < 90 MHz
APC = RWSC = 0.
APC = RWSC = 1.
APC = RWSC = 2.
APC = RWSC = 3.
This field is set to 0b00010 by hardware reset.
00000
00001
00010
...
111111
BK0_RWWC
No additional wait states are added.
1 additional wait state is added.
2 additional wait states are added.
31 additional wait states are added.
Bank0 Read-While-Write Control
This 3-bit field defines the controller response to flash reads while the array is busy with a program
(write) or erase operation.
0xx
100
101
110
111
Reserved. This configuration should be avoided.
Generate a bus stall for a read while write/erase, enable the operation termination and
the abort notification interrupt.
Generate a bus stall for a read while write/erase, enable the operation abort, disable
the abort notification interrupt.
Generate a bus stall for a read while write/erase, enable the stall notification interrupt,
disable the abort + abort notification interrupt.
Generate a bus stall for a read while write/erase, disable the stall notification interrupt,
disable the abort + abort notification interrupt.
This field is set to 0b111 by hardware reset enabling the stall-while-write/erase and disabling the
abort and notification interrupts.
Reserved
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Table 139. PFCR0 field descriptions (continued)
Field
B0_P0_BCFG
Description
Bank0, Port 0 Page Buffer Configuration
This field controls the configuration of the four page buffers in the PFLASH controller. The buffers
can be organized as a “pool” of available resources, or with a fixed partition between instruction
and data buffers.
If enabled, when a buffer miss occurs, it is allocated to the least-recently-used buffer within the
group and the just-fetched entry then marked as most-recently-used. If the flash access is for the
next-sequential line, the buffer is not marked as most-recently-used until the given address
produces a buffer hit.
00 All four buffers are available for any flash access, that is, there is no partitioning of the buffers
based on the access type.
01 Reserved.
10 The buffers are partitioned into two groups with buffers 0 and 1 allocated for instruction fetches
and buffers 2 and 3 for data accesses.
11 The buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches
and buffer 3 for data accesses.
This field is set to 2b11 by hardware reset.
B0_P0_DPFE
Bank0, Port 0 Data Prefetch Enable
This field enables or disables prefetching initiated by a data read access. This field is cleared by
hardware reset.
0 No prefetching is triggered by a data read access.
1 If page buffers are enabled (B0_P0_BFE = 1), prefetching is triggered by any data read access.
B0_P0_IPFE
Bank0, Port 0 Instruction Prefetch Enable
This field enables or disables prefetching initiated by an instruction fetch read access. This field is
set by hardware reset.
0 No prefetching is triggered by an instruction fetch read access.
1 If page buffers are enabled (B0_P0_BFE = 1), prefetching is triggered by any instruction fetch
read access.
B0_P0_PFLM
Bank0, Port 0 Prefetch Limit
This field controls the prefetch algorithm used by the PFLASH controller. This field defines the
prefetch behavior. In all situations when enabled, only a single prefetch is initiated on each buffer
miss or hit. This field is set to 2b10 by hardware reset.
00 No prefetching is performed.
01 The referenced line is prefetched on a buffer miss, that is, prefetch on miss.
1x The referenced line is prefetched on a buffer miss, or the next sequential page is prefetched
on a buffer hit (if not already present), that is, prefetch on miss or hit.
B0_P0_BFE
Bank0, Port 0 Buffer Enable
This bit enables or disables page buffer read hits. It is also used to invalidate the buffers. This bit
is set by hardware reset.
0 The page buffers are disabled from satisfying read requests, and all buffer valid bits are cleared.
1 The page buffers are enabled to satisfy read requests on hits. Buffer valid bits may be set when
the buffers are successfully filled.
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18.2.4.2.2
Platform Flash Configuration Register 1 (PFCR1)
The Platform Flash Configuration Register 1 (PFCR1) defines the configuration associated with flash
memory bank1. This corresponds to the data flash. The register is described in Figure 136 and Table 140.
NOTE
This register is not implemented on the data flash block.
PFCR1[BK1_APC] must equal to PFCR1[BK1_RWSC]. Refer datasheet
for correct setting of RWSC.
0
1
Access: User read/write
2
3
4
5
6
7
8
9
10
11
12
13
14
R
W
Reset
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
B1_P0_BFE
W
BK1_RWSC
BK1_RWWC
R
BK1_WWSC
BK1_RWWC
Reset
BK1_APC
15
BK1_RWWC
Address: Base + 0x0020
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
Figure 136. Platform Flash Configuration Register 1 (PFCR1)
Table 140. PFCR1 field descriptions
Field
Description
BK1_APC
Bank1 Address Pipelining Control
This field controls the number of cycles between flash array access requests. This field must be set
to a value appropriate to the operating frequency of the PFLASH. Higher operating frequencies
require non-zero settings for this field for proper flash operation. This field is set to 0b00010 by
hardware reset.
00000
00001
00010
...
11110
11111
Accesses may be initiated on consecutive (back-to-back) cycles.
Access requests require one additional hold cycle.
Access requests require two additional hold cycles.
Access requests require 30 additional hold cycles.
Access requests require 31 additional hold cycles.
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Table 140. PFCR1 field descriptions (continued)
Field
Description
BK1_WWSC Bank1 Write Wait State Control
This field controls the number of wait states to be added to the flash array access time for writes. This
field must be set to a value appropriate to the operating frequency of the PFLASH. Higher operating
frequencies require non-zero settings for this field for proper flash operation. This field is set to an
appropriate value by hardware reset. This field is set to 0b00010 by hardware reset.
00000
00001
00010
...
111111
No additional wait states are added.
1 additional wait state is added.
2 additional wait states are added.
31 additional wait states are added.
BK1_RWSC Bank1 Read Wait State Control
This field controls the number of wait states to be added to the flash array access time for reads. This
field must be set to a value corresponding to the operating frequency of the PFLASH and the actual
read access time of the PFLASH. Higher operating frequencies require non-zero settings for this field
for proper flash operation.
0 MHz, < 23 MHz
23 MHz, < 45 MHz
45 MHz, < 68 MHz
68 MHz, < 90 MHz
APC = RWSC = 0.
APC = RWSC = 1.
APC = RWSC = 2.
APC = RWSC = 3.
This field is set to 0b00010 by hardware reset.
00000
00001
00010
...
111111
No additional wait states are added.
1 additional wait state is added.
2 additional wait states are added.
31 additional wait states are added.
BK1_RWWC Bank1 Read-While-Write Control
This 3-bit field defines the controller response to flash reads while the array is busy with a program
(write) or erase operation.
0xx Reserved. This configuration should be avoided.
100 Generate a bus stall for a read while write/erase, enable the operation abort and the abort
notification interrupt.
101 Generate a bus stall for a read while write/erase, enable the operation abort, disable the abort
notification interrupt.
110 Generate a bus stall for a read while write/erase, enable the stall notification interrupt, disable
the abort + abort notification interrupt.
111 Generate a bus stall for a read while write/erase, disable the stall notification interrupt, disable
the abort + abort notification interrupt.
This field is set to 0b111 by hardware reset enabling the stall-while-write/erase and disabling the abort
and notification interrupts.
Reserved, should be cleared.
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Table 140. PFCR1 field descriptions (continued)
Field
Description
Bank1, Port 0 Buffer Enable
B1_P0_PFE This bit enables or disables read hits from the 32-bit holding register. It is also used to invalidate the
contents of the holding register. This bit is set by hardware reset, enabling the use of the holding
register.
0 The holding register is disabled from satisfying read requests.
1 The holding register is enabled to satisfy read requests on hits.
18.2.4.2.3
Platform Flash Access Protection Register (PFAPR)
The Platform Flash Access Protection Register (PFAPR) controls read and write accesses to the flash based
on system master number. Prefetching capabilities are defined on a per master basis. This register also
defines the arbitration mode for controllers supporting two AHB ports. The register is described in
Figure 137 and Table 141.
The contents of the register are loaded from location 0x20_3E00 of the shadow region in the code flash
(bank0) array at reset. To temporarily change the values of any of the fields in the PFAPR, a write to the
IPS-mapped register is performed. To change the values loaded into the PFAPR at reset, the word location
at address 0x20_3E00 of the shadow region in the flash array must be programmed using the normal
sequence of operations. The reset value shown in Table 137 reflects an erased or unprogrammed value
from the shadow region.
NOTE
This register is not implemented on the data flash block.
Address: Base + 0x0024
R
Access: User read/write
0
1
2
3
4
5
0
0
0
0
0
0
1
1
1
1
1
1
1
16
17
18
19
20
21
22
W
Reset
R
W
Reset
M7AP
1
M6AP
1
1
1
M5AP
1
1
6
7
8
9
10
0
0
0
1
1
1
1
1
1
1
1
1
23
24
25
26
27
28
29
30
31
ARBM
M4AP
1
1
M3AP
1
1
11
M2AP
1
12
13
14
15
M4
M3
M2
M1
M0
PFD PFD PFD PFD PFD
1
M1AP
1
1
M0AP
1
1
Figure 137. Platform Flash Access Protection Register (PFAPR)
Table 141. PFAPR field descriptions
Field
Description
Reserved, should be cleared.
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Table 141. PFAPR field descriptions (continued)
Field
ARBM
Description
Arbitration Mode
This 2-bit field controls the arbitration for PFLASH controllers supporting 2 AHB ports.
00 Fixed priority arbitration with AHB p0 > p1.
01 Fixed priority arbitration with AHB p1 > p0.
1x Round-robin arbitration.
MxPFD
Master x Prefetch Disable (x = 0,1,2,...,7)
These bits control whether prefetching may be triggered based on the master number of the requesting
AHB master. This field is further qualified by the PFCR0[B0_Px_DPFE, B0_Px_IPFE, Bx_Py_BFE]
bits.
0 Prefetching may be triggered by this master.
1 No prefetching may be triggered by this master.
MxAP
Master x Access Protection (x = 0,1,2,...,7)
These fields control whether read and write accesses to the flash are allowed based on the master
number of the initiating module.
00
01
10
11
18.2.5
No accesses may be performed by this master.
Only read accesses may be performed by this master.
Only write accesses may be performed by this master.
Both read and write accesses may be performed by this master.
Functional description
The platform flash controller interfaces between the AHB-Lite 2.v6 system bus and the flash memory
arrays.
The platform flash controller generates read and write enables, the flash array address, write size, and write
data as inputs to the flash array. The platform flash controller captures read data from the flash array
interface and drives it onto the AHB. As much as four pages of data (128-bit width) from bank0 are
buffered by the platform flash controller. Lines may be prefetched in advance of being requested by the
AHB interface, allowing single-cycle (0 AHB wait states) read data responses on buffer hits.
Several prefetch control algorithms are available for controlling page read buffer fills. Prefetch triggering
may be restricted to instruction accesses only, data accesses only, or may be unrestricted. Prefetch
triggering may also be controlled on a per-master basis.
Buffers may also be selectively enabled or disabled for allocation by instruction and data prefetch.
Access protections may be applied on a per-master basis for both reads and writes to support security and
privilege mechanisms.
Throughout this discussion, bkn_ is used as a prefix to refer to two signals, each for each bank: bk0_ and
bk1_. Also, the nomenclature Bx_Py_RegName is used to reference a program-visible register field
associated with bank “x” and port “y”.
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18.2.6
Basic interface protocol
The platform flash controller interfaces to the flash array by driving addresses (bkn_fl_addr[23:0]) and
read or write enable signals (bkn_fl_rd_en, bkn_fl_wr_en).
The read or write enable signal (bkn_fl_rd_en, bkn_fl_wr_en) is asserted in conjunction with the reference
address for a single rising clock when a new access request is made.
Addresses are driven to the flash array in a flow-through fashion to minimize array access time. When no
outstanding access is in progress, the platform flash controller drives addresses and asserts bkn_fl_rd_en
or bkn_fl_wr_en and then may change to the next outstanding address in the next cycle.
Accesses are terminated under control of the appropriate read/write wait state control setting. Thus, the
access time of the operation is determined by the settings of the wait state control fields. Access timing
can be varied to account for the operating conditions of the device (frequency, voltage, temperature) by
appropriately setting the fields in the programming model for either bank.
The platform flash controller also has the capability of extending the normal AHB access time by inserting
additional wait states for reads and writes. This capability is provided to allow emulation of other
memories that have different access time characteristics. The added wait state specifications are provided
by bit 28 to bit 24 of Flash address (haddr[28:24], see Table 143 and Table 144). These wait states are
applied in addition to the normal wait states incurred for flash accesses. Refer to Section 18.2.17, “Wait
state emulation”, for more details.
Prefetching of next sequential page is blocked when haddr[28:24] is non-zero. Buffer hits are also blocked
as well, regardless of whether the access corresponds to valid data in one of the page read buffers. These
steps are taken to ensure that timing emulation is correct and that excessive prefetching is avoided. In
addition, to prevent erroneous operation in certain rare cases, the buffers are invalidated on any
non-sequential AHB access with a non-zero value on haddr[28:24].
18.2.7
Access protections
The platform flash controller provides programmable configurable access protections for both read and
write cycles from masters via the Platform Flash Access Protection Register (PFAPR). It allows restriction
of read and write requests on a per-master basis. This functionality is described in Section 18.2.4.2.3,
“Platform Flash Access Protection Register (PFAPR)”. Detection of a protection violation results in an
error response from the platform flash controller on the AHB transfer.
18.2.8
Read cycles — buffer miss
Read cycles from the flash array are initiated by driving a valid access address on bkn_fl_addr[23:0] and
asserting bkn_fl_rd_en for the required setup (and hold) time before (and after) the rising edge of hclk.
The platform flash controller then waits for the programmed number of read wait states before sampling
the read data on bkn_fl_rdata[127:0]. This data is normally stored in the least-recently updated page read
buffer for bank0 in parallel with the requested data being forwarded to the AHB. For bank1, the data is
captured in the page-wide temporary holding register as the requested data is forwarded to the AHB bus.
Timing diagrams of basic read accesses from the flash array are shown in Figure 138 through Figure 141.
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If the flash access was the direct result of an AHB transaction, the page buffer is marked as
most-recently-used as it is being loaded. If the flash access was the result of a speculative prefetch to the
next sequential line, it is first loaded into the least-recently-used buffer. The status of this buffer is not
changed to most-recently-used until a subsequent buffer hit occurs.
18.2.9
Read cycles — buffer hit
Single cycle read responses to the AHB are possible with the platform flash controller when the requested
read access was previously loaded into one of the bank0 page buffers. In these “buffer hit” cases, read data
is returned to the AHB data phase with a 0 wait state response.
Likewise, the bank1 logic includes a single 32-bit temporary holding register and sequential accesses that
“hit” in this register are also serviced with a 0 wait state response.
18.2.10 Write cycles
In a write cycle, address, write data, and control signals are launched off the same edge of hclk at the
completion of the first AHB data phase cycle. Write cycles to the flash array are initiated by driving a valid
access address on bkn_fl_addr[23:0], driving write data on bkn_fl_wdata[63:0], and asserting
bkn_fl_wr_en. Again, the controller drives the address and control information for the required setup time
before the rising edge of hclk, and provides the required amount of hold time. The platform flash controller
then waits for the appropriate number of write wait states before terminating the write operation. On the
cycle following the programmed wait state value, the platform flash controller asserts hready_out to
indicate to the AHB port that the cycle has terminated.
18.2.11 Error termination
The platform flash controller follows the standard procedure when an AHB bus cycle is terminated with
an ERROR response. First, the platform flash controller asserts hresp[0] and negates hready_out to signal
an error has occurred. On the following clock cycle, the platform flash controller asserts hready_out and
holds both hresp[0] and hready_out asserted until hready_in is asserted.
The first case that can cause an error response to the AHB is when an access is attempted by an AHB
master whose corresponding Read Access Control or Write Access Control settings do not allow the
access, thus causing a protection violation. In this case, the platform flash controller does not initiate a
flash array access.
The second case that can cause an error response to the AHB is when an access is performed to the flash
array and is terminated with a flash error response. See Section 18.2.13, “Flash error response operation”.
This may occur for either a read or a write operation.
The third case that can cause an error response to the AHB is when a write access is attempted to the flash
array and is disallowed by the state of the bkn_fl_ary_access control input. This case is similar to case 1.
A fourth case involves an attempted read access while the flash array is busy doing a write (program) or
erase operation if the appropriate read-while-write control field is programmed for this response. The 3-bit
read-while-write control allows for immediate termination of an attempted read, or various
stall-while-write/erase operations are occurring.
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The platform flash controller can also terminate the current AHB access if hready_in is asserted before the
end of the current bus access. While this circumstance should not occur, this does not result in an error
condition being reported, as this behavior is initiated by the AHB. In this circumstance, the platform flash
controller control state machine completes any flash array access in progress (without signaling the AHB)
before handling a new access request.
18.2.12 Access pipelining
The platform flash controller does not support access pipelining since this capability is not supported by
the flash array. As a result, the APC (Address Pipelining Control) field should typically be the same value
as the RWSC (Read Wait State Control) field for best performance, that is, BKn_APC = BKn_RWSC. It
cannot be less than the RWSC.
18.2.13 Flash error response operation
The flash array may signal an error response by asserting bkn_fl_xfr_err to terminate a requested access
with an error. This may occur due to an uncorrectable ECC error, or because of improper sequencing
during program/erase operations. When an error response is received, the platform flash controller does
not update or validate a bank0 page read buffer nor the bank1 temporary holding register. An error
response may be signaled on read or write operations. For more information on the specifics related to
signaling of errors, including flash ECC, refer to subsequent sections in this chapter.
18.2.14 Bank0 page read buffers and prefetch operation
The logic associated with bank0 of the platform flash controller contains four 128-bit page read buffers
that hold data read from the flash array. Each buffer operates independently, and is filled using a single
array access. The buffers are used for both prefetch and normal demand fetches.
The organization of each page buffer is described as follows in a pseudo-code representation. The
hardware structure includes the buffer address and valid bit, along with 128 bits of page read data and
several error flags.
struct {
}
// bk0_page_buffer
reg
addr[23:4];// page address
reg
valid;
// valid bit
reg
rdata[127:0];// page read data
reg
xfr_error;
// transfer error indicator from flash array
reg
multi_ecc_error;// multi-bit ECC error indicator from flash array
reg
single_ecc_error;// single-bit correctable ECC indicator from flash array
bk0_page_buffer[4];
For the general case, a page buffer is written at the completion of an error-free flash access and the valid
bit asserted. Subsequent flash accesses that “hit” the buffer, that is, the current access address matches the
address stored in the buffer, can be serviced in 0 AHB wait states as the stored read data is routed from the
given page buffer back to the requesting bus master.
As noted in Section 18.2.13, “Flash error response operation”, a page buffer is not marked as valid if the
flash array access terminated with any type of transfer error. However, the result is that flash array accesses
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that are tagged with a single-bit correctable ECC event are loaded into the page buffer and validated. For
additional comments on this topic, see Section 18.2.14.4, “Buffer invalidation”.
Prefetch triggering is controllable on a per-master and access-type basis. Bus masters may be enabled or
disabled from triggering prefetches, and triggering may be further restricted based on whether a read
access is for instruction or data. A read access to the platform flash controller may trigger a prefetch to the
next sequential page of array data on the first idle cycle following the request. The access address is
incremented to the next-higher 16-byte boundary, and a flash array prefetch is initiated if the data is not
already resident in a page buffer. Prefetched data is always loaded into the least-recently-used buffer.
Buffers may be in one of six states, listed here in prioritized order:
1. Invalid—the buffer contains no valid data.
2. Used—the buffer contains valid data that has been provided to satisfy an AHB burst type read.
3. Valid—the buffer contains valid data that has been provided to satisfy an AHB single type read.
4. Prefetched—the buffer contains valid data that has been prefetched to satisfy a potential future
AHB access.
5. Busy AHB—the buffer is currently being used to satisfy an AHB burst read.
6. Busy Fill—the buffer has been allocated to receive data from the flash array, and the array access
is still in progress.
Selection of a buffer to be loaded on a miss is based on the following replacement algorithm:
1. First, the buffers are examined to determine if there are any invalid buffers. If there are multiple
invalid buffers, the one to be used is selected using a simple numeric priority, where buffer 0 is
selected first, then buffer 1, etc.
2. If there are no invalid buffers, the least-recently-used buffer is selected for replacement.
Once the candidate page buffer has been selected, the flash array is accessed and read data loaded into the
buffer. If the buffer load was in response to a miss, the just-loaded buffer is immediately marked as
most-recently-used. If the buffer load was in response to a speculative fetch to the next-sequential line
address after a buffer hit, the recently-used status is not changed. Rather, it is marked as most-recently-used
only after a subsequent buffer hit.
This policy maximizes performance based on reference patterns of flash accesses and allows for
prefetched data to remain valid when non-prefetch enabled bus masters are granted flash access.
Several algorithms are available for prefetch control that trade off performance versus power. They are
defined by the Bx_Py_PFLM (prefetch limit) register field. More aggressive prefetching increases power
slightly due to the number of wasted (discarded) prefetches, but may increase performance by lowering
average read latency.
In order for prefetching to occur, a number of control bits must be enabled. Specifically, the global buffer
enable (Bx_Py_BFE) must be set, the prefetch limit (Bx_Py_PFLM) must be non-zero and either
instruction prefetching (Bx_Py_IPFE) or data prefetching (Bx_Py_DPFE) enabled. Refer to
Section 18.2.4.2, “Registers description”, for a description of these control fields.
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18.2.14.1 Instruction/data prefetch triggering
Prefetch triggering may be enabled for instruction reads via the Bx_Py_IPFE control field, while
prefetching for data reads is enabled via the Bx_Py_DPFE control field. Additionally, the Bx_Py_PFLIM
field must also be set to enable prefetching. Prefetches are never triggered by write cycles.
18.2.14.2 Per-master prefetch triggering
Prefetch triggering may be also controlled for individual bus masters. AHB accesses indicate the
requesting master via the hmaster[3:0] inputs. Refer to Section 18.2.4.2.3, “Platform Flash Access
Protection Register (PFAPR)” for details on these controls.
18.2.14.3 Buffer allocation
Allocation of the line read buffers is controlled via page buffer configuration (Bx_Py_BCFG) field. This
field defines the operating organization of the four page buffers. The buffers can be organized as a “pool”
of available resources (with all four buffers in the pool) or with a fixed partition between buffers allocated
to instruction or data accesses. For the fixed partition, two configurations are supported. In one
configuration, buffers 0 and 1 are allocated for instruction fetches and buffers 2 and 3 for data accesses. In
the second configuration, buffers 0, 1, and 2 are allocated for instruction fetches and buffer 3 reserved for
data accesses.
18.2.14.4 Buffer invalidation
The page read buffers may be invalidated under hardware or software control.
Any falling edge transition of the array’s bkn_fl_done signal causes the page read buffers to be marked as
invalid. This input is negated by the flash array at the beginning of all program/erase operations as well as
in certain other cases. Buffer invalidation occurs at the next AHB non-sequential access boundary, but does
not affect a burst from a page read buffer in progress.
Software may invalidate the buffers by clearing the Bx_Py_BFE bit, which also disables the buffers.
Software may then re-assert the Bx_Py_BFE bit to its previous state, and the buffers will have been
invalidated.
One special case needing software invalidation relates to page buffer “hits” on flash data that was tagged
with a single-bit ECC event on the original array access. Recall that the page buffer structure includes an
status bit signaling the array access detected and corrected a single-bit ECC error. On all subsequent buffer
hits to this type of page data, a single-bit ECC event is signaled by the platform flash controller. Depending
on the specific hardware configuration, this reporting of a single-bit ECC event may generate an ECC alert
interrupt. In order to prevent repeated ECC alert interrupts, the page buffers need to be invalidated by
software after the first notification of the single-bit ECC event.
Finally, the buffers are invalidated by hardware on any non-sequential access with a non-zero value on
haddr[28:24] to support wait state emulation.
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18.2.15 Bank1 temporary holding register
Recall the bank1 logic within the flash includes a single 128-bit data register, used for capturing read data.
Since this bank does not support prefetching, the read data for the referenced address is bypassed directly
back to the AHB data bus. The page is also loaded into the temporary data register and subsequent accesses
to this page can hit from this register, if it is enabled (B1_Py_BFE).
The organization of the temporary holding register is described as follows, in a pseudo-code
representation. The hardware structure includes the buffer address and valid bit, along with 128 bits of
page read data and several error flags and is the same as an individual bank0 page buffer.
struct {
}
// bk1_page_buffer
reg
addr[23:4];// page address
reg
valid;
// valid bit
reg
rdata[127:0];// page read data
reg
xfr_error;
// transfer error indicator from flash array
reg
multi_ecc_error;// multi-bit ECC error indicator from flash array
reg
single_ecc_error;// single-bit correctable ECC indicator from flash array
bk1_page_buffer;
For the general case, a temporary holding register is written at the completion of an error-free flash access
and the valid bit asserted. Subsequent flash accesses that “hit” the buffer, that is, the current access address
matches the address stored in the temporary holding register, can be serviced in 0 AHB wait states as the
stored read data is routed from the temporary register back to the requesting bus master.
The contents of the holding register are invalidated by the falling edge transition of bk1_fl_done and on
any non-sequential access with a non-zero value on haddr[28:24] (to support wait state emulation) in the
same manner as the bank0 page buffers. Additionally, the B1_Py_BFE register bit can be cleared by
software to invalidate the contents of the holding register.
As noted in Section 18.2.13, “Flash error response operation”, the temporary holding register is not
marked as valid if the flash array access terminated with any type of transfer error. However, the result is
that flash array accesses that are tagged with a single-bit correctable ECC event are loaded into the
temporary holding register and validated. Accordingly, one special case needing software invalidation
relates to holding register “hits” on flash data that was tagged with a single-bit ECC event. Depending on
the specific hardware configuration, the reporting of a single-bit ECC event may generate an ECC alert
interrupt. In order to prevent repeated ECC alert interrupts, the page buffers need to be invalidated by
software after the first notification of the single-bit ECC event.
The bank1 temporary holding register effectively operates like a single page buffer.
18.2.16 Read-While-Write functionality
The platform flash controller supports various programmable responses for read accesses while the flash
is busy performing a write (program) or erase operation. For all situations, the platform flash controller
uses the state of the flash array’s bkn_fl_done output to determine if it is busy performing some type of
high-voltage operation, namely, if bkn_fl_done = 0, the array is busy.
Specifically, there are two 3-bit read-while-write (BKn_RWWC) control register fields that define the
platform flash controller’s response to these types of access sequences. There are five unique responses
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that are defined by the BKn_RWWC setting: one immediately reports an error on an attempted read, and
four settings that support various stall-while-write capabilities. Consider the details of these settings.
• BKn_RWWC = 0b0xx
— For this mode, any attempted flash read to a busy array is immediately terminated with an AHB
error response and the read is blocked in the controller and not seen by the flash array.
• BKn_RWWC = 0b111
— This defines the basic stall-while-write capability and represents the default reset setting. For
this mode, the platform flash controller module stalls any read reference until the flash has
completed its program/erase operation. If a read access arrives while the array is busy or if a
falling-edge on bkn_fl_done occurs while a read is still in progress, the AHB data phase is
stalled by negating hready_out and saving the address and attributes into holding registers.
Once the array has completed its program/erase operation, the platform flash controller uses
the saved address and attribute information to create a pseudo address phase cycle to “retry”
the read reference and sends the registered information to the array as bkn_fl_rd_en is asserted.
Once the retried address phase is complete, the read is processed normally and once the data is
valid, it is forwarded to the AHB bus and hready_out negated to terminate the system bus
transfer.
• BKn_RWWC = 0b110
— This setting is similar to the basic stall-while-write capability provided when
BKn_RWWC = 0b111 with the added ability to generate a notification interrupt if a read
arrives while the array is busy with a program/erase operation. There are two notification
interrupts, one for each bank.
• BKn_RWWC = 0b101
— Again, this setting provides the basic stall-while-write capability with the added ability to
terminate any program/erase operation if a read access is initiated. For this setting, the read
request is captured and retried as described for the basic stall-while-write, plus the
program/erase operation is terminated by the platform flash controller’s assertion of the
bkc_fl_abort signal. The bkn_fl_abort signal remains asserted until bkn_fl_done is driven high.
For this setting, there are no notification interrupts generated.
• BKn_RWWC = 0b100
— This setting provides the basic stall-while-write capability with the ability to terminate any
program/erase operation if a read access is initiated plus the generation of a termination
notification interrupt. For this setting, the read request is captured and retried as described for
the basic stall-while-write, the program/erase operation is terminated by the platform flash
controller’s assertion of the bkn_fl_abort signal and a termination notification interrupt
generated. There are two termination notification interrupts, one for each bank.
As detailed above, there are a total of four interrupt requests associated with the stall-while-write
functionality. These interrupt requests are captured as part of MCM’s Interrupt Register and logically
summed together to form a single request to the interrupt controller.
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Table 142. Platform flash controller stall-while-write interrupts
MIR[n]
Interrupt description
MCM.MIR[7]
Platform flash bank0 termination notification, MIR[FB0AI]
MCM.MIR[6]
Platform flash bank0 stall notification, MIR[FB0SI]
MCM.MIR[5]
Platform flash bank1 termination notification, MIR[FB1AI]
MCM.MIR[4]
Platform flash bank1 stall notification, MIR[FB1S1]
For example timing diagrams of the stall-while-write and terminate-while-write operations, see Figure 142
and Figure 143 respectively.
18.2.17 Wait state emulation
Emulation of other memory array timings are supported by the platform flash controller on read cycles to
the flash. This functionality may be useful to maintain the access timing for blocks of memory that were
used to overlay flash blocks for the purpose of system calibration or tuning during code development.
The platform flash controller inserts additional wait states according to the values of haddr[28:24],where
haddr represents the Flash address. When these inputs are non-zero, additional cycles are added to AHB
read cycles. Write cycles are not affected. In addition, no page read buffer prefetches are initiated, and
buffer hits are ignored.
Table 143 and Table 144 show the relationship of haddr[28:24] to the number of additional primary wait
states. These wait states are applied to the initial access of a burst fetch or to single-beat read accesses on
the AHB system bus.
Note that the wait state specification consists of two components: haddr[28:26] and haddr[25:24] and
effectively extends the flash read by (8 × haddr[25:24] + haddr[28:26]) cycles.
Table 143. Additional wait state encoding
Memory address
haddr[28:26]
Additional wait states
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
Table 144 shows the relationship of haddr[25:24] to the number of additional wait states. These are applied
in addition to those specified by haddr[28:26] and thus extend the total wait state specification capability.
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Table 144. Extended additional wait state encoding
Memory address
haddr[25:24]
Additional wait states
(added to those specified by
haddr[28:26])
00
0
01
8
10
16
11
24
18.2.18 Timing diagrams
Since the platform flash controller is typically used in platform configurations with a cacheless core, the
operation of the processor accesses to the platform memories, for example flash and SRAM, plays a major
role in the overall system performance. Given the core/platform pipeline structure, the platform’s memory
controllers (PFLASH, PRAM) are designed to provide a 0 wait state data phase response to maximize
processor performance. The following diagrams illustrate operation of various cycle types and responses
referenced earlier in this chapter including stall-while-read (Figure 142) and terminate-while-read
(Figure 143) diagrams.
Read, no buffering, no prefetch, APC = 0, RWSC = 0, PFLM = 0
1
2
3
4
5
6
7
8
okay
okay
okay
hclk
htrans
nonseq
haddr, hprot
addr y
seq
seq
seq
addr y+4
addr y+12
addr y+8
hwrite
C(y)
hrdata
C(y+4)
C(y+8)
C(y+12)
hwdata
hready_out
hresp
bkn_fl_addr
okay
okay
y
okay
y+4
okay
y+8
okay
y+12
bkn_fl_rd_en
addr y
addr y+4
addr y+8 addr+12
bkn_fl_wr_en
bkn_fl_rdata
C(y)
C(y+4)
C(y+8)
C(y+12)
Figure 138. 1-cycle access, no buffering, no prefetch
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Burst Read, buffer miss, no prefetch, APC=2, RWSC=2, PFLM=0
1
2
3
4
5
6
7
8
hclk
htrans
nonseq
seq
haddr,hprot
addr y
addr y+4
seq
seq
addr y+8
addr y+12
hwrite
C(y)
hrdata
C(y+4)
hwdata
hready_out
hresp
bkn_fl_addr
okay
okay
y
okay
okay
okay
okay
okay
y+4
okay
y+8
bkn_fl_rd_en
addr y
addr y+4
addr y+8
C(y)
C(y+4)
bkn_fl_wr_en
bkn_fl_rdata
bkn_fl_xfr_err
Figure 139. 3-cycle access, no prefetch, buffering disabled
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Burst Read, buffer miss, no prefetch, APC = 2, RWSC = 2, PFLM = 0
1
2
3
4
5
6
7
8
hclk
htrans
nonseq
haddr,hprot
addr y
seq
seq
addr y+8
addr y+4
seq
addr y+12
hwrite
C(y)
hrdata
C(y+4)
C(y+8)
C(y+12)
hwdata
hready_out
hresp
okay
bkn_fl_addr
okay
okay
okay
okay
okay
okay
okay
Y
bkn_fl_wr_en
addr y
bkn_fl_wr_en
bkn_fl_rdata
C(y)
bkn_fl_xfr_err
Figure 140. 3-cycle access, no prefetch, buffering enabled
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Burst Read, buffer miss, prefetch, APC = 2, RWSC = 2, PFLM = 2
1
2
3
4
5
6
seq
7
8
hclk
htrans
haddr, hprot
nonseq
seq
seq
addr y
addr y+4
addr y+8
addr y+12
seq
seq
addr y+16
addr y+20
hwrite
C(y+4)
C(y)
hrdata
C(y+16)
C(y+12)
C(y+8)
hwdata
hready_out
hresp
bkn_fl_addr
okay
okay
y
okay
okay
okay
okay
okay
y+16
okay
y+32
bkn_fl_rd_en
addr y
addr y+16
addr y+32
bkn_fl_wr_en
bkn_fl_rdata
C(y)
C(y+16)
bkn_fl_xfr_err
Figure 141. 3-cycle access, prefetch and buffering enabled
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Burst Read, Stall-and-Retry, APC = 2, RWSC = 2, PFLM = 2
1
2
3
4
5
7
6
8
9
10
hclk
htrans
nonseq
seq
seq
haddr, hprot
addr y
addr y+4
addr y+8
hwrite
C(y)
hrdata
C(y+4)
hwdata
hready_out
hresp
okay
okay
y
bkn_fl_addr
okay
y+16
okay
okay
okay
okay
y
okay
okay
okay
y+16
bkn_fl_rd_en
addr y
addr y (retry)
addr y+16
bkn_fl_wr_en
C(y)
bkn_fl_rdata
bkn_fl_xfr_err
bkn_done
bkn_abort
mcm_mir[fbnsi]
mcm_mir[fbnai]
Figure 142. 3-cycle access, stall-and-retry with BKn_RWWC = 11x
As shown in Figure 142, the 3-cycle access to address y is interrupted when an operation causes the
bkn_done signal to be negated, signaling that the array bank is busy with a high-voltage program or erase
event. Eventually, this array operation completes (at the end of cycle 4) and bkn_done returns to a logical
1. In cycle 6, the platform flash controller module retries the read to address y that was interrupted by the
negation of bkn_done in cycle 3. Note that throughout cycles 2–9, the AHB bus pipeline is stalled with a
read to address y in the AHB data phase and a read to address y + 4 in the address phase. Depending on
the state of the least-significant-bit of the BKn_RWWC control field, the hardware may also signal a stall
notification interrupt (if BKn_RWWC = 110). The stall notification interrupt is shown as the optional
assertion of MCM’s MIR[FBnSI] (flash bank n stall interrupt).
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Burst Read, Abort-and-Retry, APC = 2, RWSC = 2, PFLM = 2
1
2
3
4
5
7
6
8
10
9
hclk
htrans
nonseq
haddr, hprot
addr y
seq
seq
addr y+8
addr y+4
hwrite
C(y)
hrdata
C(y+4)
hwdata
hready_out
hresp
bkn_fl_addr
okay
okay
y
okay
y+16
okay
okay
okay
okay
y
okay
okay
okay
y+16
bkn_fl_rd_en
addr y
addr y (retry)
addr y+16
bkn_fl_wr_en
C(y)
bkn_fl_rdata
bkn_fl_xfr_err
bkn_done
bkn_abort
mcm_mir[fbnsi]
mcm_mir[fbnai]
Figure 143. 3-cycle access, terminate-and-retry with BKn_RWWC = 10x
Figure 143 shows the terminate-while-write timing diagram. In this example, the 3-cycle access to address
y is interrupted when an operation causes the bkn_done signal to be negated, signaling that the array bank
is busy with a high-voltage program or erase event. Based on the setting of BKn_RWWC, once the
bkn_done signal is detected as negated, the platform flash controller asserts bkn_abort, which forces the
flash array to cancel the high-voltage program or erase event. The array operation completes (at the end of
cycle 4) and bkn_done returns to a logical 1. It should be noted that the time spent in cycle 4 for Figure 143
is considerably less than the time in the same cycle in Figure 142 (because of the terminate operation). In
cycle 6, the platform flash controller module retries the read to address y that was interrupted by the
negation of bkn_done in cycle 3. Note that throughout cycles 2–9, the AHB bus pipeline is stalled with a
read to address y in the AHB data phase and a read to address y+4 in the address phase. Depending on the
state of the least-significant-bit of the BKn_RWWC control field, the hardware may also signal an
termination notification interrupt (if BKn_RWWC = 100). The stall notification interrupt is shown as the
optional assertion of MCM’s MIR[FBnAI] (flash bank n termination interrupt).
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18.3
Code Flash Memory (C90LC)
18.3.1
Overview
The primary function of the Flash Module is to serve as electrically programmable and erasable
Non-Volatile Memory.
NV Memory may be used for instruction and/or data storage.
The Module is a Non-Volatile solid-state silicon memory device consisting of blocks (called also sectors)
of single transistor storage elements, an electrical means for selectively adding (programming) and
removing (erasing) charge from these elements, and a means of selectively sensing (reading) the charge
stored in these elements.
The Flash Module is arranged as two functional units: the Flash Core and the Memory Interface.
The Flash Core is composed of arrayed Non-Volatile storage elements, sense amplifiers, row decoders,
column decoders and charge pumps. The arrayed storage elements in the Flash Core are sub-divided into
physically separate units referred to as blocks (or sectors).
The Memory Interface contains the registers and logic which control the operation of the Flash Core. The
Memory Interface is also the interface between the Flash Module and a Bus Interface Unit (BIU) and may
contain the ECC logic and redundancy logic.
A BIU connects the Flash Module to a system bus, and contains all system level customization required
for the SoC application. The Flash Module is generic and requires a BIU to configure it for different SoC
applications. A BIU is not included as a part of the Flash Module.
18.3.2
•
•
•
•
•
•
•
•
•
•
Features
Good Access Time
High Read parallelism (128 bits)
Error Correction Code (SEC-DED) to enhance Data Retention
Double Word Program (64 bits)
Sector Erase
Single Bank: Read-While-Modify not available
Erase Suspend available (Program Suspend not available)
Software programmable Program/Erase Protection to avoid unwanted writings
Censored Mode against piracy
Usable as main Code Memory of the device: Shadow Sector available
18.3.3
Block Diagram
The Flash Macrocell contains one Matrix Module, composed by a Single Bank: Bank 0, normally used for
Code storage. No Read-While-Modify operations are possible.
The Modify operations are managed by an embedded Flash Program/Erase Controller (FPEC). Commands
to the FPEC are given through a User Registers Interface.
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The read data bus is 128 bits wide, while the Flash registers are on a separate bus 32 bits wide.
The High Voltages needed for Program/Erase operations are internally generated.
HV generator
Flash
Program/Erase
Controller
Flash Bank 0
Flash
Registers
Matrix
Interface
Registers
Interface
Figure 144. Flash Macrocell Structure
18.3.4
18.3.4.1
Functional Description
Macrocell Structure
The Flash Macrocell is designed for use in embedded MCU/SoC applications which require high density
Non-Volatile Memories with high speed read access. The Flash Module is addressable by Word (32 bits)
or Double Word (64 bits) for program, and page (128 bits) for read. Reads done to the Flash always return
128 bits, although read page buffering may be done in the platform BIU.
Each read of the Flash Module retrieves a page, or 4 consecutive words (128 bits) of information. The
address for each word retrieved within a page differ from the other addresses in the page only by address
bits (3:2). The Flash page read architecture easily supports both cache and burst mode at the BIU level for
high speed read application.
The Flash Module supports fault tolerance through Error Correction Code (ECC) and/or error detection.
The ECC implemented within the Flash Module will correct single bit failures and detect double bit
failures.
The Flash Module uses an embedded hardware algorithm implemented in the Memory Interface to
program and erase the Flash Core. Control logic that works with the software block enables, and software
lock mechanisms, is included in the embedded hardware algorithm to guard against accidental
program/erase. The hardware algorithm performs the steps necessary to ensure that the storage elements
are programmed and erased with sufficient margin to guarantee data integrity and reliability.
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A programmed bit in the Flash Module reads as logic level 0 (or low). An erased bit in the Flash Module
reads as logic level 1 (or high). Program and erase of the Flash Module requires multiple system clock
cycles to complete. The erase sequence may be suspended. The program and erase sequences may be
aborted.
18.3.5
Code flash sectorization
The Flash Module supports total memory sizes ranging from 32 KB to 512 KB of User Memory, plus
16 KB of Test Memory (a portion of which is One-Time Programmable by the User). Optionally an extra
sector of 8 or 16 KB can be available as Shadow space.
• There are three User Address Spaces: Low, Mid and High Address Space.
• Low Address Space must always be present and be up to 256 KB in size.
• Mid Address Space can be present and be up to 256 KB in size.
• High Address Space is normally always empty, but it can be present in case there are holes in the
address space. High Address Space may extend up to 1.5 MB in the address mapping.
In any case the total size of the Flash Module will be not greater than 512 KB and the maximum number
of blocks cannot exceed 16, included Test and eventually Shadow Sector.
There are five sizes of blocks available to the User in the Flash Core: 128 KB, 64 KB, 32 KB, 16 KB, 8
KB. These blocks can be mapped anywhere in the Low, Mid and High address spaces, provided that the
total Flash Memory size is not greater than 512 KB.
The Flash Module is composed by a single Bank (Bank 0): Read-While-Modify is not supported.
Bank 0 of the 544 KB Flash macrocell is divided in 10 sectors. Bank 0 contains also a reserved sector
named TestFlash in which some One Time Programmable User data are stored. Besides Bank 0 contains
also a Shadow Sector in which User erasable configuration values can be stored.
Table 145. 544 KB Code flash module sectorization
Bank
Sector
Addresses
Size
Address space
B0
B0F0
0x0000_0000–0x0000_3FFF
16 KB
Low Address Space
B0
B0F1
0x0000_4000–0x0000_7FFF
16 KB
Low Address Space
B0
B0F2
0x0000_8000–0x0000_FFFF
32 KB
Low Address Space
B0
B0F3
0x0001_0000–0x0001_7FFF
32 KB
Low Address Space
B0
B0F4
0x0001_8000–0x0001_BFFF
16 KB
Low Address Space
B0
B0F5
0x0001_C000–0x0001_FFFF
16 KB
Low Address Space
B0
B0F6
0x0002_0000–0x0002_FFFF
64 KB
Low Address Space
B0
B0F7
0x0003_0000–0x0003_FFFF
64 KB
Low Address Space
B0
B0F8
0x0004_0000–0x0005_FFFF
128 KB
Mid Address Space
B0
B0F9
0x0006_0000–0x0007_FFFF
128 KB
Mid Address Space
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Table 145. 544 KB Code flash module sectorization
Bank
Sector
Addresses
Size
Address space
B0
Reserved
0x0008_0000–0x001F_FFFF
1536 KB
High Address Space
B0
B0SH
0x0020_0000–0x0020_3FFF
16 KB
Shadow Address Space
B0
B0TF
0x0040_0000–0x0040_3FFF
16 KB
Test Address Space
The Flash Module is divided into blocks also to implement independent Erase/Program protection. A
software mechanism is provided to independently lock/unlock each block in low, mid and high address
space against program and erase.
18.3.5.1
Test Flash Block
The TestFlash block exists outside the normal address space and is programmed, erased and read
independently of the other blocks. The independent TestFlash block is included also to support systems
which require Non-Volatile Memory for security and/or to store system initialization information.
A section of the TestFlash is reserved to store the Non Volatile informations related to Redundancy,
Configuration and Protection.
Due to this special usage, the TestFlash sector is not affected by the Column Redundancy. The ECC, on
the contrary, is applied also to TestFlash.
The usage of reserved TestFlash sector is detailed in the following table.
Table 146. TestFlash Structure
Name
Description
Addresses
Size
User OTP Area
0x400000 to 0x401FFF
8192 byte
Reserved
0x402000 to 0x403CFF 7424 byte
User Reserved
0x403D00 to 0x403DE7
232 byte
NV Low/Mid address space block Locking reg
0x403DE8 to 0x403DEF
8 byte
NVHBL
Non Volatile High address space Block Locking reg 0x403DF0 to 0x403DF7
8 byte
NVSLL
NV Secondary Low/mid add space block Lock reg
0x403DF8 to 0x403DFF
8 byte
User Reserved
0x403E00 to 0x403EFF
256 byte
Reserved
0x403F00 to 0x403FFF
256 byte
NVLML
The Test Flash block can be enabled by the BIU.
When the Test space is enabled, all the operations are mapped to the Test block.
User Mode program of the test block are enabled only when MCR.PEAS is high, also if the Shadow block
is available.
The Test Flash block may be locked/unlocked against program by using the LML.TSLK and SLL.STSLK
registers. Erase of Test Flash block is always locked in user mode.
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Program of the TestFlash block has similar restriction as the array in terms of how ECC is calculated. Only
one program is allowed per 64 bit ECC segment, unless ECC evaluation is disabled on TestFlash block
(SoC dependent).
The TestFlash block contains specified data that are needed for Flash Macrocell or SoC features.
The first 8KB of TestFlash block may be used for user defined functions (possibly to store boot code, other
configuration words or factory process codes). Locations of the TestFlash block marked as reserved cannot
be programmed by the User application.
18.3.5.2
Shadow block
A Shadow block is present in the 544 KB Flash Macrocell. The Shadow block can be enabled by the BIU.
When the Shadow space is enabled, all the operations are mapped to the Shadow block.
User Mode program and erase of the shadow block are enabled only when MCR.PEAS is high.
The Shadow block may be locked/unlocked against program or erase by using the LML.TSLK and
SLL.STSLK registers.
Program of the Shadow block has similar restriction as the array in terms of how ECC is calculated. Only
one program is allowed per 64 bit ECC segment between erases, unless ECC evaluation is disabled on
Shadow block (SoC dependent).
Erase of the Shadow block is done similarly as an array erase.
The Shadow block contains specified data that are needed for SoC features.
The first 8KB of Shadow block may be used for user defined functions (possibly to store boot code, other
configuration words or factory process codes).
The usage of Shadow sector is detailed in the following table:
Table 147. Shadow Sector Structure
Addresses
Name
Description
Size
0x200000 to 0x203DCF
User Area
15824 byte
0x203DD0 to 0x203DD7
Reserved
8 byte
0x203DD8 to 0x203DDF NVPWD0-1 Non Volatile private censorship PassWorD 0-1 reg
8 byte
0x203DE0 to 0x203DE7
Non Volatile System Censorship Information 0-1
8 byte
Reserved
24 byte
Non Volatile Bus Interface Unit 2-3 regs
16 byte
Reserved
8 byte
Non Volatile USeR Options register
8 byte
Reserved
480 byte
NVSCI0-1
0x203DE8 to 0x203DFF
0x203E00 to 0x203E0F
NVBIU2-3
0x203E10 to 0x203E17
0x203E18 – 0x203E1F
0x203E20 – 0x203FFF
NVUSRO
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18.3.5.3
User Mode Operation
In User Mode the Flash Module may be read and written (register writes and interlock writes),
programmed or erased.
The default state of the Flash Module is read. The main, shadow and test address space can be read only
in the read state. The Flash registers are always available for read, also when the Module is in disable mode
(except few documented registers).
The Flash Module enters the read state on reset. The Module is in the read state under two sets of
conditions:
• The read state is active when the Module is enabled (User Mode Read)
• The read state is active when MCR.ERS and MCR.ESUS are high and MCR.PGM is low (Erase
Suspend).
NOTE
No Read-While-Modify is available.
Flash Core reads return 128 bits (1 Page = 2 Double Words).
Registers reads return 32 bits (1 Word).
Flash Core reads are done through the Bus Interface Unit.
In many cases the BIU will do “read page buffering” to allow sequential reads to be done with higher
performance. This could provide Data Coherency issue that must be handled with software. Data
Coherency may be an issue after a program or an erase operation, as well as Shadow or Test block
operations.
Registers reads to unmapped register address space will return all 0’s.
Registers writes to unmapped register address space will have no effect.
Array reads attempted to invalid locations will result in indeterminate data. Invalid locations occur when
addressing is done to blocks that do not exist in non 2n array sizes.
Interlock writes attempted to invalid locations, will result in an interlock occurring, but attempts to
program these blocks will not occur since they are forced to be locked. Erase will occur to selected and
unlocked blocks even if the interlock write is to an invalid location.
Simultaneous Read cycle on the Flash Matrix and Read/Write cycles on the Registers are possible. On the
contrary Registers Read/Write accesses simultaneous to a Flash Matrix interlock write are forbidden.
Chip Select, Write Enable, Addresses and Data Input of Registers are not internally latched and must be
kept stable by the CPU for all the read/write access that lasts 2 clock cycles.
18.3.5.4
Reset
A reset is the highest priority operation for the Flash Module and terminates all other operations.
The Flash Module uses reset to initialize register and status bits to their default reset values.
If the Flash Module is executing a Program or Erase operation (MCR.PGM = 1 or MCR.ERS = 1) and a
reset is issued, the operation will be suddenly terminated and the module will disable the high voltage logic
without damage to the high voltage circuits. Reset terminates all operations and forces the Flash Module
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into User Mode ready to receive accesses.
Reset and power-off must not be used as a systematic way to terminate a Program or Erase operation.
After reset is negated, read register access may be done, although it should be noted that registers that
require updating from shadow information, or other inputs, may not read updated values until
MCR.DONE transitions. MCR.DONE may be polled to determine if the Flash Module has transitioned
out of reset. Notice that the registers cannot be written until MCR.DONE is high.
18.3.5.5
Disable Mode (Power-Down)
The Disable (or Power-Down) Mode allows to turn-off all Flash DC current sources, so that all power
dissipation is due only to leakage in this mode.
In Disable Mode no reads from or write to the Module are possible.
The User may not read some registers (UMISR0-4, UT1-2 and part of UT0) until the Disable Mode is
exited . On the contrary write access is locked on all the registers in Disable Mode.
When enabled the Flash Module returns to its pre-disable state in all cases unless in the process of
executing an erase high voltage operation at the time of disable.
If the Flash Module is disabled during an erase operation, MCR.ESUS bit is set to 1. The User may resume
the erase operation at the time the Module is enabled by clearing MCR.ESUS bit. MCR.EHV must be high
to resume the erase operation.
If the Flash Module is disabled during a program operation, the operation will be in any case completed
and the Disable Mode will be entered only after the programming end.
If the Flash Macrocell is put in Power-Down Mode and the Vector Table remain mapped in the Flash
Address space, the User must take care than the Flash Macrocell will strongly increase the interrupt
response time by adding several Wait States.
It is forbidden to enter in Sleep Mode when the Disable Mode is active.
18.3.5.6
Sleep Mode (Low Power Mode)
The Sleep Mode turns-off most of the DC current sources within the Flash Module.
Wake-up time from sleep is faster than wake-up time from disable mode.
In Sleep Mode no reads from or write to the Module are possible.
The User may not read some registers (UMISR0-4, UT1-2 and part of UT0) until the Sleep Mode is exited
. On the contrary write access is locked on all the registers in Sleep Mode.
When exiting from sleep mode the Flash Module returns to its pre-sleep state in all cases unless in the
process of executing an erase high voltage operation at the time of sleep entering.
If the Flash Module is put in sleep during an erase operation, MCR.ESUS bit is set to 1. The User may
resume the erase operation at the time the Module is exited from sleep by clearing MCR.ESUS bit.
MCR.EHV must be high to resume the erase operation.
If the Flash Module is put in sleep during a program operation, the operation will be in any case completed
and the Sleep Mode will be entered only after the programming end.
It is forbidden to enter in Disable Mode when the Sleep Mode is active.
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18.3.6
Registers Description
The Flash User registers represents the communication interface between the host CPU and the FPEC. me
register bits (command bits) are read/write for the CPU and read-only for the FPEC.
Some other register bits (status bits) are read/write for the FPEC and read-only for the CPU.
Table 148. Code flash module registers
Address Offset
Register Name
Reset Value
0x0000
Module Configuration Register (MCR)
0x02700600
0x0004
Low/Mid address space block Locking reg (LML)
0x00XX00XX
0x0008
High address space Block Locking reg (HBL)
0x00000000
0x000C
Secondary Low/mid address space block Lock reg (SLL)
0x00XX00XX
0x0010
Low/Mid address space block Select reg (LMS)
0x00000000
0x0014
High address space Block Select reg (HBS)
0x00000000
0x0018
ADress Register (ADR)
0x00000000
0x001C
Bus Interface Unit reg 0 (BIU0)1
0xXXXXXXXX
0x0020
Bus Interface Unit reg 1 (BIU1)1
0xXXXXXXXX
0x0024
Bus Interface Unit reg 2 (BIU2)2
0xXXXXXXXX
0x002C
Reserved
—
0x003C
User Test reg 0 (UT0)
0x00000001
0x0040
User Test reg 1 (UT1)
0x00000000
0x0044
User Test reg 2 (UT2)
0x00000000
0x0048
User Multiple Input Signature Reg 0 (UMISR0)
0x00000000
0x004C
User Multiple Input Signature Reg 1 (UMISR1)
0x00000000
0x0050
User Multiple Input Signature Reg 2 (UMISR2)
0x00000000
0x0054
User Multiple Input Signature Reg 3 (UMISR3)
0x00000000
0x0058
User Multiple Input Signature Reg 4 (UMISR4)
0x00000000
1
Bus Interface Unit register 0 and 1 (BIU0 and BIU1) are same as Section 18.2.4.2.1, “Platform Flash
Configuration Register 0 (PFCR0)” and Section 18.2.4.2.2, “Platform Flash Configuration Register 1
(PFCR1)”.
2
Bus Interface Unit register 2 (BIU2) is same as Section 18.2.4.2.3, “Platform Flash Access Protection
Register (PFAPR)”
In the following some Non Volatile Registers are described. Please notice that such entities are not
Flip-Flops, but locations of TestFlash or Shadow sectors with a special meaning.
During the Flash Initialization phase, the FPEC reads these Non Volatile Registers and update their related
Volatile Registers. When the FPEC detects ECC double errors in these special locations, it behaves in the
following way:
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•
•
In case of a failing system locations (configurations, device options, redundancy, EmbAlgo
firmware), the initialization phase is interrupted and a Fatal Error is flagged .
In case of failing user locations (protections, censorship, BIU, ...), the Volatile Registers are filled
with all ‘1’s and the Flash initialization ends setting low the PEG bit of MCR.
In this section, the following abbreviations are used.
Table 149. Abbreviations
Case
Abbrev.
Description
read/write
rw
The software can read and write to these bits.
read/clear
rc
The software can read and clear to these bits.
read-only
r
The software can only read these bits.
write-only
w
The software should only write to these bits.
18.3.6.1
Module Configuration Register (MCR)
The Module Configuration Register enables and monitors all the modify operations of each flash module.
Identical MCRs are provided in the code flash and the data flash blocks.
Address: Base + 0x0000
0
Access: User read/write
1
2
3
4
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
16
17
18
19
20
21
22
23
24
25
26
0
0
0
0
0
0
0
0
0
0
0
0
R EDC
5
6
7
SIZE2 SIZE1 SIZE0
8
0
9
10
11
12
13
14
15
0
0
0
MAS
1
0
0
0
0
27
28
29
30
31
LAS2 LAS1 LAS0
W r1c
Reset
R EER RWE
W r1c
Reset
0
PEAS DONE PEG
r1c
0
0
1
1
PGM PSUS ERS ESUS EHV
0
0
0
0
0
Figure 145. Module Configuration Register (MCR)
Table 150. MCR field descriptions
Field
Description
EDC
ECC Data Correction
EDC provides information on previous reads. If a ECC Single Error detection and correction occurs,
the EDC bit is set to 1. This bit must then be cleared, or a reset must occur before this bit will return
to a 0 state. This bit may not be set to 1 by the user.
In the event of a ECC Double Error detection, this bit is not set.
If EDC is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing
of EDC) were not corrected through ECC.
Since this bit is an error flag, it must be cleared to 0 by writing 1 to the register location. A write of 0
will have no effect.
0 Reads are occurring normally.
1 An ECC Single Error occurred and was corrected during a previous read.
Reserved (Read Only)
A write to these bits has no effect. A read of these bits always outputs 0.
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Table 150. MCR field descriptions (continued)
Field
SIZE[2:0]
Description
Array space SIZE 2–0
The value of SIZE field depends on the size of the flash module:
000 128 KB
001 256 KB
010 512 KB
011 Reserved (1024 KB)
100 Reserved (1536 KB)
101 Reserved (2048 KB)
110 64 KB (the value for the device in the data flash module)
111 Reserved
Note: The value for this bitfield is different between the code and data flash modules.
Reserved (Read Only)
A write to these bits has no effect. A read of these bits always outputs 0.
LAS[2:0]
Low Address Space 2–0
The value of the LAS field corresponds to the configuration of the Low Address Space:
000 Reserved
001 Reserved
011 Reserved
100 Reserved
101 Reserved
110 4 × 16 KB (the value for the device in the data flash module)
Note: The value for this bitfield is different between the code and data flash modules.
Reserved (Read Only)
A write to these bits has no effect. A read of these bits always outputs 0.
MAS
Mid Address Space
The value of the MAS field corresponds to the configuration of the Mid Address Space:
0 2 × 128 KB
1 Reserved
EER
ECC Event Error
EER provides information on previous reads. When an ECC Double Error detection occurs, the EER
bit is set to 1.
This bit must then be cleared, or a reset must occur before this bit will return to a 0 state. This bit may
not be set to 1 by the user.
In the event of a ECC Single Error detection and correction, this bit will not be set.
If EER is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing
of EER) were correct.
Since this bit is an error flag, it must be cleared to 0 by writing 1 to the register location. A write of 0
will have no effect.
0 Reads are occurring normally.
1 An ECC Double Error occurred during a previous read.
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Table 150. MCR field descriptions (continued)
Field
Description
RWE
Read-while-Write event Error
RWE provides information on previous reads when a Modify operation is on going. If a RWW Error
occurs, the RWE bit is set to 1. Read-While-Write Error means that a read access to the flash module
has occurred while the FPEC was performing a program or Erase operation or an Array Integrity
Check.
This bit must then be cleared, or a reset must occur before this bit will return to a 0 state. This bit may
not be set to 1 by the user.
If RWE is not set, or remains 0, this indicates that all previous RWW reads (from the last reset, or
clearing of RWE) were correct.
Since this bit is an error flag, it must be cleared to 0 by writing 1 to the register location. A write of 0
will have no effect.
0 Reads are occurring normally.
1 A RWW Error occurred during a previous read.
Note: If stall/terminate-while-write is used, the software should ignore the setting of the RWE flag and
should clear this flag after each erase operation. If stall/terminate-while-write is not used,
software can handle the RWE error normally.
Reserved (Read Only)
A write to these bits has no effect. A read of these bits always outputs 0.
PEAS
Program/Erase Access Space
PEAS indicates which space is valid for program and Erase operations: main array space or
shadow/test space.
PEAS = 0 indicates that the main address space is active for all flash module program and erase
operations.
PEAS = 1 indicates that the test or shadow address space is active for program and erase.
The value in PEAS is captured and held with the first interlock write done for Modify operations. The
value of PEAS is retained between sampling events (that is, subsequent first interlock writes).
0 Shadow/Test address space is disabled for program/erase and main address space enabled.
1 Shadow/Test address space is enabled for program/erase and main address space disabled.
DONE
Modify Operation Done
DONE indicates if the flash module is performing a high voltage operation.
DONE is set to 1 on termination of the flash module reset.
DONE is cleared to 0 just after a 0-to-1 transition of EHV, which initiates a high voltage operation, or
after resuming a suspended operation.
DONE is set to 1 at the end of program and erase high voltage sequences.
DONE is set to 1 (within tPABT or tEABT, equal to P/E Abort Latency) after a 1-to-0 transition of EHV,
which terminates a high voltage program/erase operation.
DONE is set to 1 (within tESUS, time equal to Erase Suspend Latency) after a 0-to-1 transition of
ESUS, which suspends an erase operation.
0 Flash is executing a high voltage operation.
1 Flash is not executing a high voltage operation.
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Table 150. MCR field descriptions (continued)
Field
Description
PEG
Program/Erase Good
The PEG bit indicates the completion status of the last flash program or erase sequence for which
high voltage operations were initiated. The value of PEG is updated automatically during the program
and erase high voltage operations.
Aborting a program/erase high voltage operation causes PEG to be cleared to 0, indicating the
sequence failed.
PEG is set to 1 when the flash module is reset, unless a flash initialization error has been detected.
The value of PEG is valid only when PGM = 1 and/or ERS = 1 and after DONE transitions from 0 to
1 due to a termination or the completion of a program/erase operation. PEG is valid until PGM/ERS
makes a 1-to-0 transition or EHV makes a 0-to-1 transition.
The value in PEG is not valid after a 0-to-1 transition of DONE caused by ESUS being set to logic 1.
If program or erase are attempted on blocks that are locked, the response is PEG = 1, indicating that
the operation was successful, and the content of the block were properly protected from the program
or erase operation.
If a program operation tries to program at 1 bits that are at 0, the program operation is correctly
executed on the new bits to be programmed at 0, but PEG is cleared, indicating that the requested
operation has failed.
In Array Integrity Check or Margin Mode, PEG is set to 1 when the operation is completed, regardless
the occurrence of any error. The presence of errors can be detected only comparing checksum value
stored in UMIRS[0:1].
0 Program or erase operation failed; or program, erase, Array Integrity Check, or Margin Mode was
terminated.
1 Program or erase operation successful; or Array Integrity Check or Margin Mode completed
successfully.
Reserved (Read Only)
A write to these bits has no effect. A read of these bits always outputs 0.
PGM
Program
PGM sets up the flash module for a program operation.
A 0-to-1 transition of PGM initiates a program sequence.
A 1-to-0 transition of PGM ends the program sequence.
PGM can be set only under User mode Read (ERS is low and UT0[AIE] is low). PGM can be cleared
by the user only when EHV is low and DONE is high. PGM is cleared on reset.
0 Flash is not executing a program sequence.
1 Flash is executing a program sequence.
PSUS
Program Suspend
Writing to this bit has no effect, but the written data can be read back.
ERS
Erase
ERS sets up the flash module for an Erase operation.
A 0-to-1 transition of ERS initiates an Erase sequence.
A 1-to-0 transition of ERS ends the Erase sequence.
ERS can be set only under User mode Read (PGM is low and UT0[AIE] is low). ERS can be cleared
by the user only when ESUS and EHV are low and DONE is high. ERS is cleared on reset.
0 Flash is not executing an Erase sequence.
1 Flash is executing an Erase sequence.
MPC5604E Reference Manual, Rev. 5
18-322
Freescale Semiconductor
Flash Memory
Table 150. MCR field descriptions (continued)
Field
Description
ESUS
Erase Suspend
ESUS indicates that the flash module is in Erase Suspend or in the process of entering a Suspend
state. The flash module is in Erase Suspend when ESUS = 1 and DONE = 1.
ESUS can be set high only when ERS = 1 and EHV = 1, and PGM = 0.
A 0-to-1 transition of ESUS starts the sequence that sets DONE and places the flash in erase
suspend. The flash module enters Suspend within tESUS of this transition.
ESUS can be cleared only when DONE = 1 and EHV = 1, and PGM = 0.
A 1-to-0 transition of ESUS with EHV = 1 starts the sequence that clears DONE and returns the
Module to Erase.
The flash module cannot exit Erase Suspend and clear DONE while EHV is low.
ESUS is cleared on reset.
0 Erase sequence is not suspended.
1 Erase sequence is suspended.
EHV
Enable High Voltage
The EHV bit enables the flash module for a high voltage program/Erase operation. EHV is cleared
on reset.
EHV must be set after an interlock write to start a program/Erase sequence. EHV may be set under
one of the following conditions:
• Erase (ERS = 1, ESUS = 0, UT0[AIE] = 0)
• Program (ERS = 0, ESUS = 0, PGM = 1, UT0[AIE] = 0)
In normal operation, a 1-to-0 transition of EHV with DONE high and ESUS low terminates the current
program/Erase high voltage operation.
When an operation is terminated, there is a 1-to-0 transition of EHV with DONE low and the eventual
Suspend bit low. A termination causes the value of PEG to be cleared, indicating a failing
program/Erase; address locations being operated on by the terminated operation contain
indeterminate data after a termination. A suspended operation cannot be terminated. Terminating a
high voltage operation leaves the flash module addresses in an indeterminate data state. This may
be recovered by executing an Erase on the affected blocks.
EHV may be written during Suspend. EHV must be high to exit Suspend. EHV may not be written
after ESUS is set and before DONE transitions high. EHV may not be cleared after ESUS is cleared
and before DONE transitions low.
0 Flash is not enabled to perform an high voltage operation.
1 Flash is enabled to perform an high voltage operation.
A number of MCR bits are protected against write when another bit, or set of bits, is in a specific state.
These write locks are covered on a bit by bit basis in the preceding description, but those locks do not
consider the effects of trying to write two or more bits simultaneously.
The flash module does not allow the user to write bits simultaneously which would put the device into an
illegal state. This is implemented through a priority mechanism among the bits. Table 151 shows the bit
changing priorities.
Table 151. MCR bits set/clear priority levels
Priority level
MCR bits
1
ERS
2
PGM
3
EHV
4
ESUS
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Freescale Semiconductor
18-323
Flash Memory
If the user attempts to write two or more MCR bits simultaneously, only the bit with the lowest priority
level is written.
18.3.6.2
Low/Mid Address Space Block Locking register (LML)
The Low/Mid Address Space Block Locking register provides a means to protect blocks from being
modified. These bits, along with bits in the SLL register, determine if the block is locked from program or
erase. An “OR” of LML and SLL determine the final lock status. Identical LML registers are provided in
the code flash and the data flash blocks.
In the code flash module, the LML register has a related Non-Volatile Low/Mid Address Space Block
Locking register (NVLML) located in TestFlash that contains the default reset value for LML. The
NVLML register is read during the reset phase of the flash module and loaded into the LML. The reset
value is 0x00XX_XXXX, initially determined by the NVLML value from test sector.
Address: Base + 0x0004
0
Access: User read/write
1
2
3
4
5
6
7
8
9
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
LLK
7
LLK
6
LLK
5
LLK
4
LLK
3
LLK
2
LLK
1
LLK
0
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
R LME
W
Reset
R
W
Reset
11
TSLK
x
12
13
0
0
0
0
14
15
MLK1 MLK0
x
x
Figure 146. Low/Mid Address Space Block Locking register (LML)
18.3.6.3
Non-Volatile Low/Mid Address Space Block Locking register (NVLML)
Address: Base + 0x40_3DE8
0
Delivery value:
0xFFFFFFFF
1
2
3
4
5
6
7
8
9
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
LLK
7
LLK
6
LLK
5
LLK
4
LLK
3
LLK
2
LLK
1
LLK
0
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
R LME
W
Reset
R
W
Reset
11
TSLK
x
12
13
0
0
0
0
14
15
MLK1 MLK0
x
x
Figure 147. Non-Volatile Low/Mid Address Space Block Locking register (NVLML)
The NVLML register is a 64-bit register, the 32 most significant bits of which (bits 63:32) are “don’t care”
bits that are eventually used to manage ECC codes. Identical NVLML registers are provided in the code
flash and the data flash blocks.
MPC5604E Reference Manual, Rev. 5
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Freescale Semiconductor
Flash Memory
Table 152. LML /NVLML field descriptions
Field
Description
LME1
Low/Mid Address Space Block Enable
This bit enables the Lock registers (TSLK and LLK[15:0]) to be set or cleared by registers writes.
This bit is a status bit only. The method to set this bit is to write a password, and if the password
matches, the LME bit is set to reflect the status of enabled, and is enabled until a reset operation
occurs. For LME the password 0xA1A11111 must be written to the LML register.
0 Low Address Locks are disabled: TSLK and LLK[15:0] cannot be written.
1 Low Address Locks are enabled: TSLK and LLK[15:0] can be written.
TSLK
Test/Shadow Address Space Block Lock
This bit locks the block of Test and Shadow Address Space from program and Erase (Erase is any
case forbidden for Test block).
A value of 1 in the TSLK register signifies that the Test/Shadow block is locked for program and
Erase. A value of 0 in the TSLK register signifies that the Test/Shadow block is available to receive
program and Erase pulses.
The TSLK register is not writable once an interlock write is completed until MCR[DONE] is set at
the completion of the requested operation. Likewise, the TSLK register is not writable if a high
voltage operation is suspended.
Upon reset, information from the TestFlash block is loaded into the TSLK register. The TSLK bit
may be written as a register. Reset will cause the bit to go back to its TestFlash block value. The
default value of the TSLK bit (assuming erased fuses) would be locked.
TSLK is not writable unless LME is high.
0 Test/Shadow Address Space Block is unlocked and can be modified (if also SLL[STSLK] = 0).
1 Test/Shadow Address Space Block is locked and cannot be modified.
MLK[1:0]
Mid Address Space Block Lock 1-0
These bits lock the blocks of Mid Address Space from program and Erase.
MLK[1:0] are related to sectors B0F[7:6], respectively.
A value of 1 in a bit of the MLK bitfield signifies that the corresponding block is locked for program
and Erase. A value of 0 in a bit of the MLK bitfield signifies that the corresponding block is available
to receive program and Erase pulses.
The MLK bitfield is not writable once an interlock write is completed until MCR[DONE] is set at the
completion of the requested operation. Likewise, the MLK bitfield is not writable if a high voltage
operation is suspended. Upon reset, information from the TestFlash block is loaded into the MLK
bitfields. The MLK bits may be written as a register. Reset causes the bits to revert to their
TestFlash block value. The default value of the MLK bits (assuming erased fuses) would be locked.
In the event that blocks are not present (due to configuration or total memory size), the MLK bits
default to locked, and are not writable. The reset value will always be 1 (independent of the
TestFlash block), and register writes will have no effect.
MLK is not writable unless LME is high.
0 Mid Address Space Block is unlocked and can be modified (if also SLL[SMLK] = 0).
1 Mid Address Space Block is locked and cannot be modified.
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
18-325
Flash Memory
Table 152. LML /NVLML field descriptions (continued)
1
Field
Description
LLK[7:0]
LLK7-0: Low address space block LocK 7-0 (Read/Write)
These bits are used to lock the blocks of Low Address Space from Program and Erase.
LLK7-0 are related to sectors B0F7-0, respectively.
A value of 1 in a bit of the LLK register signifies that the corresponding block is locked for Program
and Erase.
A value of 0 in a bit of the LLK register signifies that the corresponding block is available to receive
Program and Erase pulses.
The LLK register is not writable once an interlock write is completed until MCR.DONE is set at the
completion of the requested operation. Likewise, the LLK register is not writable if a high voltage
operation is suspended.
Upon reset, information from the TestFlash block is loaded into the LLK registers. The LLK bits may
be written as a register. Reset will cause the bits to go back to their TestFlash block value. The
default value of the LLK bits (assuming erased fuses) would be locked.
In the event that blocks are not present (due to configuration or total memory size), the LLK bits
will default to locked, and will not be writable. The reset value will always be 1 (independent of the
TestFlash block), and register writes will have no effect.
LLK is not writable unless LME is high.
0: Low Address Space Block is unlocked and can be modified (if also SLL.SLK=0).
1: Low Address Space Block is locked and cannot be modified.
This field is present only in LML
18.3.6.4
High address space Block Locking register (HBL)
The High Address Space Block Locking (HBL) register provides a means to protect blocks from being
modified.
The HBL register has a related Non Volatile High Address Space Block Locking register located in
TestFlash that contains the default reset value for HBL: the NVHBL register is read during the reset phase
of the Flash Module and loaded into the HBL.
The NVHBL register is a 64 bit register, the 32 most significative bits of which (bits 63-32) are don’t care
and eventually used to manage ECC codes.
Address: Base + 0x0008
0
Access: User read-only
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R HBE
W
Reset
R
W
Reset
Figure 148. High address space Block Locking register (HBL)
MPC5604E Reference Manual, Rev. 5
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Freescale Semiconductor
Flash Memory
18.3.6.5
Non Volatile High address space Block Locking register (NVHBL)
Address: Base + 0x403DF0
0
Delivery value:
0xFFFFFFFF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R HBE
W
Reset
R
W
Reset
Figure 149. Non Volatile High address space Block Locking register (NVHBL)
Table 153. HBL/NVHBL field descriptions
Field
HBE
18.3.6.6
Description
High address space Block Enable (Read Only)
This bit is used to enable the Lock registers (HLK) to be set or cleared by registers writes.
This bit is a status bit only. The method to set this bit is to write a password, and if the password
matches, the HBE bit will be set to reflect the status of enabled, and is enabled until a reset
operation occurs. For HBE the password 0xB2B22222 must be written to the HBL register.
0: High Address Locks are disabled: none cannot be written.
1: High Address Locks are enabled: none can be written.
Secondary Low/Mid Address Space Block Locking register (SLL)
The Secondary Low/Mid Address Space Block Locking register provides an alternative means to protect
blocks from being modified. These bits, along with bits in the LML register, determine if the block is
locked from program or Erase. An “OR” of LML and SLL determine the final lock status. Identical SLL
registers are provided in the code flash and the data flash blocks.
In the code flash module, the SLL register has a related Non-Volatile Secondary Low/Mid Address Space
Block Locking register (NVSLL) located in TestFlash that contains the default reset value for SLL. The
reset value is 0x00XX_XXXX, initially determined by NVSLL.
The NVSLL register is read during the reset phase of the flash module and loaded into the SLL.
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
18-327
Flash Memory
Address: Base + 0x000C
0
Access: User read/write
1
2
3
4
5
6
7
8
9
10
11
12
13
0
0
0
0
0
0
0
0
0
0
STS
LK
0
0
0
0
0
0
0
0
0
0
0
0
0
x
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
SLK
7
SLK
6
SLK
5
SLK
4
SLK
3
SLK
2
SLK
1
SLK
0
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
R SLE
W
Reset
R
W
Reset
14
15
SMK SMK
1
0
x
x
Figure 150. Secondary Low/mid address space block Locking reg (SLL)
18.3.6.7
Non-Volatile Secondary Low/Mid Address Space Block Locking register
(NVSLL)
The NVSLL register is a 64-bit register, the 32 most significant bits of which (bits 63:32) are “don’t care”
bits that are eventually used to manage ECC codes. Identical NVSLL registers are provided in the code
flash and the data flash blocks.
Address: Base + 0x40_3DF8
0
Delivery value:
0xFFFFFFFF
1
2
3
4
5
6
7
8
9
10
11
12
13
0
0
0
0
0
0
0
0
0
0
STS
LK
0
0
0
0
0
0
0
0
0
0
0
0
0
x
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
SLK
7
SLK
6
SLK
5
SLK
4
SLK
3
SLK
2
SLK
1
SLK
0
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
R SLE
W
Reset
R
W
Reset
14
15
SMK SMK
1
0
x
x
Figure 151. Non-Volatile Secondary Low/Mid Address Space Block Locking register (NVSLL)
Table 154. SLL and NVSLL field descriptions
Field
Description
SLE1
Secondary Low/Mid Address Space Block Enable
This bit enables the Lock registers (STSLK and SLK[15:0]) to be set or cleared by registers writes.
This bit is a status bit only. The method to set this bit is to write a password, and if the password
matches, the SLE bit is set to reflect the status of enabled, and is enabled until a reset operation
occurs. For SLE the password 0xC3C3_3333 must be written to the SLL register.
0 Secondary Low/Mid Address Locks are disabled: STSLK and SLK[15:0] cannot be written.
1 Secondary Low/Mid Address Locks are enabled: STSLK and SLK[15:0] can be written.
MPC5604E Reference Manual, Rev. 5
18-328
Freescale Semiconductor
Flash Memory
Table 154. SLL and NVSLL field descriptions (continued)
Field
Description
STSLK
Secondary Test/Shadow address space block LocK
This bit is used as an alternate means to lock the block of Test and Shadow Address Space from
program and Erase (Erase is any case forbidden for Test block).
A value of 1 in the STSLK bitfield signifies that the Test/Shadow block is locked for program and
Erase.
A value of 0 in the STSLK register signifies that the Test/Shadow block is available to receive
program and Erase pulses.
The STSLK register is not writable once an interlock write is completed until MCR[DONE] is set at
the completion of the requested operation. Likewise, the STSLK register is not writable if a high
voltage operation is suspended.
Upon reset, information from the TestFlash block is loaded into the STSLK register. The STSLK bit
may be written as a register. Reset will cause the bit to go back to its TestFlash block value. The
default value of the STSLK bit (assuming erased fuses) would be locked.
STSLK is not writable unless SLE is high.
0 Test/Shadow Address Space Block is unlocked and can be modified (if also LML[TSLK] = 0).
1 Test/Shadow Address Space Block is locked and cannot be modified.
SMK[1:0]
Secondary Mid Address Space Block Lock 1–0
These bits are used as an alternate means to lock the blocks of Mid Address Space from program
and Erase.
SMK[1:0] are related to sectors B0F[7:6], respectively.
A value of 1 in a bit of the SMK register signifies that the corresponding block is locked for program
and Erase.
A value of 0 in a bit of the SMK register signifies that the corresponding block is available to receive
program and Erase pulses.
The SMK register is not writable once an interlock write is completed until MCR[DONE] is set at the
completion of the requested operation. Likewise, the SMK register is not writable if a high voltage
operation is suspended.
Upon reset, information from the TestFlash block is loaded into the SMK registers. The SMK bits
may be written as a register. Reset will cause the bits to go back to their TestFlash block value. The
default value of the SMK bits (assuming erased fuses) would be locked.
In the event that blocks are not present (due to configuration or total memory size), the SMK bits
will default to locked, and will not be writable. The reset value will always be 1 (independent of the
TestFlash block), and register writes have no effect. SMK is not writable unless SLE is high.
0 Mid Address Space Block is unlocked and can be modified (if also LML[MLK] = 0).
1 Mid Address Space Block is locked and cannot be modified.
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
18-329
Flash Memory
Table 154. SLL and NVSLL field descriptions (continued)
1
Field
Description
SLK[7:0]
SLK7-0: Secondary Low address space block locK 7-0 (Read/Write)
These bits are used as an alternate means to lock the blocks of Low Address Space from Program
and Erase.
SLK7-0 are related to sectors B0F7-0, respectively.
A value of 1 in a bit of the SLK register signifies that the corresponding block is locked for Program
and Erase.
A value of 0 in a bit of the SLK register signifies that the corresponding block is available to receive
Program and Erase pulses.
The SLK register is not writable once an interlock write is completed until MCR.DONE is set at the
completion of the requested operation. Likewise, the SLK register is not writable if a high voltage
operation is suspended.
Upon reset, information from the TestFlash block is loaded into the SLK registers. The SLK bits may
be written as a register. Reset will cause the bits to go back to their TestFlash block value. The
default value of the SLK bits (assuming erased fuses) would be locked.
In the event that blocks are not present (due to configuration or total memory size), the SLK bits will
default to locked, and will not be writable. The reset value will always be 1 (independent of the
TestFlash block), and register writes will have no effect.
SLK is not writable unless SLE is high.
0: Low Address Space Block is unlocked and can be modified (if also LML.LLK=0).
1: Low Address Space Block is locked and cannot be modified.
This field is present only in SLL
18.3.6.8
Low/Mid Address Space Block Select register (LMS)
The Low/Mid Address Space Block Select register provides a means to select blocks to be operated on
during erase. Identical LMS registers are provided in the code flash and the data flash blocks.
Address: Base + 0x0010
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
LSL
7
LSL
6
LSL
5
LSL
4
LSL
3
LSL
2
LSL
1
LSL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
14
15
MSL MSL
1
0
0
0
Figure 152. Low/Mid Address Space Block Select register (LMS)
MPC5604E Reference Manual, Rev. 5
18-330
Freescale Semiconductor
Flash Memory
Table 155. LMS field descriptions
Field
Description
MSL[1:0]
Mid Address Space Block Select 1–0
A value of 1 in the select register signifies that the block is selected for erase.
A value of 0 in the select register signifies that the block is not selected for erase. The reset value
for the select register is 0, or unselected.
MSL[1:0] are related to sectors B0F[7:6], respectively.
The blocks must be selected (or unselected) before doing an erase interlock write as part of the
Erase sequence. The select register is not writable once an interlock write is completed or if a high
voltage operation is suspended.
In the event that blocks are not present (due to configuration or total memory size), the
corresponding MSL bits default to unselected, and are not writable. The reset value will always be
0, and register writes have no effect.
0 Mid Address Space Block is unselected for Erase.
1 Mid Address Space Block is selected for Erase.
LSL[7:0]
LSL7-0: Low address space block SeLect 7-0 (Read/Write)
A value of 1 in the select register signifies that the block is selected for erase.
A value of 0 in the select register signifies that the block is not selected for erase. The reset value
for the select register is 0, or unselected.
LSL7-0 are related to sectors B0F7-0, respectively.
The blocks must be selected (or unselected) before doing an erase interlock write as part of the
Erase sequence. The select register is not writable once an interlock write is completed or if a high
voltage operation is suspended.
In the event that blocks are not present (due to configuration or total memory size), the
corresponding LSL bits will default to unselected, and will not be writable. The reset value will
always be 0, and register writes will have no effect.
0: Low Address Space Block is unselected for Erase.
1: Low Address Space Block is selected for Erase.
18.3.6.9
High address space Block Select register (HBS)
The High Address Space Block Select register provides a means to select blocks to be operated on during
erase.
Address: Base + 0x0014
R
Access: User read-only
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 153. High address space Block Select register (HBS)
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Flash Memory
18.3.6.10 Address Register (ADR)
The Address Register provides the first failing address in the event module failures (ECC, RWW, or FPEC)
or the first address at which a ECC single error correction occurs.
Address: Base + 0x0018
0
R
1
SAD TAD
Access: User read-only
2
3
4
5
6
7
8
9
10
11
12
13
14
15
AD
19
AD
18
AD
17
AD
16
0
0
0
0
0
0
0
0
0
0
0
0
0
AD
20
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
16
R AD
15
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
AD
14
AD
13
AD
12
AD
11
AD
10
AD
9
AD
8
AD
7
AD
6
AD
5
AD
4
AD
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
Figure 154. Address Register (ADR)
Table 156. ADR field descriptions
Field
Description
SAD
SAD: Shadow ADdress (Read Only)
When this bit is high, the address indicated by AD20-3 belongs to the Shadow Sector.
TAD
TAD: Test ADdress (Read Only)
When this bit is high, the address indicated by AD20-3 belongs to the Test Sector.
AD[20:3]
Address 20–3
ADR provides the first failing address in the event of ECC error (MCR[EER] set) or the first failing
address in the event of RWW error (MCR[RWE] set), or the address of a failure that may have
occurred in a FPEC operation (MCR[PEG] cleared). ADR also provides the first address at which a
ECC single error correction occurs (MCR[EDC] set).
The ECC double error detection takes the highest priority, followed by the RWW error, the FPEC
error, and the ECC single error correction. When accessed ADR will provide the address related to
the first event occurred with the highest priority. The priorities between these four possible events
is summarized in Table 157.
This address is always a double word address that selects 64 bits.
In case of a simultaneous ECC double error detection on both double words of the same page, bit
AD3 will output 0. The same is valid for a simultaneous ECC single error correction on both double
words of the same page.
In User mode, ADR is read only.
Table 157. ADR content: priority list
Priority level
Error flag
ADR content
1
MCR[EER] = 1
Address of first ECC Double Error
2
MCR[RWE] = 1
Address of first RWW Error
3
MCR[PEG] = 0
Address of first FPEC Error
4
MCR[EDC] = 1
Address of first ECC Single Error Correction
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Flash Memory
18.3.6.11 Bus Interface Unit 0 register (BIU0)
Address offset: 0x0001C
Reset value: 0xXXXX_XXXX
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BI031
BI030
BI029
BI028
BI027
BI026
BI025
BI024
BI023
BI022
BI021
BI020
BI019
BI018
BI017
BI016
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
BI015
BI014
BI013
BI012
BI011
BI010
BI009
BI008
BI007
BI006
BI005
BI004
BI003
BI002
BI001
BI000
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
Figure 155. Bus Interface Unit 0 register (BIU0)
The Bus Interface Unit 0 Register provides a means for BIU specific information or BIU configuration
information to be stored. Please refer to Section 18.2.4.2.1, “Platform Flash Configuration Register 0
(PFCR0)” for more information about register description.
Table 158. BIU0 field descriptions
Field
BI0
Description
BI0[31:00]: Bus Interface unit 0 31-00 (Read/Write)
The writability of the bits in this register can be locked.
18.3.6.12 Bus Interface Unit 1 register (BIU1)
Address offset: 0x00020
Reset value: 0xXXXX_XXXX
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BI131
BI130
BI129
BI128
BI127
BI126
BI125
BI124
BI123
BI122
BI121
BI120
BI119
BI118
BI117
BI116
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
BI115
BI114
BI113
BI112
BI111
BI110
BI109
BI108
BI107
BI106
BI105
BI104
BI103
BI102
BI101
BI100
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
Figure 156. Bus Interface Unit 1 register (BIU1)
The Bus Interface Unit 1 Register provides a means for BIU specific information or BIU configuration
information to be stored. Please refer to Section 18.2.4.2.2, “Platform Flash Configuration Register 1
(PFCR1)” for more information about register description.
Table 159. BIU1 field descriptions
Field
BI1
Description
BI1[31:00]: Bus Interface unit 1 31-00 (Read/Write)
The writability of the bits in this register can be locked.
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Flash Memory
18.3.6.13 Bus Interface Unit 2 register (BIU2)
Address offset: 0x00024
Reset value: 0xXXXX XXXX
Please refer to Section 18.2.4.2.3, “Platform Flash Access Protection Register (PFAPR)” to see register
description.
18.3.6.13.1 Non-volatile Bus Interface Unit 2 register (NVBIU2)
Address offset: 0x003E001
Delivery value: 0xXXXX_XXXX
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BI231
BI230
BI229
BI228
BI227
BI226
BI225
BI224
BI223
BI222
BI221
BI220
BI219
BI218
BI217
BI216
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
BI215
BI214
BI213
BI212
BI211
BI210
BI209
BI208
BI207
BI206
BI205
BI204
BI203
BI202
BI201
BI200
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
Figure 157. Bus Interface Unit 2 register (BIU2)
1
See device memory map table for base address information of shadow flash.
The Bus Interface Unit 2 Register provides a means for BIU specific information or BIU configuration
information to be stored. Please refer to Section 18.2.4.2.3, “Platform Flash Access Protection Register
(PFAPR)”for more information about register description.
The BIU2 register has a related Non-volatile Bus Interface Unit 2 register located in the Shadow Sector
that contains the default reset value for BIU2. During the reset phase of the Flash module, the NVBIU2
register content is read and loaded into the BIU2.
The NVBIU2 register is a 64-bit register, of which the 32 most significant bits 63:32 are ‘don’t care’ and
eventually used to manage ECC codes.
Table 160. BIU2 field descriptions
Field
Description
BI2[31:00]: Bus Interface unit 2 31-00 (Read/Write)
The BI2[31:00] generic registers are reset based on the information stored in NVBIU2.
The writability of the bits in this register can be locked.
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Flash Memory
18.3.6.14 Non Volatile Bus Interface Unit 3 register (NVBIU3)
Address offset: 0x003E081
1
Delivery value: 0xXXXX_XXXX
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BI331
BI330
BI329
BI328
BI327
BI326
BI325
BI324
BI323
BI322
BI321
BI320
BI319
BI318
BI317
BI316
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
BI315
BI314
BI313
BI312
BI311
BI310
BI309
BI308
BI307
BI306
BI305
BI304
BI303
BI302
BI301
BI300
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
rw/X
See device memory map table for base address information of shadow flash.
The Bus Interface Unit 3 Register provides a means for BIU specific information or BIU configuration
information to be stored.
The BIU3 register has a related Non-Volatile Bus Interface Unit 3 register located in the Shadow Sector
that contains the default reset value for BIU3. the NVBIU3 register is read during the reset phase of the
Flash Module and loaded into the BIU3.
The NVBIU3 register is a 64-bit register, the 32 most significative bits of which (bits 63:32) are
‘don’t care’ and eventually used to manage ECC codes.
Table 161. BIU3 field descriptions
Field
Description
BI331-00: Bus Interface unit 3 31-00 (Read/Write)
The BI331-00 generic registers are reset based on the information stored in NVBIU3.
The writability of the bits in this register can be locked.
The use of this bus is SoC specific.
18.3.6.15 User Test 0 register (UT0)
The User Test feature gives the user of the flash module the ability to perform test features on the flash.
The User Test 0 register allows controlling the way in which the flash content check is done.
The UT0[MRE], UT0[MRV], UT0[AIS], UT0[EIE], and DSI[7:0] bits are not accessible whenever
MCR[DONE] or UT0[AID] are low. Reads return indeterminate data. Writes have no effect.
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Flash Memory
Address: Base + 0x003C
0
1
R UTE SBC
E
W
Reset
Access: User read/write
2
3
4
5
6
7
0
0
0
0
0
0
8
9
10
11
12
13
14
DSI7 DSI6 DSI5 DSI4 DSI3 DSI2 DSI1 DSI0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
Reset
15
X
MRE MRV
0
0
0
EIE
AIS
AIE
0
0
0
0
31
AID
1
Figure 158. User Test 0 register (UT0)
Table 162. UT0 field descriptions
Field
Description
UTE
User Test Enable
This status bit indicates when User Test is enabled. All bits in UT0–2 and UMISR0–4 are locked
when this bit is 0.
This bit is not writeable to a 1, but may be cleared. The reset value is 0.
The method to set this bit is to provide a password, and if the password matches, the UTE bit is set
to reflect the status of enabled, and is enabled until it is cleared by a register write.
For UTE the password 0xF9F9_9999 must be written to the UT0 register.
Reserved (Read Only)
A write to these bits has no effect. A read of these bits always outputs 0.
DSI7-0
Data Syndrome Input 7–0
These bits represent the input of Syndrome bits of ECC logic used in the ECC Logic Check. The
DSI7–0 bits correspond to the 8 syndrome bits on a double word.
These bits are not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return
indeterminate data, and writes have no effect.
0 The syndrome bit is forced at 0.
1 The syndrome bit is forced at 1.
Reserved (Read Only)
A write to these bits has no effect. A read of these bits always outputs 0.
Reserved (Read/Write)
This bit can be written and its value can be read back, but there is no function associated.
This bit is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate
data, and writes have no effect.
MRE
Margin Read Enable
MRE enables margin reads to be done. This bit, combined with MRV, enables regular user mode
reads to be replaced by margin reads.
Margin reads are only active during Array Integrity Checks; Normal user reads are not affected by
MRE.
This bit is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate
data, and writes have no effect.
0 Margin reads are disabled. All reads are User mode reads.
1 Margin reads are enabled.
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Flash Memory
Table 162. UT0 field descriptions (continued)
Field
Description
MRV
Margin Read Value
If MRE is high, MRV selects the margin level that is being checked. Margin can be checked to an
erased level (MRV = 1) or to a programmed level (MRV = 0).
This bit is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate
data, and writes have no effect.
0 Zero’s (programmed) margin reads are requested (if MRE = 1).
1 One’s (erased) margin reads are requested (if MRE = 1).
EIE
ECC data Input Enable
EIE enables the ECC Logic Check operation to be done.
This bit is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate
data, and writes have no effect.
0 ECC Logic Check is disabled.
1 ECC Logic Check is enabled.
AIS
Array Integrity Sequence
AIS determines the address sequence to be used during array integrity checks or Margin Mode.
The default sequence (AIS = 0) is meant to replicate sequences normal user code follows, and
thoroughly checks the read propagation paths. This sequence is proprietary.
The alternative sequence (AIS = 1) is just logically sequential.
It should be noted that the time to run a sequential sequence is significantly shorter than the time
to run the proprietary sequence.
This bit is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate
data, and writes have no effect. In Margin Mode only the linear sequence (AIS = 1) is allowed, while
the proprietary sequence (AIS = 0) is forbidden.
0 Array Integrity sequence is a proprietary sequence.
1 Array Integrity or Margin Mode sequence is sequential.
AIE
Array Integrity Enable
AIE set to 1 starts the Array Integrity Check done on all selected and unlocked blocks.
The pattern is selected by AIS, and the MISR (UMISR0–4) can be checked after the operation is
complete, to determine if a correct signature is obtained.
AIE can be set only if MCR[ERS], MCR[PGM], and MCR[EHV] are all low.
0 Array Integrity Checks are disabled.
1 Array Integrity Checks are enabled.
AID
Array Integrity Done
AID is cleared upon an Array Integrity Check being enabled (to signify the operation is on-going).
Once completed, AID is set to indicate that the Array Integrity Check is complete. At this time, the
MISR (UMISR0–4) can be checked.
0 Array Integrity Check is on-going.
1 Array Integrity Check is done.
18.3.6.16 User Test 1 register (UT1)
The User Test 1 register allows to enable the checks on the ECC logic related to the 32 LSB of the Double
Word.
The User Test 1 register is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return
indeterminate data. Writes have no effect.
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Flash Memory
Address: Base + 0x0040
0
R DAI
W 31
Reset
0
16
R DAI
W 15
Reset
0
Access: User read/write
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DAI
30
DAI
29
DAI
28
DAI
27
DAI
26
DAI
25
DAI
24
DAI
23
DAI
22
DAI
21
DAI
20
DAI
19
DAI
18
DAI
17
DAI
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DAI
14
DAI
13
DAI
12
DAI
11
DAI
10
DAI
9
DAI
8
DAI
7
DAI
6
DAI
5
DAI
4
DAI
3
DAI
2
DAI
1
DAI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 159. User Test 1 register (UT1)
Table 163. UT1 field descriptions
Field
Description
DAI[31:0]
Data Array Input 31–0
These bits represent the input of the even word of ECC logic used in the ECC Logic Check. The
DAI[31:0] bits correspond to the 32 array bits representing Word 0 within the double word.
0 The array bit is forced at 0.
1 The array bit is forced at 1.
18.3.6.17 User Test 2 register (UT2)
The User Test 2 register allows to enable the checks on the ECC logic related to the 32 MSB of the Double
Word.
The User Test 2 register is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return
indeterminate data. Writes have no effect.
Address: Base + 0x0044
0
R DAI
63
W
Reset
0
16
R DAI
W 47
Reset
0
Access: User read/write
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DAI
62
DAI
61
DAI
60
DAI
59
DAI
58
DAI
57
DAI
56
DAI
55
DAI
54
DAI
53
DAI
52
DAI
51
DAI
50
DAI
49
DAI
48
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DAI
46
DAI
45
DAI
44
DAI
43
DAI
42
DAI
41
DAI
40
DAI
39
DAI
38
DAI
37
DAI
36
DAI
35
DAI
34
DAI
33
DAI
32
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 160. User Test 2 register (UT2)
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Flash Memory
Table 164. UT2 field descriptions
Field
Description
DAI[63:32]
Data Array Input [63:32]
These bits represent the input of the odd word of ECC logic used in the ECC Logic Check. The
DAI[63:32] bits correspond to the 32 array bits representing Word 1 within the double word.
0 The array bit is forced at 0.
1 The array bit is forced at 1.
18.3.6.18 User Multiple Input Signature Register 0 (UMISR0)
The Multiple Input Signature Register 0 (UMISR0) provides a mean to evaluate the array integrity.
UMISR0 represents the bits 31:0 of the whole 144-bit word (2 double words including ECC).
UMISR0 is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate data.
Writes have no effect.
Address: Base + 0x0048
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MS
030
MS
029
MS
028
MS
027
MS
026
MS
025
MS
024
MS
023
MS
022
MS
021
MS
020
MS
019
MS
018
MS
017
MS
016
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MS
014
MS
013
MS
012
MS
011
MS
010
MS
009
MS
008
MS
007
MS
006
MS
005
MS
004
MS
003
MS
002
MS
001
MS
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R MS
W 031
Reset
R MS
W 015
Reset
Access: User read/write
0
Figure 161. User Multiple Input Signature Register 0 (UMISR0)
Table 165. UMSIR0 field descriptions
Field
Description
MS[031:000]
Multiple input Signature 031–000
These bits represent the MISR value obtained by accumulating the bits 31:0 of all the pages read
from the flash memory.
The MS can be seeded to any value by writing the UMISR0 register.
18.3.6.19 User Multiple Input Signature Register 1 (UMISR1)
The Multiple Input Signature Register 1 (UMISR1) provides a means to evaluate the array integrity.
UMISR1 represents bits 63:32 of the whole 144-bit word (2 double words including ECC).
UMISR1 is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate data.
Writes have no effect.
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Flash Memory
Address: Base + 0x004C
0
R MS
W 063
Reset
0
16
R MS
W 047
Reset
0
Access: User read/write
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MS
062
MS
061
MS
060
MS
059
MS
058
MS
057
MS
056
MS
055
MS
054
MS
053
MS
052
MS
051
MS
050
MS
049
MS
048
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MS
046
MS
045
MS
044
MS
043
MS
042
MS
041
MS
040
MS
039
MS
038
MS
037
MS
036
MS
035
MS
034
MS
033
MS
032
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 162. User Multiple Input Signature Register 1 (UMISR1)
Table 166. UMISR1 field descriptions
Field
Description
MS[063:032]
Multiple input Signature 063–032
These bits represent the MISR value obtained accumulating the bits 63:32 of all the pages read
from the flash memory.
The MS can be seeded to any value by writing the UMISR1 register.
18.3.6.20 User Multiple Input Signature Register 2 (UMISR2)
The Multiple Input Signature Register (UMISR2) provides a mean to evaluate the array integrity. UMISR2
represents the bits 95-64 of the whole 144-bit word (2 double words including ECC).
UMISR2 is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate data.
Writes have no effect.
Address: Base + 0x0050
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MS
094
MS
093
MS
092
MS
091
MS
090
MS
089
MS
088
MS
087
MS
086
MS
085
MS
084
MS
083
MS
082
MS
081
MS
080
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MS
078
MS
077
MS
076
MS
075
MS
074
MS
073
MS
072
MS
071
MS
070
MS
069
MS
068
MS
067
MS
066
MS
065
MS
064
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R MS
W 095
Reset
R MS
W 079
Reset
Access: User read/write
0
Figure 163. User Multiple Input Signature Register 2 (UMISR2)
Table 167. UMISR2 field descriptions
Field
Description
MS[095:064]
Multiple input Signature 095–064
These bits represent the MISR value obtained by accumulating the bits 95:64 of all the pages read
from the flash memory.
The MS can be seeded to any value by writing the UMISR2 register.
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18.3.6.21 User Multiple Input Signature Register 3 (UMISR3)
The Multiple Input Signature Register 3 (UMISR3) provides a means to evaluate the array integrity.
UMISR3 represents bits 127:96 of the whole 144-bit word (2 double words including ECC).
UMISR3 is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate data.
Writes have no effect.
Address: Base + 0x0054
0
R MS
W 127
Reset
0
16
R MS
W 111
Reset
0
Access: User read/write
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MS
126
MS
125
MS
124
MS
123
MS
122
MS
121
MS
120
MS
119
MS
118
MS
117
MS
116
MS
115
MS
114
MS
113
MS
112
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MS
110
MS
109
MS
108
MS
107
MS
106
MS
105
MS
104
MS
103
MS
102
MS
101
MS
100
MS
099
MS
098
MS
097
MS
096
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 164. User Multiple Input Signature Register 3 (UMISR3)
Table 168. UMISR3 field descriptions
Field
Description
MS[127:096] Multiple Input Signature 127–096
These bits represent the MISR value obtained accumulating bits 127:96 of all the pages read from
the flash memory.
The MS can be seeded to any value by writing the UMISR3 register.
18.3.6.22 User Multiple Input Signature Register 4 (UMISR4)
The Multiple Input Signature Register 4 (UMISR4) provides a means to evaluate the array integrity. The
UMISR4 represents the ECC bits of the whole 144-bit word (2 double words including ECC). Bits 8:15
are ECC bits for the odd double word and bits 24:31 are the ECC bits for the even double word. Bits 4:5
and 20:21 of UMISR4 are the double and single ECC error detection for odd and even double words,
respectively.
UMISR4 is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate data.
Writes have no effect.
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Flash Memory
Address: Base + 0x0058
0
R MS
W 159
Reset
0
16
R MS
W 143
Reset
0
Access: User read/write
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MS
158
MS
157
MS
156
MS
155
MS
154
MS
153
MS
152
MS
151
MS
150
MS
149
MS
148
MS
147
MS
146
MS
145
MS
144
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MS
142
MS
141
MS
140
MS
139
MS
138
MS
137
MS
136
MS
135
MS
134
MS
133
MS
132
MS
131
MS
130
MS
129
MS
128
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 165. User Multiple Input Signature Register 4 (UMISR4)
Table 169. UMISR4 field descriptions
Field
Description
MS[159:128] Multiple Input Signature 159:128
These bits represent the MISR value obtained accumulating:
• MS[135:128]—8 ECC bits for the even double word
• MS138—Single ECC error detection for even double word
• MS139—Double ECC error detection for even double word
• MS[151:144]—8 ECC bits for the odd double word
• MS154—Single ECC error detection for odd double word
• MS155—Double ECC error detection for odd double word
The MS can be seeded to any value by writing the UMISR4 register.
18.3.6.23 Non-Volatile Private Censorship Password 0 register (NVPWD0)
The Non-Volatile Private Censorship Password 0 register (NVPWD0) contains the 32 LSB of the
password used to validate the Censorship information contained in NVSCI0–1 registers.
NOTE
This register is not implemented on the data flash block.
Address: 0x20_3DD8
0
1
Access: User read/write
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
W 31
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W 15
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 166. Non-Volatile private Censorship Password 0 register (NVPWD0)
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Flash Memory
Table 170. NVPWD0 field descriptions
Field
Description
PWD[31:0]
Password 31–0
The PWD[31:0] bits represent the 32 LSB of the private censorship password.
18.3.6.24 Non-Volatile Private Censorship Password 1 register (NVPWD1)
The Non-Volatile Private Censorship Password 1 Register (NVPWD1) contains the 32 MSB of the
password used to validate the Censorship information contained in NVSCI0–1 registers.
NOTE
This register is not implemented on the data flash block.
Address: 0x20_3DDC
0
1
Access: User read/write
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
W 63
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD PWD
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
W 47
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 167. Non-Volatile Private Censorship Password 1 register (NVPWD1)
Table 171. NVPWD1 field descriptions
Field
Description
PWD63–32: PassWorD 63–32
The PWD63–32 registers represent the 32 MSB of the Private Censorship Password.
18.3.6.25 Non-Volatile System Censoring Information 0 register (NVSCI0)
The Non-Volatile System Censoring Information 0 register (NVSCI0) stores the 32 LSB of the Censorship
Control Word of the device.
NVSCI0 is a non-volatile register located in Shadow sector. It is read during the reset phase of the flash
module and the protection mechanisms are activated consequently.
The parts are delivered uncensored to the user. Delivery value: 0x55AA_55AA.
NOTE
This register is not implemented on the data flash block.
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Flash Memory
Address: 0x20_3DE0
0
R SC
W 15
Reset
0
16
R CW
W 15
Reset
0
Access: User read/write
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SC
14
SC
13
SC
12
SC
11
SC
10
SC
9
SC
8
SC
7
SC
6
SC
5
SC
4
SC
3
SC
2
SC
1
SC
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
CW
14
CW
13
CW
12
CW
11
CW
10
CW
9
CW
8
CW
7
CW
6
CW
5
CW
4
CW
3
CW
2
CW
1
CW
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
Figure 168. Non-Volatile System Censoring Information 0 register (NVSCI0)
Table 172. NVSCI0 field descriptions
Field
Description
SC[15:0]
Serial Censorship control word 15–0
These bits represent the 16 LSB of the Serial Censorship Control Word (SCCW).
If SC[15:0] = 0x55AA and NVSCI1 = NVSCI0, the Public Access is disabled.
If SC[15:0] ≠ 0x55AA or NVSCI1 ≠ NVSCI0, the Public Access is enabled.
CW[15:0]
Censorship control Word 15–0
These bits represent the 16 LSB of the Censorship Control Word (CCW).
If CW[15:0] = 0x55AA and NVSCI1 = NVSCI0, the Censored mode is disabled.
If CW[15:0] ≠ 0x55AA or NVSCI1 ≠ NVSCI0, the Censored mode is enabled.
18.3.6.26 Non-Volatile System Censoring Information 1 register (NVSCI1)
The Non-Volatile System Censoring Information 1 register (NVSCI1) stores the 32 MSB of the
Censorship Control Word of the device.
NVSCI1 is a non-volatile register located in Shadow sector. It is read during the reset phase of the flash
module and the protection mechanisms are activated consequently.
The parts are delivered uncensored to the user. Delivery value: 0x55AA_55AA.
NOTE
This register is not implemented on the data flash block.
Address: 0x20_3DE4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SC
30
SC
29
SC
28
SC
27
SC
26
SC
25
SC
24
SC
23
SC
22
SC
21
SC
20
SC
19
SC
18
SC
17
SC
16
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
CW
30
CW
29
CW
28
CW
27
CW
26
CW
25
CW
24
CW
23
CW
22
CW
21
CW
20
CW
19
CW
18
CW
17
CW
16
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
R SC
W 31
Reset
R CW
W 31
Reset
Access: User read/write
0
Figure 169. Non-Volatile System Censoring Information 1 register (NVSCI1)
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Flash Memory
Table 173. NVSCI1 field descriptions
Field
Description
SC[32:16]
Serial Censorship control word 32–16
These bits represent the 16 MSB of the Serial Censorship Control Word (SCCW).
If SC[32:16] = 0x55AA and NVSCI1 = NVSCI0, the Public Access is disabled.
If SC[32:16] ≠ 0x55AA or NVSCI1≠ NVSCI0, the Public Access is enabled.
CW[32:16]
Censorship control Word 32–16
These bits represent the 16 MSB of the Censorship Control Word (CCW).
CW[32:16] = 0x55AA and NVSCI1 = NVSCI0, the Censored mode is disabled.
CW[32:16]≠ 0x55AA or NVSCI1≠ NVSCI0, the Censored mode is enabled.
18.3.6.27 Non-Volatile User Options register (NVUSRO)
The Non-Volatile User Options Register (NVUSRO) contains configuration information for the user
application.
NVUSRO is a 64-bit register, the 32 most significant bits of which (bits 63:32) are “don’t care” bits that
are eventually used to manage ECC codes.
NOTE
This register is not implemented on the data flash block.
Address: 0x20_3E18
0
R
W
1
Access: User read/write
2
3
4
5
6
7
8
9
10
11
12
14
15
UO31 UO30 UO29 UO28 UO27 UO26 UO25 UO24 UO23 UO22 UO21 UO20 UO19 UO18 UO17 UO16
Reset
x
x
x
x
x
x
x
x
x
x
x
x
x
x
16
17
18
19
20
21
22
23
24
25
26
27
28
29
R
W
13
0
UO15 UO14 UO13 UO12 UO11 UO10 UO9 UO8 UO7 UO6 UO5 UO4 UO3
Reset
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
30
31
OSCI
WAT
LLAT
CH
OR_
DOG
MAR
_EN
GIN
x
x
Figure 170. Non-Volatile User Options register (NVUSRO)
The Non-Volatile User Options Register (NVUSRO) contains configuration information for the user
application.
NVUSRO is a 64-bit register, the 32 most significant bits of which (bits 63:32) are “don’t care” bits that
are eventually used to manage ECC codes.
Table 174. NVUSRO field descriptions
Field
UO
Description
User Options 31–3
The UO[31:3] bits are reset based on the information stored in NVUSRO.
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Table 174. NVUSRO field descriptions (continued)
Field
Description
OSCILLATOR_ Oscillator Margin
MARGIN
0 Low consumption configuration (4 MHz/8 MHz).
1 High margin configuration (4/16 MHz).
Default manufacturing value before flash initialization is '1'
WATCHDOG_E Watchdog Enable
N
0 Disable after reset.
1 Enable after reset.
Default manufacturing value before flash initialization is '1'
18.3.7
Programming Considerations
NOTE
Like all flash memory, before an arbitrary value can be written to a memory
location in flash on these devices, the block containing that address must be
erased (all values set to “1”). The electrical characteristics of flash memory
allow write operations to only transition individual bits from “1” to “0”, and
to perform erase operations only at the block-level.
18.3.7.1
Modify Operations
All the modify operations of the flash modules are managed through the flash array control registers. All
blocks of each flash array module belong to the same partition (bank), therefore when a modify operation
is active on some blocks no read access is possible on any other block within the same array module.
During a flash modify operation any attempt to read any flash location within the same module will output
invalid data and bit RWE of MCR will be automatically set. This means that the flash module is not
fetchable when a modify operation is active within the same array module: the modify operation
commands must be executed from another array.
If during a modify operation a reset occurs, the operation is suddenly interrupted and the array is reset to
Read Mode. The data integrity of the flash section where the modify operation has been aborted is not
guaranteed: the interrupted flash modify operation must be repeated.
In general each modify operation is started through a sequence of 3 steps:
1. The first instruction is used to select the desired operation by setting its corresponding selection bit
in MCR (PGM or ERS) or UT0 (MRE or EIE).
2. The second step is the definition of the operands: the Address and the Data for programming or the
blocks for erase or factory margin read.
3. The third instruction is used to start the modify operation, by setting EHV in MCR or AIE in
theUT0 register.
Once selected, but not yet started, one operation can be canceled by resetting the operation selection bit.
A summary of the available flash modify operations are shown in Table 175.
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Table 175. Flash Modify Operations
Operation
Select bit
Operands
Start bit
Double Word Program
MCR.PGM
Address and Data by Interlock Writes
MCR.EHV
Block Erase
MCR.ERS
LMS, HBS
MCR.EHV
Array Integrity Check1
None
LMS, HBS
UT0.AIE
Factory Margin Read 1
UT0.MRE
UT0.MRV + LMS, HBS
UT0.AIE
ECC Logic Check 1
UT0.EIE
UT0.DSI, UT1, UT2
UT0.AIE
1
This operation is executed from User Test Mode. See Section 18.3.7.1.4, “User Test Mode”,for details.
In general each modify operation is completed through a sequence of 4 steps:
1. Wait for operation completion: wait for bit MCR.DONE (or UT0.AID) to go high.
2. Check operation result: check bit MCR.PEG (or compare UMISR0-4 with expected value).
3. Switch-Off flash controller by resetting MCR.EHV (or UT0.AIE).
4. Deselect current operation by clearing MCR.PGM/ERS (or UT0.MRE/EIE).
If a modify operation is on-going in an array then it is forbidden to start any other modify operation in the
other arrays on the device.
In the following sections all modify operations are described and some examples of the sequences needed
to activate them are presented.
18.3.7.1.1
Double Word Program
A flash program sequence operates on any double word within the flash. Up to 2 words within the double
word may be altered in a single program operation. During a program operation, ECC bits are
programmed. ECC is handled on a 64 bit boundary. Thus, if only 1 word in any given 64 bit ECC segment
is programmed, the adjoining word (in that segment) should not be programmed since ECC calculation
has already completed for that 64 bit segment. Attempts to program the adjoining word will result in an
operation failure. It is recommended that all programming operations be of 64 bits. The programming
operation should completely fill selected ECC segments within the double word.
Programming changes the value stored in an array bit from logic 1 to logic 0 only. Programming cannot
change a stored logic 0 to a logic 1.
Addresses in locked/disabled blocks cannot be programmed.
You can program the values in any or all of 2 words, of a double word, with a single program sequence.
Double word-bound words have addresses which differ only in address bit 2.
The Program operation consists of the following sequence of events:
1. Change the value in the MCR.PGM bit from 0 to 1.
2. Ensure the block that contains the address to be programmed is unlocked.
— Write the first address to be programmed with the program data.
— The flash module latches address bits (22:3) at this time.
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3.
4.
5.
6.
7.
8.
9.
— The flash module latches data written as well.
— This write is referred to as a program data interlock write. An interlock write may be as large
as 64 bits, and as small as 32 bits (depending on the CPU bus).
If more than one word is to be programmed, write the additional address in the double word with
data to be programmed. This is referred to as a program data write.
The flash modules ignore address bits (22:3) for program data writes.
The eventual unwritten data word default to 0xFFFFFFFF.
Write a logic 1 to the MCR.EHV bit to start the internal program sequence or skip to step 9 to
terminate.
Wait until the MCR.DONE bit goes high.
Confirm MCR.PEG=1.
Write a logic 0 to the MCR.EHV bit.
If more addresses are to be programmed, return to step 2.
Write a logic 0 to the MCR.PGM bit to terminate the program operation.
A program may be initiated with the 0 to 1 transition of the MCR.PGM bit or by clearing the MCR.EHV
bit at the end of a previous program.
The first write after a program is initiated determines the page address to be programmed. This first write
is referred to as an interlock write. The interlock write determines if the shadow or normal array space will
be programmed by causing MCR.PEAS to be set/cleared.
An interlock write must be performed before setting MCR.EHV. An application may terminate a program
sequence by clearing MCR.PGM prior to setting MCR.EHV.
While MCR.DONE is low and MCR.EHV is high, an application may clear EHV, resulting in a program
abort.
A program abort forces the Module to step 8 of the program sequence.
An aborted program will result in MCR.PEG being set low, indicating a failed operation. MCR.DONE
must be checked to know when the aborting command has completed.
The data space being operated on before the abort will contain indeterminate data. This may be recovered
by repeating the same program instruction with the same data or executing an erase of the affected blocks.
Example 18-1. Double Word Program of data 0x55AA55AA at address 0x00AAA8 and data 0xAA55AA55 at
address 0x00AAAC.
MCR = 0x00000010; /* Set PGM in MCR: Select PGM Operation */
(0x00AAA8) = 0x55AA55AA; /* Latch Address and 32 LSB data */
(0x00AAAC) = 0xAA55AA55; /* Latch 32 MSB data */
MCR = 0x00000011; /* Set EHV in MCR: Operation Start */
do /* Loop to wait for DONE=1 */
{ tmp = MCR; /* Read MCR */
} while ( !(tmp & 0x00000400) );
status = MCR & 0x00000200; /* Check PEG flag */
MCR = 0x00000010; /* Reset EHV in MCR: Operation End */
MCR = 0x00000000; /* Reset PGM in MCR: Deselect Operation */
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18.3.7.1.2
Block Erase
Erase changes the value stored in all bits of the selected block(s) to logic 1. An erase sequence operates on
any combination of blocks in the low, mid or high address space, or the shadow block (if available).
• The erase sequence is fully automated within the flash. an application only needs to select the
blocks to be erased and initiate the erase sequence.
• Locked/disabled blocks cannot be erased.
• If multiple blocks are selected for erase during an erase sequence, no specific operation order must
be assumed.
The Erase operation consists of the following sequence of events:
1. Change the value in the MCR.ERS bit from 0 to 1.
2. Select the block(s) to be erased by writing 1’s to the appropriate register(s) in LMSR or HSR
registers.
If the shadow block is to be erased, this step may be skipped, and LMSR and HSR are ignored.
Note that Lock and Select are independent. If a block is selected and locked, no erase will occur.
3. Write to any address in flash. This is referred to as an erase interlock write.
4. Write a logic 1 to the MCR.EHV bit to start the internal erase sequence or skip to step 9 to
terminate.
5. Wait until the MCR.DONE bit goes high.
6. Confirm MCR.PEG=1.
7. Write a logic 0 to the MCR.EHV bit.
8. If more blocks are to be erased, return to step 2.
9. Write a logic 0 to the MCR.ERS bit to terminate the erase operation.
Additional considerations:
• After setting MCR.ERS, one write, referred to as an interlock write, must be performed before
MCR.EHV can be set to 1.
• Data words written during erase sequence interlock writes are ignored.
• An application may terminate the erase sequence by clearing ERS before setting EHV.
• An erase operation may be aborted by clearing MCR.EHV assuming MCR.DONE is low,
• MCR.EHV is high and MCR.ESUS is low.
• An erase abort forces the Module to step 8 of the erase sequence.
• An aborted erase will result in MCR.PEG being set low, indicating a failed operation.
• MCR.DONE must be checked to know when the aborting command has completed.
• The block(s) being operated on before the abort contain indeterminate data. This may be recovered
by executing an erase on the affected blocks.
• An application may not abort an erase sequence while in erase suspend.
The following example selects two blocks using the LSEL[2-1] bits of the LMSR register to select blocks
2a and 1b (see Table 137 for the flash space memory map and Section 18.3.6.2, “Low/Mid Address Space
Block Locking register (LML)”, ) and performs an erase.
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Example 18-2. Erase of Blocks 2a and 1b
MCR = 0x00000004; /* Set ERS in MCR: Select ERS Operation */
LMSR = 0x00000006; /* Set LSEL2-1 in LMSR: Select blocks to erase */
(0x000000) = 0xFFFFFFFF; /* Latch a Flash Address with any data */
MCR = 0x00000005; /* Set EHV in MCR: Operation Start */
do /* Loop to wait for DONE=1 */
{ tmp = MCR; /* Read MCR */
} while ( !(tmp & 0x00000400) );
status = MCR & 0x00000200; /* Check PEG flag */
MCR = 0x00000004; /* Reset EHV in MCR: Operation End */
MCR = 0x00000000; /* Reset ERS in MCR: Deselect Operation */
18.3.7.1.3
Erase Suspend/Resume
The erase sequence may be suspended to allow read access to the flash array. It is not possible to program
or to erase during an erase suspend. During erase suspend, all reads to blocks targeted for erase return
indeterminate data.
An erase suspend is initiated by changing the value of the MCR.ESUS bit from 0 to 1. MCR.ESUS can be
set to 1 at any time when MCR.ERS and MCR.EHV are high and MCR.PGM is low. A 0 to 1 transition
of MCR.ESUS causes the array module to start the sequence which places it in erase suspend.
An application must wait until MCR.DONE=1 before the erase operation is suspended and further actions
are attempted. MCR.DONE will go high after MCR.ESUS is set to 1.
Once suspended, the array may be read. Reads while MCR.ESUS=1 from the block(s) being erased return
indeterminate data.
Example 18-3. Block Erase Suspend.
MCR = 0x00000007; /* Set ESUS in MCR: Erase Suspend */
do /* Loop to wait for DONE=1 */
{ tmp = MCR; /* Read MCR */
} while ( !(tmp & 0x00000400) );
Note that there is no need to clear MCR.EHV and MCR.ERS in order to perform reads during erase
suspend. The erase sequence is resumed by writing a logic 0 to MCR.ESUS.
MCR.EHV must be set to 1 before MCR.ESUS can be cleared to resume the operation.
The array module continues the erase sequence from one of a set of predefined points. This may
extend the time required for the erase operation.
Example 18-4. Block Erase Resume.
MCR = 0x00000005; /* Reset ESUS in MCR: Erase Resume */
18.3.7.1.4
User Test Mode
User Test Mode is a mode that customers can put the flash array module in to do specific tests to check
integrity.
Three kinds of test can be performed:
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•
•
•
Array Integrity Self Check
Factory Margin Mode Read
ECC Logic Check
The User Test Mode is equivalent to a modify operation: read accesses attempted during User Test Mode
generate a Read-While-Write Error (RWE of MCR set).
User Test operations are not allowed on the Test and Shadow blocks.
Array Integrity Self Check
Array Integrity is checked using a pre-defined address sequence (proprietary), and is executed on selected
and unlocked blocks. Once the operation is completed, the results of the reads can be checked by reading
the MISR value (stored in UMISR0-4), to determine if an incorrect read, or ECC detection was noted.
The internal MISR calculator is a 32 bit register.
The 128-bit data, the 16 ECC data and the single and double ECC errors of the two double words are
therefore captured by the MISR through 5 different read accesses at the same location.
The whole check is done through 5 complete scans of the memory address space:
1. The first pass will scan only bits 31-0 of each page.
2. The second pass will scan only bits 63-32 of each page.
3. The third pass will scan only bits 95-64 of each page.
4. The fourth pass will scan only bits 127-96 of each page.
5. The fifth pass will scan only the ECC bits (8 + 8) and the single and double ECC errors (2 + 2) of
both double words of each page.
The 128 data bit and the 16 ECC data are sampled before the eventual ECC correction, while the single
and double error flags are sampled after the ECC evaluation.
Only data from existing and unlocked locations are captured by the MISR.
The MISR can be seeded to any value by writing the UMISR0-4 registers.
The Array Integrity Self Check consists of the following sequence of events:
1. Set UTE in UT0 by writing the related password in UT0.
2. Select the block(s) to be checked by writing 1’s to the appropriate register(s) in LMSR or HSR
registers.
Note that Lock and Select are independent. If a block is selected and locked, no Array Integrity
Check will occur.
3. Set UT0.AIS bit for a sequential addressing only.
4. Write a logic 1 to the UT0.AIE bit to start the Array Integrity Check.
5. Wait until the UT0.AID bit goes high.
6. Compare UMISR0-4 content with the expected result.
7. Write a logic 0 to the UT0.AIE bit.
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8. If more blocks are to be checked, return to step 2.
It is recommended to leave UT0.AIS at 0 and use the proprietary address sequence that checks the read
path more fully, although this sequence takes more time. While UT0.AID is low and UT0.AIE is high, an
application may clear AIE, resulting in a Array Integrity Check abort. UT0.AID must be checked to know
when the aborting command has completed.
The following example selects two blocks using the LSEL[2-1] bits of the LMSR register to select blocks
2a and 1b and performs an array integrity check of those blocks.
Example 18-5. Array Integrity Check of Blocks 2a and 1b
UT0 = 0xF9F99999; /* Set UTE in UT0: Enable User Test */
LMSR = 0x00000006; /* Set LSEL2-1 in LMSR: Select blocks */
UT0 = 0x80000002; /* Set AIE in UT0: Operation Start */
do /* Loop to wait for AID=1 */
{ tmp = UT0; /* Read UT0 */
} while ( !(tmp & 0x00000001) );
data0 = UMISR0; /* Read UMISR0 content*/
data1 = UMISR1; /* Read UMISR1 content*/
data2 = UMISR2; /* Read UMISR2 content*/
data3 = UMISR3; /* Read UMISR3 content*/
data4 = UMISR4; /* Read UMISR4 content*/
UT0 = 0x00000000; /* Reset UTE and AIE in UT0: Operation End */
Factory Margin Read
NOTE
Factory margin read is a diagnostic to check proper programming, for
example by 3rd party programming service providers. It is not supported in
customer applications because the voltages used for margin reads can
reduce the life expectancy of the flash array.
The factory margin read procedure (either Margin 0 or Margin 1) can be run on unlocked blocks to
unbalance the sense amplifiers with respect to standard read conditions so that all read accesses reduce the
margin vs ‘0’ (UT0.MRV = ‘0’) or vs ‘1’ (UT0.MRV = ‘1’). Locked sectors are ignored by MISR
calculation and ECC flagging.
The results of the factory margin reads can be checked by comparing the checksum value in the UMISR0-4
registers.
Since factory margin reads are done at voltages that are higher than the normal read voltages, lifetime
expectancy of the flash may be impacted. Doing factory margin reads repeatedly results in degradation of
the flash array and shortens the lifetime expected with normal read levels. For these reasons this capability
is reserved for factory use only and is not supported in user applications. Charge losses detected via margin
reads are not considered failures of the device and no Failure Analysis will be opened on them.
The Margin Read Setup operation consists of the following sequence of events:
1. Set UTE in UT0 by writing the related password in UT0.
2. Select the block(s) to be checked by writing 1’s to the appropriate register(s) in LMS or HBS
registers.
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Note that Lock and Select are independent. If a block is selected and locked, no Margin Read will
occur.
3. Set eventually UT0.AIS bit for a sequential addressing only.
4. Change the value in the UT0.MRE bit from 0 to 1.
5. Select the Margin level: UT0.MRV=0 for 0’s margin, UT0.MRV=1 for 1’s margin.
6. Write a logic 1 to the UT0.AIE bit to start the Margin Read Setup or skip to step 6 to terminate.
7. Wait until the UT0.AID bit goes high.
8. Compare UMISR0-4 content with the expected result.
9. Write a logic 0 to the UT0.AIE, UT0.MRE and UT0.MRV bits.
10. If more blocks are to be checked, return to step 2.
It is recommended to leave UT0.AIS at 1 and use the linear address sequence, which takes less time.
During the execution of the Margin Read operation it is forbidden to modify the content of Block Select
(LMS, HBS) and Lock (LML, SLL, HBL) registers, otherwise the MISR value can vary in an
unpredictable way.
The read accesses will be done with the addition of a proper number of Wait States to guarantee the
correctness of the result.
While UT0.AID is low and UT0.AIE is high, the user may clear AIE, resulting in a Array Integrity Check
abort.
UT0.AID must be checked to know when the aborting command has completed.
Example 18-6. Margin Read Check versus 1’s .
UMISR0 = 0x00000000; /* Reset UMISR0 content */
UMISR1 = 0x00000000; /* Reset UMISR1 content */
UMISR2 = 0x00000000; /* Reset UMISR2 content */
UMISR3 = 0x00000000; /* Reset UMISR3 content */
UMISR4 = 0x00000000; /* Reset UMISR4 content */
UT0 = 0xF9F99999; /* Set UTE in UT0: Enable User Test */
LMS = 0x00000006; /* Set LSL2-1 in LMS: Select Sectors */
UT0 = 0x80000004; /* Set AIS in UT0: Select Operation */
UT0 = 0x80000024; /* Set MRE in UT0: Select Operation */
UT0 = 0x80000034; /* Set MRV in UT0: Select Margin versus 1’s */
UT0 = 0x80000036; /* Set AIE in UT0: Operation Start */
do /* Loop to wait for AID=1 */
{ tmp = UT0; /* Read UT0 */
} while ( !(tmp & 0x00000001) );
data0 = UMISR0; /* Read UMISR0 content*/
data1 = UMISR1; /* Read UMISR1 content*/
data2 = UMISR2; /* Read UMISR2 content*/
data3 = UMISR3; /* Read UMISR3 content*/
data4 = UMISR4; /* Read UMISR4 content*/
UT0 = 0x80000034; /* Reset AIE in UT0: Operation End */
UT0 = 0x00000000; /* Reset UTE, MRE, MRV, AIS in UT0: Deselect Op. */
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ECC Logic Check
ECC Logic Check verifies the integrity of the ECC correction and detection logic. The operation provides
user control over the 64 data bit + 8 parity bit inputs. Results of the ECC logic can be checked by reading
the MISR value.
The ECC Logic Check operation consists of the following sequence of events:
1. Set UTE in UT0 by writing the related password in UT0.
2. Write in UT1.DAI31-0 and UT2.DAI63-32 the double word input value.
3. Write in UT0.DSI7-0 the Syndrome Input value.
4. Select the ECC Logic Check: write a logic 1 to the UT0.EIE bit.
5. Write a logic 1 to the UT0.AIE bit to start the ECC Logic Check.
6. Wait until the UT0.AID bit goes high.
7. Compare UMISR0-4 content with the expected result.
8. Write a logic 0 to the UT0.AIE bit.
Notice that when UT0.AID is low UMISR0-4, UT1-2 and bits MRE, MRV, EIE, AIS and DSI7-0 of UT0
are not accessible: reading returns indeterminate data and writing has no effect.
Example 18-7. ECC Logic Check
UT0 = 0xF9F99999; /* Set UTE in UT0: Enable User Test */
UT1 = 0x55555555; /* Set DAI31-0 in UT1: Even Word Input Data */
UT2 = 0xAAAAAAAA; /* Set DAI63-32 in UT2: Odd Word Input Data */
UT0 = 0x80FF0000; /* Set DSI7-0 in UT0: Syndrome Input Data */
UT0 = 0x80FF0008; /* Set EIE in UT0: Select ECC Logic Check */
UT0 = 0x80FF000A; /* Set AIE in UT0: Operation Start */
do /* Loop to wait for AID=1 */
{ tmp = UT0; /* Read UT0 */
} while ( !(tmp & 0x00000001) );
data0 = UMISR0; /* Read UMISR0 content (expected 0x55555555) */
data1 = UMISR1; /* Read UMISR1 content (expected 0xAAAAAAAA) */
data2 = UMISR2; /* Read UMISR2 content (expected 0x55555555) */
data3 = UMISR3; /* Read UMISR3 content (expected 0xAAAAAAAA) */
data4 = UMISR4; /* Read UMISR4 content (expected 0x00FF00FF) */
UT0 = 0x00000000; /* Reset UTE, AIE and EIE in UT0: Operation End */
18.3.7.2
Error correction code
The Flash module provides a method to improve the reliability of the data stored in Flash: the usage of an
Error Correction Code. The word size is fixed at 64 bits.
Eight ECC bits, programmed to guarantee a Single Error Correction and a Double Error Detection
(SEC-DED), are associated to each 64-bit Double Word.
ECC circuitry provides correction of single bit faults and is used to achieve automotive reliability targets.
Some units will experience single bit corrections throughout the life of the product with no impact to
product reliability.
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18.3.7.2.1
ECC algorithms
The Flash module supports one ECC Algorithm: “All ‘1’s No Error”. A modified Hamming code is used
that ensures the all erased state (that is, 0xFFFF.....FFFF) data is a valid state, and will not cause an ECC
error. This allows the user to perform a blank check after a sector erase operation.
18.3.7.3
EEprom emulation
18.3.7.4
Eprom Emulation
The choosen ECC algorithm allows some bit manipulations so that a Double Word can be rewritten several
times without needing an erase of the sector. This allows to use a Double Word to store flags useful for the
Eeprom Emulation. As an example the choosen ECC algorithm allows to start from an All ‘1’s Double
Word value and rewrite whichever of its four 16-bits Half-Words to an All ‘0’s content by keeping the same
ECC value.
The following table shows a set of Double Words sharing the same ECC value:
Table 176. Bits Manipulation: Double Words with the same ECC value
Double Word
ECC All ‘1’s No Error
0xFFFF_FFFF_FFFF_FFFF
0xFF
0xFFFF_FFFF_FFFF_0000
0xFF
0xFFFF_FFFF_0000_FFFF
0xFF
0xFFFF_0000_FFFF_FFFF
0xFF
0x0000_FFFF_FFFF_FFFF
0xFF
0xFFFF_FFFF_0000_0000
0xFF
0xFFFF_0000_FFFF_0000
0xFF
0x0000_FFFF_FFFF_0000
0xFF
0xFFFF_0000_0000_FFFF
0xFF
0x0000_FFFF_0000_FFFF
0xFF
0x0000_0000_FFFF_FFFF
0xFF
0xFFFF_0000_0000_0000
0xFF
0x0000_FFFF_0000_0000
0xFF
0x0000_0000_0000_0000
0xFF
When some Flash sectors are used to perform an Eeprom Emulation, it is reccomended for safety reasons
to reserve at least 3 sectors to this purpose.
18.3.7.4.1
All ‘1’s No Error
The All ‘1’s No Error Algorithm detects as valid any Double Word read on a just erased sector (all the 72
bits are ‘1’s).
This option allows to perform a Blank Check after a Sector Erase operation.
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18.3.7.5
Protection strategy
Two kinds of protection are available: Modify Protection to avoid unwanted program/erase in Flash sectors
and Censored Mode to avoid piracy.
18.3.7.5.1
Modify protection
The Flash Modify Protection information is stored in non-volatile Flash cells located in the TestFlash. This
information is read once during the Flash initialization phase following the exiting from Reset and is stored
in volatile registers that act as actuators.
The reset state of all the volatile modify protection registers is the protected state.
All the non-volatile modify protection registers can be programmed through a normal Double Word
Program operation at the related locations in TestFlash.
The non-volatile modify protection registers cannot be erased.
• The non-volatile Modify Protection Registers are physically located in TestFlash their bits can be
programmed to ‘0’ only once and they can no more be restored to ‘1’.
• The Volatile Modify Protection Registers are Read/Write registers which bits can be written at ‘0’
or ‘1’ by the user application.
A software mechanism is provided to independently lock/unlock each Low, Mid and High Address Space
Block against program and erase.
Software locking is done through the LML (Low/Mid Address Space Block Lock Register) or HBL (High
Address Space Block Lock Register) registers.
An alternate means to enable software locking for blocks of Low Address Space only is through the SLL
(Secondary Low/Mid Address Space Block Lock Register).
All these registers have a non-volatile image stored in TestFlash (NVLML, NVHBL, NVSLL), so that the
locking information is kept on reset.
On delivery the TestFlash non-volatile image is at all ‘1’s, meaning all sectors are locked.
By programming the non-volatile locations in TestFlash the selected sectors can be unlocked.
Being the TestFlash One Time Programmable (that is, not erasable), once unlocked the sectors cannot be
locked again.
Of course, on the contrary, all the volatile registers can be written at 0 or 1 at any time, therefore the user
application can lock and unlock sectors when desired.
18.3.7.5.2
Censored Mode
The Censored Mode information is stored in non-volatile Flash cells located in the Shadow Sector. This
information is read once during the Flash initialization phase following the exiting from Reset and is stored
in volatile registers that act as actuators.
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The reset state of all the Volatile Censored Mode Registers is the protected state.
All the non-volatile Censored Mode registers can be programmed through a normal Double Word Program
operation at the related locations in the Shadow Sector.
The non-volatile Censored Mode registers can be erased by erasing the Shadow Sector.
• The non-volatile Censored Mode Registers are physically located in the Shadow Sector their bits
can be programmed to ‘0’ and eventually restored to ‘1’ by erasing the Shadow Sector.
• The Volatile Censored Mode Registers are registers not accessible by the user application.
The Flash module provides two levels of protection against piracy:
• If bits CW15:0 of NVSCI0 are programmed at 0x55AA and NVSC1 = NVSCI0 the Censored
Mode is disabled, while all the other possible values enable the Censored Mode.
• If bits SC15:0 of NVSCI0 are programmed at 0x55AA and NVSC1 = NVSCI0 the Public Access
is disabled, while all the other possible values enable the Public Access.
The parts are delivered to the user with Censored Mode and Public Access disabled.
18.4
18.4.1
Data Flash Memory
Block Overview
The primary function of the Flash Module is to serve as electrically programmable and erasable
Non-Volatile Memory.
NV Memory may be used for instruction and/or data storage.
The Module is a Non-Volatile solid-state silicon memory device consisting of blocks (called also sectors)
of single transistor storage elements, an electrical means for selectively adding (programming) and
removing (erasing) charge from these elements, and a means of selectively sensing (reading) the charge
stored in these elements.
The Flash Module is arranged as two functional units: the Flash Core and the Memory Interface.
The Flash Core is composed of arrayed Non-Volatile storage elements, sense amplifiers, row decoders,
column decoders and charge pumps. The arrayed storage elements in the Flash Core are sub-divided into
physically separate units referred to as blocks (or sectors).
Flash core is organized including ECC correction code. ECC circuitry provides correction of single bit
faults and is used to achieve automotive reliability targets. Some units will experience single bit
corrections throughout the life of the product with no impact to product reliability.
The Memory Interface contains the registers and logic which control the operation of the Flash Core. The
Memory Interface is also the interface between the Flash Module and a Bus Interface Unit (BIU) and may
contain the ECC logic and redundancy logic.
A BIU connects the Flash Module to a system bus, and contains all system level customization required
for the SoC application. The Flash Module is generic and requires a BIU to configure it for different SoC
applications. A BIU is not included as a part of the Flash Module.
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18.4.2
•
•
•
•
•
•
•
•
•
Features
120 ns Access Time
32 bits Read/Write parallelism
7 bits Error Correction Code (SEC-DED) to enhance Data Retention
Sector Erase
Single Bank: Read-While-Modify not available
Erase Suspend available (Program Suspend not available)
Software programmable Program/Erase Protection to avoid unwanted writings
Shadow Sector not available
Optimized Data Flash is a slave IP that requires clocks and reference current coming from Master
LC Data Flash
18.4.3
Block Diagram
The Flash Macrocell contains one Matrix Module, composed by a Single Bank: Bank 0, normally used for
Code storage. No Read-While-Modify operations are possible.
The Modify operations are managed by an embedded Flash Program/Erase Controller (FPEC). Commands
to the FPEC are given through a User Registers Interface. The read data bus is 32 bits wide, while the Flash
registers are on a separate bus 32 bits wide. The High Voltages needed for Program/Erase operations are
internally generated.
HV generator
Flash Bank 0
Flash
Program/Erase
Controller
64KB
+ 8KB TestFlash
Flash
Registers
Matrix
Interface
Registers
Interface
Figure 171. Flash Macrocell Structure
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18.4.4
18.4.4.1
Functional Description
Macrocell Structure
The Flash Macrocell is designed for use in embedded MCU/SoC applications which require Data
Non-Volatile Memories for EE emulation.
The Flash Module is addressable by Word (32 bits) for program and for read.
The Flash Module supports fault tolerance through Error Correction Code (ECC) and/or error detection.
The ECC implemented within the Flash Module will correct single bit failures and detect double bit
failures.
The Flash Module uses an embedded hardware algorithm implemented in the Memory Interface to
program and erase the Flash Core.
Control logic that works with the software block enables, and software lock mechanisms, is included in
the embedded hardware algorithm to guard against accidental program/erase.
The hardware algorithm perform the steps necessary to ensure that the storage elements are programmed
and erased with sufficient margin to guarantee data integrity and reliability.
A programmed bit in the Flash Module reads as logic level 0 (or low).
An erased bit in the Flash Module reads as logic level 1 (or high).
Program and erase of the Flash Module requires multiple system clock cycles to complete.
The erase sequence may be suspended.
The program and erase sequences may be aborted.
Being a slave IP, Data Flash requires Code Flash to be active (means not under reset or in Disable Mode
or in Sleep Mode) in order to be active.
18.4.4.2
Data flash sectorization
The Flash Module supports memory sizes of 72 KB of User Memory, plus 8KB of Test Memory.
There are two User Address Spaces: Low and Mid Address Space.
There is only one size of blocks available to the User in the Flash Core: 16KB. 8KB is reseved for Test
Flash
The Flash Module is composed by a single Bank (Bank 0): Read-While-Modify is not supported.
Bank 0 of the 72 KB Flash macrocell is divided in 4 sectors. Bank 0 contains also a reserved sector named
TestFlash in which some One Time Programmable User data are stored.
Table 177. Data Flash Module Sectorization
Bank
Sector
Addresses
Size
Address Space
B0
B0F0
0x000000 to 0x003FFF
16KB
Low Address Space
B0
B0F1
0x004000 to 0x007FFF
16KB
Low Address Space
B0
B0F2
0x008000 to 0x00BFFF
16KB
Low Address Space
B0
B0F3
0x00C000 to 0x00FFFF
16KB
Low Address Space
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Table 177. Data Flash Module Sectorization
Bank
Sector
Addresses
Size
Address Space
B0
Reserved
0x010000 to 0x03FFFF
192KB
Low Address Space
B0
Reserved
0x040000 to 0x07FFFF
256KB
Mid Address Space
B0
B0TF
0x402000 to 0x403FFF
8KB
Test Address Space
B0
Reserved
0x404000 to 0x7FFFFF
4080KB
Test Address Space
The Flash Module is divided into blocks also to implement independent Erase/Program protection. A
software mechanism is provided to independently lock/unlock each block in low, mid address space
against program and erase.
18.4.4.3
Test Flash Block
The TestFlash block exists outside the normal address space and is programmed, erased and read
independently of the other blocks. The independent TestFlash block is reserved to store the Non Volatile
informations related to Redundancy, Configuration and Protection.
Due to this special usage, the TestFlash sector is not affected by the Column Redundancy. The ECC, on
the contrary, is applied also to TestFlash.
The usage of reserved TestFlash sector is detailed in the following table.
Table 178. TestFlash structure
Name
NVLML
NVSLL
Description
Addresses
Size
User Reserved
0x403D00 to 0x403DE7
232 byte
NV Low/Mid address space block Locking reg
0x403DE8 to 0x403DEF
8 byte
Reserved
0x403DF0 to 0x403DF7
8 byte
NV Secondary Low/mid add space block Lock reg
0x403DF8 to 0x403DFF
8 byte
User Reserved
0x403E00 to 0x403EFF
256 byte
Reserved
0x403F00 to 0x403FB7
184 byte
The Test Flash block can be enabled by the BIU. When the Test space is enabled, the program operations
to the Test block are allowed from 0x403D00 to 0x403EFF (User/Lock area is One Time Programmable).
User Mode program of the test block are enabled only when MCR.PEAS is high. The TestFlash block
contains specified data that are needed for Flash Macrocell or the device features.
In User Mode the Flash Module may be read and written (register writes and interlock writes),
programmed or erased. The default state of the Flash Module is read. The main and test address space can
be read only in the read state.
The Flash registers are always available for read, also when the Module is in disable mode (except few
documented registers). The Flash Module enters the read state on reset. The Module is in the read state
under two sets of conditions:
• The read state is active when the Module is enabled (User Mode Read)
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•
The read state is active when MCR.ERS and MCR.ESUS are high and MCR.PGM is low (Erase
Suspend).
Notice that no Read-While-Modify is available. Flash Core reads return 32 bits. Registers reads return 32
bits (1 Word). Flash Core reads are done through the Bus Interface Unit.
Registers reads to unmapped register address space will return all 0’s. Registers writes to unmapped
register address space will have no effect. Array reads attempted to invalid locations will result in
indeterminate data. Invalid locations occur when addressing is done to blocks that do not exist in non 2n
array sizes.
Interlock writes attempted to invalid locations, will result in an interlock occurring, but attempts to
program these blocks will not occur since they are forced to be locked. Erase will occur to selected and
unlocked blocks even if the interlock write is to an invalid location.
Simultaneous Read cycle on the Flash Matrix and Read/Write cycles on the Registers are possible. On the
contrary Registers Read/Write accesses simultaneous to a Flash Matrix interlock write are forbidden.
18.4.4.4
Reset
A reset is the highest priority operation for the Flash module and terminates all other operations.
The Flash Module uses reset to initialize register and status bits to their default reset values. If the Flash
Module is executing a Program or Erase operation (MCR.PGM = 1 or MCR.ERS = 1) and a reset is issued,
the operation will be suddently terminated and the module will disable the high voltage logic without
damage to the high voltage circuits. Reset terminates all operations and forces the Flash Module into User
mode ready to receive accesses. Reset and power-off must not be used as a systematic way to terminate a
Program or Erase operation.
After reset is negated, read register access may be done, although it should be noted that registers that
require updating from TEST block or KRAM information, or other inputs, may not be read until
MCR.DONE transitions. MCR.DONE may be polled to determine if the Flash module has transitioned out
of reset. Notice that the registers cannot be written until MCR.DONE is high.
18.4.4.5
Power-down mode
The power-down mode allows to turn off all Flash DC current sources, so that all power dissipation is due
only to leakage in this mode.
Reads from or writes to the module are not possible in power-down mode.
The user may not read some registers (UMISR0–1, UT1–1 and part of UT0) until the power-down mode
is exited. On the contrary write access is locked on all the registers in Disable Mode.
When enabled the Flash Module returns to its pre-disable state in all cases unless in the process of
executing an erase high voltage operation at the time of disable.
If the Flash Module is disabled during an erase operation, MCR.ESUS bit is set to 1. This means that Flash
macrocell is first put into suspend state (after tSUSP). The User may resume the erase operation at the time
the Module is enabled by clearing MCR.ESUS bit. MCR.EHV must be high to resume the erase operation.
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If the Flash Module is disabled during a program operation, the Disable Mode will be entered only after
the programming ends.
18.4.4.6
Slave Mode
Being a slave, Data Flash requires Code Flash to be active (means not under reset or in Disable Mode or
in Sleep Mode) in order to be active.
It is forbidden to put code flash0 in Disable Mode or in Sleep mode or under reset when the data flash is
active.
18.4.5
Register description
The Flash user registers mapping is shown in the Table 179.
Table 179. Data Flash Registers
Address offset
Register name
0x0000
Module Configuration Register (MCR)
0x0004
Low/Mid Address Space Block Locking register (LML)
0x0008
Reserved
0x000C
Secondary Low/Mid Address Space Block Locking register (SLL)
0x0010
Low/Mid Address Space Block Select register (LMS)
0x0014
Reserved
0x0018
Address Register (ADR)
0x001C-0x0038 Reserved
0x003C
User Test 0 register (UT0)
0x0040
User Test 1 register (UT1)
0x0044
Reserved
0x0048
User Multiple Input Signature Register 0 (UMISR0)
0x004C
User Multiple Input Signature Register 1 (UMISR1)
0x0050-0x0058 Reserved
Locations 0x0044, 0x0050, 0x0054 and 0x0058 are Write/Read from user point of view but no functionaly
is associated. Registers are not accessible whenever MCR.DONE or UT0.AID are low: reading returns
indeterminate data while writing has no effect.
In the following some non-volatile registers are described. Please notice that such entities are not
Flip-Flops, but locations of TestFlash sector with a special meaning.
During the Flash initialization phase, the FPEC reads these non-volatile registers and update the
corresponding volatile registers. When the FPEC detects ECC double errors in these special locations, it
behaves in the following way:
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•
•
In case of a failing system locations (configurations, redundancy, EmbAlgo firmware), the
initialization phase is interrupted and a Fatal Error is flagged.
In case of failing user locations (protections, ...), the volatile registers are filled with all ‘1’s and
the Flash initialization ends setting low the PEG bit of MCR.
Table 180 lists bit access type abbreviations used in this section.
Table 180. Abbreviations
Abbreviation
Case
rw
read/write
The software can read and write to these bits.
rc
read/clear
The software can read and clear to these bits.
r
read-only
The software can only read these bits.
w
write-only
The software should only write to these bits.
18.4.5.1
Description
Module Configuration Register (MCR)
The Module Configuration Register enables and monitors all the modify operations of each flash module.
Identical MCRs are provided in the data flash blocks.
Address: Base + 0x0000
0
R
EDC
1
Access: User read/write
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MAS MAS MAS
2
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
SIZE2 SIZE1 SIZE0
0
LAS2 LAS1 LAS0
0
W r1c
Reset
R EER RWE
W r1c
Reset
0
PEAS DONE PEG
r1c
0
0
X
1
PGM PSUS ERS ESUS EHV
0
0
0
0
0
Figure 172. Module Configuration Register (MCR)
Table 181. MCR field descriptions
Field
Description
EDC
EDC: Ecc Data Correction (Read/Clear)
EDC provides information on previous reads. If a ECC Single Error detection and correction
occurred, the EDC bit will be set to 1. This bit must then be cleared, or a reset must occur before this
bit will return to a 0 state. This bit may not be set to 1 by the User.
In the event of a ECC Double Error detection, this bit will not be set.
If EDC is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing
of EDC) were not corrected through ECC.
Since this bit is an error flag, it must be cleared to 0 by writing 1 to the register location. A write of 0
will have no effect.
The function of this bit is SoC dependent and it can be configured to be disabled.
0: Reads are occurring normally.
1: An ECC Single Error occurred and was corrected during a previous read.
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Table 181. MCR field descriptions (continued)
Field
Description
SIZE[2:0]
Array space SIZE 2–0
The value of SIZE field depends on the size of the flash module:
110 64 KB
LAS[2:0]
Low Address Space 2–0
The value of the LAS field corresponds to the configuration of the Low Address Space:
110 4 × 16 KB
MAS[2:0]
Mid Address Space
The value of the MAS field corresponds to the configuration of the Mid Address Space:
EER
EER: ECC event Error (Read/Clear)
EER provides information on previous reads. If an ECC Double Error detection occurred, the EER bit
is set to ‘1’.
This bit must then be cleared, or a reset must occur before this bit will return to a 0 state. This bit may
not be set to ‘1’ by the user.
In the event of an ECC Single Error detection and correction, this bit will not be set.
If EER is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing
of EER) were correct.
Since this bit is an error flag, it must be cleared to ‘0’ by writing 1 to the register location. A write of 0
will have no effect.
0: Reads are occurring normally.
1: An ECC Double Error occurred during a previous read.
RWE
RWE: Read-while-Write event Error (Read/Clear)
RWE provides information on previous reads when a Modify operation is on going. If a RWW Error
occurs, the RWE bit will be set to 1. Read-While-Write Error means that a read access to the Flash
Matrix has occurred while the FPEC was performing a Program or Erase operation or an Array
Integrity Check.
This bit must then be cleared, or a reset must occur before this bit will return to a 0 state. This bit may
not be set to 1 by the User.
If RWE is not set, or remains 0, this indicates that all previous RWW reads (from the last reset, or
clearing of RWE) were correct.
Since this bit is an error flag, it must be cleared to 0 by writing 1 to the register location. A write of 0
will have no effect.
0: Reads are occurring normally.
1: A RWW Error occurred during a previous read.
PEAS
PEAS: Program/Erase Access Space (Read Only)
PEAS is used to indicate which space is valid for program and erase operations: main array space
or test space.
PEAS = 0 indicates that the main address space is active for all Flash module program and erase
operations.
PEAS = 1 indicates that the test address space is active for program and erase.
The value in PEAS is captured and held with the first interlock write done for Modify operations. The
value of PEAS is retained between sampling events (that is, subsequent first interlock writes).
0: Test address space is disabled for program/erase and main address space enabled.
1: Test address space is enabled for program/erase and main address space disabled.
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Table 181. MCR field descriptions (continued)
Field
Description
DONE
DONE: modify operation DONE (Read Only)
DONE indicates if the Flash Module is performing a high voltage operation.
DONE is set to 1 on termination of the Flash Module reset.
DONE is cleared to 0 just after a 0 to 1 transition of EHV, which initiates a high voltage operation, or
after
resuming a suspended operation.
DONE is set to 1 at the end of program and erase high voltage sequences.
DONE is set to 1 (within tPABT or tEABT, equal to P/E Abort Latency) after a 1 to 0 transition of EHV,
which aborts a high voltage Program/Erase operation.
DONE is set to 1 (within tESUS, time equals to Erase Suspend Latency) after a 0 to 1 transition of
ESUS,
which suspends an erase operation.
0: Flash is executing a high voltage operation.
1: Flash is not executing a high voltage operation.
PEG
PEG: Program/Erase Good (Read Only)
The PEG bit indicates the completion status of the last Flash Program, Erase, AIC or MM sequence
for which high voltage operations were initiated. The value of PEG is updated automatically during
the Program, Erase, AIC or MM high voltage operations.
Aborting a Program/Erase/AIC/MM high voltage operation will cause PEG to be cleared to ‘0’,
indicating the sequence failed.
PEG is set to ‘1’ when the Flash Module is reset, unless a Flash initialization error has been detected.
The value of PEG is valid only when PGM=1 and/or ERS=1 and after DONE transitions from ‘0’ to ‘1’
due to an abort or the completion of a Program/Erase/AIC/MM operation. PEG is valid until
PGM/ERS makes a ‘1’ to ‘0’ transition or EHV makes a ‘0’ to ‘1’ transition.
The value in PEG is not valid after a ‘0’ to ‘1’ transition of DONE caused by ESUS being set to logic ‘1’.
If Program or Erase are attempted on blocks that are locked, the response will be PEG=1, indicating
that the operation was successful, and the content of the block were properly protected from the
Program or Erase operation.
If a Program operation tries to program at ‘1’ bits that are at ‘0’, the program operation is correctly
executed on the new bits to be programmed at ‘0’, but PEG is cleared, indicating that the requested
operation has failed.
In AIC or MM PEG is set to ‘1’ when the operation is completed, regardless the occurrence of any
error.
The presence of errors can be detected only comparing checksum value stored in UMIRS0-1.
0: Program or Erase, operation failed or aborted.
1: Program or Erase operation successful.
0: AIC or MM aborted.
1: AIC or MM operation successfully concluded, with or without checksum errors.
PGM
PGM: ProGraM (Read/Write)
PGM is used to set up the Flash module for a Program operation.
A 0 to 1 transition of PGM initiates a Program sequence.
A 1 to 0 transition of PGM ends the Program sequence.
PGM can be set only under User Mode Read (ERS is low and UT0.AIE is low).
PGM can be cleared by the user only when EHV is low and DONE is high.
PGM is cleared on reset.
0: Flash is not executing a Program sequence.
1: Flash is executing a Program sequence.
PSUS
PSUS: Program SUSpend (Read/Write)
Write this bit has no effect, but the written data can be read back.
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Table 181. MCR field descriptions (continued)
Field
ERS
Description
ERS: ERaSe (Read/Write)
ERS is used to set up the Flash module for an erase operation.
A 0 to 1 transition of ERS initiates an erase sequence.
A 1 to 0 transition of ERS ends the erase sequence.
ERS can be set only under User Mode Read (PGM is low and UT0.AIE is low).
ERS can be cleared by the user only when ESUS and EHV are low and DONE is high.
ERS is cleared on reset.
0: Flash is not executing an erase sequence.
1: Flash is executing an erase sequence.
ESUS
ESUS: Erase SUSpend (Read/Write)
ESUS is used to indicate that the Flash module is in Erase Suspend or in the process of entering a
Suspend state. The Flash module is in Erase Suspend when ESUS = 1 and DONE = 1.
ESUS can be set high only when ERS and EHV are high and PGM is low.
A 0 to 1 transition of ESUS starts the sequence which sets DONE and places the Flash in Erase
Suspend. The Flash module enters Suspend within tESUS of this transition.
ESUS can be cleared only when DONE and EHV are high and PGM is low.
A 1 to 0 transition of ESUS with EHV = 1 starts the sequence which clears DONE and returns the
module to Erase.
The Flash module cannot exit Erase Suspend and clear DONE while EHV is low.
ESUS is cleared on reset.
0: Erase sequence is not suspended.
1: Erase sequence is suspended.
EHV
EHV: Enable High Voltage (Read/Write)
The EHV bit enables the Flash Module for a high voltage Program/Erase operation.
EHV is cleared on reset.
EHV must be set after an interlock write to start a Program/Erase sequence. EHV may be set under
one
of the following conditions:
Erase (ERS=1, ESUS=0, UT0.AIE=0)
Program (ERS=0, ESUS=0, PGM=1, UT0.AIE=0)
In normal operation, a 1 to 0 transition of EHV with DONE high and ESUS low terminates the current
Program/Erase high voltage operation.
When an operation is aborted, there is a 1 to 0 transition of EHV with DONE low and the eventual
Suspend bit low. An abort causes the value of PEG to be cleared, indicating a failing
Program/Erase;address locations being operated on by the aborted operation contain indeterminate
data after an abort.
A suspended operation cannot be aborted.
Aborting a high voltage operation will leave the Flash Module addresses in an undeterminate data
state.
This may be recovered by executing an Erase on the affected blocks.
EHV may be written during Suspend. EHV must be high to exit Suspend. EHV may not be written
after ESUS is set and before DONE transitions high. EHV may not be cleared after ESUS is cleared
and before DONE transitions low.
0: Flash is not enabled to perform an high voltage operation.
1: Flash is enabled to perform an high voltage operation.
A number of MCR bits are protected against write when another bit, or set of bits, is in a specific state.
These write locks are covered on a bit by bit basis in the preceding description, but those locks do not
consider the effects of trying to write two or more bits simultaneously.
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The flash module does not allow the user to write bits simultaneously which would put the device into an
illegal state. This is implemented through a priority mechanism among the bits. Table 151 shows the bit
changing priorities.
Table 182. MCR bits set/clear priority levels
Priority level
MCR bits
1
ERS
2
PGM
3
EHV
4
ESUS
If the user attempts to write two or more MCR bits simultaneously, only the bit with the lowest priority
level is written.
18.4.5.2
Low/Mid Address Space Block Locking register (LML)
The Low/Mid Address Space Block Locking register provides a means to protect blocks from being
modified. These bits, along with bits in the SLL register, determine if the block is locked from program or
erase. An “OR” of LML and SLL determine the final lock status. Identical LML registers are provided in
the code flash and the data flash blocks.
The LML register has a related Non Volatile Low/Mid Address Space Block Locking register located in
TestFlash that contains the default reset value for LML: the NVLML register is read during the reset phase
of the Flash Module and loaded into the LML.
Address: Base + 0x0004
0
Access: User read/write
1
2
3
4
5
6
7
8
9
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
LLK
3
LLK
2
LLK
1
LLK
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
R LME
W
Reset
R
11
TSLK
W
Reset
12
13
14
15
0
0
0
0
0
0
0
0
Figure 173. Low/Mid Address Space Block Locking register (LML)
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18.4.5.3
Non-Volatile Low/Mid Address Space Block Locking register (NVLML)
Address: Base + 0x40_3DE8
0
Delivery value:
0xFFFFFFFF
1
2
3
4
5
6
7
8
9
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
LLK
3
LLK
2
LLK
1
LLK
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
R LME
W
Reset
R
11
TSLK
W
Reset
12
13
14
15
0
0
0
0
0
0
0
0
Figure 174. Non-Volatile Low/Mid Address Space Block Locking register (NVLML)
The NVLML register is a 64-bit register, the 32 most significant bits of which (bits 63:32) are “don’t care”
bits that are eventually used to manage ECC codes. Identical NVLML registers are provided in the code
flash and the data flash blocks.
Table 183. LML /NVLML field descriptions
Field
Description
LME1
LME: Low/Mid address space block Enable (Read Only)
This bit is used to enable the Lock registers (TSLK and LLK3-0) to be set or cleared by registers
writes.
This bit is a status bit only. The method to set this bit is to write a password, and if the password
matches, the LME bit will be set to reflect the status of enabled, and is enabled until a reset
operation occurs. For LME the password 0xA1A11111 must be written to the LML register.
0: Low Address Locks are disabled: TSLK and LLK3-0 cannot be written.
1: Low Address Locks are enabled: TSLK and LLK3-0 can be written.
TSLK
TSLK: Test address space block LocK (Read/Write)
This bit is used to lock the block of Test Address Space from Program and Erase (Erase is any
case forbidden for Test block).
A value of 1 in the TSLK register signifies that the Test block is locked for Program and Erase.
A value of 0 in the TSLK register signifies that the Test block is available to receive Program and
Erase pulses.
The TSLK register is not writable once an interlock write is completed until MCR.DONE is set at
the completion of the requested operation. Likewise, the TSLK register is not writable if a high
voltage operation is suspended or if a margin mode is on going.
Upon reset, information from the TestFlash block is loaded into the TSLK register. The TSLK bit
may be written as a register. Reset will cause the bit to go back to its TestFlash block value. The
default value of the TSLK bit (assuming erased fuses) would be locked.
TSLK is not writable unless LME is high.
0: Test Address Space Block is unlocked and can be modified (if also SLL.STSLK=0).
1: Test Address Space Block is locked and cannot be modified.
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Table 183. LML /NVLML field descriptions (continued)
1
Field
Description
LLK[3:0]
LLK3-0: Low address space block LocK 3-0 (Read/Write)
These bits are used to lock the blocks of Low Address Space from Program and Erase.
LLK3-0 are related to sectors B0F3-0, respectively.
A value of 1 in a bit of the LLK register signifies that the corresponding block is locked for Program
and Erase.
A value of 0 in a bit of the LLK register signifies that the corresponding block is available to receive
Program and Erase pulses.
The LLK register is not writable once an interlock write is completed until MCR.DONE is set at the
completion of the requested operation. Likewise, the LLK register is not writable if a high voltage
operation is suspended or if a margin mode is on going.
Upon reset, information from the TestFlash block is loaded into the LLK registers. The LLK bits may
be written as a register. Reset will cause the bits to go back to their TestFlash block value. The
default value of the LLK bits (assuming erased fuses) would be locked.
In the event that blocks are not present (due to configuration or total memory size), the LLK bits
will default to locked, and will not be writable. The reset value will always be 1 (independent of
the TestFlash block), and register writes will have no effect.
In the 72 KB Flash Macrocell the writability of bits LLK3-0 is controlled by bits CS3-0 of FVSCR.
LLK is not writable unless LME is high.
0: Low Address Space Block is unlocked and can be modified (if also SLL.SLK=0).
1: Low Address Space Block is locked and cannot be modified.
This field is present only in LML
18.4.5.4
Secondary Low/Mid Address Space Block Locking register (SLL)
The Secondary Low/Mid Address Space Block Locking register provides an alternative means to protect
blocks from being modified. These bits, along with bits in the LML register, determine if the block is
locked from program or Erase. An “OR” of LML and SLL determine the final lock status. Identical SLL
registers are provided in the code flash and the data flash blocks.
The SLL register has a related Non Volatile Secondary Low/Mid Address Space Block Locking register
located in TestFlash that contains the default reset value for SLL: the NVSLL register is read during the
reset phase of the Flash Module and loaded into the SLL.
Address: Base + 0x000C
0
Access: User read/write
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
STS
LK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
SLK
3
SLK
2
SLK
1
SLK
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
R SLE
W
Reset
R
W
Reset
Figure 175. Secondary Low/mid address space block Locking reg (SLL)
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18.4.5.5
Non-Volatile Secondary Low/Mid Address Space Block Locking register
(NVSLL)
The NVSLL register is a 64-bit register, the 32 most significant bits of which (bits 63:32) are “don’t care”
bits that are eventually used to manage ECC codes. Identical NVSLL registers are provided in the code
flash and the data flash blocks.
Address: Base + 0x40_3DF8
0
Delivery value:
0xFFFFFFFF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
STS
LK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
SLK
3
SLK
2
SLK
1
SLK
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
R SLE
W
Reset
R
W
Reset
Figure 176. Non-Volatile Secondary Low/Mid Address Space Block Locking register (NVSLL)
Table 184. SLL and NVSLL field descriptions
Field
Description
SLE1
Secondary Low/Mid Address Space Block Enable
This bit is used to enable the Lock registers (STSLK and SLK3-0) to be set or cleared by registers
writes.
This bit is a status bit only. The method to set this bit is to write a password, and if the password
matches, the SLE bit will be set to reflect the status of enabled, and is enabled until a reset
operation occurs. For SLE the password 0xC3C33333 must be written to the SLL register.
0: Secondary Low/Mid Address Locks are disabled: STSLK and SLK3-0 cannot be written.
1: Secondary Low/Mid Address Locks are enabled: STSLKand SLK3-0 can be written.
STSLK
Secondary Test/Shadow address space block LocK
This bit is used as an alternate means to lock the block of Test Address Space from Program and
Erase (Erase is any case forbidden for Test block).
A value of 1 in the STSLK register signifies that the Test block is locked for Program and Erase.
A value of 0 in the STSLK register signifies that the Test block is available to receive Program and
Erase pulses.
The STSLK register is not writable once an interlock write is completed until MCR.DONE is set at
the completion of the requested operation. Likewise, the STSLK register is not writable if a high
voltage operation is suspended or if a margin mode is on going.
Upon reset, information from the TestFlash block is loaded into the STSLK register. The STSLK bit
may be written as a register. Reset will cause the bit to go back to its TestFlash block value. The
default value of the STSLK bit (assuming erased fuses) would be locked.
STSLK is not writable unless SLE is high.
0: Test Address Space Block is unlocked and can be modified (if also LML.TSLK=0).
1: Test Address Space Block is locked and cannot be modified.
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Flash Memory
Table 184. SLL and NVSLL field descriptions (continued)
1
Field
Description
SLK[3:0]
Secondary Low Address Space Block Lock 3–0
These bits are used as an alternate means to lock the blocks of Low Address Space from Program
and Erase.
SLK3-0 are related to sectors B0F3-0, respectively.
A value of 1 in a bit of the SLK register signifies that the corresponding block is locked for Program
and Erase.
A value of 0 in a bit of the SLK register signifies that the corresponding block is available to receive
Program and Erase pulses.
The SLK register is not writable once an interlock write is completed until MCR.DONE is set at the
completion of the requested operation. Likewise, the SLK register is not writable if a high voltage
operation is suspended or if a margin mode is on going.
Upon reset, information from the TestFlash block is loaded into the SLK registers. The SLK bits may
be written as a register. Reset will cause the bits to go back to their TestFlash block value. The
default value of the SLK bits (assuming erased fuses) would be locked.
In the event that blocks are not present (due to configuration or total memory size), the SLK bits will
default to locked, and will not be writable. The reset value will always be 1 (independent of the
TestFlash block), and register writes will have no effect.
SLK is not writable unless SLE is high.
0: Low Address Space Block is unlocked and can be modified (if also LML.LLK=0).
1: Low Address Space Block is locked and cannot be modified.
This field is present only in SLL
18.4.5.6
Low/Mid Address Space Block Select register (LMS)
The Low/Mid Address Space Block Select register provides a means to select blocks to be operated on
during erase. Identical LMS registers are provided in the code flash and the data flash blocks.
Address: Base + 0x0010
R
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
LSL
3
LSL
2
LSL
1
LSL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
Figure 177. Low/Mid Address Space Block Select register (LMS)
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Flash Memory
Table 185. LMS field descriptions
Field
Description
LSL[3:0]
Low Address Space Block Select 3–0
LSL3-0: Low address space block SeLect 3-0 (Read/Write)
A value of 1 in the select register signifies that the block is selected for erase.
A value of 0 in the select register signifies that the block is not selected for erase. The reset value
for the select register is 0, or unselected.
LSL3-0 are related to sectors B0F3-0, respectively.
The blocks must be selected (or unselected) before doing an erase interlock write as part of the
Erase sequence. The select register is not writable once an interlock write is completed or if a
high voltage operation is suspended or if a margin mode is on going.
In the event that blocks are not present (due to configuration or total memory size), the
corresponding LSL bits will default to unselected, and will not be writable. The reset value will
always be 0, and register writes will have no effect.
0: Low Address Space Block is unselected for Erase.
1: Low Address Space Block is selected for Erase.
18.4.5.7
Address Register (ADR)
The Address Register provides the first failing address in the event module failures (ECC, RWW or FPEC)
or the first address at which a ECC single error correction occurs.
Address: Base + 0x0018
0
R
1
Access: User read-only
2
3
4
5
6
7
8
9
10
11
12
13
14
15
AD
21
AD
20
AD
19
AD
18
AD
17
AD
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AD
22
0
0
0
0
0
0
0
0
0
0
W
Reset
16
R AD
15
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
AD
14
AD
13
AD
12
AD
11
AD
10
AD
9
AD
8
AD
7
AD
6
AD
5
AD
4
AD
3
AD
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
Figure 178. Address Register (ADR)
Table 186. ADR field descriptions
Field
Description
Reserved (Read Only)
A write to these bits has no effect. A read of these bits always outputs 0.
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Flash Memory
Table 186. ADR field descriptions (continued)
Field
Description
AD[22:2]
Address 20–3
AD22-2: ADdress 22-2 (Read Only)
The Address Register provides the first failing address in the event of ECC error (MCR.EER set) or
the first failing address in the event of RWW error (MCR.RWE set), or the address of a failure that
may have occurred in a FPEC operation (MCR.PEG cleared). The Address Register provides also
the first address at which a ECC single error correction occurs (MCR.EDC set), if the SoC is
configured to show this feature.
The ECC double error detection takes the highest priority, followed by the RWW error, the FPEC
error and the ECC single error correction. When accessed ADR will provide the address related to
the first event occurred with the highest priority. The priorities between these 4 possible events is
summarized in the following table.
In User Mode the Address Register is read only.
Table 187. ADR content: priority list
18.4.5.8
Priority level
Error flag
ADR content
1
MCR[EER] = 1
Address of first ECC Double Error
2
MCR[RWE] = 1
Address of first RWW Error
3
MCR[PEG] = 0
Address of first FPEC Error
4
MCR[EDC] = 1
Address of first ECC Single Error Correction
User Test 0 register (UT0)
The User Test feature gives the user of the flash module the ability to perform test features on the flash.
The User Test 0 register allows controlling the way in which the flash content check is done.
The UT0[MRE], UT0[MRV], UT0[AIS], UT0[EIE], and DSI[6:0] bits are not accessible whenever
MCR[DONE] or UT0[AID] are low. Reads return indeterminate data. Writes have no effect.
Address: Base + 0x003C
0
1
R UTE SBC
E
Access: User read/write
2
3
4
5
6
7
8
0
0
0
0
0
0
0
W
Reset
R
10
11
12
13
14
15
DSI6 DSI5 DSI4 DSI3 DSI2 DSI1 DSI0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
9
X
MRE MRV
0
0
0
EIE
AIS
AIE
0
0
0
0
31
AID
1
Figure 179. User Test 0 register (UT0)
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Flash Memory
Table 188. UT0 field descriptions
Field
Description
UTE
UTE: User Test Enable (Read/Clear)
This status bit gives indication when User Test is enabled. All bits in UT0-1 and UMISR0-1 are
locked when this bit is 0.
This bit is not writeable to a 1, but may be cleared. The reset value is 0.
The method to set this bit is to provide a password, and if the password matches, the UTE bit is set
to reflect the status of enabled, and is enabled until it is cleared by a register write.
For UTE the password 0xF9F99999 must be written to the UT0 register.
1:8
DSI6-0
16:24
Reserved (Read Only)
A write to these bits has no effect. A read of these bits always outputs 0.
DSI6-0: Data Syndrome Input 6-0 (Read/Write)
These bits represents the input of Syndrome bits of ECC logic used in the ECC Logic Check. The
DSI6-0 correspond to the 7 syndrome bits on a single word.
These bits are not accessible whenever MCR.DONE or UT0.AID are low: reading returns
indeterminate data while writing has no effect.
0: The syndrome bit is forced at 0.
1: The syndrome bit is forced at 1.
Reserved (Read Only)
A write to these bits has no effect. A read of these bits always outputs 0.
25
Reserved (Read/Write)
This bit can be written and its value can be read back, but there is no function associated.
This bit is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate
data, and writes have no effect.
MRE
Margin Read Enable
MRE enables margin reads to be done. This bit, combined with MRV, enables regular user mode
reads to be replaced by margin reads.
Margin reads are only active during Array Integrity Checks; Normal user reads are not affected by
MRE.
This bit is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate
data, and writes have no effect.
0 Margin reads are disabled. All reads are User mode reads.
1 Margin reads are enabled.
MRV
Margin Read Value
If MRE is high, MRV selects the margin level that is being checked. Margin can be checked to an
erased level (MRV = 1) or to a programmed level (MRV = 0).
This bit is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate
data, and writes have no effect.
0 Zero’s (programmed) margin reads are requested (if MRE = 1).
1 One’s (erased) margin reads are requested (if MRE = 1).
EIE
ECC data Input Enable
EIE enables the ECC Logic Check operation to be done.
This bit is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate
data, and writes have no effect.
0 ECC Logic Check is disabled.
1 ECC Logic Check is enabled.
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Flash Memory
Table 188. UT0 field descriptions (continued)
Field
Description
AIS
Array Integrity Sequence
AIS determines the address sequence to be used during array integrity checks or Margin Mode.
The default sequence (AIS = 0) is meant to replicate sequences normal user code follows, and
thoroughly checks the read propagation paths. This sequence is proprietary.
The alternative sequence (AIS = 1) is just logically sequential.
It should be noted that the time to run a sequential sequence is significantly shorter than the time
to run the proprietary sequence.
This bit is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate
data, and writes have no effect. In Margin Mode only the linear sequence (AIS = 1) is allowed, while
the proprietary sequence (AIS = 0) is forbidden.
0 Array Integrity sequence is a proprietary sequence.
1 Array Integrity or Margin Mode sequence is sequential.
AIE
Array Integrity Enable
AIE set to 1 starts the Array Integrity Check done on all selected and unlocked blocks.
The pattern is selected by AIS, and the MISR (UMISR0–4) can be checked after the operation is
complete, to determine if a correct signature is obtained.
AIE can be set only if MCR[ERS], MCR[PGM], and MCR[EHV] are all low.
0 Array Integrity Checks are disabled.
1 Array Integrity Checks are enabled.
AID
Array Integrity Done
AID is cleared upon an Array Integrity Check being enabled (to signify the operation is on-going).
Once completed, AID is set to indicate that the Array Integrity Check is complete. At this time, the
MISR (UMISR0–4) can be checked.
0 Array Integrity Check is on-going.
1 Array Integrity Check is done.
18.4.5.9
User Test 1 register (UT1)
The User Test 1 register allows to enable the checks on the ECC logic related to the 32 LSB of the Double
Word.
The User Test 1 register is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return
indeterminate data. Writes have no effect.
Address: Base + 0x0040
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DAI
30
DAI
29
DAI
28
DAI
27
DAI
26
DAI
25
DAI
24
DAI
23
DAI
22
DAI
21
DAI
20
DAI
19
DAI
18
DAI
17
DAI
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DAI
14
DAI
13
DAI
12
DAI
11
DAI
10
DAI
9
DAI
8
DAI
7
DAI
6
DAI
5
DAI
4
DAI
3
DAI
2
DAI
1
DAI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R DAI
W 31
Reset
R DAI
W 15
Reset
Access: User read/write
0
Figure 180. User Test 1 register (UT1)
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Flash Memory
Table 189. UT1 field descriptions
Field
Description
DAI[31:0]
Data Array Input 31–0
These bits represent the input of the even word of ECC logic used in the ECC Logic Check. The
DAI[31:0] bits correspond to the 32 array bits representing Word 0 within the double word.
0 The array bit is forced at 0.
1 The array bit is forced at 1.
18.4.5.10 User Multiple Input Signature Register 0 (UMISR0)
The Multiple Input Signature Register 0 (UMISR0) provides a mean to evaluate the array integrity.
UMISR0 represents the bits 31:0 of the whole 144-bit word (2 double words including ECC).
UMISR0 is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate data.
Writes have no effect.
Address: Base + 0x0048
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MS
030
MS
029
MS
028
MS
027
MS
026
MS
025
MS
024
MS
023
MS
022
MS
021
MS
020
MS
019
MS
018
MS
017
MS
016
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MS
014
MS
013
MS
012
MS
011
MS
010
MS
009
MS
008
MS
007
MS
006
MS
005
MS
004
MS
003
MS
002
MS
001
MS
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R MS
W 031
Reset
R MS
W 015
Reset
Access: User read/write
0
Figure 181. User Multiple Input Signature Register 0 (UMISR0)
Table 190. UMSIR0 field descriptions
Field
Description
MS[031:000]
Multiple input Signature 031–000
These bits represent the MISR value obtained by accumulating the bits 31:0 of all the pages read
from the flash memory.
The MS can be seeded to any value by writing the UMISR0 register.
18.4.5.11 User Multiple Input Signature Register 1 (UMISR1)
The Multiple Input Signature Register 1 (UMISR1) provides a means to evaluate the array integrity.
UMISR1 represents bits 63:32 of the whole 144-bit word (2 double words including ECC).
UMISR1 is not accessible whenever MCR[DONE] or UT0[AID] are low. Reads return indeterminate data.
Writes have no effect.
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Flash Memory
Address: Base + 0x004C
0
R MS
W 063
Reset
0
16
R MS
W 047
Reset
0
Access: User read/write
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MS
062
MS
061
MS
060
MS
059
MS
058
MS
057
MS
056
MS
055
MS
054
MS
053
MS
052
MS
051
MS
050
MS
049
MS
048
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MS
046
MS
045
MS
044
MS
043
MS
042
MS
041
MS
040
MS
039
MS
038
MS
037
MS
036
MS
035
MS
034
MS
033
MS
032
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 182. User Multiple Input Signature Register 1 (UMISR1)
Table 191. UMISR1 field descriptions
Field
MS[063:032]
18.4.6
18.4.6.1
Description
Multiple input Signature 063–032
These bits represent the MISR value obtained accumulating the bits 63:32 of all the pages read
from the flash memory.
The MS can be seeded to any value by writing the UMISR1 register.
Programming considerations
Modify operation
All the Modify Operations of the Flash Module are managed through the Flash User Registers Interface.
All the sectors of the Flash Module belong to the same partition (Bank), therefore when a Modify operation
is active on some sectors no read access is possible on any other sector (Read-While-Modify is not
supported).
During a Flash Modify Operation any attempt to read any Flash location will output invalid data and bit
RWE of MCR will be automatically set. This means that the Flash Module is not fetchable when a Modify
Operation is active: the Modify Operation commands must be executed from another Memory (internal
Ram or external Memory). If during a Modify Operation a reset occurs, the operation is suddenly
terminated and the Macrocell is reset to Read Mode. The data integrity of the Flash section where the
Modify Operation has been terminated or aborted is not guaranteed: the interrupted Flash Modify
Operation must be repeated. In general each Modify Operation is started through a sequence of 3 steps:
1. The first instruction is used to select the desired operation by setting its corresponding selection bit
in MCR (PGM or ERS) or UT0 (MRE or EIE).
2. The second step is the definition of the operands: the Address and the Data for programming or the
Sectors for erase or margin read.
3. The third instruction is used to start the Modify Operation, by setting EHV in MCR or AIE in UT0.
Once selected, but not yet started, one operation can be canceled by resetting the operation
selection bit.
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Flash Memory
A summary of the available Flash modify operations is shown in the Table 192.
Table 192. Flash modify operations
Operation
Select bit
Operands
Start bit
Double word program
MCR.PGM
Address and data by interlock writes
MCR.EHV
Sector erase
MCR.ERS
LMS
MCR.EHV
Array integrity check
None
LMS
UT0.AIE
Margin read
UT0.MRE
UT0.MRV + LMS
UT0.AIE
ECC logic check
UT0.EIE
UT0.DSI, UT1, UT2
UT0.AIE
Once bit MCR.EHV (or UT0.AIE) is set, all the operands can no more be modified until bit MCR.DONE
(or UT0.AID) is high.
In general each modify operation is completed through a sequence of four steps:
1. Wait for operation completion: wait for bit MCR.DONE (or UT0.AID) to go high.
2. Check operation result: check bit MCR.PEG (or compare UMISR0-1 with expected value).
3. Switch off FPEC by resetting MCR.EHV (or UT0.AIE).
4. Deselect current operation by clearing MCR.PGM/ERS (or UT0.MRE/EIE).
In the following all the possible modify operations are described and some examples of the sequences
needed to activate them are presented.
18.4.6.2
Word program
A Flash program sequence operates on any word within the Flash core.
Whenever flash bits are programmed, ECC bits also get programmed, unless the selected address belongs
to a sector in which the ECC has been disabled in order to allow bit manipulation. ECC is handled on a
32-bit boundary.
Programming changes the value stored in an array bit from logic 1 to logic 0 only. Programming cannot
change a stored logic 0 to a logic 1. Addresses in locked/disabled blocks cannot be programmed.
The user may program the values in any words within a single program sequence.
The Program operation consists of the following sequence of events:
1. Change the value in the MCR.PGM bit from 0 to 1.
2. Ensure the block that contains the address to be programmed is unlocked.
a) Write the first address to be programmed with the program data.
b) The Flash module latches address bits (22:2) at this time.
c) The Flash module latches data written as well.
d) This write is referred to as a program data interlock write. An interlock is at 32 bits.
3. Write a logic 1 to the MCR[EHV] bit to start the internal program sequence or skip to step 8 to
terminate. .
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Flash Memory
4.
5.
6.
7.
8.
Wait until the MCR[DONE] bit goes high.
Confirm MCR[PEG]=1.
Write a logic 0 to the MCR[EHV] bit.
If more addresses are to be programmed, return to step 2.
Write a logic 0 to the MCR[PGM] bit to terminate the program operation.
Program may be initiated with the 0 to 1 transition of the MCR[PGM] bit or by clearing the MCR[EHV]
bit at the end of a previous program. The first write after a program is initiated determines the page address
to be programmed. This first write is referred to as an interlock write. The interlock write determines if the
test or normal array space will be programmed by causing MCR[PEAS] to be set/cleared. An interlock
write must be performed before setting MCR[EHV]. The user may terminate a program sequence by
clearing MCR[PGM] prior to setting MCR[EHV]. After the interlock write, additional writes only affect
the data to be programmed in the word. If multiple writes are done to the same location the data for the last
write is used in programming.
While MCR[DONE] is low and MCR[EHV] is high, the user may clear EHV, resulting in a program abort.
A Program abort forces the module to step 7 of the program sequence. An aborted program will result in
MCR[PEG] being set low, indicating a failed operation. MCR[DONE] must be checked to know when the
aborting command has completed. The data space being operated on before the abort will contain
indeterminate data. This may be recovered by repeating the same program instruction or executing an erase
of the affected blocks.
Example 1. Word program of data 0x55AA55AA at address 0x00AAA8
MCR
= 0x00000010;
(0x00AAA8)
= 0x55AA55AA;
MCR
= 0x00000011;
do
{ tmp
= MCR;
} while ( !(tmp & 0x00000400) );
status
= MCR & 0x00000200;
MCR
= 0x00000010;
MCR
= 0x00000000;
18.4.6.3
/*
/*
/*
/*
/*
Set PGM in MCR: Select Operation */
Latch Address and 32 LSB data */
Set EHV in MCR: Operation Start */
Loop to wait for DONE=1 */
Read MCR */
/* Check PEG flag */
/* Reset EHV in MCR: Operation End */
/* Reset PGM in MCR: Deselect Operation */
Sector erase
Erase changes the value stored in all bits of the selected block(s) to logic 1. An erase sequence operates on
any combination of blocks (sectors). The test block cannot be erased.
The erase sequence is fully automated within the Flash. The user only needs to select the blocks to be
erased and initiate the erase sequence. Locked/disabled blocks cannot be erased. If multiple blocks are
selected for erase during an erase sequence, no specific operation order must be assumed.
The erase operation consists of the following sequence of events:
1. Change the value in the MCR.ERS bit from 0 to 1.
2. Select the block(s) to be erased by writing ‘1’s to the appropriate register(s).
Note that Lock and Select are independent. If a block is selected and locked, no erase will occur.
3. Write to any address in Flash. This is referred to as an erase interlock write.
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4. Write a logic 1 to the MCR.EHV bit to start the internal erase sequence or skip to step 9 to
terminate.
5. Wait until the MCR.DONE bit goes high.
6. Confirm MCR.PEG=1.
7. Write a logic 0 to the MCR.EHV bit.
8. If more blocks are to be erased, return to step 2.
9. Write a logic 0 to the MCR.ERS bit to terminate the erase operation.
After setting MCR.ERS, one write, referred to as an interlock write, must be performed before MCR.EHV
can be set to 1. Data words written during erase sequence interlock writes are ignored. The User may
terminate the erase sequence by clearing ERS before setting EHV.
An erase operation may be aborted by clearing MCR.EHV assuming MCR.DONE is low, MCR.EHV is
high and MCR.ESUS is low. An erase abort forces the Module to step 8 of the erase sequence.
An aborted erase will result in MCR.PEG being set low, indicating a failed operation. MCR.DONE must
be checked to know when the aborting command has completed. The block(s) being operated on before
the abort contain indeterminate data. This may be recovered by executing an erase on the affected blocks.
The User may not abort an erase sequence while in erase suspend.
Example 2. Erase of sectors B0F1 and B0F2
MCR
= 0x00000004;
LMS
= 0x00000006;
(0x000000)
= 0xFFFFFFFF;
MCR
= 0x00000005;
do
{ tmp
= MCR;
} while ( !(tmp & 0x00000400) );
status
= MCR & 0x00000200;
MCR
= 0x00000004;
MCR
= 0x00000000;
18.4.6.3.1
/*
/*
/*
/*
/*
/*
Set ERS in MCR: Select Operation */
Set LSL2-1 in LMS: Select Sectors to erase */
Latch a Flash Address with any data */
Set EHV in MCR: Operation Start */
Loop to wait for DONE=1 */
Read MCR */
/* Check PEG flag */
/* Reset EHV in MCR: Operation End */
/* Reset ERS in MCR: Deselect Operation */
Erase suspend/resume
The erase sequence may be suspended to allow read access to the Flash Core. It is not possible to program
or to erase during an erase suspend. During erase suspend, all reads to blocks targeted for erase return
indeterminate data.An erase supend can be initiated by changing the value of the MCR.ESUS bit from 0
to 1. MCR.ESUS can be set to 1 at any time when MCR.ERS and MCR.EHV are high and MCR.PGM is
low. A 0 to 1 transition of MCR.ESUS causes the Module to start the sequence which places it in erase
suspend.
The User must wait until MCR.DONE=1 before the Module is suspended and further actions are
attempted. MCR.DONE will go high no more than tESUS after MCR.ESUS is set to 1. Once suspended,
the array may be read. Flash Core reads while MCR.ESUS=1 from the block(s) being erased return
indeterminate data.
Example 3. Sector erase suspend
MCR
do
= 0x00000007;
/* Set ESUS in MCR: Erase Suspend */
/* Loop to wait for DONE=1 */
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{ tmp
= MCR;
} while ( !(tmp & 0x00000400) );
/* Read MCR */
Notice that there is no need to clear MCR.EHV and MCR.ERS in order to perform reads during erase
suspend. The erase sequence is resumed by writing a logic 0 to MCR.ESUS. MCR.EHV must be set to ‘1’
before MCR.ESUS can be cleared to resume the operation. The module continues the erase sequence from
one of a set of predefined points. This may extend the time required for the erase operation.
Example 4. Sector erase resume
MCR
18.4.6.4
= 0x00000005;
/* Reset ESUS in MCR: Erase Resume */
User Test Mode
User Test Mode is a procedure to check the integrity of the Flash Module.
Three kinds of test can be performed:
• Array Integrity Self Check
• Margin Read
• ECC Logic Check
The User Test Mode is equivalent to a Modify operation: read accesses attempted by the user during User
Test Mode generates a Read-While-Write Error (RWE of MCR set).
It is not allowed to perform User Test operations on the Test and Shadow blocks.
18.4.6.4.1
Array integrity self check
Array Integrity is checked using a pre-defined address sequence (proprietary), and this operation is
executed on selected and unlocked blocks. Once the operation is completed, the results of the reads can be
checked by reading the MISR value (stored in UMISR0-1), to determine if an incorrect read, or ECC
detection was noted.
The internal MISR calculator is a 32 bit register. The 32 bit data, the 7 ECC data and the single and double
ECC errors of the Word are therefore captured by the MISR through 2 different read accesses at the same
location. The whole check is done through 2 complete scans of the memory address space:
1. The 1st pass will scan only bits 31-0 of each word.
2. The 2nd pass will scan only the ECC bits (7) and the single and double ECC errors (1 + 1) of each
word.
The 32 data bit and the 7 ECC data are sampled before the eventual ECC correction, while the single and
double error flags are sampled after the ECC evaluation. Only data from existing and unlocked locations
are captured by the MISR. The MISR can be seeded to any value by writing the UMISR0-1 registers.
Once command is started, Array Integrity check is run by FPEC using system clock and the number of
wait states identified by address and data wait states.
The Array Integrity Self Check consists of the following sequence of events:
1. Set UTE in UT0 by writing the related password in UT0.
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2. Select the block(s) to be checked by writing 1’s to the appropriate register(s) in LMS. Note that
Lock and Select are independent. If a block is selected and locked, no Array Integrity Check will
occur.
3. Set eventually UT0.AIS bit for a sequential addressing only.
4. Clear (or insert seed) UMISR0-1
5. Write a logic 1 to the UT0.AIE bit to start the Array Integrity Check.
6. Wait until the UT0.AID bit goes high.
7. Compare UMISR0-1 content with the expected result.
8. Write a logic 0 to the UT0.AIE bit.
9. If more blocks are to be checked, return to step 2.
10. clear UT0 writing UT0.UTE to ‘0’
It is recomended to leave UT0.AIS at 0 and use the proprietary address sequence that checks the read path
more fully, although this sequence takes more time. While UT0.AID is low and UT0.AIE is high, the User
may clear AIE, resulting in a Array Integrity Check abort.
UT0.AID must be checked to know when the aborting command has completed.
Example 5. Array integrity check of sectors B0F1 and B0F2
UT0
= 0xF9F99999;
LMS
= 0x00000006;
UT0
= 0x80000002;
do
{ tmp
= UT0;
} while ( !(tmp & 0x00000001) );
data0
= UMISR0;
data1
= UMISR1;
UT0
= 0x00000000;
18.4.6.4.2
/*
/*
/*
/*
/*
Set UTE in UT0: Enable User Test */
Set LSL2-1 in LMS: Select Sectors */
Set AIE in UT0: Operation Start */
Loop to wait for AID=1 */
Read UT0 */
/* Read UMISR0 content*/
/* Read UMISR1 content*/
/* Reset UTE and AIE in UT0: Operation End */
Margin read
Margin read procedure (either Margin 0 or Margin 1), can be run on unlocked blocks in order to unbalance
the Sense Amplifiers, respect to standard read conditions, so that all the read accesses reduce the margin
vs ‘0’ (UT0.MRV = ‘0’) or vs ‘1’ (UT0.MRV = ‘1’). Locked sectors are ignored by MISR calculation and
ECC flagging.
The results of the margin reads can be checked comparing checksum value in UMISR0-1. Since Margin
reads are done at voltages that differ than the normal read voltage, lifetime expectancy of the Flash
macrocell is impacted by the execution of Margin reads.
Doing Margin reads repetitively results in degradation of the Flash Array, and shorten expected lifetime
experienced at normal read levels. It is recommended the Margin reads be done on a limited basis (less
than 10 times before the next chip erase).
The Margin Read Setup operation consists of the following sequence of events:
1. Set UTE in UT0 by writing the related password in UT0.
2. Select the block(s) to be checked by writing 1’s to the appropriate register(s) in LMS. Note that
Lock and Select are independent. If a block is selected and locked, no Margin Readwill occur.
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Flash Memory
3.
4.
5.
6.
7.
8.
9.
Set eventually UT0.AIS bit for a sequential addressing only.
Change the value in the UT0.MRE bit from 0 to 1.
Select the Margin level: UT0.MRV=0 for 0’s margin, UT0.MRV=1 for 1’s margin.
Write a logic 1 to the UT0.AIE bit to start the Margin Read Setup or skip to step 6 to terminate.
Wait until the UT0.AID bit goes high.
Compare UMISR0-1 content with the expected result.
Write a logic 0 to the UT0.AIE UT0.MRE and UT0.MRV bits.
It is recomended to leave UT0.AIS at 1 and use the linear address sequence and takes less time. While
UT0.AID is low and UT0.AIE is high, the User may clear AIE, resulting in a Margin Mode abort.
UT0.AID must be checked to know when the aborting command has completed.
Example 6. Margin read setup versus ‘1’s
UT0
= 0xF9F99999;
UT0
= 0x80000020;
UT0
= 0x80000030;
UT0
= 0x80000032;
do
{ tmp = UT0;
} while ( !(tmp & 0x00000001) );
data0
= UMISR0;
data1
= UMISR1;
UT0
= 0x00000000;
Operation */
18.4.6.4.3
/*
/*
/*
/*
/*
/*
Set UTE in UT0: Enable User Test */
Set MRE in UT0: Select Operation */
Set MRV in UT0: Select Margin versus 1’s */
Set AIE in UT0: Operation Start */
Loop to wait for AID=1 */
Read UT0 */
/* Read UMISR0 content*/
/* Read UMISR1 content*/
/* Reset UTE, AIE, MRE, MRV in UT0: Deselect
ECC logic check
ECC logic can be checked by forcing the input of ECC logic: the 32 bits of data and the 7 bits of ECC
syndrome can be individually forced and they will drive simultaneously at the same value the ECC logic
of the word.
The results of the ECC Logic Check can be verified by reading the MISR value. The ECC Logic Check
operation consists of the following sequence of events:
1. Set UTE in UT0 by writing the related password in UT0.
2. Write in UT1.DAI31-0 Word Input value.
3. Write in UT0.DSI6-0 the Syndrome Input value.
4. Select the ECC Logic Check: write a logic 1 to the UT0.EIE bit.
5. Write a logic 1 to the UT0.AIE bit to start the ECC Logic Check.
6. Wait until the UT0.AID bit goes high.
7. Compare UMISR0-1 content with the expected result.
8. Write a logic 0 to the UT0.AIE bit.
Notice that when UT0.AID is low UMISR0-1, UT1 and bits MRE, MRV, EIE, AIS and DSI6-0 of UT0 are
not accessible: reading returns undeterminate data and write has no effect.
Example 7. ECC logic check
UT0
= 0xF9F99999;
/* Set UTE in UT0: Enable User Test */
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Flash Memory
UT1
= 0x55555555;
UT0
= 0x80380000;
UT0
= 0x80380008;
UT0
= 0x8038000A;
do
{ tmp
= UT0;
} while ( !(tmp & 0x00000001) );
data0
= UMISR0;
UT0
= 0x00000000;
18.4.7
/*
/*
/*
/*
/*
/*
Set DAI31-0 in UT1: Word Input Data */
Set DSI6-0 in UT0: Syndrome Input Data */
Set EIE in UT0: Select ECC Logic Check */
Set AIE in UT0: Operation Start */
Loop to wait for AID=1 */
Read UT0 */
/* Read UMISR0 content (expected 0x55555555) */
/* Reset UTE, AIE and EIE in UT0: Operation End */
Error correction code
The Flash Macrocell provides a method to improve the reliability of the data stored in Flash: the usage of
an Error Correction Code. ECC circuitry provides correction of single bit faults and is used to achieve
automotive reliability targets. Some units will experience single bit corrections throughout the life of the
product with no impact to product reliability. Word size is fixed at 32 bits.
At each Word of 32 bits there are associated 7 ECC bits that are programmed in such a way to guarantee
a Single Error Correction and a Double Error Detection (SEC-DED).
18.4.7.1
ECC algorithms
The Flash module supports one ECC Algorithm: “All ‘1’s No Error”. A modified Hamming code is used
that ensures the all erased state (that is, 0xFFFF.....FFFF) data is a valid state, and will not cause an ECC
error. This allows the user to perform a blank check after a sector erase operation.
18.4.7.2
ECC Algorithms Features
The Flash Macrocell ECC Algorithm supports the following features:
• All ‘0’s Error
— The All ‘0’s Error Algorithm detects as Double ECC Error any Word in which all the 39 bits
are “0’s.
• All ‘1’s No Error
— The All ‘1’s No Error Algorithm detects as valid any Word read on a just erased sector (all the
39 bits are “1’s).
This option allows to perform a Blank Check after a Sector Erase operation.
• Bit Manipulation
— 8 bits clears (by byte) are allowed on any erased word mantaining valid the syndrome of the
word. 8 bits clears can be done on any byte of the word without a specific order. This featured
is intended as a counter for EE-Emulation.
Example 1: data patterns with the same ECC syndrome (equal to 0x7F).
0xFFFFFFFF -> 7F
0xFFFFFF00 -> 7F
0xFFFF00FF -> 7F
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Flash Memory
0xFF00FFFF
0x00FFFFFF
0xFFFF0000
0x0000FFFF
0xFF000000
0x000000FF
0x00000000
•
7F
7F
7F
7F
7F
7F
7F
Enhanced flagging
In case flagging method is required for more then 4 writes, the following sequence aloows up to 7
pattern with the same ECC syndrome.
0xFFFFFFFF
0xFFFFFFB1
0xFFFFFF00
0xFFACFF00
0xFF00FF00
0xCA00FF00
0x0000FF00
0x00000000
•
->
->
->
->
->
->
->
->
->
->
->
->
->
->
->
7F
7F
7F
7F
7F
7F
7F
7F
3 Bits Error Detection
— 40.21% of the possible 3 bits errors are detects as Double ECC Error.
— 59.79% of the possible 3 bits errors are instead detects as Single ECC Error and miscorrected..
18.4.8
Protection strategy
Two kinds of protection are available: Modify Protection to avoid unwanted program/erase in Flash
sectors. The Censored Mode to avoid piracy must be managed by the associated Code Flash Macrocell
embedded in the same device.
18.4.8.1
Modify protection
The Flash Modify Protection information is stored in non-volatile Flash cells located in the TestFlash. This
information is read once during the Flash initialization phase following the exiting from Reset and they
are stored in volatile registers that act as actuators.
The reset state of all the Volatile Modify Protection Registers is the protected state.
All the non-volatile Modify Protection registers can be programmed through a normal Word Program
operation at the related locations in TestFlash.
The non-volatile Modify Protection registers cannot be erased.
• The non-volatile Modify Protection Registers are physically located in TestFlash their bits can be
programmed to ‘0’ only once and they can no more be restored to ‘1’.
• The Volatile Modify Protection Registers are Read/Write registers which bits can be written at ‘0’
or ‘1’ by the user application.
A software mechanism is provided to independently lock/unlock each Low, Mid Address Space Block
against program and erase.
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Software locking is done through the LML (Low/Mid Address Space Block Lock Register). An alternate
means to enable software locking for blocks of Low Address Space only is through the SLL (Secondary
Low/Mid Address Space Block Lock Register).
All these registers have a Non Volatile image stored in TestFlash (NVLML, NVSLL), so that the locking
information is kept on reset.
On delivery the TestFlash Non Volatile image is at all 1’s that means all sectors locked. By programming
the Non Volatile locations in TestFlash the selected sectors can be unlocked. Being the TestFlash One Time
Programmable (i.e. not erasable), once unlocked the sectors cannot be locked again.
Of course, on the contrary, all the volatile registers can be written at 0 or 1 at any time, therefore the User
Application can lock and unlock sectors when desired.
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Chapter 19
Enhanced Direct Memory Access (eDMA)
19.1
Introduction
The enhanced direct memory access (eDMA) controller is a second-generation module capable of
performing complex data transfers with minimal intervention from a host processor. The hardware
microarchitecture includes a DMA engine that performs source- and destination-address calculations, and
the actual data-movement operations, along with local memory containing transfer control descriptors
(TCD) for each channel.
The following figure is a block diagram of the eDMA module.
eDMA
Write Address
Write Data
0
Transfer Control
Descriptor (TCD)
n-1
64
eDMA Engine
Program Model/
Channel Arbitration
Read Data
Internal Peripheral Bus
To/From Crossbar Switch
j
j+1
Read Data
Address Path
Control
Data Path
Write Data
Address
eDMA Peripheral
Request
eDMA Done
Figure 183. eDMA block diagram
19.1.1
Overview
The eDMA is a highly-programmable data-transfer engine optimized to minimize the required
intervention from the host processor. It is intended for use in applications where the data size to be
transferred is statically known and not defined within the data packet itself.
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Throughout this document, n is used to reference the channel number. Additionally, data sizes are defined
as byte (8-bit), halfword (16-bit), word (32-bit) and doubleword (64-bit).
19.1.2
Features
The DMA module supports the following features:
• All data movement via dual-address transfers: read from source, write to destination
— Programmable source, destination addresses, transfer size, plus support for enhanced
addressing modes
• 16-channel implementation that performs complex data transfers with minimal intervention from
a host processor
— Internal data buffer, used as temporary storage to support 16-byte burst transfers
— Connections to the crossbar switch for bus mastering the data movement
• Transfer control descriptor organized to support two-deep, nested transfer operations
— An inner data transfer loop defined by a “minor” byte transfer count
— An outer data transfer loop defined by a “major” iteration count
• Channel service request via one of three methods:
— Explicit software initiation
— Initiation via a channel-to-channel linking mechanism for continuous transfers
– Independent channel linking at end of minor loop and/or major loop
— Peripheral-paced hardware requests (one per channel)
— For all three methods, one service request per execution of the minor loop is required
• Support for fixed-priority and round-robin channel arbitration
• Channel completion reported via optional interrupt requests (chip dependent)
— One interrupt per channel, optionally asserted at completion of major iteration count
— Error terminations are optionally enabled per channel, and logically summed together to form
a small number of error interrupt outputs
• Support for scatter/gather DMA processing
The structure of the transfer control descriptor is fundamental to the operation of the DMA module. It is
defined below in a ‘C’ pseudo-code specification, where int refers to a 32-bit variable (unless noted
otherwise) and short is a 16-bit variable.
NOTE
To compile these structures, change any periods '.' in the variable name to
underscores '_'.
typedef union {
struct {
unsigned short citer.linkch:6;
unsigned short citer:9;
} minor_link_enabled;
struct {
unsigned short citer:15;
/*
/*
/*
/*
/*
/*
citer.e_link = 1 */
link channel number, */
current (“major”) iteration count */
channel link at end of the minor loop */
citer.e_link = 0 */
current (“major”) iteration count */
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} minor_link_disabled;
} t_minor_link_citer;
/* no linking at end of the minor loop */
typedef union {
struct {
unsigned short biter.linkch:6;
unsigned short biter:9;
} init_minor_link_enabled;
struct {
unsigned short biter:15;
} init_minor_link_disabled;
} t_minor_link_biter;
/*
/*
/*
/*
/*
/*
/*
typedef struct {
unsigned intsaddr;
/*
unsigned intsmod:5;
/*
unsigned intssize:3;
/*
unsigned intdmod:5;
/*
unsigned intdsize:3;
/*
short
soff;
/*
unsigned intnbytes;
/*
int
slast;
/*
unsigned intdaddr;
/*
unsigned shortciter.e_link:1;
/*
t_minor_link_citerminor_link_citer;/*
short
doff;
/*
int
dlast_sga;
/*
} tcd
unsigned shortbiter.e_link:1;
/*
t_minor_link_biterminor_link_biter;/*
unsigned intbwc:2;
/*
unsigned intmajor.linkch:6;
/*
unsigned intdone:1;
/*
unsigned intactive:1;
/*
unsigned intmajor.e_link:1;
/*
unsigned inte_sg:1;
/*
unsigned intd_req:1;
/*
unsigned intint_half:1;
/*
unsigned intint_maj:1;
/*
unsigned intstart:1;
/*
/*
biter.e_link = 1 */
link channel number, */
beginning (“major”) iteration count */
channel link at end of the minor loop */
biter.e_link = 0 */
beginning (“major”) iteration count */
no linking at end of the minor loop */
source address */
source address modulo */
source transfer size */
destination address modulo */
destination transfer size */
signed source address offset */
inner (“minor”) byte count */
last source address adjustment */
destination address */
enable channel linking on minor loop */
conditional current iteration count */
signed destination address offset */
last destination address adjustment, or
scatter/gather address (if e_sg = 1) */
beginning channel link enable */
beginning (“major”) iteration count */
bandwidth control */
link channel number */
channel done */
channel executing */
enable channel linking on major loop*/
enable scatter/gather descriptor */
disable ipd_req when done */
interrupt on citer = (biter >> 1) */
interrupt on major loop completion */
explicit channel start */
transfer_control_descriptor */
The basic operation of a channel is defined as:
1. The channel is initialized by software loading the transfer control descriptor into the eDMA’s
programming model, memory-mapped through the slave bus space, and implemented as local memory.
2. The channel requests service; either explicitly by software, a peripheral request or a linkage from
another channel.
NOTE
The major loop executes one iteration per service request.
3. The contents of the transfer control descriptor for the activated channel is read from the local memory
and loaded into the eDMA engine’s internal register file.
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4. The eDMA engine executes the data transfer defined by the transfer control descriptor, reading from the
source and writing to the destination. The number of iterations in the minor loop is automatically
calculated by the eDMA engine. The number of iterations within the minor loop is a function of the number
of bytes to transfer (nbytes), the source size (ssize) and the destination size (dsize). The completion of the
minor loop is equal to one iteration of the major loop.
5. At the conclusion of the minor loop’s execution, certain fields of the transfer control descriptor are
written back to the local TCD memory.
The process (steps 2-5) is repeated until the outer major loop’s iteration count is exhausted. At that time,
additional processing steps are completed, e.g., the optional assertion of an interrupt request signaling the
transfer’s completion, final adjustments to the source and destination addresses, etc. A more detailed
description of the channel processing is listed in the pseudo-code below. This simplified example is
intended to represent basic data transfers. Detailed processing associated with the error handling is
omitted.
/* the given eDMA channel is requesting service by the software assertion of the
tcd[channel].start bit, the assertion of an enabled ipd_req from a device, or
the implicit assertion of a channel-to-channel link */
/* begin by reading the transfer control descriptor from the local RAM
into the local dma_engine registers */
dma_engine
= read_from_local_memory [channel];
dma_engine.active = 1;
/* set active flag */
dma_engine.done
= 0;
/* clear done flag */
/* check the transfer control descriptor for consistency */
if (dma_engine.config_error == 0) {
/ * begin execution of the inner “minor” loop transfers */
{
/* convert the source transfer
switch (dma_engine.ssize) {
case 0:
src_xfr_size = 1;
break;
case 1:
src_xfr_size = 2;
break;
case 2:
src_xfr_size = 4;
break;
case 3:
/*
src_xfr_size = 16;
break;
case 4:
src_xfr_size = 32;
break;
}
size into a byte count */
/* 8-bit transfer */
/* 16-bit transfer */
/* 32-bit transfer */
16-byte burst transfer */
/* 32-byte burst transfer */
/* convert the destination transfer size into a byte count */
switch (dma_engine.dsize) {
case 0:
/* 8-bit transfer */
dest_xfr_size = 1;
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break;
case 1:
dest_xfr_size
break;
case 2:
dest_xfr_size
break;
case 3:
dest_xfr_size
break;
case 4:
dest_xfr_size
break;
case 5:
dest_xfr_size
break;
}
/* 16-bit transfer */
= 2;
/* 32-bit transfer */
= 4;
/* 64-bit transfer */
= 8;
/* 16-byte burst transfer */
= 16;
/* 32-byte burst transfer */
= 32;
/*
/*
/*
if
determine the larger of the two transfer sizes, this value reflects */
the number of bytes transferred per read->write sequence. */
number of iterations of the minor loop = nbytes / xfer_size */
(dma_engine.ssize < dma_engine.dsize)
xfr_size = dest_xfer_size;
else
xfr_size = src_xfer_size;
/* process the source address, READ data into the buffer*/
/* read “xfr_size” bytes from the source */
/* if the ssize < dsize, do multiple reads to equal the dsize */
/* if the ssize => dsize, do a single read of source data */
number_of_source_reads = xfer_size / src_xfer_size;
for (number_of_source_reads) {
dma_engine.data = read_from_amba-ahb (dma_engine.saddr, src_xfr_size);
/* generate the next-state source address */
/* sum the current saddr with the signed source offset */
ns_addr = dma_engine.saddr + (int) dma_engine.soff; }
/* if enabled, apply the power-of-2 modulo to the next-state addr */
if (dma_engine.smod != 0)
address_select = (1 << dma_engine.smod) - 1; }
else
address_select = 0xffff_ffff;
dma_engine.saddr = ns_addr
&
address_select
| dma_engine.saddr & ~address_select; }
}
/* process the destination address, WRITE data from buffer */
/* write “xfr_size” bytes to the destination */
/* if the dsize < ssize, do multiple writes to equal the ssize */
/* if the dsize => ssize, do a single write of dest data */
number_of_dest_writes = xfer_size / dest_xfer_size;
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19-391
for (number_of_dest_writes) {
write_to_amba-ahb (dma_engine.daddr, dest_xfr_size) = dma_engine.data;
/* generate the next-state destination address */
/* sum the current daddr with the signed destination offset */
ns_addr = dma_engine.daddr + (int) dma_engine.doff;
/* if enabled, apply the power-of-2 modulo to the next-state dest addr */
if (dma_engine.dmod != 0)
address_select = (1 << dma_engine.dmod) - 1;
else
address_select = 0xffff_ffff;
dma_engine.daddr = ns_addr
&
address_select
| dma_engine.daddr & ~address_select;
}
if (cancel_transfer)
break;
/*
/*
/*
/*
/*
if
check for a higher priority channel to service if: */
1) preemption is enabled */
2) in fixed arbitration mode */
3) a higher priority channel is requesting service */
4) not already servicing a preempting channel */
((DCHPRIn.ecp = 1) & fixed_arbitration_mode
higher_pri_request & ~current_channel_is_preempt)
service_preempt_channel;
/* the bandwidth control field determines when the next read/write occurs */
if (dma_engine.bwc > 1)
stall_dma_engine (1 << dma_engine.bwc);
/* decrement the minor loop byte count */
dma_engine.nbytes = dma_engine.nbytes - xfr_size;
}while (dma_engine.nbytes > 0) /* end of minor inner loop */
dma_engine.citer--;
/* decrement major loop iteration count */
/* if the major loop is not yet exhausted, update certain TCD values in the RAM */
if (dma_engine.citer != 0) {
write_to_local_memory [channel].saddr = dma_engine.saddr;
write_to_local_memory [channel].daddr = dma_engine.daddr;
write_to_local_memory [channel].citer = dma_engine.citer;
/* if minor loop linking is enabled, make the channel link */
if (dma_engine.citer.e_link)
TCD[citer.linkch].start = 1;
/* specified channel service req */
/* check for interrupt assertion if half of the major iterations are done */
if (dma_engine.int_half && (dma_engine.citer == (dma_engine.biter >> 1)))
generate_interrupt (channel);
dma_engine.active = 0;
/* clear the channel busy flag */
}
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Freescale Semiconductor
else { /* major loop is complete, dma_engine.citer == 0 */
/* since the major loop is complete, perform the final address adjustments */
/* sum the current {src,dst} addresses with “last” adjustment */
write_to_local_memory [channel].saddr = dma_engine.saddr + dma_engine.slast;
write_to_local_memory [channel].daddr = dma_engine.daddr + dma_engine.dlast;
/* restore the major iteration count to the beginning value */
write_to_local_memory [channel].citer = dma_engine.biter;
/* check for interrupt assertion at completion of the major iteration */
if (dma_engine.int_maj)
generate_interrupt (channel);
/* check if the ipd_req is to be disabled at completion of the major iteration */
if (dma_engine.d_req)
DMAERQ [channel] = 0;
/* check for a scatter/gather transfer control descriptor */
if (dma_engine.e_sg) {
/* load new transfer control descriptor from the address defined by dlast_sga */
write_to_local_memory [channel] =
read_from_amba-ahb(dma_engine.dlast_sga,32);
}
if (dma_engine.major.e_link)
TCD[major.linkch].start = 1;
/* specified channel service req */
dma_engine.active = 0;
dma_engine.done = 1;
/* clear the channel busy flag */
/* set the channel done flag */
}
else { /* configuration error detected, abort the channel */
dma_engine.error_status = error_type; /* record the error */
dma_engine.active = 0;
/* clear the channel busy flag */
/* check for interrupt assertion on error */
if (dma_engine.int_err)
generate_interrupt (channel);
}
For more details, consult Section 19.2.1, Register descriptions and Section 19.3, Functional description.
19.2
Memory map/register definition
The eDMA’s programming model is partitioned into two sections, both mapped into the slave bus space:
the first region defines a number of registers providing control functions, while the second region
corresponds to the local transfer control descriptor memory.
Reading an unimplemented register bit or memory location will return the value of zero. Write the value
of zero to unimplemented register bits. Any access to a reserved memory location will result in a bus error.
Reserved memory locations are indicated in the memory map. For 16- and 32-channel implementations,
reserved memory also includes the high order "H" registers containing channels 63-32 data (i.e.,
DMAERQH, DMAEEIH, DMAINTH, DMAERRH).
Many of the control registers have a bit width that matches the number of channels implemented in the
module, i.e., 16-, 32- or 64-bits in size. Registers associated with a 64-channel design are implemented as
two 32-bit registers, and include an “H” and “L” suffixes, signaling the “high” and “low” portions of the
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control function. The descriptions in this section define the 64-channel implementation. For 16- or
32-channel designs, the unused bits are not implemented: reads return zeroes, and writes are ignored.
The eDMA module does not include any logic which provides access control. Rather, this function is
supported using the standard access control logic provided by the PBRIDGE controller.
Table 193 is a 32-bit view of the eDMA’s memory map.
Table 193. eDMA 32-bit memory map
eDMA Offset
Register
0x0000
eDMA Control Register (DMACR)
0x0004
eDMA Error Status (DMAES)
0x0008
Reserved
0x000c
eDMA Enable Request Low (DMAERQL, Channels 31-00)
0x0010
Reserved
0x0014
eDMA Enable Error Interrupt Low (DMAEEIL, Channels 31-00)
0x0018
eDMA Set Enable
Request
(DMASERQ)
eDMA Clear Enable
Request
(DMACERQ)
eDMA Set Enable
Error Interrupt
(DMASEEI)
eDMA Clear Enable
Error Interrupt
(DMACEEI)
0x001c
eDMA Clear Interrupt
Request
(DMACINT)
eDMA Clear
Error
(DMACERR)
eDMA Set Start Bit
(DMASSRT)
eDMA Clear Done
Status Bit
(DMACDNE)
0x0020
Reserved
0x0024
eDMA Interrupt Request Low (DMAINTL, Channels 31-00)
0x0028
Reserved
0x002c
eDMA Error Low (DMAERRL, Channels 31-00)
0x0030
Reserved
0x0034
eDMA Hardware Request Status Low (DMAHRSL, Channels 31-00)
0x0038 – 0x00FF
Reserved
0x0100
eDMA Channel 0
Priority (DCHPRI0)
eDMA Channel 1
Priority (DCHPRI1)
eDMA Channel 2
Priority (DCHPRI2)
eDMA Channel 3
Priority (DCHPRI3)
0x0104
eDMA Channel 4
Priority (DCHPRI4)
eDMA Channel 5
Priority (DCHPRI5)
eDMA Channel 6
Priority (DCHPRI6)
eDMA Channel 7
Priority (DCHPRI7)
0x0108
eDMA Channel 8
Priority (DCHPRI8)
eDMA Channel 9
Priority (DCHPRI9)
eDMA Channel 10
Priority (DCHPRI10)
eDMA Channel 11
Priority (DCHPRI11)
0x010c
eDMA Channel 12
Priority (DCHPRI12)
eDMA Channel 13
Priority (DCHPRI13)
eDMA Channel 14
Priority (DCHPRI14)
eDMA Channel 15
Priority (DCHPRI15)
0x0110-0x0fff
Reserved
0x1000-0x11ff
TCD00-TCD15
0x1200-0x3fff
Reserved
19.2.1
19.2.1.1
Register descriptions
eDMA Control Register (DMACR)
The 32-bit DMACR defines the basic operating configuration of the eDMA.
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Arbitration can be configured to use either a fixed-priority or a round-robin selection. In fixed-priority
arbitration, the highest priority channel requesting service is selected to execute. The priorities are
assigned by the channel priority registers (see Section 19.2.1.16, eDMA Channel n Priority (DCHPRIn),
n = 0,..., {15}). In round-robin arbitration mode, the channel priorities are ignored and the channels are
cycled through without regard to priority.
Minor loop offsets are address offset values added to the final source address (saddr) or destination address
(daddr) upon minor loop completion. When minor loop offsets are enabled, the minor loop offset (mloff)
is added to the final source address (saddr), or the final destination address (daddr), or both prior to the
addresses being written back into the TCD. If the major loop is complete, the minor loop offset is ignored
and the major loop address offsets (slast and dlast_sga) are used to compute the next saddr and daddr
values.
When minor loop mapping is enabled (DMACR[EMLM] = 1), TCDn word2 is redefined. A portion of
TCDn word2 is used to specify multiple fields: an source enable bit (smloe) to specify the minor loop offset
should be applied to the source address (saddr) upon minor loop completion, an destination enable bit
(dmloe) to specify the minor loop offset should be applied to the destination address (daddr) upon minor
loop completion, and the sign extended minor loop offset value (mloff). The same offset value (mloff) is
used for both source and destination minor loop offsets. When either minor loop offset is enabled (smloe
set or dmloe set), the nbytes field is reduced to 10 bits. When both minor loop offsets are disabled (smloe
cleared and dmloe cleared), the nbytes field is a 30-bit vector.
When minor loop mapping is disabled (DMACR[EMLM] = 0), all 32 bits of TCDn word2 are assigned to
the nbytes field. See Section 19.2.1.17, Transfer Control Descriptor (TCD), for more details.
See Figure 184 and Table 194 for the DMACR definition.
Register address: DMA_Offset + 0x0000
R
W
RESET:
R
W
RESET:
0
0
16
0
1
0
17
0
2
0
18
0
3
0
19
0
4
0
20
0
5
0
21
0
6
0
7
0
22
23
GRP0PRI
0
0
8
0
9
0
10
0
11
0
12
0
13
0
14
CX
15
ECX
0
0
24
25
26
27
28
29
30
31
EML CLM HALT HOE ERG ERC EDB EBW
M
A
A
G
0
0
0
0
0
0
0
0
= Unimplemented
Figure 184. eDMA Control Register (DMACR)
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Table 194. eDMA Control Register (DMACR) field descriptions
Name
Description
Value
CX
Cancel Transfer
ECX
Error Cancel Transfer
GRP0PRI
Channel Group 0 Priority
EMLM
Enable Minor Loop Mapping
CLM
Continuous Link Mode
A minor loop channel link made to itself will go
through channel arbitration before being activated
again.
1 A minor loop channel link made to itself will not go
through channel arbitration before being activated
again. Upon minor loop completion the channel will
active again if that channel has has a minor loop
channel link enabled and the link channel is itself.
This effectively applies the minor loop offsets and
restarts the next minor loop.
HALT
Halt eDMA Operations
0
1
Normal operation.
Stall the start of any new channels. Executing
channels are allowed to complete. Channel
execution will resume when the HALT bit is cleared.
HOE
Halt On Error
0
1
Normal operation.
Any error will cause the HALT bit to be set.
Subsequently, all service requests will be ignored
until the HALT bit is cleared.
0
1
Normal operation.
Cancel the remaining data transfer. Stop the
executing channel and force the minor loop to be
finished. The cancel takes effect after the last write
of the current read/write sequence. The CXFR bit
clears itself after the cancel has been honored. This
cancel retires the channel normally as if the minor
loop was completed.
0 Normal operation.
1 Cancel the remaining data transfer in the same
fashion as the CX cancel transfer. Stop the
executing channel and force the minor loop to be
finished. The cancel takes effect after the last write
of the current read/write sequence. The ECX bit
clears itself after the cancel cancel has been
honored. In addition to cancelling the transfer, the
ECX treats the cancel as an error condition; thus
updating the DMAES register and generating an
optional error interrupt (see Section 19.2.1.2, eDMA
Error Status (DMAES)).
Group 0 priority level when fixed priority group
arbitration is enabled.
0
Minor loop mapping disabled. TCDn.word2 is
defined as a 32-bit NBYTES field.
1 Minor loop mapping enabled. When set,
TCDn.word2 is redefined to include individual
enable fields, an offset field and the NBYTES field.
The individual enable fields allow the minor loop
offset to be applied to the source address, the
destination address, or both. The NBYTES field is
reduced when either offset is enabled.
0
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Table 194. eDMA Control Register (DMACR) field descriptions
Name
Description
Value
ERGA
Enable Round Robin Group Arbitration
0 Fixed priority arbitration is used for selection among
the groups.
1 Round robin arbitration is used for selection among
the groups.
ERCA
Enable Round Robin Channel Arbitration 0
Fixed priority arbitration is used for channel
selection within each group.
1 Round robin arbitration is used for channel selection
within each group.
EDBG
Enable Debug
EBW
Enable Buffered Writes
19.2.1.2
0
1
The assertion of the ipg_debug input is ignored.
The assertion of the ipg_debug input causes the
eDMA to stall the start of a new channel. Executing
channels are allowed to complete. Channel
execution will resume when either the ipg_debug
input is negated or the EDBG bit is cleared.
0 The bufferable write signal (hprot[2]) is not asserted
during AMBA AHB writes.
1 The bufferable write signal (hprot[2]) is asserted on
all AMBA AHB writes except for the last write
sequence.
eDMA Error Status (DMAES)
The DMAES register provides information concerning the last recorded channel error. Channel errors can
be caused by a configuration error (an illegal setting in the transfer control descriptor or an illegal priority
register setting in fixed arbitration mode) or an error termination to a bus master read or write cycle.
A configuration error is caused when the starting source or destination address, source or destination
offsets, minor loop byte count and the transfer size represent an inconsistent state. The addresses and
offsets must be aligned on 0-modulo-transfer_size boundaries, and the minor loop byte count must be a
multiple of the source and destination transfer sizes. All source reads and destination writes must be
configured to the natural boundary of the programmed transfer size respectively. In fixed arbitration mode,
a configuration error is caused by any two channel priorities being equal within a group, or any group
priority levels being equal among the groups. All channel priority levels within a group must be unique
and all group priority levels among the groups must be unique when fixed arbitration mode is enabled. If
a scatter/gather operation is enabled upon channel completion, a configuration error is reported if the
scatter/gather address (dlast_sga) is not aligned on a 32-byte boundary. If minor loop channel linking is
enabled upon channel completion, a configuration error is reported when the link is attempted if the
TCD.citer.e_link bit does not equal the TCD.biter.e_link bit. All configuration error conditions except
scatter/gather and minor loop link error are reported as the channel is activated and assert an error interrupt
request, if enabled. A scatter/gather configuration error is reported when the scatter/gather operation
begins at major loop completion when properly enabled. A minor loop channel link configuration error is
reported when the link operation is serviced at minor loop completion.
If a system bus read or write is terminated with an error, the data transfer is stopped and the appropriate
bus error flag set. In this case, the state of the channel’s transfer control descriptor is updated by the eDMA
engine with the current source address, destination address and current iteration count at the point of the
fault. When a system bus error occurs, the channel is terminated after the read or write transaction which
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is already pipelined after errant access, has completed. If a bus error occurs on the last read prior to
beginning the write sequence, the write will execute using the data captured during the bus error. If a bus
error occurs on the last write prior to switching to the next read sequence, the read sequence will execute
before the channel is terminated due to the destination bus error.
A transfer may be cancelled by software via the DMACR[CX] bit. When a cancel transfer request is
recognized, the eDMA engine stops processing the channel. The current read-write sequence is allowed to
finish. If the cancel occurs on the last read-write sequence of a major or minor loop, the cancel request is
discarded and the channel retires normally.
The error cancel transfer is the same as a cancel transfer except the DMAES register is updated with the
cancelled channel number and error cancel bit is set. The TCD of a cancelled channel has the source
address and destination address of the last transfer saved in the TCD. It is the responsibility of the user to
initialize the TCD again should the channel need to be restarted because the aforementioned fields have
been modified by the eDMA engine and no longer represent the original parameters. When a transfer is
cancelled via the error cancel transfer mechanism (setting the DMACR[ECX]), the channel number is
loaded into the ERRCHN field and the ECX and VLD bits are set are set in the DMAES register. In
addition, an error interrupt may be generated if enabled. See Section 19.2.1.14, eDMA Error (DMAERRL)
for error interrupt details.The occurrence of any type of error causes the eDMA engine to immediately
stop, and the appropriate channel bit in the eDMA Error register to be asserted. At the same time, the
details of the error condition are loaded into the DMAES register. The major loop complete indicators,
setting the transfer control descriptor done flag and the possible assertion of an interrupt request, are not
affected when an error is detected. See Figure 185 and Table 195 for the DMAES definition.
Register address: DMA_Offset + 0x0004
0
R
VLD
W
RESET:
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
0
9
0
10
0
11
0
12
0
13
0
14
0
15
ECX
0
16
17
R
GPE CPE
W
RESET:
0
0
18
0
19
0
20
0
0
0
21
22
23
ERRCHN[0:3]
0
0
0
24
25
26
27
28
29
30
31
SAE SOE DAE DOE NCE SGE SBE DBE
0
0
0
0
0
0
0
0
= Unimplemented
Figure 185. eDMA Error Status (DMAES) Register
Table 195. eDMA Error Status (DMAES) field descriptions
Name
Description
VLD
Logical OR of all DMAERRH and
DMAERRL status bits.
ECX
Transfer cancelled
Value
0
1
No DMAERR bits are set.
At least one DMAERR bit is set indicating a valid
error exists that has not been cleared.
0 No cancelled transfers.
1 The last recorded entry was a cancelled transfer via
the error cancel transfer input.
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Table 195. eDMA Error Status (DMAES) field descriptions (Continued)
Name
Description
Value
GPE
Group Priority Error
CPE
Channel Priority Error
ERRCHN[0:3]
Error/Cancelled Channel Number
SAE
Source Address Error
0
1
No source address configuration error.
The last recorded error was a configuration error
detected in the TCD.saddr field. TCD.saddr is
inconsistent with TCD.ssize.
SOE
Source Offset Error
0
1
No source offset configuration error.
The last recorded error was a configuration error
detected in the TCD.soff field. TCD.soff is
inconsistent with TCD.ssize.
DAE
Destination Address Error
0
1
No destination address configuration error.
The last recorded error was a configuration error
detected in the TCD.daddr field. TCD.daddr is
inconsistent with TCD.dsize.
DOE
Destination Offset Error
0
1
No destination offset configuration error.
The last recorded error was a configuration error
detected in the TCD.doff field. TCD.doff is
inconsistent with TCD.dsize.
NCE
Nbytes/Citer Configuration Error
0
1
No nbytes/citer configuration error.
The last recorded error was a configuration error
detected in the TCD.nbytes or TCD.citer fields.
TCD.nbytes is not a multiple of TCD.ssize and
TCD.dsize, or TCD.citer is equal to zero, or
TCD.citer.e_link is not equal to TCD.biter.e_link.
SGE
Scatter/Gather Configuration Error
0
1
No scatter/gather configuration error.
The last recorded error was a configuration error
detected in the TCD.dlast_sga field. This field is
checked at the beginning of a scatter/gather
operation after major loop completion if TCD.e_sg is
enabled. TCD.dlast_sga is not on a 32 byte
boundary.
SBE
Source Bus Error
DBE
Destination Bus Error
0
1
No group priority error.
The last recorded error was a configuration error
among the group priorities. All group priorities are
not unique.
0 No channel priority error.
1 The last recorded error was a configuration error in
the channel priorities within a group. All channel
priorities within a group are not unique.
The channel number of the last recorded error
(excluding GPE and CPE errors)or last recorded
transfer that was cancelled with error exit.
0 No source bus error.
1 The last recorded error was a bus error on a source
read.
0
1
No destination bus error.
The last recorded error was a bus error on a
destination write.
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19.2.1.3
eDMA Enable Request (DMAERQL)
The DMAERQL register provide a bit map for the implemented channels to enable the request signal for
each channel. DMAEQRL covers channels 15-00. The state of any given channel enable is directly
affected by writes to this register; it is also affected by writes to the DMASERQ and DMACERQ registers.
The eDMA{S,C}ERQ registers are provided so that the request enable for a single channel can easily be
modified without the need to perform a read-modify-write sequence to the DMAERQ{H,L} registers.
Both the eDMA request input signal and this enable request flag must be asserted before a channel’s
hardware service request is accepted. The state of the eDMA enable request flag does not affect a channel
service request made explicitly through software or a linked channel request. See Figure 186 and
Table 196 for the DMAERQ definition.
0
0
31
0
R
RESET:
1
0
30
0
2
0
29
0
3
0
28
0
4
0
27
0
5
0
26
0
6
0
25
0
7
0
24
0
8
0
23
0
9
0
22
0
10
0
21
0
11
0
20
0
12
0
19
0
13
0
18
0
14
0
17
0
15
0
16
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ ERQ
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 186. eDMA Enable Request (DMAERQL) Register
Table 196. eDMA Enable Request (DMAERQL) field description
Name
Description
ERQn,
n = 0,... 15
Enable eDMA Request n
Value
0
1
The eDMA request signal for channel n is disabled.
The eDMA request signal for channel n is enabled.
As a given channel completes the processing of its major iteration count, there is a flag in the transfer
control descriptor that may affect the ending state of the DMAERQ bit for that channel. If the TCD.d_req
bit is set, then the corresponding DMAERQ bit is cleared, disabling the eDMA request; else if the d_req
bit is cleared, the state of the DMAERQ bit is unaffected.
19.2.1.4
eDMA Enable Error Interrupt (DMAEEIL)
The DMAEEIL register provides a bit map for the implemented channels to enable the error interrupt
signal for each channel. DMAEEIL covers channels 15-00. The state of any given channel’s error interrupt
enable is directly affected by writes to this register; it is also affected by writes to the DMASEEI and
DMACEEI registers. The eDMA{S,C}EEI registers are provided so that the error interrupt enable for a
single channel can easily be modified without the need to perform a read-modify-write sequence to the
DMAEEIL register.
Both the eDMA error indicator and this error interrupt enable flag must be asserted before an error
interrupt request for a given channel is asserted. See Figure 187 and Table 197 for the DMAEEI definition.
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R
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
0
9
0
10
0
11
0
12
0
13
0
14
0
15
0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
EEI15 EEI14 EEI13 EEI12 EEI11 EEI10 EEI09 EEI08 EEI07 EEI06 EEI05 EEI04 EEI03 EEI02 EEI01 EEI00
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 187. eDMA Enable Error Interrupt (DMAEEIL) Register
Table 197. eDMA Enable Error Interrupt (DMAEEIL) field descriptions
Name
Description
Value
EEIn,
n = 0,... 15
Enable Error Interrupt n
0 The error signal for channel n does not generate an
error interrupt.
1 The assertion of the error signal for channel n
generate an error interrupt request.
19.2.1.5
eDMA Set Enable Request (DMASERQ)
The DMASERQ register provides a simple memory-mapped mechanism to set a given bit in the
DMAERQL register to enable the eDMA request for a given channel. The data value on a register write
causes the corresponding bit in the DMAERQL register to be set. A data value of 64 to 127 (regardless of
the number of implemented channels) provides a global set function, forcing the entire contents of
DMAERQL to be asserted. If NOP bit is set, the command is ignored. This allows multiple byte registers
to be written as a 32-bit word. Reads of this register return all zeroes. See Figure 188 and Table 198 for
the DMASERQ definition.
Register address: DMA_Offset + 0x0018
0
0
NOP
R
W
RESET:
1
0
2
0
3
0
0
0
0
4
0
SERQ[0:6]
0
5
0
6
0
7
0
0
0
0
= Unimplemented
Figure 188. eDMA Set Enable Request (DMASERQ) Register
Table 198. eDMA Set Enable Request (DMASERQ) field descriptions
Name
Description
NOP
No Operation
SERQ[0:6]
Set Enable Request
Value
0
1
Normal operation.
No operation, ignore bits 1-7
0-15 Set the corresponding bit in DMAERQL
16-63 Reserved
64-127 Set all bits in DMAERQL
Note: Bit 2 (SERQ1) and Bit 3 (SERQ2) is not used.
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
19-401
19.2.1.6
eDMA Clear Enable Request (DMACERQ)
The DMACERQ register provides a simple memory-mapped mechanism to clear a given bit in the
DMAERQL register to disable the eDMA request for a given channel. The data value on a register write
causes the corresponding bit in the DMAERQL register to be cleared. A data value of 64 to 127 (regardless
of the number of implemented channels) provides a global clear function, forcing the entire contents of the
DMAERQL to be zeroed, disabling all eDMA request inputs. If the NOP bit is set, the command is
ignored. This allows multiple byte registers to be written as a 32-bit word.Reads of this register return all
zeroes. See Figure 189 and Table 199 for the DMACERQ definition.
Register address: DMA_Offset + 0x0019
R
W
RESET:
0
0
NOP
1
0
2
0
3
0
0
0
0
4
0
CERQ[0:6]
0
5
0
6
0
7
0
0
0
0
= Unimplemented
Figure 189. eDMA Clear Enable Request (DMACERQ) Register
Table 199. eDMA Clear Enable Request (DMACERQ) field descriptions
Name
Description
NOP
No Operation
CERQ[0:6]
Clear Enable Request
19.2.1.7
Value
0
1
Normal operation.
No operation, ignore bits 1-7
0-15 Clear corresponding bit in DMAERQL
16-63 Reserved
64-127 Clear all bits in DMAERQL
Note: Bit 2 (CERQ1) and Bit 3 (CERQ2) is not used.
eDMA Set Enable Error Interrupt (DMASEEI)
The DMASEEI register provides a simple memory-mapped mechanism to set a given bit in the DMAEEIL
register to enable the error interrupt for a given channel. The data value on a register write causes the
corresponding bit in the DMAEEIL register to be set. A data value of 64 to 127 (regardless of the number
of implemented channels) provides a global set function, forcing the entire contents of DMAEEI to be
asserted. If the NOP bit is set, the command is ignored. This allows multiple byte registers to be written as
a 32-bit wordReads of this register return all zeroes. See Figure 190 and Table 200 for the DMASEEI
definition.
Register address: DMA_Offset + 0x001a
R
W
RESET:
0
0
NOP
1
0
2
0
3
0
0
0
0
4
0
SEEI[0:6]
0
5
0
6
0
7
0
0
0
0
= Unimplemented
Figure 190. eDMA Set Enable Error Interrupt (DMASEEI) Register
MPC5604E Reference Manual, Rev. 5
19-402
Freescale Semiconductor
Table 200. eDMA Set Enable Error Interrupt (DMASEEI) field descriptions
Name
Description
NOP
No Operation
SEEI[0:6]
Set Enable Error Interrupt
19.2.1.8
Value
0
1
Normal operation.
No operation, ignore bits 1-7
0-15 Set the corresponding bit in DMAEEIL
16-63 Reserved
64-127 Set all bits in DMAEEIL
Note: Bit 2 (SEEI1) and Bit 3 (SEEI2) is not used.
eDMA Clear Enable Error Interrupt (DMACEEI)
The DMACEEI register provides a simple memory-mapped mechanism to clear a given bit in the
DMAEEIL register to disable the error interrupt for a given channel. The data value on a register write
causes the corresponding bit in the DMAEEIL register to be cleared. A data value of 64 to 127 (regardless
of the number of implemented channels) provides a global clear function, forcing the entire contents of the
DMAEEIL to be zeroed, disabling all eDMA request inputs. If the NOP bit is set, the command is ignored.
This allows multiple byte registers to be written as a 32-bit word. Reads of this register return all zeroes.
See Figure 191 and Table 201 for the DMACEEI definition.
Register address: DMA_Offset + 0x001b
0
0
NOP
R
W
RESET:
1
0
2
0
3
0
0
0
0
4
0
CEEI[0:6]
0
5
0
6
0
7
0
0
0
0
= Unimplemented
Figure 191. eDMA Clear Enable Error Interrupt (DMACEEI) Register
Table 201. eDMA Clear Enable Error Interrupt (DMACEEI) field descriptions
Name
Description
NOP
No Operation
CEEI[0:6]
Clear Enable Error Interrupt
19.2.1.9
Value
0
1
Normal operation.
No operation, ignore bits 1-7
0-15 Clear corresponding bit in DMAEEIL
16-63 Reserved
64-127 Clear all bits in DMAEEIL
Note: Bit 2 (CEEI1) and Bit 3 (CEEI2) is not used.
eDMA Clear Interrupt Request (DMACINT)
The DMACINT register provides a simple memory-mapped mechanism to clear a given bit in the
DMAINTL registers to disable the interrupt request for a given channel. The given value on a register write
causes the corresponding bit in the DMAINTL register to be cleared. A data value of 64 to 127 (regardless
of the number of implemented channels) provides a global clear function, forcing the entire contents of the
DMAINTL to be zeroed, disabling all eDMA interrupt requests. If the NOP bit is set, the command is
ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of this register return all
zeroes. See Figure 192 and Table 202 for the DMACINT definition.
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
19-403
Register address: DMA_Offset + 0x001c
R
W
RESET:
0
0
NOP
1
0
2
0
3
0
0
0
0
4
0
CINT[0:6]
0
5
0
6
0
7
0
0
0
0
= Unimplemented
Figure 192. eDMA Clear Interrupt Request (DMACINT) Fields
Table 202. eDMA Clear Interrupt Request (DMACINT) field descriptions
Name
Description
Value
NOP
No Operation
CINT[0:6]
Clear Interrupt Request
0
1
Normal operation.
No operation, ignore bits 1-7
0-15 Clear the corresponding bit in DMAINTL
16-63 Reserved
64-127 Clear all bits in DMAINTL
Note: Bit 2 (CINT1) and Bit 3 (CINT2) is not used.
19.2.1.10 eDMA Clear Error (DMACERR)
The DMACEER register provides a simple memory-mapped mechanism to clear a given bit in the
DMAERRL register to disable the error condition flag for a given channel. The given value on a register
write causes the corresponding bit in the DMAERRL register to be cleared. A data value of 64 to 127
(regardless of the number of implemented channels) provides a global clear function, forcing the entire
contents of the DMAERRL to be zeroed, clearing all channel error indicators. If the NOP bit is set, the
command is ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of this
register return all zeroes. See Figure 193 and Table 203 for the DMACERR definition.
Register address: DMA_Offset + 0x001d
R
W
RESET:
0
0
NOP
1
0
2
0
3
0
0
0
0
4
0
CERR[0:6]
0
5
0
6
0
7
0
0
0
0
= Unimplemented
Figure 193. eDMA Clear Error (DMACERR) Register
Table 203. eDMA Clear Error (DMACERR) field descriptions
Name
Description
NOP
No Operation
CERR[0:6]
Clear Error Indicator
Value
0
1
Normal operation.
No operation, ignore bits 1-7
0-15 Clear corresponding bit in DMAERRL
16-63 Reserved
64-127 Clear all bits in DMAERRL
Note: Bit 2 (CERR1) and Bit 3 (CERR2) is not used.
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Freescale Semiconductor
19.2.1.11 eDMA Set START Bit (DMASSRT)
The DMASSRT register provides a simple memory-mapped mechanism to set the START bit in the TCD
of the given channel. The data value on a register write causes the START bit in the corresponding Transfer
Control Descriptor to be set. A data value of 64 to 127 (regardless of the number of implemented channels)
provides a global set function, forcing all START bits to be set. If the NOP bit is set, the command is
ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of this register return all
zeroes. See Table 218 for the TCD START bit definition.
Register address: DMA_Offset + 0x001e
R
W
RESET:
0
0
NOP
1
0
2
0
3
0
0
0
0
4
0
SSRT[0:6]
0
5
0
6
0
7
0
0
0
0
= Unimplemented
Figure 194. eDMA Set START Bit (DMASSRT) Register
Table 204. eDMA Set START Bit (DMASSRT) field descriptions
Name
Description
Value
NOP
No Operation
SSRT[0:6]
Set START Bit
(Channel Service Request)
0
1
Normal operation.
No operation, ignore bits 1-7
0-15 Set the corresponding channel’s TCD start bit
16-63 Reserved
64-127 Set all TCD.start bits
Note: Bit 2 (SSRT1) and Bit 3 (SSRT2) is not used.
19.2.1.12 eDMA Clear DONE Status (DMACDNE)
The DMACDNE register provides a simple memory-mapped mechanism to clear the DONE bit in the
TCD of the given channel. The data value on a register write causes the DONE bit in the corresponding
Transfer Control Descriptor to be cleared. A data value of 64 to 127 (regardless of the number of
implemented channels) provides a global clear function, forcing all DONE bits to be cleared. If bit 7 is set,
the command is ignored. This allows multiple byte registers to be written as a 32-bit word. Reads of this
register return all zeroes. See Table 218 for the TCD DONE bit definition.
Register address: DMA_Offset + 0x001f
R
W
RESET:
0
0
NOP
1
0
2
0
3
0
0
0
0
4
0
CDNE[0:6]
0
5
0
6
0
7
0
0
0
0
= Unimplemented
Figure 195. eDMA Clear DONE Status (DMACDNE) Register
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
19-405
Table 205. eDMA Clear DONE Status (DMACDNE) field descriptions
Name
Description
Value
NOP
No Operation
CDNE[0:6]
Clear DONE Status Bit
0
1
Normal operation.
No operation, ignore bits 1-7
0-15 Clear the corresponding channel’s TCD Start bit
16-63 Reserved
64-127 Clear all TCD.Start bits
Note: Bit 2 (CDNE1) and Bit 3 (CDNE2) is not used.
19.2.1.13 eDMA Interrupt Request (DMAINTL)
The DMAINTL register provides a bit map for the implemented channels signaling the presence of an
interrupt request for each channel. DMAINTL covers channels 15-00. The eDMA engine signals the
occurrence of a programmed interrupt upon the completion of a data transfer as defined in the transfer
control descriptor by setting the appropriate bit in this register. The outputs of this register are directly
routed to the platform’s interrupt controller. During the execution of the interrupt service routine
associated with any given channel, it is software’s responsibility to clear the appropriate bit, negating the
interrupt request. Typically, a write to the DMACINT register in the interrupt service routine is used for
this purpose.
The state of any given channel’s interrupt request is directly affected by writes to this register; it is also
affected by writes to the DMACINT register. On writes to the DMAINT, a one in any bit position clears
the corresponding channel’s interrupt request. A zero in any bit position has no affect on the corresponding
channel’s current interrupt status. The DMACINT register is provided so the interrupt request for a single
channel can easily be cleared without the need to perform a read-modify-write sequence to the DMAINTL
registers. See Figure 196 and Table 206 for the DMAINT definition.
Register address: DMA_Offset + 0x0024 (DMAINTL)
R
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
0
9
0
10
0
11
0
12
0
13
0
14
0
15
0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
INT1 INT1 INT1 INT1 INT1 INT1 INT0 INT0 INT0 INT0 INT0 INT0 INT0 INT0 INT0 INT0
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 196. eDMA Interrupt Request (DMAINTL) Register
Table 206. eDMA Interrupt Request (DMAINTL) field descriptions
Name
Description
INTn,
n = 0,... 15
DMA Interrupt Request n
Value
0
1
The interrupt request for channel n is cleared.
The interrupt request for channel n is active.
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Freescale Semiconductor
19.2.1.14 eDMA Error (DMAERRL)
The DMAERRL registers provide a bit map for the implemented channels signaling the presence of an
error for each channel. DMAERRL covers channels 15-00. The eDMA engine signals the occurrence of a
error condition by setting the appropriate bit in this register. The outputs of this register are enabled by the
contents of the DMAEEI register, then logically summed across groups to form several group error
interrupt requests which is then routed to the platform’s interrupt controller. During the execution of the
interrupt service routine associated with any eDMA errors, it is software’s responsibility to clear the
appropriate bit, negating the error interrupt request. Typically, a write to the DMACERR register in the
interrupt service routine is used for this purpose. Recall the normal eDMA channel completion indicators,
setting the transfer control descriptor done flag and the possible assertion of an interrupt request, are not
affected when an error is detected.
The contents of this register can also be polled and a non-zero value indicates the presence of a channel
error, regardless of the state of the DMAEEI register. The state of any given channel’s error indicators is
affected by writes to this register; it is also affected by writes to the DMACERR register. On writes to the
DMAERR, a one in any bit position clears the corresponding channel’s error status. A zero in any bit
position has no affect on the corresponding channel’s current error status. The DMACERR register is
provided so the error indicator for a single channel can easily be cleared. See Figure 197 and Table 207 for
the DMAERR definition.
R
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
0
9
0
10
0
11
0
12
0
13
0
14
0
15
0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 197. eDMA Error (DMAERRL) Register
Table 207. eDMA Error (DMAERRL) field descriptions
Name
Description
ERRn,
n = 0,... 15
DMA Error n
Value
0
1
An error in channel n has not occurred.
An error in channel n has occurred.
19.2.1.15 eDMA Hardware Request Status (DMAHRSL)
The DMAHRSL registers provide a bit map for the implemented channels to show the current hardware
request status for each channel. DMAHRSL covers channels 15-00. Hardware request status reflects the
current state of the registered and qualified (via the DMAERQ field) ipd_req lines as seen by the DMA2’s
arbitration logic. This view into the hardware request signals may be used for debug purposes.
See Figure 198 and Figure 208 for the DMAHRS definition.
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
19-407
R
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
0
9
0
10
0
11
0
12
0
13
0
14
0
15
0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS HRS
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 198. eDMA Hardware Request Status (DMAHRSL) Register
Table 208. eDMA Hardware Request Status (DMAHRSL) field descriptions
Name
Description
Value
HRSn,
n = 0,... 15
DMA Hardware Request Status n
0
1
A hardware service request for channel n is not present.
A hardware service request for channel n is present.
Note: The hardware request status reflects the state of the request as seen
by the arbitration logic. Therefore, this status is affected by the
DMAERQn bit.
19.2.1.16 eDMA Channel n Priority (DCHPRIn), n = 0,..., {15}
When the fixed-priority channel arbitration mode is enabled (DMACR[ERCA] = 0), the contents of these
registers define the unique priorities associated with each channel within a group. The channel priorities
are evaluated by numeric value, i.e., 0 is the lowest priority, 1 is the next higher priority, then 2, 3, etc.
Software must program the channel priorities with unique values, otherwise a configuration error will be
reported. The range of the priority value is limited to the values of 0–15. When read, the GRPPRI bits of
the DCHPRIn register reflect the current priority level of the group of channels in which the corresponding
channel resides. GRPPRI bits are not affected by writes to the DCHPRIn registers. The group priority is
assigned in the DMACR. See Figure 184 and Table 194 for the DMACR definition.
Channel preemption is enabled on a per channel basis by setting the ECP bit in the DCHPRIn register.
Channel preemption allows the executing channel’s data transfers to be temporarily suspended in favor of
starting a higher priority channel. After the preempting channel has completed all of its minor loop data
transfers, the preempted channel is restored and resumes execution. After the restored channel completes
one read/write sequence, it is again eligible for preemption. If any higher priority channel is requesting
service, the restored channel will be suspended and the higher priority channel will be serviced. Nested
preemption (attempting to preempt a preempting channel) is not supported. After a preempting channel
begins execution, it cannot be preempted. Preemption is only available when fixed arbitration is selected
for both group and channel arbitration modes. A channel’s ability to preempt another channel can be
disabled by setting the DPA bit in the DCHPRIn register. When a channel’s preempt ability is disabled,
that channel cannot suspend a lower priority channel’s data transfer; regardless of the lower priority
channel’s ECP setting. This allows for a pool of low priority, large data moving channels to be defined.
These low priority channels can be configured to not preempt each other, thus preventing a low priority
MPC5604E Reference Manual, Rev. 5
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Freescale Semiconductor
channel from consuming the preempt slot normally available a true, high priority channel. See Figure 199
and Table 209 for the DCHPRIn definition.
Register address: DMA_Offset + 0x100 + n
R
W
RESET:
0
ECP
1
DPA
0
0
2
3
GRPPRI[0:1]
4
5
6
CHPRI[0:3]
7
*
*
*
*
*
*
= Unimplemented,
= defaults to channel number (n) after reset
*
Figure 199. eDMA Channel n Priority (DCHPRIn) Register
Table 209. eDMA Channel n Priority (DCHPRIn) field descriptions
Name
Description
Value
ECP
Enable Channel Preemption
0 Channel n cannot be suspended by a higher priority
channel’s service request.
1 Channel n can be temporarily suspended by the
service request of a higher priority channel.
DPA
Disable Preempt Ability
0 Channel n can suspend a lower priority channel.
1 Channel n cannot suspend any channel, regardless
of channel priority.
GRPPRI[0:1]
Channel n Current Group Priority
Group priority assigned to this channel group when
fixed-priority arbitration is enabled. These two bits are
read only; writes are ignored.
CHPRI[0:3]
Channel n Arbitration Priority
Channel priority when fixed-priority arbitration is
enabled.
19.2.1.17 Transfer Control Descriptor (TCD)
Each channel requires a 32-byte transfer control descriptor for defining the desired data movement
operation. The TCD structure was previously discussed in detail in Section 19.1.2, Features.” The channel
descriptors are stored in the local memory in sequential order: channel 0, channel 1, ... channel [n-1]. The
definitions of the TCD are presented as eight 32-bit values. Table 210 is a 32-bit view of the basic TCD
structure.
Table 210. TCDn 32-bit memory structure
eDMA Offset
TCDn Field
0x1000 + (32 x n) + 0x00
Source Address (saddr)
0x1000 + (32 x n) + 0x04
0x1000 + (32 x n) + 0x08
0x1000 + (32 x n) + 0x0c
0x1000 + (32 x n) + 0x10
0x1000 + (32 x n) + 0x14
0x1000 + (32 x n) + 0x18
Transfer Attributes
(smod, ssize, dmod, dsize)
Signed Source Address Offset (soff)
Signed Minor Loop Offset (smloe, dmloe, mloff)
Inner “Minor” Byte
Count (nbytes)
Last Source Address Adjustment (slast)
Destination Address (daddr)
Current “Major” Iteration Count (citer)
Signed Destination Address Offset (doff)
Last Destination Address Adjustment/Scatter Gather Address (dlast_sga)
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
19-409
Table 210. TCDn 32-bit memory structure (Continued)
0x1000 + (32 x n) + 0x1c
Beginning “Major” Iteration Count (biter)
Channel Control/Status
(bwc, major.linkch, done, active,
major.e_link, e_sg, d_req, int_half, int_maj,
start)
Figure 200 and Table 211 define word 0 of the TCDn structure, the saddr field.
Register address: DMA_Offset + 0x1000 + (32 x n) + 0x00
R
W
RESET:
R
W
RESET:
0
1
2
3
4
5
6
-
-
-
-
-
-
-
16
17
18
19
20
21
22
-
-
-
-
-
-
-
7
8
saddr[0:15]
-
-
23
24
saddr[16:31]
-
-
9
10
11
12
13
14
15
-
-
-
-
-
-
-
25
26
27
28
29
30
31
-
-
-
-
-
-
-
= Unimplemented
Figure 200. TCDn Word 0 (TCDn.saddr) field
Table 211. TCDn Word 0 (TCDn.saddr) field description
Name
Description
Value
saddr[[0:31]
Source address
Memory address pointing to the source data.
Figure 201 and Table 212 define word 1 of the TCDn structure, the soff and transfer attribute fields.
Register address: DMA_Offset + 0x1000 + (32 x n) + 0x04
R
W
RESET:
R
W
RESET:
0
1
2
3
smod[0:4]
4
5
-
-
-
16
17
-
-
6
7
ssize[0:2]
-
-
-
-
18
19
20
21
22
-
-
-
-
-
-
8
9
-
-
-
25
-
23
24
soff[16:31]
-
-
10
11
dmod[0:4]
12
13
14
15
dsize[0:2]
-
-
-
-
-
26
27
28
29
30
31
-
-
-
-
-
-
= Unimplemented
Figure 201. TCDn Word 1 (TCDn.{soff,smod,ssize,dmod,dsize}) fields
MPC5604E Reference Manual, Rev. 5
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Freescale Semiconductor
Table 212. TCDn Word 1 (TCDn.{smod,ssize,dmod,dsize,soff}) field descriptions
Name
Description
Value
smod[0:4]
Source address modulo
0 Source address modulo feature is disabled.
non-0
The value defines a specific address bit which is
selected to be either the value after saddr + soff
calculation is performed or the original register value.
This feature provides the ability to easily implement a
circular data queue. For data queues requiring
power-of-2 “size” bytes, the queue should be based at
a 0-modulo-size address and the smod field set to the
appropriate value to freeze the upper address bits. The
bit select is defined as ((1 << smod[4:0]) - 1) where a
resulting 1 in a bit location selects the next state
address for the corresponding address bit location and
a 0 selects the original register value for the
corresponding address bit location. For this
application, the soff is typically set to the transfer size
to implement post-increment addressing with the smod
function constraining the addresses to a 0-modulo-size
range.
ssize[0:2]
Source data transfer size
000
001
010
011
100
101
110
111
8-bit
16-bit
32-bit
Reserved
16-byte
32-byte
Reserved
Reserved
dmod[0:4]
Destination address modulo
See the smod[5:0] definition.
dsize[0:2]
Destination data transfer size
See the ssize[2:0] definition.
soff[16:31]
Source address signed offset
Sign-extended offset applied to the current source
address to form the next-state value as each source
read is completed.
Figure 202 and Table 213 define word 2 of the TCDn structure, the nbytes field.
Register address: DMA_Offset + 0x1000 + (32 x n) + 0x08
R
W
RESET:
R
W
RESET:
0
1
2
3
4
5
6
-
-
-
-
-
-
-
16
17
18
19
20
21
22
-
-
-
-
-
-
-
7
8
nbytes[0:15]
-
-
9
10
11
12
13
14
15
-
-
-
-
-
-
-
26
27
28
29
30
31
-
-
-
-
-
-
23
24
25
nbytes[16:31]
-
-
-
= Unimplemented
Figure 202. TCDn Word 2 (TCDn.nbytes) field
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Freescale Semiconductor
19-411
Table 213. TCDn Word 2 (TCDn.nbytes) field description
Name
Description
Value
nbytes[0:31]
Inner “minor” byte transfer count
Number of bytes to be transferred in each service
request of the channel.
As a channel is activated, the contents of the
appropriate TCD is loaded into the eDMA engine, and
the appropriate reads and writes performed until the
complete byte transfer count has been transferred.
This is an indivisible operation and cannot be stalled or
halted. After the minor count is exhausted, the current
values of the saddr and daddr are written back into the
local memory, the major iteration count is decremented
and restored to the local memory. If the major iteration
count is completed, additional processing is performed.
The nbytes value 0x0000_0000 is interpreted as
0x1_0000_0000, thus specifying a 4 GB transfer.
When minor loop mapping (DMACR[EMLM] = 1) is enabled, TCD word2 is redefined as four fields: a
source minor loop offset enable, a destination minor loop offset enable, a minor loop offset field and a
nbytes field.
Figure 203. TCDn Word 2 (TCDn.nbytes) field (DMACR[EMLM] = 1)
Figure 204 and Table 214 define word 3 of the TCDn structure, the slast field.
Register address: DMA_Offset + 0x1000 + (32 x n) + 0x0c
R
W
RESET:
R
W
RESET:
0
1
2
3
4
5
6
-
-
-
-
-
-
-
16
17
18
19
20
21
22
-
-
-
-
-
-
-
7
8
slast[0:15]
-
-
23
24
slast[16:31]
-
-
9
10
11
12
13
14
15
-
-
-
-
-
-
-
25
26
27
28
29
30
31
-
-
-
-
-
-
-
= Unimplemented
Figure 204. TCDn Word 3 (TCDn.slast) field
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Table 214. TCDn Word 3 (TCDn.slast) field descriptions
Name
Description
Value
slast[0:31]
Last source address adjustment
Adjustment value added to the source address at the
completion of the outer major iteration count.
This value can be applied to “restore” the source
address to the initial value, or adjust the address to
reference the next data structure.
Figure 205 and Table 215 define word 4 of the TCDn structure, the daddr field.
Register address: DMA_Offset + 0x1000 + (32 x n) + 0x10
R
W
RESET:
R
W
RESET:
0
1
2
3
4
5
6
-
-
-
-
-
-
-
16
17
18
19
20
21
22
-
-
-
-
-
-
-
7
8
daddr[0:15]
-
-
23
24
daddr[16:31]
-
-
9
10
11
12
13
14
15
-
-
-
-
-
-
-
25
26
27
28
29
30
31
-
-
-
-
-
-
-
= Unimplemented
Figure 205. TCDn Word 4 (TCDn.daddr) field
Table 215. TCDn Word 4 (TCDn.daddr) field description
Name
Description
Value
daddr[0:31]
Destination address
Memory address pointing to the destination data.
Figure 206 and Table 216 define word 5 of the TCDn structure, the citer and doff fields.
Register address: DMA_Offset + 0x1000 + (32 x n) + 0x14
0
R
citer.
e_link
W
RESET:
-
R
W
RESET:
1
-
2
3
4
5
citer[0:5] or
citer.linkch[0:5]
-
6
7
8
9
10
-
-
-
-
-
-
25
26
-
-
16
17
18
19
20
21
22
-
-
-
-
-
-
-
23
24
doff[16:31]
-
-
11
12
citer[6:14]
13
14
15
-
-
-
-
27
28
29
30
31
-
-
-
-
-
= Unimplemented
Figure 206. TCDn Word 5 (TCDn.{citer,doff}) fields
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Table 216. TCDn Word 5 (TCDn.{doff,citer}) field descriptions
Name
Description
Value
citer.e_link
Enable channel-to-channel linking
on minor loop complete
As the channel completes the inner minor loop, this
flag enables the linking to another channel, defined
by citer.linkch[5:0]. The link target channel initiates a
channel service request via an internal mechanism
that sets the TCD.start bit of the specified channel. If
channel linking is disabled, the citer value is
extended to 15 bits in place of a link channel number.
If the "major" loop is exhausted, this link mechanism
is suppressed in favor of the major.e_link channel
linking. This bit must be equal to the biter.e_link bit
otherwise a configuration error will be reported.
0
1
citer[0:5]
or
citer.linkch[0:5]
Current “major” iteration count
or
Link channel number
The channel-to-channel linking is disabled.
The channel-to-channel linking is enabled.
if (TCD.citer.e_link = 0) then
No channel-to-channel linking (or chaining) is
performed after the inner "minor" loop is exhausted.
TCD word 5, bits [30:25] are used to form a 15 bit citer
field.
else
After the "minor" loop is exhausted, the eDMA engine
initiates a channel service request at the channel
defined by citer.linkch[5:0] by setting that channel’s
TCD.start bit.
The value contained in citer.linkch[5:0] must not
exceed the number of implemented channels.
citer[6:14]
Current “major” iteration count
This 9 or 15-bit count represents the current major
loop count for the channel. It is decremented each
time the minor loop is completed and updated in the
transfer control descriptor memory. Once the major
iteration count is exhausted, the channel performs a
number of operations (e.g., final source and
destination address calculations), optionally
generating an interrupt to signal channel completion
before reloading the citer field from the beginning
iteration count (biter) field.
When the citer field is initially loaded by software, it
must be set to the same value as that contained in the
biter field.
If the channel is configured to execute a single
service request, the initial values of biter and citer
should be 0x0001.
doff[16:31]
Destination address signed offset
Sign-extended offset applied to the current
destination address to form the next-state value as
each destination write is completed.
Figure 207 and Table 217 define word 6 of the TCDn structure, the dlast_sga field.
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Register address: DMA_Offset + 0x1000 + (32 x n) + 0x18
R
W
RESET:
R
W
RESET:
0
1
2
3
4
5
6
-
-
-
-
-
-
-
16
17
18
19
20
21
22
-
-
-
-
-
-
-
7
8
9
dlast_sga[0:15]
-
-
-
23
24
25
dlast_sga[16:31]
-
-
-
10
11
12
13
14
15
-
-
-
-
-
-
26
27
28
29
30
31
-
-
-
-
-
-
= Unimplemented
Figure 207. TCDn Word 6 (TCDn.dlast_sga) field
Table 217. TCDn Word 6 (TCDn.dlast_sga) field description
Name
Description
Value
dlast_sga[31:0 Last destination address adjustment or
if (TCD.e_sg = 0) then
0:31]
the memory address for the next transfer Adjustment value added to the destination address at
control descriptor to be loaded into this
the completion of the outer major iteration count.
channel (scatter/gather)
This value can be applied to “restore” the destination
address to the initial value, or adjust the address to
reference the next data structure.
else
This address points to the beginning of a 0-modulo-32
region containing the next transfer control descriptor to
be loaded into this channel. This channel reload is
performed as the major iteration count completes. The
scatter/gather address must be 0-modulo-32, else a
configuration error is reported.
Figure 208 and Table 218 define word 7 of the TCDn structure, the biter and control/status fields.
Register address: DMA_Offset + 0x1000 + (32 x n) + 0x1c
R
W
RESET:
0
1
2
3
4
5
6
-
-
-
-
-
-
-
-
17
18
19
20
21
22
23
16
R
W
RESET:
bwc
-
7
8
biter[0:15]
major.linkch[0:5]
-
-
-
-
-
9
10
11
12
13
14
15
-
-
-
-
-
-
-
-
24
25
26
27
28
29
30
done active major. e_sg d_req int_ha int_m
e_link
lf
aj
-
-
0
0
-
-
-
-
-
31
start
0
= Unimplemented
Figure 208. TCDn Word 7 (TCDn.{biter,control/status}) fields
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Table 218. TCDn Word 7 (TCDn.{biter, control/status}) field descriptions
Name
Description
Value
biter.e_link
Enable channel-to-channel linking
on minor loop complete
This is the initial value copied into the citer.e_link field
when the major loop is completed. The citer.e_link
field controls channel linking during channel
execution. This bit must be equal to the citer.e_link bit
otherwise a configuration error will be reported.
0
1
biter[0:5]
or
biter.linkch[0:5]
Beginning “major” iteration count
or
Beginning Link channel number
The channel-to-channel linking is disabled.
The channel-to-channel linking is enabled.
This is the initial value copied into the citer field or
citer.linkch field when the major loop is completed.
The citer fields controls the iteration count and linking
during channel execution.
if (TCD.biter.e_link = 0) then
No channel-to-channel linking (or chaining) is
performed after the inner "minor" loop is exhausted.
TCD word 5, bits [30:25] are used to form a 15 bit biter
field.
else
After the "minor" loop is exhausted, the eDMA engine
initiates a channel service request at the channel
defined by biter.linkch[5:0] by setting that channel’s
TCD.start bit.
The value contained in biter.linkch[5:0] must not
exceed the number of implemented channels.
biter[6:14]
Beginning “major” iteration count
This is the initial value copied into the citer field or
citer.linkch field when the major loop is completed.
The citer fields controls the iteration count and linking
during channel execution.
This 9- or 15-bit count represents the beginning major
loop count for the channel. As the major iteration
count is exhausted, the contents of the entire 16-bit
biter entry is reloaded into the 16-bit citer entry.
When the biter field is initially loaded by software, it
must be set to the same value as that contained in the
citer field.
If the channel is configured to execute a single
service request, the initial values of biter and citer
should be 0x0001.
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Table 218. TCDn Word 7 (TCDn.{biter, control/status}) field descriptions (Continued)
Name
Description
Value
bwc[0:1]
Bandwidth control
This two-bit field provides a mechanism to effectively
throttle the amount of bus bandwidth consumed by
the eDMA. In general, as the eDMA processes the
inner minor loop, it continuously generates
read/write, read/write, ... sequences until the minor
count is exhausted. This field forces the eDMA to stall
after the completion of each read/write access to
control the bus request bandwidth seen by the
platform’s cross-bar arbitration switch. To minimize
start-up latency, bandwidth control stalls are
suppressed for the first two AHB bus cycles and after
the last write of each minor loop.
The dynamic priority elevation setting elevates the
priority of the eDMA as seen by the cross-bar
arbitration switch for the executing channel. Dynamic
priority elevation is suppressed during the first two
AHB bus cycles.
00
01
10
11
major.linkch[0:5]
Link channel number
No eDMA engine stalls
Dynamic priority elevation
eDMA engine stalls for 4 cycles after each r/w
eDMA engine stalls for 8 cycles after each r/w
if (TCD.major.e_link = 0) then
No channel-to-channel linking (or chaining) is
performed after the outer "major" loop counter is
exhausted.
else
After the "major" loop counter is exhausted, the
eDMA engine initiates a channel service request at
the channel defined by major.linkch[5:0] by setting
that channel’s TCD.start bit.
The value contained in major.linkch[5:0] must not
exceed the number of implemented channels.
done
Channel done
This flag indicates the eDMA has completed the outer
major loop. It is set by the eDMA engine as the citer
count reaches zero; it is cleared by software, or the
hardware when the channel is activated.
This bit must be cleared in order to write the
major.e_link or e_sg bits.
active
Channel active
This flag signals the channel is currently in execution.
It is set when channel service begins, and is cleared
by the eDMA engine as the inner minor loop
completes or if any error condition is detected.
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Table 218. TCDn Word 7 (TCDn.{biter, control/status}) field descriptions (Continued)
Name
Description
Value
major.e_link
Enable channel-to-channel linking
on major loop complete
As the channel completes the outer major loop, this
flag enables the linking to another channel, defined
by major.linkch[5:0]. The link target channel initiates
a channel service request via an internal mechanism
that sets the TCD.start bit of the specified channel. To
support the dynamic linking coherency model, this
field is forced to zero when written to while the
TCD.done bit is set.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
e_sg
Enable scatter/gather processing
As the channel completes the outer major loop, this
flag enables scatter/gather processing in the current
channel. If enabled, the eDMA engine uses dlast_sga
as a memory pointer to a 0-modulo-32 address
containing a 32-byte data structure which is loaded as
the transfer control descriptor into the local memory.
To support the dynamic scatter/gather coherency
model, this field is forced to zero when written to while
the TCD.done bit is set.
0 The current channel’s TCD is “normal” format.
1 The current channel’s TCD specifies a scatter
gather format. The dlast_sga field provides a
memory pointer to the next TCD to be loaded into
this channel after the outer major loop completes
its execution.
d_req
Disable request
If this flag is set, the eDMA hardware automatically
clears the corresponding DMAERQ bit when the
current major iteration count reaches zero.
0 The channel’s DMAERQ bit is not affected.
1 The channel’s DMAERQ bit is cleared when the
outer major loop is complete.
int_half
Enable an interrupt when major counter If this flag is set, the channel generates an interrupt
is half complete
request by setting the appropriate bit in the DMAINT
register when the current major iteration count
reaches the halfway point. Specifically, the
comparison performed by the eDMA engine is (citer
== (biter >> 1)). This halfway point interrupt request is
provided to support double-buffered schemes or
other types of data movement where the processor
needs an early indication of the transfer’s progress.
0 The half-point interrupt is disabled.
1 The half-point interrupt is enabled.
Note: If biter = 1, do not use int_half; use int_major
instead.
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Table 218. TCDn Word 7 (TCDn.{biter, control/status}) field descriptions (Continued)
Name
int_maj
Description
Value
Enable an interrupt when major iteration If this flag is set, the channel generates an interrupt
count completes
request by setting the appropriate bit in the DMAINT
register when the current major iteration count
reaches zero.
0 The end-of-major loop interrupt is disabled.
1 cThe end-of-major loop interrupt is enabled.
start
Channel start
If this flag is set, the channel is requesting service.
The eDMA hardware automatically clears this flag
after the channel begins execution.
0 The channel is not explicitly started.
1 The channel is explicitly started via a software
initiated service request.
19.3
Functional description
This section provides an overview of the microarchitecture and functional operation of the eDMA module.
19.3.1
eDMA microarchitecture
The eDMA module is partitioned into two major modules: the eDMA engine and the transfer control
descriptor local memory. Additionally, the eDMA engine is further partitioned into four submodules,
which are detailed below.
• eDMA engine
— addr_path: This module implements registered versions of two channel transfer control
descriptors: channel “x” and channel “y”, and is responsible for all the master bus address
calculations. All the implemented channels provide the exact same functionality. This
hardware structure allows the data transfers associated with one channel to be preempted after
the completion of a read/write sequence if a higher priority channel service request is asserted
while the first channel is active. Once a channel is activated, it runs until the minor loop is
completed unless preempted by a higher priority channel. This capability provides a
mechanism (optionally enabled by DCHPRIn[ECP]) where a large data move operation can be
preempted to minimize the time another channel is blocked from execution.
When any other channel is activated, the contents of its transfer control descriptor is read from
the local memory and loaded into the registers of the other addr_path.channel_{x,y}. Once the
inner minor loop completes execution, the addr_path hardware writes the new values for the
TCDn.{saddr, daddr, citer} back into the local memory. If the major iteration count is
exhausted, additional processing is performed, including the final address pointer updates,
reloading the TCDn.citer field, and a possible fetch of the next TCDn from memory as part of
a scatter/gather operation.
— data_path: This module implements the actual bus master read/write datapath. It includes 32
bytes of register storage (matching the maximum transfer size) and the necessary mux logic to
support any required data alignment. The AMBA-AHB read data bus is the primary input, and
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19-419
the AHB write data bus is the primary output.
•
The addr_ and data_path modules directly support the 2-stage pipelined AMBA-AHB bus. The
addr_path module represents the 1st stage of the bus pipeline (the address phase), while the
data_path module implements the 2nd stage of the pipeline (the data phase).
— pmodel_charb: This module implements the first section of eDMA’s programming model as
well as the channel arbitration logic. The programming model registers are connected to the
slave bus (not shown). The ipd_req[n] inputs and dma_ipi_int[n] outputs are also connected to
this module (via the control logic).
— control: This module provides all the control functions for the eDMA engine. For data transfers
where the source and destination sizes are equal, the eDMA engine performs a series of source
read, destination write operations until the number of bytes specified in the inner ‘minor loop’
byte count has been moved. For descriptors where the sizes are not equal, multiple access of
the smaller size data are required for each reference of the larger size. As an example, if the
source size references 16-bit data and the destination is 32-bit data, two reads are performed,
then one 32-bit write.
transfer_control_descriptor local memory
— memory controller: This logic implements the required dual-ported controller, handling
accesses from both the eDMA engine as well as references from the slave bus. As noted earlier,
in the event of simultaneous accesses, the eDMA engine is given priority and the slave bus
transaction is stalled. The hooks to a BIST controller for the local TCD memory are included
in this module.
— memory array: The TCD is implemented using a single-ported, synchronous compiled RAM
memory array
19.3.2
eDMA basic data flow
The basic flow of a data transfer can be partitioned into three segments. As shown in Figure 209, the first
segment involves the channel service request. In the diagram, this example uses the assertion of the
ipd_req[n] signal to request service for channel n. Channel service request via software and the TCDn.start
bit follows the same basic flow as an ipd_req. The ipd_req[n] input signal is registered internally and then
routed to through the eDMA engine, first through the control module, then into the programming
model/channel arbitration (pmodel_charb) module. In the next cycle, the channel arbitration is performed,
either using the fixed-priority or round-robin algorithm. After the arbitration is complete, the activated
channel number is sent through the address path (addr_path) and converted into the required address to
access the TCD local memory. Next, the TCD memory is accessed and the required descriptor read from
the local memory and loaded into the dma_engine.addr_path.channel_{x,y} registers. The TCD memory
is organized 64-bits in width to minimize the time needed to fetch the activated channel’s descriptor and
load it into the dma_engine.addr_path.channel_{x,y} registers.
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DMA
addr
wdata[31:0]
0
j
j+1
SRAM
Transfer
Control
Descriptor (TCD)
n-1
DMA engine
pmodel_charb
hrdata[{63,31}:0]
rdata[31:0]
addr_path
data_path
c
o
n
t
r
o
l
IPS
Bus
hwdata[{63,31}:0]
haddr[31:0]
AMBA
Bus
dma_ipi_int[n-1:0]
dma_ipd_done[n-1:0]
ipd_req[n-1:0]
Figure 209. eDMA operation, part 1
In the second part of the basic data flow as shown in Figure 210, the modules associated with the data
transfer (addr_path, data_path and control) sequence through the required source reads and destination
writes to perform the actual data movement. The source reads are initiated and the fetched data is
temporarily stored in the data_path module until it is gated onto the AMBA-AHB bus during the
destination write. This source read/destination write processing continues until the inner minor byte count
has been transferred. The dma_ipd_done[n] signal is asserted at the end of the minor byte count transfer.
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DMA
addr
wdata[31:0]
0
j
j+1
SRAM
Transfer
Control
Descriptor (TCD)
n-1
DMA engine
hrdata[{63,31}:0]
pmodel_charb
rdata[31:0]
addr_path
data_path
c
o
n
t
r
o
l
IPS
Bus
hwdata[{63,31}:0]
haddr[31:0]
AMBA
Bus
dma_ipi_int[n-1:0]
dma_ipd_done[n-1:0]
ipd_req[n-1:0]
Figure 210. eDMA operation, part 2
Once the inner minor byte count has been moved, the final phase of the basic data flow is performed. In
this segment, the addr_path logic performs the required updates to certain fields in the channel’s TCD, e.g.,
saddr, daddr, citer. If the outer major iteration count is exhausted, then there are additional operations
which are performed. These include the final address adjustments and reloading of the biter field into the
citer. Additionally, assertion of an optional interrupt request occurs at this time, as does a possible fetch of
a new TCD from memory using the scatter/gather address pointer included in the descriptor. The updates
to the TCD memory and the assertion of an interrupt request are shown in Figure 211.
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DMA
addr
wdata[31:0]
0
j
j+1
SRAM
Transfer
Control
Descriptor (TCD)
n-1
DMA engine
pmodel_charb
hrdata[{63,31}:0]
rdata[31:0]
addr_path
data_path
c
o
n
t
r
o
l
IPS
Bus
hwdata[{63,31}:0]
haddr[31:0]
AMBA
Bus
dma_ipi_int[n-1:0]
dma_ipd_done[n-1:0]
ipd_req[n-1:0]
Figure 211. eDMA operation, part 3
19.4
19.4.1
Initialization/application information
eDMA initialization
A typical initialization of the eDMA is:
1. Write the DMACR register if a configuration other than the default is desired.
2. Write the channel priority levels into the DCHPRIn registers if a configuration other than the
default is desired.
3. Enable error interrupts in the DMAEEI registers if so desired.
4. Write the 32 byte TCD for each channel that may request service.
5. Enable any hardware service requests via the DMAERQ register.
6. Request channel service by either software (setting the TCD.start bit) or by hardware (slave device
asserting its ipd_req signal).
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After any channel requests service, a channel is selected for execution based on the arbitration and priority
levels written into the programmer's model. The eDMA engine will read the entire TCD for the selected
channel into its internal address path module. As the TCD is being read, the first transfer is initiated on the
AHB bus unless a configuration error is detected. Transfers from the source (as defined by the source
address, TCD.saddr) to the destination (as defined by the destination address, TCD.daddr) continue until
the specified number of bytes (TCD.nbytes) have been transferred. When the transfer is complete, the
eDMA engine's local TCD.saddr, TCD.daddr, and TCD.citer are written back to the main TCD memory
and any minor loop channel linking is performed, if enabled. If the major loop is exhausted, further post
processing is executed, i.e. interrupts, major loop channel linking, and scatter/gather operations, if enabled.
19.4.2
eDMA programming errors
The eDMA performs various tests on the Transfer Control Descriptor to verify consistency in the
descriptor data. Most programming errors are reported on a per channel basis with the exception of two
errors; Group Priority Error and Channel Priority Error, GPE and CPE in the DMAES register respectively.
For all error types other than Group or Channel Priority Errors, the channel number causing the error is
recorded in the DMAES register. If the error source is not removed before the next activation of the
problem channel, the error will be detected and recorded again.
The sequence listed below is correct. For item 2, the dma_ipd_ack{done} lines will assert only if the
selected channel is requesting service via the ipd_req signal. I think the typical application will enable error
interrupts for all channels. So the user will get an error interrupt, but the channel number for the DMAERR
register and the error interrupt request line may be wrong because they reflect the selected channel.
Channel priority errors are identified within a group after that group has been selected as the active group.
For example:
1. The eDMA is configured for fixed group and fixed channel arbitration modes.
2. Group3 is the highest priority and all channels are unique in that group.
3. Group2 is the next highest priority and has two channels with the same priority level.
4. If Group3 has any service requests, those requests will be executed.
5. Once all of Group3 requests have completed, Group2 will be the next active group.
6. If Group2 has a service request, then an undefined channel in Group2 will be selected and a channel
priority error will occur.
7. This will repeat until the all of Group2 requests have been removed or a higher priority Group3
request comes in.
A group priority error is global and any request in any group will cause a group priority error.
In general, if priority levels are not unique, the highest (channel/group) priority that has an active request
will be selected, but the lowest numbered (channel/group) with that priority will be selected by arbitration
and executed by the eDMA engine. The hardware service request handshake signals, error interrupts and
error reporting will be associated with the selected channel.
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19.4.3
19.4.3.1
eDMA arbitration mode considerations
Fixed group arbitration, fixed channel arbitration
In this mode, the channel service request from the highest priority channel in the highest priority group
will be selected to execute. If the eDMA is programmed so the channels within one group use “fixed”
priorities, and that group is assigned the highest “fixed” priority of all groups, it is possible for that group
to take all the bandwidth of the eDMA controller — i.e. no other groups will be serviced if there is always
at least one eDMA request pending on a channel in the highest priority group when the controller arbitrates
the next eDMA request.
The advantage of this scenario is that latency can be small for channels that need to be serviced quickly.
Preemption is available in this scenario only.
19.4.3.2
Round-robin group arbitration, fixed channel arbitration
The occurrence of one or more eDMA requests from one or more groups, the channel with the highest
priority from a specific group will be serviced first. Groups are serviced starting with the highest group
number with an service request and rotating through to the lowest group number containing a service
request.
Once the channel request is serviced, the group round robin algorithm will select the highest pending
request from the next group in the round robin sequence. Servicing continues round robin, always
servicing the highest priority channel in the next group in the sequence, or just skipping a group if it has
no pending requests.
If a channel requests service at a rate that equals or exceeds the round robin service rate, then that channel
will always be serviced before lower priority channels in the same group, and thus the lower priority
channels will never be serviced.
The advantage of this scenario is that no one group uses all the eDMA bandwidth.
The highest priority channel selection latency is potentially greater than fixed/fixed arbitration.
Excessive request rates on high priority channels can prevent the servicing of lower priority channels in
the same group.
19.4.3.3
Round-robin group arbitration, round-robin channel arbitration
Groups will be serviced as described in Section 19.4.3.2, Round-robin group arbitration, fixed channel
arbitration, but this time channels will be serviced in channel number order. Only one channel is serviced
from each requesting group for each round robin pass through the groups.
Within each group, channels are serviced starting with the highest channel number and rotating through to
the lowest channel number without regard to channel priority levels.
Because channels are serviced in round robin manner, any channel that generates eDMA requests faster
than a combination of the group round robin service rate and the channel service rate for its group will not
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prevent the servicing of other channels in its group. Any eDMA requests that are not serviced are simply
lost, but at least one channel will be serviced.
This scenario ensures that all channels will be guaranteed service at some point, regardless of the request
rates. However, the potential latency could be quite high.
All channels are treated equally. Priority levels are not used in round robin/round robin mode.
19.4.3.4
Fixed group arbitration, round-robin channel arbitration
The highest priority group with a request will be serviced. Lower priority groups will be serviced if no
pending requests exist in the higher priority groups.
Within each group, channels are serviced starting with the highest channel number and rotating through to
the lowest channel number without regard to the channel priority levels assigned within the group.
This scenario could cause the same bandwidth consumption problem as indicated in Section 19.4.3.1,
Fixed group arbitration, fixed channel arbitration, but all the channels in the highest priority group will be
serviced.
Service latency will be short on the highest priority group, but can become much longer as the group
priority decreases.
19.4.4
eDMA transfer
19.4.4.1
Single request
To perform a simply transfer of ‘n’ bytes of data with one activation, set the major loop to one (TCD.citer
= TCD.biter = 1). The data transfer will begin after the channel service request is acknowledged and the
channel is selected to execute. Once the transfer is complete, the TCD.done bit will be set and an interrupt
will be generated if properly enabled.
For example, the following TCD entry is configured to transfer 16 bytes of data. The eDMA is
programmed for one iteration of the major loop transferring 16 bytes per iteration. The source memory has
a byte wide memory port located at 0x1000. The destination memory has a word wide port located at
0x2000. The address offsets are programmed in increments to match the size of the transfer; one byte for
the source and four bytes for the destination. The final source and destination addresses are adjusted to
return to their beginning values.
TCD.citer
= TCD.biter = 1
TCD.nbytes
= 16
TCD.saddr
= 0x1000
TCD.soff
=1
TCD.ssize
=0
TCD.slast
= -16
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TCD.daddr
= 0x2000
TCD.doff
=4
TCD.dsize
=2
TCD.dlast_sga= -16
TCD.int_maj = 1
TCD.start
= 1 (TCD.word7 should be written last after all other fields have been initialized)
All other TCD fields = 0
This generates the following sequence of events:
1. slave bus write to the TCD.start bit requests channel service
2. The channel is selected by arbitration for servicing
3. eDMA engine writes: TCD.done = 0, TCD.start = 0, TCD.active = 1
4. eDMA engine reads: channel TCD data from local memory to internal register file
5. The source to destination transfers are executed as follows:
a. read_byte(0x1000), read_byte(0x1001), read_byte(0x1002), read_byte(0x1003)
b.
write_word(0x2000) -> first iteration of the minor loop
c.
read_byte(0x1004), read_byte(0x1005), read_byte(0x1006), read_byte(0x1007)
d.
write_word(0x2004) -> second iteration of the minor loop
e.
read_byte(0x1008), read_byte(0x1009), read_byte(0x100a), read_byte(0x100b)
f.
write_word(0x2008) -> third iteration of the minor loop
g.
read_byte(0x100c), read_byte(0x100d), read_byte(0x100e), read_byte(0x100f)
h.
write_word(0x200c) -> last iteration of the minor loop -> major loop complete
6. eDMA engine writes: TCD.saddr = 0x1000, TCD.daddr = 0x2000, TCD.citer = 1 (TCD.biter)
7. eDMA engine writes: TCD.active = 0, TCD.done = 1, DMAINT[n] = 1
8. The channel retires
The eDMA goes idle or services next channel.
19.4.4.2
Multiple requests
The next example is the same as the previous example, with the exception of transferring 32 bytes via two
hardware requests. The only fields that change are the major loop iteration count and the final address
offsets. The DMAis programmed for two iterations of the major loop transferring 16 bytes per iteration.
After the channel’s hardware requests is enabled in the DMAERQ register, channel service requests are
initiated by the slave device.
TCD.citer
= TCD.biter = 2
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TCD.slast
= -32
TCD.dlast_sga = -32
This would generate the following sequence of events:
1. First hardware (ipd_req) request for channel service
2. The channel is selected by arbitration for servicing
3. eDMA engine writes: TCD.done = 0, TCD.start = 0, TCD.active = 1
4. eDMA engine reads: channel TCD data from local memory to internal register file
5. The source to destination transfers are executed as follows:
a. read_byte(0x1000), read_byte(0x1001), read_byte(0x1002), read_byte(0x1003)
b.
write_word(0x2000) -> first iteration of the minor loop
c.
read_byte(0x1004), read_byte(0x1005), read_byte(0x1006), read_byte(0x1007)
d.
write_word(0x2004) -> second iteration of the minor loop
e.
read_byte(0x1008), read_byte(0x1009), read_byte(0x100a), read_byte(0x100b)
f.
write_word(0x2008) -> third iteration of the minor loop
g.
read_byte(0x100c), read_byte(0x100d), read_byte(0x100e), read_byte(0x100f)
h.
write_word(0x200c) -> last iteration of the minor loop
6. eDMA engine writes: TCD.saddr = 0x1010, TCD.daddr = 0x2010, TCD.citer = 1
7. eDMA engine writes: TCD.active = 0
8. The channel retires -> one iteration of the major loop
The eDMA goes idle or services next channel.
9. Second hardware (ipd_req) requests channel service
10. The channel is selected by arbitration for servicing
11. eDMA engine writes: TCD.done = 0, TCD.start = 0, TCD.active = 1
12. eDMA engine reads: channel TCD data from local memory to internal register file
13. The source to destination transfers are executed as follows:
a. read_byte(0x1010), read_byte(0x1011), read_byte(0x1012), read_byte(0x1013)
b.
write_word(0x2010) -> first iteration of the minor loop
c.
read_byte(0x1014), read_byte(0x1015), read_byte(0x1016), read_byte(0x1017)
d.
write_word(0x2014) -> second iteration of the minor loop
e.
read_byte(0x1018), read_byte(0x1019), read_byte(0x101a), read_byte(0x101b)
f.
write_word(0x2018) -> third iteration of the minor loop
g.
read_byte(0x101c), read_byte(0x101d), read_byte(0x101e), read_byte(0x101f)
h.
write_word(0x201c) -> last iteration of the minor loop -> major loop complete
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14. eDMA engine writes: TCD.saddr = 0x1000, TCD.daddr = 0x2000, TCD.citer = 2 (TCD.biter)
15. eDMA engine writes: TCD.active = 0, TCD.done = 1, DMAINT[n] = 1
16. The channel retires -> major loop complete
The eDMA goes idle or services the next channel.
19.4.5
19.4.5.1
TCD status
Minor loop complete
There are two methods to test for minor loop completion when using software initiated service requests.
The first method is to read the TCD.citer field and test for a change. Another method may be extracted
from the sequence shown below. The second method is to test the TCD.start bit AND the TCD.active bit.
The minor loop complete condition is indicated by both bits reading zero after the TCD.start was written
to a one. Polling the TCD.active bit may be inconclusive because the active status may be missed if the
channel execution is short in duration.
The TCD status bits execute the following sequence for a software activated channel:
1. TCD.start = 1, TCD.active = 0, TCD.done = 0 (channel service request via software)
2. TCD.start = 0, TCD.active = 1, TCD.done = 0 (channel is executing)
3. TCD.start = 0, TCD.active = 0, TCD.done = 0 (channel has completed the minor loop and is idle)
or
TCD.start = 0, TCD.active = 0, TCD.done = 1 (channel has completed the major loop and is idle)
The best method to test for minor loop completion when using hardware initiated service requests is to
read the TCD.citer field and test for a change. The hardware request and acknowledge handshakes signals
are not visible in the programmer’s model.
The TCD status bits execute the following sequence for a hardware activated channel:
1. ipd_req asserts (channel service request via hardware)
2. TCD.start = 0, TCD.active = 1, TCD.done = 0 (channel is executing)
3. TCD.start = 0, TCD.active = 0, TCD.done = 0 (channel has completed the minor loop and is idle)
or
TCD.start = 0, TCD.active = 0, TCD.done = 1 (channel has completed the major loop and is idle)
For both activation types, the major loop complete status is explicitly indicated via the TCD.done bit.
The TCD.start bit is cleared automatically when the channel begins execution regardless of how the
channel was activated.
19.4.5.2
Active channel TCD reads
The eDMA will read back the ‘true’ TCD.saddr, TCD.daddr, and TCD.nbytes values if read while a
channel is executing. The ‘true’ values of the saddr, daddr, and nbytes are the values the eDMA engine is
currently using in its internal register file and not the values in the TCD local memory for that channel.
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The addresses (saddr and daddr) and nbytes (decrements to zero as the transfer progresses) can give an
indication of the progress of the transfer. All other values are read back from the TCD local memory.
19.4.5.3
Preemption status
Preemption is only available when fixed arbitration is selected for both group and channel arbitration
modes. A preempt-able situation is one in which a preempt-enabled channel is running and a higher
priority request becomes active. When the eDMA engine is not operating in fixed group, fixed channel
arbitration mode, the determination of the relative priority of the actively running and the outstanding
requests become undefined. Channel and/or group priorities are treated as equal (constantly rotating) when
round-robin arbitration mode is selected.
The TCD.active bit for the preempted channel remains asserted throughout the preemption. The preempted
channel is temporarily suspended while the preempting channel executes one iteration of the major loop.
Two TCD.active bits set at the same time in the overall TCD map indicates a higher priority channel is
actively preempting a lower priority channel.
The worst case latency when switching to a preempt channel is the summation of:
• arbitration latency (2 cycles)
• bandwidth control stalls (if enabled)
• the time to execute two read/write sequences (including AHB bus holds; a system dependency
driven by the slave devices or the crossbar)
19.4.6
Channel linking
Channel linking (or chaining) is a mechanism where one channel sets the TCD.start bit of another channel
(or itself) thus initiating a service request for that channel. This operation is automatically performed by
the eDMA engine at the conclusion of the major or minor loop when properly enabled.
The minor loop channel linking occurs at the completion of the minor loop (or one iteration of the major
loop). The TCD.citer.e_link field are used to determine whether a minor loop link is requested. When
enabled, the channel link is made after each iteration of the major loop except for the last. When the major
loop is exhausted, only the major loop channel link fields are used to determine if a channel link should be
made. For example, with the initial fields of:
TCD.citer.e_link = 1
TCD.citer.linkch = 0xC
TCD.citer value
= 0x4
TCD.major.e_link = 1
TCD.major.linkch = 0x7
will execute as:
1. minor loop done -> set channel 12 TCD.start bit
2. minor loop done -> set channel 12 TCD.start bit
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3. minor loop done -> set channel 12 TCD.start bit
4. minor loop done, major loop done -> set channel 7 TCD.start bit
When minor loop linking is enabled (TCD.citer.e_link = 1), the TCD.citer field uses a nine bit vector to
form the current iteration count.
When minor loop linking is disabled (TCD.citer.e_link = 0), the TCD.citer field uses a 15 bit vector to form
the current iteration count. The bits associated with the TCD.citer.linkch field are concatenated onto the
citer value to increase the range of the citer.
NOTE
The TCD.citer.e_link bit and the TCD.biter.e_link bit must equal or a
configuration error will be reported. The citer and biter vector widths must
be equal to calculate the major loop, half-way done interrupt point.
19.4.7
19.4.7.1
Dynamic programming
Dynamic priority changing
The following two options are recommended for dynamically changing channel priority levels:
1. Switch to round-robin channel arbitration mode, change the channel priorities, then switch back to
fixed arbitration mode.
2. Disable all the channels within a group, then change the channel priorities within that group only,
then enable the appropriate channels.
The following two options are available for dynamically changing group priority levels:
1. Switch to round-robin group arbitration mode, change the group priorities, then switch back to
fixed arbitration mode.
2. Disable all channels, change the group priorities, then enable the appropriate channels.
19.4.7.2
Dynamic channel linking
Dynamic channel linking is the process of setting the TCD.major.e_link bit during channel execution. This
bit is read from the TCD local memory at the end of channel execution, thus allowing the user to enable
the feature during channel execution.
Because the user is allowed to change the configuration during execution, a coherency model is needed.
Consider the scenario where the user attempts to execute a dynamic channel link by enabling the
TCD.major.e_link bit at the same time the eDMA engine is retiring the channel. The TCD.major.e_link
would be set in the programmer’s model, but it would be unclear whether the actual link was made before
the channel retired.
The coherency model in Table 219 is recommended when executing a dynamic channel link request.
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Table 219. Coherency model for a dynamic channel link request
Step
Action
1
Write 1b to the TCD.major.e_link bit.
2
Read back the TCD.major.e_link bit.
3
Test the TCD.major.e_link request status:
• If TCD.major.e_link = 1b, the dynamic link attempt was successful.
• If TCD.major.e_link = 0b, the attempted dynamic link did not succeed (the channel was
already retiring).
For this request, the TCD local memory controller forces the TCD.major.e_link bit to zero on any writes
to a channel’s TCD.word7 after that channel’s TCD.done bit is set, indicating the major loop is complete.
NOTE
The user must clear the TCD.done bit before writing the TCD.major.e_link
bit. The TCD.done bit is cleared automatically by the eDMA engine after a
channel begins execution.
19.4.7.3
Dynamic scatter/gather
Dynamic scatter/gather is the process of setting the TCD.e_sg bit during channel execution. This bit is read
from the TCD local memory at the end of channel execution, thus allowing the user to enable the feature
during channel execution.
Because the user is allowed to change the configuration during execution, a coherency model is needed.
Consider the scenario where the user attempts to execute a dynamic scatter/gather operation by enabling
the TCD.e_sg bit at the same time the eDMA engine is retiring the channel. The TCD.e_sg would be set
in the programmer’s model, but it would be unclear whether the actual scatter/gather request was honored
before the channel retired.
Two methods for this coherency model are shown in the following subsections. Method 1 has the
advantage of reading the major.linkch field and the e_sg bit with a single read. For both dynamic channel
linking and scatter/gather requests, the TCD local memory controller forces the TCD.major.e_link and
TCD.e_sg bits to zero on any writes to a channel’s TCD.word7 if that channel’s TCD.done bit is set
indicating the major loop is complete.
NOTE
The user must clear the TCD.done bit before writing the TCD.major.e_link
or TCD.e_sg bits. The TCD.done bit is cleared automatically by the eDMA
engine after a channel begins execution.
19.4.7.3.1
Method 1 (channel not using major loop channel linking)
For a channel not using major loop channel linking, the coherency model in Table 220 may be used for a
dynamic scatter/gather request.
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When the TCD.major.e_link bit is zero, the TCD.major.linkch field is not used by the eDMA. In this case,
the TCD.major.linkch bits may be used for other purposes. This method uses the TCD.major.linkch field
as a TCD indentification (ID).
Table 220. Coherency model for method 1
19.4.7.3.2
Step
Action
1
When the descriptors are built, write a unique TCD ID in the TCD.major.linkch field for each
TCD associated with a channel using dynamic scatter/gather.
2
Write 1b to theTCD.d_req bit.
Note: Should a dynamic scatter/gather attempt fail, setting the d_req bit will prevent a future
hardware activation of this channel. This stops the channel from executing with a
destination address (daddr) that was calculated using a scatter/gather address
(written in the next step) instead of a dlast final offest value.
3
Write theTCD.dlast_sga field with the scatter/gather address.
4
Write 1b to the TCD.e_sg bit.
5
Read back the 16 bit TCD control/status field.
6
Test the TCD.e_sg request status and TCD.major.linkch value:
• If e_sg = 1b, the dynamic link attempt was successful.
• If e_sg = 0b and the major.linkch (ID) did not change, the attempted dynamic link did not
succeed (the channel was already retiring).
• If e_sg = 0b and the major.linkch (ID) changed, the dynamic link attempt was successful
(the new TCD’s e_sg value cleared the e_sg bit).
Method 2 (channel using major loop linking)
For a channel using major loop channel linking, the coherency model in Table 221 may be used for a
dynamic scatter/gather request. This method uses the TCD.dlast_sga field as a TCD indentification (ID).
Table 221. Coherency model for method 2
Step
Action
1
Write 1b to theTCD.d_req bit.
Note: Should a dynamic scatter/gather attempt fail, setting the d_req bit will prevent a future
hardware activation of this channel. This stops the channel from executing with a
destination address (daddr) that was calculated using a scatter/gather address
(written in the next step) instead of a dlast final offest value.
2
Write theTCD.dlast_sga field with the scatter/gather address.
3
Write 1b to the TCD.e_sg bit.
4
Read back the TCD.e_sg bit.
5
Test the TCD.e_sg request status:
• If e_sg = 1b, the dynamic link attempt was successful.
• If e_sg = 0b, read the 32 bit TCD dlast_sga field.
• If e_sg = 0b and the dlast_sga did not change, the attempted dynamic link did not
succeed (the channel was already retiring).
• If e_sg = 0b and the dlast_sga changed, the dynamic link attempt was successful (the
new TCD’s e_sg value cleared the e_sg bit).
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19.4.8
Hardware request release timing
This section provides a timing diagram for deasserting the ipd_req hardware request signal. Figure 212
shows two read write sequences with grey indicating the release of the ipd_req hardware request signal.
hclk
htrans
AHB_AP
AHB_DP
rd1
wr1
rd2
wr2
rd1
wr1
rd2
wr2
hwrite
ipd_req
ipd_ack
ipd_done
done_lw
ipd_complete
Note: ipd_req must de-assert in this cycle unless another service request is intended
Figure 212. ipd_req hardware handshake
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Chapter 20
DMACHMUX
20.1
20.1.1
Introduction
Overview
The DMA Mux allows to route 21 DMA peripheral sources (called slots) to 16 DMA channels. This is
illustrated in Figure 213.
Source #1
DMA_CH_MUX
DMA Channel #0
DMA Channel #1
Source #2
Source #3
Source #21
Always #1
Always #9
Trigger #1
DMA Channel
Trigger #4
Figure 213. DMA Mux Block Diagram
20.1.2
Features
The DMA Channel Mux provides these features:
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DMACHMUX
•
•
21 peripheral slots + 9 always-on slots can be routed to 16 channels
16 independently selectable DMA channels routers
— the first 4 channels additionally provide a trigger functionality
Each channel router can be assigned to one of 21 possible peripheral DMA slots or to one of the 9
always-on slots.
•
20.1.3
Modes of Operation
The following operation modes are available:
• Disabled Mode
In this mode, the DMA channel is disabled. Since disabling and enabling of DMA channels is done
primarily via the DMA configuration registers, this mode is used mainly as the reset state for a
DMA channel in the DMA Channel Mux. It may also be used to temporarily suspend a DMA
channel while reconfiguration of the system takes place (e.g. changing the period of a DMA
trigger).
• Normal Mode
In this mode, a DMA source (such as DSPI transmit or DSPI receive for example) is routed directly
to the specified DMA channel. The operation of the DMA Mux in this mode is completely
transparent to the system.
• Periodic Trigger Mode
In this mode, a DMA source may only request a DMA transfer (such as when a transmit buffer
becomes empty or a receive buffer becomes full) periodically. Configuration of the period is done
in the registers of the Periodic Interrupt Timer (PIT). This mode is only available for channels 0-4.
20.2
20.2.1
External Signal Description
Overview
The DMA Mux has no external pins.
20.3
Memory Map and Register Definition
This section provides a detailed description of all memory-mapped registers in the DMA Mux.
Table 222 shows the memory map for the DMA Mux. Note that all addresses are offsets; the absolute
address may be computed by adding the specified offset to the base address of the DMA Mux.
Table 222. DMA_MUX memory map
Offset from
DMA_MUX_BASE
(0xFFFD_C000)
Register
Access
Reset value
Location
0x00
Channel #0 Configuration (CHCONFIG0)
R/W
0x00
on page 437
0x01
Channel #1 Configuration (CHCONFIG1)
R/W
0x00
on page 437
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DMACHMUX
Table 222. DMA_MUX memory map (continued)
Offset from
DMA_MUX_BASE
(0xFFFD_C000)
Register
Access
Reset value
Location
0x02
Channel #2 Configuration (CHCONFIG2)
R/W
0x00
on page 437
0x03
Channel #3 Configuration (CHCONFIG3)
R/W
0x00
on page 437
0x04
Channel #4 Configuration (CHCONFIG4)
R/W
0x00
on page 437
0x05
Channel #5 Configuration (CHCONFIG5)
R/W
0x00
on page 437
0x06
Channel #6 Configuration (CHCONFIG6)
R/W
0x00
on page 437
0x07
Channel #7 Configuration (CHCONFIG7)
R/W
0x00
on page 437
0x08
Channel #8 Configuration (CHCONFIG8)
R/W
0x00
on page 437
0x09
Channel #9 Configuration (CHCONFIG9)
R/W
0x00
on page 437
0x0A
Channel #10 Configuration (CHCONFIG10)
R/W
0x00
on page 437
0x0B
Channel #11 Configuration (CHCONFIG11)
R/W
0x00
on page 437
0x0C
Channel #12 Configuration (CHCONFIG12)
R/W
0x00
on page 437
0x0D
Channel #13 Configuration (CHCONFIG13)
R/W
0x00
on page 437
0x0E
Channel #14 Configuration (CHCONFIG14)
R/W
0x00
on page 437
0x0F
Channel #15 Configuration (CHCONFIG15)
R/W
0x00
on page 437
0x001F–0x3FFF
Reserved
All registers are accessible via 8-bit, 16-bit or 32-bit accesses. However, 16-bit accesses must be aligned
to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example,
CHCONFIG0 through CHCONFIG3 are accessible by a 32-bit READ/WRITE to address ‘Base + 0x00’,
but performing a 32-bit access to address ‘Base + 0x01’ is illegal.
20.3.1
Register Descriptions
The following memory-mapped registers are available in the DMA Channel Mux.
20.3.1.1
Channel Configuration Registers
Each of the DMA channels can be independently enabled/disabled and associated with one of the DMA
slots (peripheral slots or always-on slots) in the system.
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DMACHMUX
Address: Base + #n
Access: User read/write
0
1
2
ENBL
TRIG
0
0
R
3
4
5
6
7
0
0
0
SOURCE
W
Reset
0
0
0
0
Figure 214. Channel Configuration Registers (CHCONFIG#n)
Table 223. CHCONFIGxx Field Descriptions
Field
Description
0
ENBL
DMA Channel Enable. ENBL enables the DMA Channel
0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA
has separate channel enables/disables, which should be used to disable or re-configure a DMA
channel.
1 DMA channel is enabled
1
TRIG
DMA Channel Trigger Enable (for triggered channels only). TRIG enables the periodic trigger capability
for the DMA Channel
0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply
route the specified source to the DMA channel.
1 Triggering is enabled
3–7
SOURCE
DMA Channel Source (slot). SOURCE specifies which DMA source, if any, is routed to a particular DMA
channel.
Table 224. Channel and Trigger Enabling
ENBL
TRIG
Function
Mode
0
X
DMA Channel is disabled
Disabled Mode
1
0
DMA Channel is enabled with no triggering (transparent)
Normal Mode
1
1
DMA Channel is enabled with triggering
Periodic Trigger Mode
NOTE
Setting multiple CHCONFIG registers with the same Source value will
result in unpredictable behavior.
NOTE
Before changing the trigger or source settings a DMA channel must be
disabled via the CHCONFIG[#n].ENBL bit.
20.4
DMA request mapping
This sections defines the integration of the DMA channel multiplexer. Table 225, shows which modules
are connected to which DMA multiplexer slot. Table 226 shows the trigger inputs.
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DMACHMUX
Table 225. DMA channel mapping
DMA
Requesting
Module
DMA
Channel
Resource
Module
1
DSPI_TFFF
DSPI 0
DSPI_0 TX
DMA MUX Source #1
2
DSPI_RFDF
DSPI 0
DSPI_0 RX
DMA MUX Source #2
3
DSPI_TFFF
DSPI 1
DSPI_1 TX
DMA MUX Source #3
4
DSPI_RFDF
DSPI 1
DSPI_1 RX
DMA MUX Source #4
5
DSPI_TFFF
DSPI 2
DSPI_2 TX
DMA MUX Source #5
6
DSPI_RFDF
DSPI 2
DSPI_2 RX
DMA MUX Source #6
8
SAI_TFIFO
SAI_0
SAI_TX
DMA MUX Source #8
9
SAI_RFIFO
SAI_0
SAI_RX
DMA MUX Source #9
10
SAI_TFIFO
SAI_1
SAI_TX
DMA MUX Source #10
11
SAI_RFIFO
SAI_1
SAI_RX
DMA MUX Source #11
12
SAI_TFIFO
SAI_2
SAI_TX
DMA MUX Source #12
13
SAI_RFIFO
SAI_2
SAI_RX
DMA MUX Source #13
16
channel0
etimer0
eTimer_0 CH1
DMA MUX Source #16
17
channel1
etimer0
eTimer_0 CH2
DMA MUX Source #17
20
DMA
adc0
ADC_0
DMA MUX Source #20
21
Always requestor
—
—
—
22
Always requestor
—
—
—
23
Always requestor
—
—
—
24
Always requestor
—
—
—
25
Always requestor
—
—
—
26
Always requestor
—
—
—
27
Always requestor
—
—
—
28
Always requestor
—
—
—
29
Always requestor
—
—
—
30
Always requestor
—
—
—
DMA Mux Input
.
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DMACHMUX
<
Table 226. DMA Trigger Mapping
DMACHMUX
Channel Trigger
Source Module
0
PIT
Trigger Channel 0
1
PIT
Trigger Channel 1
2
PIT
Trigger Channel 2
3
PIT
Trigger Channel 3
Source Signal
The triggers can be used to gate the request signals from the individual IP modules. Using the periodic
timer impulses limits the peak bandwidth of an individual DMA channel, to prevent delay of other
transactions.
20.5
Functional Description
This section provides a functional description of the DMA Mux. The primary purpose of the DMA Mux
is to provide flexibility in the system’s use of the available DMA channels. As such, configuration of the
DMA Mux is intended to be a static procedure done during execution of the system boot code. However,
if the procedure outlined in Section 20.6.2, “Enabling and Configuring Sources” is followed, the
configuration of the DMA MUX may be changed during the normal operation of the system.
Functionally, the DMA Mux channels may be divided into two classes: Channels, which implement the
normal routing functionality plus periodic triggering capability, and channels, which implement only the
normal routing functionality.
20.5.1
DMA Channels with periodic triggering capability
Besides the normal routing functionality, the first 4 channels of the DMA Mux provide a special periodic
triggering capability that can be used to provide an automatic mechanism to transmit bytes, frames or
packets at fixed intervals without the need for processor intervention. The trigger is generated by the
Periodic Interrupt Timer (PIT); as such, the configuration of the periodic triggering interval is done via
configuration registers in the PIT. Please refer to the Periodic Interrupt Timer Block Guide for more
information on this topic.
NOTE
Because of the dynamic nature of the system (i.e. DMA channel priorities,
bus arbitration, interrupt service routine lengths, etc.), the number of clock
cycles between a trigger and the actual DMA transfer cannot be guaranteed.
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DMACHMUX
Source #1
Source #2
Source #3
Trigger #1
DMA Channel #0
Trigger #2
Source #21
Trigger #4
Always #1
DMA Channel #3
Always #9
Figure 215. DMA Mux triggered channels
The DMA channel triggering capability allows the system to “schedule” regular DMA transfers, usually
on the transmit side of certain peripherals, without the intervention of the processor. This trigger works by
gating the request from the Peripheral to the DMA until a trigger event has been seen. This is illustrated
in Figure 216.
Periph Request
Trigger
DMA Request
Figure 216. DMA Mux Channel Triggering: Normal Operation
Once the DMA request has been serviced, the peripheral will negate its request, effectively resetting the
gating mechanism until the peripheral re-asserts its request AND the next trigger event is seen. This means
that if a trigger is seen, but the peripheral is not requesting a transfer, that trigger will be ignored. This
situation is illustrated in Figure 217.
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DMACHMUX
Periph Request
Trigger
DMA Request
Figure 217. DMA Mux Channel Triggering: Ignored Trigger
This triggering capability may be used with any peripheral that supports DMA transfers, and is most useful
for two types of situations:
• Periodically polling external devices on a particular bus. As an example, the transmit side of an SPI
is assigned to a DMA channel with a trigger, as described above. Once setup, the SPI will request
DMA transfers (presumably from memory) as long as its transmit buffer is empty. By using a
trigger on this channel, the SPI transfers can be automatically performed every 5μs (as an
example). On the receive side of the SPI, the SPI and DMA can be configured to transfer receive
data into memory, effectively implementing a method to periodically read data from external
devices and transfer the results into memory without processor intervention.
• Using the GPIO Ports to drive or sample waveforms. By configuring the DMA to transfer data to
one or more GPIO ports, it is possible to create complex waveforms using tabular data stored in
on-chip memory. Conversely, using the DMA to periodically transfer data from one or more GPIO
ports, it is possible to sample complex waveforms and store the results in tabular form in on-chip
memory.
A more detailed description of the capability of each trigger (i.e.-resolution, range of values, etc.) may be
found in the Periodic Interrupt Timer (PIT) Block Guide.
20.5.2
DMA Channels with no triggering capability
The other channels of the DMA Mux provide the normal routing functionality as described in
Section 20.1.3, “Modes of Operation”.
20.5.3
"Always Enabled" DMA Sources
In addition to the peripherals that can be used as DMA sources, there are 9 additional DMA sources that
are "always enabled". Unlike the peripheral DMA sources, where the peripheral controls the flow of data
during DMA transfers, the "always enabled" sources provide no such "throttling" of the data transfers.
These sources are most useful in the following cases:
• Doing DMA transfers to/from GPIO - Moving data from/to one or more GPIO pins, either
un-throttled (i.e.-as fast as possible), or periodically (using the DMA triggering capability).
• Doing DMA transfers from memory to memory - Moving data from memory to memory, typically
as fast as possible, sometimes with software activation.
• Doing DMA transfers from memory to the external bus (or vice-versa) - Similar to memory to
memory transfers, this is typically done as quickly as possible.
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DMACHMUX
•
Any DMA transfer that requires software activation - Any DMA transfer that should be explicitly
started by software.
In cases where software should initiate the start of a DMA transfer, a "always enabled" DMA source can
be used to provide maximum flexibility. When activating a DMA channel via software, subsequent
executions of the minor loop require a new "start" event be sent. This can either be a new software
activation, or a transfer request from the DMA Channel Mux. The options for doing this are:
• Transfer all data in a single minor loop. By configuring the DMA to transfer all of the data in a
single minor loop (i.e.-major loop counter = 1), no re-activation of the channel is necessary. The
disadvantage to this option is the reduced granularity in determining the load that the DMA transfer
will incur on the system. For this option, the DMA channel should be disabled in the DMA Channel
Mux.
• Use explicit software re-activation. In this option, the DMA is configured to transfer the data using
both minor and major loops, but the processor is required to re-activate the channel (by writing to
the DMA registers) after every minor loop. For this option, the DMA channel should be disabled
in the DMA Channel Mux.
• Use a "always enabled" DMA source. In this option, the DMA is configured to transfer the data
using both minor and major loops, and the DMA Channel Mux does the channel re-activation. For
this option, the DMA channel should be enabled and pointing to an "always enabled" source. Note
that the re-activation of the channel can be continuous (DMA triggering is disabled) or can use the
DMA triggering capability. In this manner, it is possible to execute periodic transfers of packets of
data from one source to another, without processor intervention.
20.6
20.6.1
Initialization/Application Information
Reset
The reset state of each individual bit is shown within the Register Description section (See Section 20.3.1,
“Register Descriptions”). In summary, after reset, all channels are disabled and must be explicitly enabled
before use.
20.6.2
Enabling and Configuring Sources
Enabling a source with periodic triggering
1. Determine with which DMA channel the source will be associated. Note that only the first 4 DMA
channels have periodic triggering capability.
2. Clear the ENBL and TRIG bits of the DMA channel
3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be
enabled at this point
4. Configure the corresponding timer
5. Select the source to be routed to the DMA channel. Write to the corresponding CHCONFIG
register, ensuring that the ENBL and TRIG bits are set
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DMACHMUX
Example 1. Configure source #5 Transmit for use with DMA Channel 2, with periodic triggering capability
1.
2.
3.
4.
Write 0x00 to CHCONFIG2 (Base Address + 0x02)
Configure Channel 2 in the DMA, including enabling the channel
Configure a timer for the desired trigger interval
Write 0xC5 to CHCONFIG2 (Base Address + 0x02)
The following code example illustrates steps #1 and #4 above:
In File registers.h:
#define DMAMUX_BASE_ADDR
0xFC084000/* Example only ! */
/* Following example assumes char is 8-bits */
volatile unsigned char *CHCONFIG0 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG1 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG2 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG3 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG4 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG5 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG6 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG7 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG8 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG9 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG10= (volatile unsigned char *)
volatile unsigned char *CHCONFIG11= (volatile unsigned char *)
volatile unsigned char *CHCONFIG12= (volatile unsigned char *)
volatile unsigned char *CHCONFIG13= (volatile unsigned char *)
volatile unsigned char *CHCONFIG14= (volatile unsigned char *)
volatile unsigned char *CHCONFIG15= (volatile unsigned char *)
(DMAMUX_BASE_ADDR+0x0000);
(DMAMUX_BASE_ADDR+0x0001);
(DMAMUX_BASE_ADDR+0x0002);
(DMAMUX_BASE_ADDR+0x0003);
(DMAMUX_BASE_ADDR+0x0004);
(DMAMUX_BASE_ADDR+0x0005);
(DMAMUX_BASE_ADDR+0x0006);
(DMAMUX_BASE_ADDR+0x0007);
(DMAMUX_BASE_ADDR+0x0008);
(DMAMUX_BASE_ADDR+0x0009);
(DMAMUX_BASE_ADDR+0x000A);
(DMAMUX_BASE_ADDR+0x000B);
(DMAMUX_BASE_ADDR+0x000C);
(DMAMUX_BASE_ADDR+0x000D);
(DMAMUX_BASE_ADDR+0x000E);
(DMAMUX_BASE_ADDR+0x000F);
In File main.c:
#include "registers.h"
:
:
*CHCONFIG2 = 0x00;
*CHCONFIG2 = 0xC5;
Enabling a source without periodic triggering
1. Determine with which DMA channel the source will be associated. Note that only the first 4 DMA
channels have periodic triggering capability.
2. Clear the ENBL and TRIG bits of the DMA channel
3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be
enabled at this point
4. Select the source to be routed to the DMA channel. Write to the corresponding CHCONFIG
register, ensuring that the ENBL is set and the TRIG bit is cleared
Example 2. Configure source #5 Transmit for use with DMA Channel 2, with no periodic triggering capability.
1. Write 0x00 to CHCONFIG2 (Base Address + 0x02)
2. Configure Channel 2 in the DMA, including enabling the channel
3. Write 0x85 to CHCONFIG2 (Base Address + 0x02)
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DMACHMUX
The following code example illustrates steps #1 and #3 above:
In File registers.h:
#define DMAMUX_BASE_ADDR
0xFC084000/* Example only ! */
/* Following example assumes char is 8-bits */
volatile unsigned char *CHCONFIG0 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG1 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG2 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG3 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG4 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG5 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG6 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG7 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG8 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG9 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG10= (volatile unsigned char *)
volatile unsigned char *CHCONFIG11= (volatile unsigned char *)
volatile unsigned char *CHCONFIG12= (volatile unsigned char *)
volatile unsigned char *CHCONFIG13= (volatile unsigned char *)
volatile unsigned char *CHCONFIG14= (volatile unsigned char *)
volatile unsigned char *CHCONFIG15= (volatile unsigned char *)
(DMAMUX_BASE_ADDR+0x0000);
(DMAMUX_BASE_ADDR+0x0001);
(DMAMUX_BASE_ADDR+0x0002);
(DMAMUX_BASE_ADDR+0x0003);
(DMAMUX_BASE_ADDR+0x0004);
(DMAMUX_BASE_ADDR+0x0005);
(DMAMUX_BASE_ADDR+0x0006);
(DMAMUX_BASE_ADDR+0x0007);
(DMAMUX_BASE_ADDR+0x0008);
(DMAMUX_BASE_ADDR+0x0009);
(DMAMUX_BASE_ADDR+0x000A);
(DMAMUX_BASE_ADDR+0x000B);
(DMAMUX_BASE_ADDR+0x000C);
(DMAMUX_BASE_ADDR+0x000D);
(DMAMUX_BASE_ADDR+0x000E);
(DMAMUX_BASE_ADDR+0x000F);
In File main.c:
#include "registers.h"
:
:
*CHCONFIG2 = 0x00;
*CHCONFIG2 = 0x85;
Disabling a source
A particular DMA source may be disabled by not writing the corresponding source value into any of the
CHCONFIG registers. Additionally, some module specific configuration may be necessary. Please refer
to the appropriate section for more details.
Switching the source of a DMA Channel
1. Disable the DMA channel in the DMA and re-configure the channel for the new source
2. Clear the ENBL and TRIG bits of the DMA channel
3. Select the source to be routed to the DMA channel. Write to the corresponding CHCONFIG
register, ensuring that the ENBL and TRIG bits are set
Example 3. Switch DMA Channel 8 from source #5 transmit to source #7 transmit
1. In the DMA configuration registers, disable DMA channel 8 and re-configure it to handle the
transfers to peripheral slot 7. This example assumes channel 8 doesn’t have triggering capability.
2. Write 0x00 to CHCONFIG8 (Base Address + 0x08)
3. Write 0x87 to CHCONFIG8 (Base Address + 0x08). (In this example, setting the TRIG bit would
have no effect, due to the assumption that channels 8 does not support the periodic triggering
functionality).
The following code example illustrates steps #2 and #3 above:
In File registers.h:
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DMACHMUX
#define DMAMUX_BASE_ADDR
0xFC084000/* Example only ! */
/* Following example assumes char is 8-bits */
volatile unsigned char *CHCONFIG0 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG1 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG2 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG3 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG4 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG5 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG6 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG7 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG8 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG9 = (volatile unsigned char *)
volatile unsigned char *CHCONFIG10= (volatile unsigned char *)
volatile unsigned char *CHCONFIG11= (volatile unsigned char *)
volatile unsigned char *CHCONFIG12= (volatile unsigned char *)
volatile unsigned char *CHCONFIG13= (volatile unsigned char *)
volatile unsigned char *CHCONFIG14= (volatile unsigned char *)
volatile unsigned char *CHCONFIG15= (volatile unsigned char *)
(DMAMUX_BASE_ADDR+0x0000);
(DMAMUX_BASE_ADDR+0x0001);
(DMAMUX_BASE_ADDR+0x0002);
(DMAMUX_BASE_ADDR+0x0003);
(DMAMUX_BASE_ADDR+0x0004);
(DMAMUX_BASE_ADDR+0x0005);
(DMAMUX_BASE_ADDR+0x0006);
(DMAMUX_BASE_ADDR+0x0007);
(DMAMUX_BASE_ADDR+0x0008);
(DMAMUX_BASE_ADDR+0x0009);
(DMAMUX_BASE_ADDR+0x000A);
(DMAMUX_BASE_ADDR+0x000B);
(DMAMUX_BASE_ADDR+0x000C);
(DMAMUX_BASE_ADDR+0x000D);
(DMAMUX_BASE_ADDR+0x000E);
(DMAMUX_BASE_ADDR+0x000F);
In File main.c:
#include "registers.h"
:
:
*CHCONFIG8 = 0x00;
*CHCONFIG8 = 0x87;
20.6.3
Freezing in STOP and HALT mode
If a DMA capable peripheral is programmed to run on divided system clock, then do not configure
DMACHMUX to be frozen in STOP/HALT mode using the DMACHMUX PCTL register.
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Chapter 21
Video Encoder Wrapper
21.1
Introduction
Figure 218 shows the block diagram of video encoder.
The video encoder accepts either an ITU-BT656 like compatible video stream with embedded sync
signals, or a video stream with external vsync and href signals on its parallel interface. The encoder
downsamples the stream to 4:2:0 format, compresses it using JPEG encoding, and then stores it in the
output buffer.
Synchronizer receives the input video stream, and changes clocking to the ipg_video_clk (128 MHz). If
the input video stream is ITU-BT656 like compliant, it is fed to the sync extraction or decoder. The sync
extraction block extracts the ITU-BT656 like sync (FF-00-00), and sends the video to the processing
functions.
If the video stream is non ITU-BT656 like compliant, it does not go through the sync extraction block and
is directly fed to the third block.
Block 3 converts the 4:2:2 stream to a 4:2:0 stream by providing interpolation on the chroma components
of the stream.
Block 4 performs the reordering of the stream from scan line order to MCU block order.
After this, the stream is MJPEG encoded. The encoded stream is then written to a circular buffer SRAM.
Ext synch mode
1
pixclk
2
videoin
href
vsync
1
Syncho
-nizer
2
Sync
Extrac
tion
Int
synch
mode
4
3
Chroma
Down
sample
Data
Reorder
5
MJPEG
Encoder
6
Output
Buffer
Amba
Slave
Interface
7
Subchannel
Reception
1. pixclk is 80–96 MHz.
2. videoin data is YUV422 or ITU656 compliant stream.
Figure 218. Video encoder block diagram
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Video Encoder Wrapper
The block has the capability to send interrupt on the following conditions:
• Start of frame
• End of picture
• Pixel count mismatch in a line
• Line count error in a frame
• Protection bit error in decoder
• JPEG In stream received from JPEG SRAM
• Subchannel received
• Buffer filling alarm
• Configuration Error (from MJPEG Encoder)
21.1.1
•
•
•
•
•
Features
Baseline/extended sequential ISO/IEC 10918-1 JPEG encoder (8/12 bit)
Programmable huffman tables (2AC, 2DC) and quantization tables (4)
Embedded sync (ITU-BT656 like) or external synced input interface, supporting 422 video formats
Receives ‘embedded line’ information from sensor, containing all register settings, as ‘subchannel
information’ into dedicated SRAM.
Encoded stream is stored in SRAM output buffer memory, accessible over slave AHB bus.
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Video Encoder Wrapper
Block Diagram
Input Interface
Asynchronous
FIFO
href_ext
jpegout
vsync
pix_data_sync
MJPEG encoder
video_data_ext
External
sync
c_valid_ext
information
extraction y_valid_ext
block
sync_mode (select line)
Demux for
internal/
external
synced
data
data_decoder_skip
ipg_video_clk_sync
Clock
gating
cell
Decoder
(sync
information
extraction
for
embedded
sync
ITU 656
data_decoder
data)
MUX for
selection
between
external
and
internal
sync
MJPEG encoder memories
(DQT, DCT, CFG,
HUFFMAN FIFO and
HUFFMAN TABLE etc.)
ipg_video_clk
pixel data
data_valid
ipg_video_clk
href
JPEG Encoder
video_data_int
video_data_int
c_valid_int
c_valid_int
y_valid_int
y_valid_int
pixelk_we
Data or
pixel
data
AHB
slave
interface
Output buffer
(2048x32)
vsync_ext
pixel_rdy/
Pixel
clock
Output Interface
jpegout_we
21.2
Conversion from YUV422 to YUV420 format
hsync
hsync
vsync
vsync
LUMA
buffer
(10240x24)
Chroma
buffer
(10240x12)
Down
sample
buffer
(1280x12)
Figure 219. Video Encodder Wrapper Block Diagram
21.2.1
MJPEG Video Encoder
The MJPEG encoder is a third party IP, which performs 8/12 bit data encoding. The video encoder needs
to be programmed using the MJPEG encoder configuration registers. All the MJPEG control/status
registers are available for configuration through the Video Encoder Wrapper. The encoder will output
compressed data to the circular/output buffer which is an AHB slave to read by the Ethernet/DMA.
The MJPEG Encoder needs to be pre-configured to define the Huffman & Quantization tables, frame
format, length of restart interval etc. This information is provided to the MJPEG IP using its configuration
Interface.
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Video Encoder Wrapper
To implement this, the video encoder wrapper has a JPEGIn Buffer (256x32 bits). This buffer RAM needs
to be configured with the configuration stream prior to starting the MJPEG encoder. The RAM is accesible
through the IPS interface for writing. During the vertical blanking period, the core can configure this RAM
with the values required. The Video Encoder Wrapper also specifies JPEGIn offset address register, which
specifies the offset in the RAM from where the reading of configuration data shall start. The first byte is
taken from the address pointed to by JPEGIn Offset address register. Subsequent data bytes are from
subsequent addresses. The configuration stream is terminated using the EOI marker. Then the MJPEG is
configured to read in the configuration stream from the JPEGIn buffer. After the MJPEG Encoder reads
the configuration stream, the Jpeg IN stream IRQ interrupt is generated. This interrput can be cleared by
writing one to the clear bit.
21.2.2
MJPEG Operation Modes
Figure 220 shows the control flow implemented by the JPEG encoder.
After reset, the JPEG encoder enters idle mode. In the idle mode, access to the control and the status
registers is enabled. The MJPEG encoder exits the idle mode when the CONF or GO bit of the control
register are detected to be 1. The core then enters one of the operation’s mode. See Section 21.3.2.12,
“MODE”.
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Video Encoder Wrapper
AUTOCLR_
CONF=1
EOI Detected
CONFIG MODE
Y
CONF=1
Y
CONF=0
IDLE MODE
RESET
N
GO=1
N
Y
SINGLE-SCAN
ENCODING MODE
N
AUTOCLR_
GO=1
Y
GO=0
Figure 220. Global control flow (LP=SWR=0)
21.2.2.1
Configuration Mode
Configuration mode is entered after the idle mode, if the CONF bit of the MODE control-register is
detected to be 1. During the configuration mode, the core receives marker segments through the JPEGIn
interface.
Marker segments define the following:
• Huffman and Quantization tables (DQT and DHT marker segments)
• Frame format (SOF0)
• Length of the restart interval (DRI)
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•
•
Start of Scan (SOS)
Comment and application marker segments (COM and APP)
The DQT, DHT, SOF0, DRI and SOS marker segments are decoded and used for the self-configuration of
the core, while the COM and APP marker segments are internally stored so that they are available for
extracting in the JPEG stream whenever needed. Once configuration mode is completed, and if the
AUTOCLR_CONF bit of the CFG_MODE control register is 1, the CONF bit of the MODE control
register is automatically cleared.
If an error (illegal marker or corrupted marker segment) is detected during marker segments’ decoding,
the error is reported in the JPEG Stat 12 field description and the ConfigError output pin is asserted. In
order to continue working properly, a Software Reset command should be given via the control-register.
NOTE
After Soft reset (bit 30 in Status_config register) is asserted and released,
CAST registers need re-configuration. The wrapper registers need not be
re-configured once soft-reset is released, but all CAST configuration
registers like MODE, CFG_MODE, and so on need to be re-configured for
proper re-functioning of the video encoder sub-system.
The referenced marker segments must be packed in a configuration-stream. A configuration stream must
always start with a SOI marker and must always be terminated with an EOI marker. The configuration
stream may contain the rest of the marker segments reported in the table below.
Marker
Code
Description
SOI
FFD8h
Start of image
DQT
FFDBh
Define Quantization table(s)
DHT
FFC4h
Define Huffman table(s)
DRI
FFDDh
Define restart interval
SOF0
FFC0h
Baseline frame definition
SOF1
FFC1h
Extended Sequential frame definition
SOS
FFDAh
Start of scan
COM
FFFEh
Comment
APPn
FFE0h-FFEFh
Application segment, n=0...F
The configuration mode must be entered in one of the following cases:
1. After to perform encoding. In this case, the format of the configuration stream must be as follows:
SOI (Start Of Image)
APPn (Application Segment: Optional)
COM (Comment segment: Optional)
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DQT (Quantization Table(s) segment(s))1
SOF0 (Start Of Frame (JPEG Baseline) segment) (EXTSEQ=0) or
SOF1 (Start Of Frame (JPEG Extended) segment) (EXTSEQ=1)
DHT (Huffman Table(s) segment(s))
DRI (Restart Interval segment: Optional)
SOS (Start Of Scan segment(s))
EOI (End Of Image)
2. Whenever the frame format and/or the encoding options, as defined by the most recently decoded
DHT, DQT, SOF0, DRI and SOS marker segments, will change for the next frame or scan to be
encoded. In those cases, the configuration stream needs to contain only the marker segments that
need to be updated. So, for example if only the DQT marker needs to be updated, the configuration
stream can be:
SOI (Start Of Image)
DQT (Quantization Tables(s) segment(s))
EOI (End Of Image)
NOTE
Whenever the SOF0 is updated, the SOS marker must be updated too.
21.2.2.2
Encoding Mode
The MJPEG encoder will enter the single-scan encoding mode, if the control-register is configured so that:
CONF=0 and GO=1. As in all encoding modes, the core receives image samples on an MCU, raster scan
order via the Pixel-In interface and outputs a Baseline ISO/IEC 10918-1 JPEG stream via the Jpeg-Out
interface.
Figure 221 shows the control flow implemented under single-scan encoding mode. Specifically, the core
automatically outputs on the Jpeg-Out interface the marker segments that are not masked by the bits 0-7
of the control register (see Table 227). It then encodes the frame samples and outputs the entropy-coded
segments via the Jpeg-Out interface. See Section Table 239., “CFG_MODE field description”. After the
entire scan is encoded the core extracts the EOI marker and leaves the encoding mode.
To identify the end of an image (scan), the SOF0 (0 need to be an index) marker needs to define the image
geometry (Y-field > 0). Thus, the MJPEG Encoder apriori knows the number of samples to expect in each
scan and it just counts the incoming samples.
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Extract SOI
Extract Non-Masked
Marker Segments
Encode scan
Extract EOI
EXIT
Figure 221. Control flow under single-scan encoding mode
21.2.2.3
Rate Control operation
In principle there are two different set of methods of controlling the bit rate of a jpeg stream. One set of
methods is about controlling the output data peak bandwidth, and the other one is about controlling the
total size of the jpeg output stream. The first set of methods applies to bandwidth limited applications,
while the second one applies to storage limited applications.
The size based rate control gives superior results in terms of image quality but it can guarantee maximum
output rate only on a per frame basis. The size control set of methods have the add-on basic principle of
accumulating “unused threshold bits” from past DCT blocks (this happens in areas of the image which are
highly compressed) and then using these bits in the more demanding image areas, compensating thus the
quality around the whole image. Size based rate control needs to be done using software.
This version of the JPEG-E-X does not implement size based rate control; rather it implements bandwidth
based rate control.
The bandwidth based rate control is activated when one or both of the LUMTH and CHRTH control
registers are programmed with a value different than FFFF. This option of the implemented rate control is
to set a maximum number-of-bits threshold which applies uniformly to all DCT blocks. During encoding
each DCT block is prevented from producing more encoded bits than this threshold by zeroing out as many
as needed, if needed at all, quantized DCT coefficients in the Zig-Zag scan order.
One optimization of this method, implemented as a second option, is to use different thresholds between
Luminance and Chrominance DCT blocks. The core supports this by programming different values to the
LUMTH and CHRTH control registers. This option gives better results, in terms of image quality, since
the user can allocate different bandwidth between Luminance and Chrominance data. LUMTH and
CHRTH needs to be selected according to the read bandwidth of the output buffer. Thus, an overflow of
the circular output buffer can be avoided.
NOTE
In all cases proper initial selection of the quantization tables is a critical
factor for the resulting image quality after rate control.
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21.3
21.3.1
Memory Map and Register Definition
Memory Map
Table 227. Video Encoder memory map
Offset or Address
Video Encoder registers
Access
Section/Page
0x001
Status_config
RW
21.3.2.1/457
0x041
Picture_size
RW
21.3.2.2/459
0x08
Pixel_count
RW
21.3.2.3/460
0x0c1
Reserved
R
21.3.2.4/460
1
1
0x10
Dma_address
0x141
Dma_vstart_address
RW
21.3.2.5/461
0x181
Dma_vend_address
R
21.3.2.6/461
0x1C1
Dma_alarm_address
RW
21.3.2.7/462
0x201
Subchannel buffer start
RW
21.3.2.8/462
0x241
Jpeg in offset address
RW
21.3.2.9/463
Control registers
0x28
RC_REGS_SEL
W
21.3.2.10/463
0x2c
LUMTH
W
21.3.2.11/464
0x302
MODE
W
21.3.2.12/465
0x34
CFG_MODE
W
21.3.2.13/466
0x38
CHRTH
W
21.3.2.14/467
Status registers
0x40
JPEG stat 0
R
21.3.2.16/468
0x44
JPEG stat 1
R
21.3.2.17/468
0x48
JPEG stat 2
R
21.3.2.18/469
0x4C
JPEG stat 3
R
21.3.2.19/469
0x50
JPEG stat 4
R
21.3.2.20/470
0x54
JPEG stat 5
R
21.3.2.21/470
0x58
JPEG stat 6
R
21.3.2.22/471
0x5C
JPEG stat 7 (Not Used)
R
21.3.2.23/471
0x60
JPEG stat 8
R
21.3.2.24/472
0x64
JPEG stat 9
R
21.3.2.25/472
0x68
JPEG stat 10
R
21.3.2.26/473
0x6C
JPEG stat 11
R
21.3.2.27/473
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Table 227. Video Encoder memory map (continued)
Offset or Address
Video Encoder registers
Access
Section/Page
0x70
JPEG stat 12
R
21.3.2.28/474
0x74
JPEG stat 13
R
21.3.2.29/475
0x78
JPEG stat 14
R
21.3.2.30/475
0x7c
JPEG stat 15
R
21.3.2.31/476
Subchannel buffer space (256 bytes)
RW
—
0x1000–0x13ff
Jpeg in buffer space (1024 bytes)
RW
—
0x5000_0000–
0x5000_3FFF
circular buffer space. This does not reflect in IPS address
space. Instead this is AHB mapped address range.
RW
—
0x0200–0x02FF
1
The registers from offset 0x00 to 0x24 remains accessible if Video Encoder peripheral is frozen through ME_PCTL30
register in all the modes.
2 Registers 0x28 - 0x7c are resident in the MJPEG encoder but are mapped in Wrapper. The registers 0x28-0x38 are Write
Only through wrapper. We cannot read the reset values of these registers as well. However JPEG_encode CFG_MODE
register can be read from address 0x74.LUMTH can be read from 0x78.CHRTH can be read from 0x7c
NOTE
Video output buffer RAM inside Video Encoder should not be used as a
General Purpose system RAM.
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21.3.2
Register Descriptions
21.3.2.1
Status_config
0x00 status_config
0
1
read/write
2
3
4
5
6
7
R DMA
Vstart subch jpeg
len count Vend
txfer
irq an irq in irq err irq err irq irq
irq
Reset
9
10
11
12
13
14
15
DMA
subch
Vstart
Jpeg Len Count Vend error_
txfer
an irq
irq en
irq en irq en irq en irq en en
irq en
en
subch
len count Vend
Vstart
jpeg_
an irq
err irq err irq irq
irq clr
irq clr
clr
clr
clr
clear
W
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
error_ error_
subch
Subc code1 code2
_irq
buffer buffer Video annel
hann _irq
Sync
Href_ Vsync Pixel_
el error_ error_
W write restar encod data Mode Bit Width IN
Pol
_pol order
on
t
er on reque
start code1 cod21
st
point _ irq _ irq
clr
clr
Reset
0
0
0
0
0
0
0
0
0
0
1
1
0
Pixel
_cloc sw_re
k_pol set
arity
1
0
0
= Unimplemented or Reserved
Figure 222. status_config Register
Table 228. status_config Fields
Field
DMA txfer irq
Vstart irq
Subchannel
data irq
Description
DMA transfer request - given every time dma_address >= dma_alarm_address
Interrupt signalling the SOI marker of the MJPEG Encoder i.e. the MJPEG is configured for encoding.
Subchannel data received and ready for processor read.
Jpeg IN stream Request for JPEG In stream received from MJPEG encoder, and data provided from JPEGIn RAM.
irq
Line Len err irq Interrupt signalling mismatch between active line length and programmed line length
Line count err
irq
Interrupt signalling mismatch between active number of lines in an image and programmed number of
lines in the image
Interrupt signalling the completion of encoding of Current Frame. It is asserted at the detection of EOI
Vend irq
DMA txfer
irq_en
1’b1 : Interrupt is Enabled.
1’b0: Interrupt is Disabled.
Vstart irq_en
1’b1 : Interrupt is Enabled.
1’b0: Interrupt is Disabled.
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Table 228. status_config Fields
Field
Subchannel
data irq_en
Description
1’b1 : Interrupt is Enabled.
1’b0: Interrupt is Disabled.
Jpeg IN stream 1’b1 : Interrupt is Enabled.
irq_en
1’b0: Interrupt is Disabled.
Line Len err
irq_en
1’b1 : Interrupt is Enabled.
1’b0: Interrupt is Disabled.
Line count err
irq en
1’b1 : Interrupt is Enabled.
1’b0: Interrupt is Disabled.
Vend irq en
1’b1 : Interrupt is Enabled.
1’b0: Interrupt is Disabled.
Error En
1’b1 : Interrupt is Enabled.
1’b0: Interrupt is Disabled.
buffer_write_on 1: write to buffer enabled
0: write to buffer disabled
Note:- Bit will be open to be written by the software all the time, but active state of bit will be locked at
theSOI marker of the frame, and will be open to be changed again at the end of current frame encoding.
buffer_restart
1: dma_address will reload from dma_vstart_address at next SOI
0: dma_address will free-run, is not updated on next SOI
Bit clears automatically on dma_address reload.
Video_encoder 1: turn video encoder on
_on
0: video encoder off
Note:- Bit will be open to be written by the software all the time, but active state of state of bit will be
locked at the positive edge of vsync, and will be open to be changed again at the end of current frame
encoding.
Subchannel
data request
1: Request video in block to receive subchannel data
0: Do not request subchannel data.
Bit will auto-clear on reception of subchannel data.
After receiving subchannel data, Subchannel Data IRQ will be generated.
If no data is requested, interrupt is not generated.
Sync Mode
0: Hsync/Vsync external signals used for syncing
1: ITU-BT656-like embedded syncs
Bit Width In
00 : 8 bit
01 : 10 bit
10 : 12 bit
11 : Reserved, do not use
subchannel
start point
0: start counting pixels from the starting edge of vsync
1: start counting pixels from first valid pixel of frame
error code1 irq Interrupt signalling protection single bit error in decoder
error code2 irq Interrupt signalling protection double bit error in decoder
href_pol
Defines the active polarity of HREF signal.Applicable only for External Sync Mode
1’b1: HREF is active high
1’b0: HREF is active low
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Table 228. status_config Fields
Field
Description
vsync_pol
Defines the active polarity of VSYNC signal.Applicable only for External Sync Mode
1’b1: VSYNCis active high
1’b0: VSYNCis active low
pixel_order
Defines whether first chroma pixel or luma pixel will come in the camera input stream.Apllicable both for
internal & external sync modes.
1’b1: Chroma pixel first in YCbCr Stream
1’b0: Luma pixel first in YCbCr stream.
pixel_clock_pol Defines whether data is sampled on positive or negative edge of pixel clock
1’b1: data is sampled on positive edge of pixel clock
1’b0: data is sampled on negative edge of pixel clock
sw_rst
Initialises all flops of design on to a known state. Signal is active high.
Note: This bit must be cleared to exit reset state.
21.3.2.2
Picture_size
0x04 picture_size
read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
W
Reset
R
picture_vsize[10:4]
W
Reset
0
0
0
0
0
0
0
picture_hsize[10:5]
0
0
0
0
0
0
= Unimplemented or Reserved
T
Table 229. Picture size register fields
Field
Description
picture_hsize[10:5] Number of pixels in line, increments of 32. For example, if hsize is 256 then the value to be programmed is
'b001000. Number of pixels in a line should be divided by 32.
You must carefully provide number of lines in a pixel as multiples of 32.
picture_vsize[10:4] Number of lines in field, increments of 16.
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21.3.2.3
Pixel count
0x08 pixel_count
read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
R
W
Reset
R
pixel_count[8:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
T
Table 230. Pixel count register fields
Field
Description
pixel_count[8:0]
21.3.2.4
Number of pixels to be stored in subchannel RAM.
Dma_address
0x10 dma_address
0
1
read
2
3
4
5
6
R
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
dma_address[12:2]
W
Reset
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 223. dma_address Register
T
Table 231. dma_address Fields
Field
Description
dma_address[12:2] Address where the video encoder is currently writing in the output buffer.This can indicate the
current buffer fill level.
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21.3.2.5
Dma_vstart_address
0x14 dma_vstart_address
0
1
2
read/write
3
4
5
6
R
8
9
10
11
12
13
14
15
0
0
0
0
0
0
dma_vstart_address[12:2]
W
Reset
7
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 224. dma_vstart_address Register
T
Table 232. dma_vstart_address Fields
Field
Description
dma_vstart_addres Address where the write of next frame will start if buffer_restart bit is 1’b1.
s[12:2]
21.3.2.6
Dma_vend_address
0x18 dma_vend_address
read
Power PC
15
14
13
12
11
10
9
Conventional
16
17
18
19
20
21
22
R
8
7
6
5
4
3
2
1
0
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
dma_vend_address[12:2]
W
Reset
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 225. dma_vend_address Register
T
Table 233. dma_vend_address Fields
Field
Description
dma_vend_addres Belongs with vend interrupt. Address at which write of current frame ended.
s[12:2]
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21.3.2.7
Dma_alarm_address
0x1C dma_alarm_address
0
1
2
read/write
3
4
5
6
R
8
9
10
11
12
13
14
15
0
0
0
0
0
0
dma_alarm_address[12:2]
W
Reset
7
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 226. dma_alarm_address Register
T
Table 234. dma_alarm_address Fields
Field
Description
dma_alarm_addres When dma_address >= dma_alarm_address, alarm interrupt is generated.
s[12:2]
21.3.2.8
Subchannel buffer start
0x20 subchannel_buffer_start
0
1
2
3
read/write
4
5
6
7
8
9
R
10
11
12
13
14
15
subchannel_buffer_start[23:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Power PC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Conventional
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
R
subchannel_buffer_start[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Field
Description
subchannel_buff Subchannel buffer start addres. This specifies the number of pixel clocks after HREF/VSYNC from
er_start[23:0] where subchannel data starts arriving from camera.
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21.3.2.9
JPEG In Offset Address
0x24 jpeg_in_offset_address
read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
1
R
W
Reset
R
jpegin_data_offset[9:2]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Table 235. JPEG data in offset Fields
Field
Description
jpeg data in
offset[9:2]
This is a pointer in JPEG in buffer RAM where jpeg IN stream will be sourced next time MJPEG
encoder requests
21.3.2.10 RC_REGS_SEL
The RC_REGS_SEL control register is used as an indirect status register select. It selects between the two
sets of Rate-Control (RC) status registers, which are available for read at JPEG stat 14 and JPEG stat 15.
The RC_REGS_SEL register can be programmed with the values 0, 1 and 2. The corresponding set of
registers that will be available for read through status registers 14 and 15 is shown in the Table 236:
0x0028
R
write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
W
Reset
0
RC_REGS_
SEL
0
0
= Unimplemented or Reserved
Figure 227. RC_REGS_SEL control register
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Table 236. The RC_REGS_SEL control register
RC_REGS_SEL
Value
RC_REGS0
(JPEG stat 14)
RC_REGS1
(JPEG stat 15)
0
LUMATH
CHROMATH
1
LumaTruncH (Bits 31:16 of register
with total Truncated Bits of
Luminance blocks).
LumaTruncL (Bits 15:0 of register
with total Truncated Bits of
Luminance blocks).
2
ChromaTruncH (Bits 31:16 of
register with total Truncated Bits of
Chrominance blocks).
ChromaTruncL (Bits 15:0 of register
with total Truncated Bits of
Chrominance blocks).
21.3.2.11 LUMTH
This register is used with AC(0) Huffman Table. Huffman Tables must be assigned for Luminance
components in SOS marker segment accordingly. Maximum allowed programmed threshold value for
both registers is 0x03DF.
0x002C
R
write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
W
Reset
R
W
Reset
LUMTH
1
= Unimplemented or Reserved
Figure 228. LUMTH register
Table 237. LUMTH field description
Field
LUMTH
Description
Maximum number of bits threshold used in rate control of Luminance DCT blocks (the maximum
value is 0x03DF).
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Video Encoder Wrapper
21.3.2.12 MODE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
AUTOCLR_CONF
GO
CONF
EXTSEQ
R
write
AUTOCLR_GO
0x0030
SWR
LP
0
0
0
0
0
0
1
W
Reset
R
W
Reset
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 229. MODE register
Table 238. MODE field description
Field
LP
SWR
EXTSEQ
CONF
GO
AUTOCLR_CONF
AUTOCLR_GO
Description
Low Power
0 LP is disabled
1 The core enters low-power mode (all internal registers are frozen)
Soft Reset
0 SWR is not enabled
1 The core can be reset
Selector between Baseline and Extended Sequential mode of operation
0 Baseline mode is selected
1 Extended Sequential mode
Configuration. When 1 the core enters configuration mode
GO
0 GO is disabled
1 The core exits the idle mode
Auto clear CONF bit when the core exits from configuration mode
Auto clear GO bit when the core exits from its current encoding mode of operation
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Video Encoder Wrapper
21.3.2.13 CFG_MODE
write1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
MSOS
MDHT
MDQT
MDRI
MSOF0
R
0
MDNL
0x0034
1
1
1
1
1
1
Reset
0
0
0
0
0
0
1
1
MAPP
DICOM
W
MCOM
R
COMB_DHT
Reset
COMB_DQT
W
1
1
= Unimplemented or Reserved
Figure 230. CFG_MODE register
1
The register is Write only through wrapper. The reset values of this register cannot be read. However, the register can be read
from the address 0x74.
Table 239. CFG_MODE field description
Field
MSOF0
Description
Mask Start of Frame
0 No SOF0 segments are output by the core
1 SoF0 segments are output by the core
MDRI
Mask DRI
0 No DRI segments are output by the core
1 DRI segments are output by the core.
MDQT
Mask DQT
0 No DQT segments are output by the core
1 DQT segments are output by the core
MDHT
Mask DHT
0 No DHT segments are output by the core
1 DHT segments are output by the core
MSOS
Mask SOS
0 No SOS segments are output by the core
1 SOS segments are output by the core
MDNL
Mask DNL
0 No DNL segments are output by the core
1 DNL segments are output by the core
MAPP
Mask APP
0 No APP segments are output by the core
1 APP segments are output by the core
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Video Encoder Wrapper
Table 239. CFG_MODE field description
Field
Description
MCOM
Mask COM
0 No COM segments are output by the core
1 COM segments are output by the core
COMB_DQT
0 Transmits all Quantization Tables in one combined DQT segment to support EXIF 2.2 format
1 Do not transmit all Quantization Tables in one combined DQT segment to support EXIF 2.2 format
COMB_DHT
0 Transmits all Huffman Tables in one combined DHT segment to support EXIF 2.2 format
1 Do not transmits all Huffman Tables in one combined DHT segment to support EXIF 2.2 format
DICOM
0 Transmits SOF0 and SOS markers after DQT and DHT markers to support DICOM format
1 Do not transmits SOF0 and SOS markers after DQT and DHT markers to support DICOM format
21.3.2.14 CHRTH
This register is used with AC(1) Huffman Table. Huffman Tables must be assigned for Chrominance
components in SOS marker segment accordingly. Maximum allowed programmed threshold value for
both registers is 0x03DF.
0x0038
R
write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
W
Reset
R
W
Reset
CHRTH
1
= Unimplemented or Reserved
Table 240. CHRTH_SEL_ADDR field description
Field
Description
CHRTH
Maximum number of bits threshold used in rate control of Chrominance DCT blocks (the maximum
value is 0x03DF).
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Freescale Semiconductor
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Video Encoder Wrapper
21.3.2.15 Status registers
21.3.2.16 JPEG Stat 0
0x0040
Read
R
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
W
Reset
R
X
W
Reset
0
0
0
0
0
0
0
0
Figure 231. JPEG Stat 0 register
Table 241. JPEG STAT 0 field description
Field
Description
X
Image Width
21.3.2.17
JPEG Stat 1
0x0044
Read
R
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
W
Reset
R
Y
W
Reset
0
0
0
0
0
0
0
0
Figure 232. JPEG Stat 1 register
Table 242. JPEG Stat 1 field description
Field
Y
Description
Image Height
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Freescale Semiconductor
Video Encoder Wrapper
21.3.2.18 JPEG Stat 2
0x0048
R
Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
1
1
1
1
1
1
W
Reset
R
HMCU
W
Reset
0
0
0
0
1
1
1
1
1
Table 243. JPEG STAT 2 field description
Field
HMCU
Description
Number of MCUs in the current scan in horizontal direction
21.3.2.19 JPEG Stat 3
0x004C
R
Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Tq0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
W
Reset
R
VMCU
W
Reset
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 233. JPEG Stat 3
Table 244. JPEG STAT 3 field description
Field
VMCU
Description
Number of MCUs in the current scan in vertical direction
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Freescale Semiconductor
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Video Encoder Wrapper
21.3.2.20 JPEG Stat 4
0x0050
R
Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
W
Reset
R
C0
H0
V0
31
Tq0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 234. JPEG Stat 4 register
Table 245. JPEG Stat 4 field description
Field
Description
C0
Component identifier for scan component 0
H0
Horizontal sampling for scan component 0 (expected value for 4:2:0 = 2)
V0
Vertical sampling for scan component (expected value for 4:2:0 = 2)
Tq0
Quantization table identifier for scan component 0
21.3.2.21 JPEG Stat 5
0x0054
R
Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
W
Reset
R
C1
H1
V1
31
Tq1
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 235. JPEG Stat 5 register
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Video Encoder Wrapper
Table 246. JPEG Stat 5 field description
Field
Description
C1
Component identifier for scan component 1
H1
Horizontal sampling for scan component 1 (expected value for 4:2:0 = 1)
V1
Vertical sampling for scan component 1 (expected value for 4:2:0 = 1)
Tq1
Quantization table identifier for scan component 1
21.3.2.22 JPEG Stat 6
0x0058
R
Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
W
Reset
R
C2
H2
V2
31
Tq2
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 236. JPEG Stat 6 register
Table 247. JPEG Stat 6 field description
Field
Description
C2
Component identifier for scan component 2
H2
Horizontal sampling for scan component 2 (expected value for 4:2:0 = 1)
V2
Vertical sampling for scan component 2 (expected value for 4:2:0 = 1)
Tq2
Quantization table identifier for scan component 2
21.3.2.23 JPEG Stat 7
This register is not used.
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Freescale Semiconductor
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Video Encoder Wrapper
21.3.2.24 JPEG Stat 8
0x0060
R
Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
NF
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 237. JPEG Stat 8 register
Table 248. JPEG Stat 8 field description
Field
NF
Description
Number of components in frame (expected value for 4:2:0 = 3)
21.3.2.25 JPEG Stat 9
0x0064
R
Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
W
Reset
R
DRI
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 238. JPEG Stat 9 register
Table 249. JPEG Stat 9 field description
Field
DRI
Description
Restart interval
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Video Encoder Wrapper
21.3.2.26 JPEG Stat 10
0x0068
R
Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
W
Reset
R
Hmax
Vmax
NBMCU
Ns
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 239. JPEG Stat 10 register
Table 250. JPEG Stat 10 field description
Field
Description
Hmax
Maximum horizontal sampling factor in frame (expected value for 4:2:0 = 2)
Vmax
Maximum vertical sampling factor in frame (expected value for 4:2:0 = 2)
NBMCU
Number of blocks per MCU in current scan (expected value for 4:2:0 = 6)
Ns
Number of components in current scan (expected value for 4:2:0 = 3)
21.3.2.27 JPEG Stat 11
0x006C
R
Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
W
Reset
R
VHS3
VHS2
VHS1
VHS0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 240. JPEG Stat 11 register
MPC5604E Reference Manual, Rev. 5
Freescale Semiconductor
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Video Encoder Wrapper
Table 251. JPEG Stat 11 field description
Field
Description
VHS3
Number of blocks of the fourth component in MCU.
VHS2
Number of blocks of the third component in MCU.
VHS3 = VHS2 + V3 × H3 , when Ns = 4 (expected value for 4:2:0 = 0)
VHS2 = VHS1 + V2 × H2 , when Ns ≥ 3 (expected value for 4:2:0 = 6)
VHS1
Number of blocks of the second component in MCU.
VHS1 = VHS1 + V1 × H1 , when Ns ≥ 2 (expected value for 4:2:0 = 5)
VHS0
Number of blocks of the first component in MCU.
VHS0 = V0 × H0 , when Ns > 1 , VHS0 = 1 and Ns = 1 (expected value for 4:2:0 = 4)
21.3.2.28 JPEG Stat 12
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
SOF_E
SOS_E
DQT_E
DHT_E
DNL_E
DRI_E
APPn_E
COM_E
R
Read
SCANACTIVE
0x0070
CONFIFERROR
R
JPEGIN_RDY
Reset
PIXELIN_RDY
W
= Unimplemented or Reserved
Figure 241. JPEG Stat 12 register
Table 252. JPEG Stat 12 field description
Field
Description
SCANACTIVE
Indicates that core encodes entropy coded scan data
PIXELIN_RDY
Pixel input data ready: Core is ready to accept new pixel data
JPEGIN_RDY
JPEG stream input data ready: Core is ready to read new data on JPEG (0x1000:0x13ff)
CONFIGERROR
Configuration error indicator
SOF_E
SOF0 error: 1 when an error in SOF0 segment is detected
SOS_E
Scan error : 1 when an error in SOS segment is detected
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Video Encoder Wrapper
Table 252. JPEG Stat 12 field description
Field
Description
DQT_E
DQT error : 1 when an error in DQT segment is detected
DHT_E
DHT error : 1 when an error in DHT segment is detected
DNL_E
DNL error : 1 when an error in DNL segment is detected
DRI_E
DRI error : 1 when an error in DRI segment is detected
APPn_E
APPn error : 1 when an error in APPn segment is detected
COM_E
COM error : 1 when an error in COM segment is detected
21.3.2.29 JPEG Stat 13
0x0074
R
Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
1
1
1
1
1
1
W
Reset
R
CFG_MODE
W
Reset
0
0
0
0
0
0
1
1
1
= Unimplemented or Reserved
Figure 242. JPEG Stat 13 register
Table 253. JPEG Stat 13 field description
Field
CFG_MODE
Description
Programmed CFG_MODE control register. Allows to read back the value programmed to 0x34.
21.3.2.30 JPEG Stat 14
This register allows to read the values as selected by RC_REGS_SEL (at offset 0x28).
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Freescale Semiconductor
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Video Encoder Wrapper
0x0078
R
Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
W
Reset
R
RC_REGS0
W
Reset
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 243. JPEG Stat 14 register
21.3.2.31 JPEG Stat 15
This register allows to read the values as selected by RC_REGS_SEL at offset 0x28.
0x007C
R
Read
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
W
Reset
R
RC_REGS1
W
Reset
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 244. JPEG Stat 15 register
21.4
Functional Description
The video encoder receives the video data, at pixel clock from camera (vsync and href also in case of
external sync mode). This data is synchronised with ipg_video_clk with the help of asynchronous fifo, and
then this data is made to pass through Decoder block for sync extraction(for embedded sync). The data is
fed directly to the reordering logic, which downsamples the data from YUV422 to YUV420 data. This data
is fed to the MJPEG encoder in MCU 8*8 Blocks (4 Luma blocks then 2 Chroma blocks), which
compresses the JPEG Image and stores the data in a circular output buffer, from which the data can be read
via AHB Slave Interface.
MPC5604E Reference Manual, Rev. 5
21-476
Freescale Semiconductor
Video Encoder Wrapper
21.4.1
Input interface
The input interface accepts ITU-BT656 mode data with external href/vsync sync inputs. In case mode is
set to ITU-BT656, syncing is embedded per ITU-BT656 specification in the 8 most significant data lines.
In case href/vsync syncing is enabled, href and vsync signal are input. href is active when line pixel data
is valid, vsync goes active during the vertical blanking. The format on the pixel data is always YUV4:2:2.
Y pixels are alternated with U and V pixels.
The video interface can interface with 8-bit, 10-bit or 12-bit input. Input format is 8/10/12 bit,
programmable. Use of ITU-BT656-like syncing or href/vsync is programmable. In case 8 or 10 bit mode
is used, 4 or 2 bits on LSB side of input word are not used. When less than 12 bit is taken, the data is taken
from the most significant bits.
The input interface c