APT18M100B_S_C.pdf

APT18M100B
APT18M100S
1000V, 18A, 0.70Ω Max
N-Channel MOSFET
Power MOS 8™ is a high speed, high voltage N-channel switch-mode power MOSFET.
A proprietary planar stripe design yields excellent reliability and manufacturability. Low
switching loss is achieved with low input capacitance and ultra low Crss "Miller" capacitance. The intrinsic gate resistance and capacitance of the poly-silicon gate structure
help control slew rates during switching, resulting in low EMI and reliable paralleling,
even when switching at very high frequency. Reliability in flyback, boost, forward, and
other circuits is enhanced by the high avalanche energy capability.
TO
-24
7
D 3 PAK
APT18M100B
APT18M100S
D
Single die MOSFET
G
S
TYPICAL APPLICATIONS
FEATURES
• Fast switching with low EMI/RFI
• PFC and other boost converter
• Low RDS(on)
• Buck converter
• Ultra low Crss for improved noise immunity
• Two switch forward (asymmetrical bridge)
• Low gate charge
• Single switch forward
• Avalanche energy rated
• Flyback
• RoHS compliant
• Inverters
Absolute Maximum Ratings
Symbol
ID
Parameter
Unit
Ratings
Continuous Drain Current @ TC = 25°C
18
Continuous Drain Current @ TC = 100°C
12
A
IDM
Pulsed Drain Current
VGS
Gate-Source Voltage
±30
V
EAS
Single Pulse Avalanche Energy 2
1070
mJ
IAR
Avalanche Current, Repetitive or Non-Repetitive
9
A
1
68
Thermal and Mechanical Characteristics
Characteristic
Min
Typ
Max
Unit
W
PD
Total Power Dissipation @ TC = 25°C
625
RθJC
Junction to Case Thermal Resistance
0.20
RθCS
Case to Sink Thermal Resistance, Flat, Greased Surface
TJ,TSTG
Operating and Storage Junction Temperature Range
TL
Soldering Temperature for 10 Seconds (1.6mm from case)
WT
Package Weight
Torque
Mounting Torque ( TO-247 Package), 6-32 or M3 screw
0.11
-55
150
300
°C/W
°C
0.22
oz
6.2
g
10
in·lbf
1.1
N·m
050-8091 Rev C 2-2011
Symbol
Static Characteristics
TJ = 25°C unless otherwise specified
Symbol
Parameter
Test Conditions
Min
VBR(DSS)
Drain-Source Breakdown Voltage
VGS = 0V, ID = 250μA
1000
∆VBR(DSS)/∆TJ
Drain-Source On Resistance
VGS(th)
Gate-Source Threshold Voltage
∆VGS(th)/∆TJ
VGS = 10V, ID = 9A
3
Zero Gate Voltage Drain Current
IGSS
Gate-Source Leakage Current
Dynamic Characteristics
VDS = 1000V
VGS = 0V
Forward Transconductance
Ciss
Input Capacitance
Crss
Reverse Transfer Capacitance
Coss
Output Capacitance
Typ
Max
1.15
0.60
4
-10
0.70
5
TJ = 25°C
100
500
±100
TJ = 125°C
VGS = ±30V
Unit
V
V/°C
Ω
V
mV/°C
μA
nA
TJ = 25°C unless otherwise specified
Parameter
gfs
3
VGS = VDS, ID = 1mA
Threshold Voltage Temperature Coefficient
IDSS
Symbol
Reference to 25°C, ID = 250μA
Breakdown Voltage Temperature Coefficient
RDS(on)
APT18M100B_S
Min
Test Conditions
VDS = 50V, ID = 9A
VGS = 0V, VDS = 25V
f = 1MHz
Co(cr)
4
Effective Output Capacitance, Charge Related
Co(er)
5
Effective Output Capacitance, Energy Related
Typ
19
4845
65
405
Max
Unit
S
pF
165
VGS = 0V, VDS = 0V to 667V
85
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
td(on)
Turn-On Delay Time
Resistive Switching
Current Rise Time
VDD = 667V, ID = 9A
tr
td(off)
tf
Turn-Off Delay Time
150
26
70
22
20
75
19
VGS = 0 to 10V, ID = 9A,
VDS = 500V
RG = 4.7Ω 6 , VGG = 15V
Current Fall Time
nC
ns
Source-Drain Diode Characteristics
Symbol
IS
ISM
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 1
Test Conditions
MOSFET symbol
showing the
integral reverse p-n
junction diode
(body diode)
Diode Forward Voltage
ISD = 9A, TJ = 25°C, VGS = 0V
trr
Reverse Recovery Time
ISD = 9A 3
Qrr
Reverse Recovery Charge
Peak Recovery dv/dt
Typ
Max
Unit
18
A
G
VSD
dv/dt
Min
D
68
S
diSD/dt = 100A/μs, TJ = 25°C
ISD ≤ 9A, di/dt ≤1000A/μs, VDD = 800V,
TJ = 125°C
1.0
1080
24
V
ns
μC
10
V/ns
1 Repetitive Rating: Pulse width and case temperature limited by maximum junction temperature.
2 Starting at TJ = 25°C, L = 26.42mH, RG = 4.7Ω, IAS = 9A.
3 Pulse test: Pulse Width < 380μs, duty cycle < 2%.
050-8091 Rev C 2-2011
4 Co(cr) is defined as a fixed capacitance with the same stored charge as COSS with VDS = 67% of V(BR)DSS.
5 Co(er) is defined as a fixed capacitance with the same stored energy as COSS with VDS = 67% of V(BR)DSS. To calculate Co(er) for any value of
VDS less than V(BR)DSS, use this equation: Co(er) = -1.41E-8/VDS^2 + 2.48E-9/VDS + 4.81E-11.
6 RG is external gate resistance, not including internal gate resistance or gate driver impedance. (MIC4452)
Microsemi reserves the right to change, without notice, the specifications and information contained herein.
APT18M100B_S
60
V
GS
20
= 10V
T = 125°C
J
GS
40
30
TJ = 25°C
20
10
0
15
10
5V
5
TJ = 125°C
4.5V
TJ = 150°C
0
0
5
10
15
20
25
30
VDS(ON), DRAIN-TO-SOURCE VOLTAGE (V)
0
Figure 1, Output Characteristics
3.0
NORMALIZED TO
VGS = 10V @ 9A
2.5
VDS> ID(ON) x RDS(ON) MAX.
250μSEC. PULSE TEST
@ <0.5 % DUTY CYCLE
50
2.0
1.5
1.0
5
10
15
20
25
30
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 2, Output Characteristics
60
ID, DRAIN CURRENT (A)
RDS(ON), DRAIN-TO-SOURCE ON RESISTANCE
= 6, 7, 8 & 9V
V
TJ = -55°C
ID, DRIAN CURRENT (A)
ID, DRAIN CURRENT (A)
50
40
TJ = -55°C
TJ = 25°C
30
TJ = 125°C
20
10
0.5
0
0
-55 -25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C)
Figure 3, RDS(ON) vs Junction Temperature
0
1
2
3
4
5
6
7
8
VGS, GATE-TO-SOURCE VOLTAGE (V)
Figure 4, Transfer Characteristics
10,000
25
20
TJ = -55°C
C, CAPACITANCE (pF)
gfs, TRANSCONDUCTANCE
Ciss
TJ = 25°C
15
TJ = 125°C
10
1,000
100
Coss
5
Crss
VGS, GATE-TO-SOURCE VOLTAGE (V)
16
2
4
6
8
10
ID, DRAIN CURRENT (A)
Figure 5, Gain vs Drain Current
12
60
14
12
VDS = 240V
10
VDS = 600V
6
VDS = 960V
4
2
0
200
400
600
800
1000
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 6, Capacitance vs Drain-to-Source Voltage
ID = 9A
8
0
0
20 40 60 80 100 120 140 160 180 200
Qg, TOTAL GATE CHARGE (nC)
Figure 7, Gate Charge vs Gate-to-Source Voltage
50
40
TJ = 25°C
30
TJ = 150°C
20
10
0
0
0.2
0.4
0.6
0.8
1.0
1.2
VSD, SOURCE-TO-DRAIN VOLTAGE (V)
Figure 8, Reverse Drain Current vs Source-to-Drain Voltage
050-8091 Rev C 2-2011
0
10
ISD, REVERSE DRAIN CURRENT (A)
0
APT18M100B_S
100
100
IDM
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
IDM
10
13μs
100μs
1ms
1
Rds(on)
10ms
1
13μs
100μs
Rds(on)
Scaling for Different Case & Junction
Temperatures:
ID = ID(T = 25°C)*(TJ - TC)/125
DC line
0.1
10
100
1000
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 9, Forward Safe Operating Area
1ms
10ms
100ms
DC line
TJ = 150°C
TC = 25°C
1
100ms
TJ = 125°C
TC = 75°C
0.1
10
C
1
10
100
1000
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 10, Maximum Forward Safe Operating Area
0.20
D = 0.9
0.15
0.7
Note:
0.5
0.10
P DM
ZθJC, THERMAL IMPEDANCE (°C/W)
0.25
t1
t2
0.3
t1 = Pulse Duration
0.05
0
t
10-5
Duty Factor D = 1 /t2
Peak T J = P DM x Z θJC + T C
SINGLE PULSE
0.1
0.05
10-4
10-3
10-2
10-1
RECTANGULAR PULSE DURATION (seconds)
Figure 11. Maximum Effective Transient Thermal Impedance Junction-to-Case vs Pulse Duration
1.0
D3PAK Package Outline
TO-247 (B) Package Outline
15.49 (.610)
16.26 (.640)
5.38 (.212)
6.20 (.244)
Drai n
6.15 (.242) BSC
Drai n
(Heat Sink)
e3 100% Sn Plated
4.69 (.185)
5.31 (.209)
1.49 (.059)
2.49 (.098)
4.98 (.196)
5.08 (.200)
1.47 (.058)
1.57 (.062)
15.95 (.628)
16.05(.632)
Revised
4/18/95
20.80 (.819)
21.46 (.845)
1.04 (.041)
1.15(.045)
13.79 (.543)
13.99(.551)
13.41 (.528)
13.51(.532)
Revised
8/29/97
11.51 (.453)
11.61 (.457)
3.50 (.138)
3.81 (.150)
0.46 (.018)
0.56 (.022) {3 Plcs}
2.87 (.113)
3.12 (.123)
050-8091 Rev C 2-2011
4.50 (.177) Max.
0.40 (.016)
1.016(.040)
1.65 (.065)
2.13 (.084)
19.81 (.780)
20.32 (.800)
1.01 (.040)
1.40 (.055)
2.21 (.087)
2.59 (.102)
Gate
Drai n
Source
5.45 (.215) BSC
2-Plcs.
Dimensions in Millimeters and (Inches
)
0.020 (.001)
0.178 (.007)
2.67 (.105)
2.84 (.112)
1.27 (.050)
1.40 (.055)
1.22 (.048)
1.32 (.052)
1.98 (.078)
2.08 (.082)
5.45 (.215) BSC
{2 Plcs. }
Source
Drai n
Gate
Dimensions in Millimeters (Inches)
3.81 (.150)
4.06 (.160)
(Base of Lead)
Heat Sink (Drain)
and Leads
are Plated
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