NSC TP3406

TP3406
DASL Digital Adapter for Subscriber Loops
General Description
Features
The TP3406 is a complete monolithic transceiver for data
transmission on twisted pair subscriber loops. It is built on
National’s double poly microCMOS process, and requires
only a single a 5 Volt supply. Alternate Mark Inversion (AMI)
line coding, in which binary ‘1’s are alternately transmitted
as a positive pulse then a negative pulse, is used to ensure
low error rates in the presence of noise with lower emi radiation than other codes such as Bi-phase (Manchester).
Full-duplex transmission at 144 kb/s is achieved on a single
twisted wire pair using a burst-mode technique (Time Compression Multiplexed). Thus the device operates as an ISDN
‘U’ Interface for short loop applications, typically in a PBX
environment, providing transmission for 2 B channels and 1
D channel. On Ý24 cable, the range is up to 800 meters.
System timing is based on a Master/Slave configuration,
with the line card end being the Master which controls loop
timing and synchronisation. All timing sequences necessary
for loop activation and de-activation are generated on-chip.
Selection of Master and Slave mode operation is programmed via the Microwire Control Interface.
A 2.048 MHz clock, which may be synchronized to the system clock, controls all transmission-related timing functions.
Complete ISDN PBX 2-Wire Data Transceiver including:
Y 2 B plus D channel interface for PBX UÊ Interface
Y 144 kb/s full-duplex on 1 twisted pair using Burst Mode
Y Loop range up to 800 meters (Ý24AWG)
Y Alternate Mark Inversion coding with transmit filter and
scrambler for low emi radiation
Y Adaptive line equalizer
Y On-chip timing recovery, no external components
Y Standard TDM interface for B channels
Y Separate interface for D channel
Y 2.048 MHz master clock
Y Driver for line transformer
Y 4 loop-back test modes
Y Single a 5V supply
Y MICROWIRE TM compatible serial control interface
Y Applications in:
PBX Line Cards
Terminals
Regenerators
Y Available in 28-pin PLCC Package
Block Diagram
TL/H/11725 – 1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation
MICROWIRETM is a trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/H/11725
RRD-B30M115/Printed in U. S. A.
TP3406 DASL Digital Adapter for Subscriber Loops
November 1992
Connection Diagram
TP3406 Package Information
TL/H/11725 – 2
Order Number TP3406V
See NS Package Number V28A
Pin Descriptions
Name
GND
Description
Negative power supply pin, normally 0V. All
analog and digital signals are referred to this
pin.
VCC
Positive power supply input, which must be
a 5V g 5%.
The 2.048 MHz Master Clock input, which
requires a CMOS logic level clock input from
a stable source. Must be synchronous with
BCLK.
This pin is the 2.048 MHz Master Clock input, which requires either a crystal to be connected between this pin and XTAL2 or a
CMOS logic level clock from a stable source,
which must be synchronous with BCLK.
This pin is the output side of the oscillator
amplifier.
MCLK
MCLK/XTAL
XTAL2
MBS/FSC
BCLK
FSa
Name
FSb
Bx
In Master Mode, this pin is the Master Burst
Sync input, which may be clocked at 4 kHz
to synchronize Transmit bursts from a number of devices at the Master end only. The 4
kHz should be nominally a square wave signal. If not used leave this pin open. In Slave
mode, this pin is a short Frame Sync output,
suitable for driving another DASL in Master
Mode to provide a regenerator (i.e. range-extender) capability.
Bit Clock logic signal which determines the
data shift rate for B channel data on the digital interface side of the device. In Master
mode this pin is an input which may be any
multiple of 8 kHz from 256 kHz to
2.048 MHz, but must be synchronous with
MCLK. In Slave mode this pin is an output at
2.048 MHz.
Br
Digital output for B1 and B2 channel data
received from the line.
TSr/LSD
In Master mode only, this pin is an opendrain output which is normally high impedance but pulls low during both B channel active receive time slots. In Slave mode only,
this pin is an output which is normally high
impedance and pulls low when a valid line
signal is received.
Dx
Digital input for D channel data to be transmitted to the line; must be synchronous with
DCLK.
Dr
Digital output for D channel data received
from the line. Dr is a TRI-STATE output.
In Master mode this pin is an input for the
16 kHz serial shift clock for D channel data
on Dx and Dr, which should be synchronous
with BCLK. It may also be re-configured via
the Control Register to act as an enable input for clocking the D channel interface synchronized to BCLK. In Slave mode this is a
16 kHz clock output for D channel data.
DCLK/DEN
In Master mode only, this pin is the Transmit
Frame Sync pulse input, requiring a positive
edge to indicate the start of the active channel time for transmit B channel data into Bx;
FSa must be synchronous with BCLK and
MCLK. In Slave mode only, this pin is a digi-
Description
tal output pulse which indicates the 8-bit periods of the B1 channel data transfer at both
Bx and Br.
In Master mode only, this pin is the Receive
Frame Sync pulse input, requiring a positive
edge to indicate the start of the active channel time of the device for receive B channel
data out from Br; FSb must be synchronous
with BCLK and MCLK. In Slave mode only,
this pin is a digital output pulse which indicates the 8-bit periods of the B2 channel
data transfer at both Bx and Br.
Digital input for B1 and B2 channel data to
be transmitted to the line; must be synchronous with BCLK.
*Crystal specifications: 2.048 MHz parallel resonant, RS s 100X with a
20 pF load. Crystal tolerance should be g 75 ppm for aging and temperature.
2
LINE TRANSMIT SECTION
Pin Descriptions (Continued)
Name
CI
CO
CCLK
MICROWIRE control channel serial data input.
MICROWIRE control channel serial data output.
Clock input for the MICROWIRE control
channel.
CS
Chip Select input which enables the MICROWIRE control channel data to be shifted in
and out when pulled low. When high, this pin
inhibits the MICROWIRE interface.
INT
Interrupt output, a latched output signal
which is normally high-impedance and goes
low to indicate a change of status of the loop
transmission system. This latch is cleared
when the Status Register is read by the microprocessor.
Lo
Transmit AMI signal output to the line transformer. This pin is capable of driving a load
impedance t 60X.
Receive AMI signal input from the line transformer. This is a high impedance input.
Li
Alternate Mark Inversion (AMI) line coding is used on the
DASL because of its spectral efficiency and null dc energy
content. All transmitted bits, excluding the start bit, are
scrambled by a 9-bit scrambler to provide good spectral
spreading with a strong timing content. The scrambler feedback polynomial is:
x9 a x5 a 1.
Description
Pulse shaping is obtained by means of a raised cosine
switched-capacitor filter, in order to limit rf energy and
crosstalk while minimizing inter-symbol interference (isi).
Figure 3 shows the pulse shape at the Lo output, while a
template for the typical power spectrum transmitted to the
line with random data is shown in Figure 4 .
The line-driver output, Lo, is designed to drive a transformer
through a capacitor and termination resistor. A 1:1 transformer, terminated in 100X, results in a signal amplitude of
typically 1.3V pk-pk on the line. Over-voltage protection
must be included in the interface circuit.
LINE RECEIVE SECTION
The front-end of the receive section consists of a continuous anti-alias filter followed by a switched-capacitor lowpass filter designed to limit the noise bandwidth with minimum intersymbol interference. To correct pulse attenuation
and distortion caused by the transmission line an AGC circuit and first-order equalizer adapt to the received pulse
shape, thus restoring a ‘‘flat’’ channel response with maximum received eye opening over a wide spread of cable
attenuation characteristics.
From the equalized output a DPLL (Digital Phase-Locked
Loop) recovers a low-jitter clock for optimum sampling of
the received symbols. The MCLK input provides the reference clock for the DPLL at 2.048 MHz. At the Master end of
the loop this reference is the network clock (BCLK), which
controls all transmit functions; the DPLL clock is used only
for received data sampling. At the Slave end, however, a
2.048 MHz crystal is required to generate a stable local oscillator which is used as a reference by the DPLL to run both
the receive and transmit sides of the DASL device.
Following detection of the recovered symbols, the received
data is de-scrambled by the same x9 a x5 a 1 polynomial
and presented to the digital system interface circuit.
When the device is de-activated, a Line-Signal Detect circuit
remains powered-up to detect the presence of incoming
bursts if the far-end starts to activate the loop. From a
‘‘cold’’ start, acquisition of bit timing and equalizer convergence with random scrambled data takes approximately
25 ms at each end of the loop. Full loop burst synchronization is achieved approximately 50 ms after the ‘‘activate’’
command at the originating end.
Functional Description
POWER-UP/POWER-DOWN CONTROL
Following the initial application of power, the DASL enters
the power-down (de-activated) state, in which all the internal
circuits are inactive and in a low power state except for the
line-signal detect circuit and the necessary bias circuit; the
line output Lo is in a low impedance state and all digital
outputs are inactive. All bits in the Control Register powerup initially set to ‘0’, so that the device always initializes as
the Master end. Thus, at the Slave end, a control word must
be written through the MICROWIRE port to select Slave
mode. While powered-down, the Line-Signal Detect circuits
in both Master and Slave devices continually monitor the
line, to enable loop transmission to be initiated from either
end.
To power-up the device and initiate activation, bit C6 in the
Control Register must be set high. Setting C6 low de-activates the loop and powers-down the device, see Table I.
TABLE I. Master Mode Burst
Sync Control (TP3401 Only)
MBS/FSc
Pin I/P
at Master
C6
State
Don’t Care
0
Pull up this pin
to a 5V through
a resistor
4 kHz
1
1
Action
Powered-down, Line-Signal
Detect active
Powered-up, sending bursts
synchronized to FSa
Powered-up, sending bursts
synchronized to MBS
3
Functional Description (Continued)
TL/H/11725 – 3
FIGURE 3. Typical AMI Waveform at Lo
TL/H/11725 – 4
FIGURE 4. Typical AMI Transmit Spectrum Measured at LO Output (With RBW e 100 Hz).
TL/H/11725 – 5
FIGURE 5. Burst Mode Timing on the Line
4
Functional Description (Continued)
flexibility. On the B channel interface, phase skew between
transmit and receive directions may be accommodated at
the Master end since separate frame sync inputs, Fsa and
Fsb, are provided. Each of these synchronizes a counter
which gates the transfer of B1 and B2 channels in consecutive time-slots across the digital interface; since the counters are edge-synchronized the duration of the Fs input signals may vary from a single-bit pulse to a square-wave. The
serial shift rate is determined by the BCLK input, and may
be any frequency from 256 kHz to 2.048 MHz, as shown in
Figure 6.
At the Slave end, both Fsa and Fsb are outputs. Fsa goes
high for 8 cycles of BCLK coincident with the 8 bits of the
B1 channel in both Transmit and Receive directions. Fsb
goes high for the next 8 cycles of BCLK, which are coincident with the 8 bits of the B2 channel in both Transmit and
Receive directions. BCLK is also an output at 2.048 MHz,
the serial data shift rate, as shown in Figure 7. Data may be
exchanged between the B1 and B2 channels as it passes
through the device, by setting Control bit C0 e 1. An additional Frame Sync output, FSc, is provided to enable a regenerator to be built by connecting a DASL in Slave Mode
to a DASL in Master Mode. The FSc output from the Slave
directly drives the FSa and FSb inputs on the Master.
D channel information, being packet-mode, requires no synchronizing input. This interface consists of the transmit data
input, Dx, receive data output, Dr, and 16 kHz serial shift
clock DCLK, which is an input at the Master end and an
output at the Slave end. Data shifts into Dx on falling edges
of DCLK and out from Dr on rising edges, as shown in Figure 11. DCLK should be Synchronous with BCLK.
An alternative function of the DCLK/DEN pin allows Dx and
Dr to be clocked at the same rate as BCLK at the Master
end only. By setting bit C1 in the Control Register to a 1,
DCLK/DEN becomes an input for an enabling pulse to gate
2 cycles of BCLK for shifting the 2 D bits per frame. Thus, at
the Master end, the D channel bits can be interfaced to a
TDM bus and assigned to a time-slot (the same time-slot for
both transmit and receive), as shown in Figure 12.
BURST MODE OPERATION
For full-duplex operation over a single twisted-pair, burst
mode timing is used, with the line-card (exchange) end of
the link acting as the timing Master.
Each burst from the Master consists of the B1, B2 and D
channel data from 2 consecutive frames combined in the
format shown in Figure 5 . During transmit bursts the Master’s receiver input is inhibited to avoid disturbing the adaptive circuits. The Slave’s receiver is enabled at this time and
it synchronizes to the start bit of the burst, which is always
an unscrambled ‘1’ (of the opposite polarity to the last ‘1’
sent in the previous burst). When the Slave detects that 36
bits following the start bit have been received, it disables the
receiver input, waits 6 line symbol periods to match the other end settling guard time, and then begins to transmit its
burst back towards the Master, which by this time has enabled its receiver input. The burst repetition rate is thus
4 kHz, which can either free-run or be locked to a synchronizing signal at the Master end by means of the MBS input
(See Figure 10 ). In the latter case, with all Master-end
transmitters in a system synchronized together, near-end
crosstalk between pairs in the same cable binder may be
eliminated, with a consequent increase in signal-to-noise ratio (SNR).
ACTIVATION AND LOOP SYNCHRONIZATION
Activation (i.e. power-up and loop synchronization) is typically completed in 50 ms and may be initiated from either
end of the loop. If the Master is activating the loop, it sends
normal bursts of scrambled ‘1’s, which are detected by the
Slave’s line-signal detect circuit, causing it to set C0 e 1 in
the Status Register, and pull the INT pin low. Pin 6, the LSD
pin, also pulls low. To proceed with Activation, the device
must be powered up by writing to the Control Register with
C6 e 1. The Slave then replies with bursts of scrambled
‘1’s synchronized to received bursts, and the flywheel circuit
at each end searches for 4 consecutive correctly formatted
receive bursts to acquire full loop synchronization. Each receiver indicates when it is correctly in sync with received
bursts by setting the C1 bit in the Status Register high and
pulling INT low.
To activate the loop from the Slave end, bit C6 in the Control Register must be set high, which will power-up the device and begin transmission of alternate bursts i.e., the burst
repetition rate is 2 kHz, not 4 kHz. At this point the Slave is
running from its local oscillator and is not receiving any sync
information from the Master. When the Master’s line-signal
detect circuit recognizes this ‘‘wake-up’’ signal, the Master
is activated and begins to transmit bursts, synchronized, as
normal, to the MBS or FSa input with a 4 kHz repetition rate.
This enables the Slave’s receiver to correctly identify burst
timing from the Master and to re-synchronize its own burst
transmissions to those it receives. The flywheel circuits then
acquire full loop sync as described earlier.
Loop synchronization is considered to be lost if the flywheel
finds 4 consecutive receive burst ‘‘windows’’ (i.e. where a
receive burst should have arrived based on timing from previous bursts) do not contain valid bursts. At this point bit C1
in the Status Register is set low, the INT output is set low
and the receiver searches to re-acquire loop sync.
CONTROL INTERFACE
A serial interface, which can be clocked independently from
the B and D channel system interfaces, is provided for microprocessor control of various functions on the DASL device. All data transfers consist of a single byte shifted into
the Control Register via CI simultaneous with a single byte
shifted out from the Status Register via CO, see Figure 13 .
Data shifts in to CI on rising edges of CCLK and out from
CO on falling edges when CS is pulled low for 8 cycles of
CCLK. An Interrupt output, INT goes low to alert the microprocessor whenever a change in one of the status bits, C1
and/or C0 has occurred. This latched output is cleared high
following the first CCLK pulse when CS is low. No interrupt
is generated when status bit C2 (bipolar violation) goes high,
however. This bit is set whenever 1 or more violations of the
AMI coding rule is received, and cleared everytime the CS is
pulsed. Statistics on the line bit error rate can be accumulated by regularly polling this bit.
When reading the CO pin, data is always clocked into the
Control Register; therefore the CI data word should repeat
the previous instruction if no change to the device mode is
intended.
DIGITAL SYSTEM INTERFACE
The digital system interface on the DASL separates B and D
channel information onto different pins to provide maximum
Figure 13 shows the timing for this interface, and Table II
lists the control functions and status indicators.
5
Functional Description (Continued)
TABLE II. Control and Status Register Functions
Bit
C7
C6
C5
C4
C3
C2
C1
C0
State
0
Control Register Function
Status Register Function
Master Mode
Read Back C7 from Control Register
1
Slave Mode
Read Back C7 from Control Register
0
Deactivate and Power Down
Read Back C6 from Control Register
1
Power Up and Activate
Read Back C6 from Control Register
0
Normal Through Connection
Read Back C5 from Control Register
1
Loopback to Digital Interface
Read Back C5 from Control Register
0
Normal Through Connection
Read Back C4 from Control Register
1
Loopback B1 a B2 a D to Line (Note 1)
Read Back C4 from Control Register
0
Normal Through Connection
Read Back C3 from Control Register
1
Loopback B1 Only to Line (Note 1)
Read Back C3 from Control Register
0
Normal Through Connection
No Error
1
Loopback B2 Only to Line (Note 1)
Bipolar Violation Since Last READ (Note 2)
0
DCLK/DEN pin e 16 kHz Clock
Out-Of-Sync
1
DCLK/DEN pin e D Channel Enable (Note 3)
Loop In-Sync and Activation Complete
0
B1/B2 Channels Direct
No Line Signal at Receiver Input
1
B1/B2 Channels Exchanged
Line Signal Present at Receiver Input
Note 1: Receive data active.
Note 2: After the device is in sync.
Note 3: In Master mode only.
Note 4: C7 is the first bit clocked in and out of the device.
Timing Diagrams
TL/H/11725 – 6
FIGURE 6. B Channel Interface Timing: Master Mode
6
Timing Diagrams (Continued)
TL/H/11725 – 7
FIGURE 7. B Channel Interface Timing: Slave Mode
Typical Applications
TL/H/11725 – 8
FIGURE 8. Typical Application for Slave End
Note 1: The TP3076 Programmable Combos also must be connected to the MICROWIRE interface.
Note 2: Only necessary if a mechanical Hookswitch is connected to the NMI input of the HPC.
Note 3: Crystal load capacitors include board and trace capacitance. Oscillator frequency can be checked by measuring the BCLK output frequency when slave
mode part is in digital loopback.
7
Typical Applications (Continued)
TL/H/11725 – 9
FIGURE 9. Typical Application for Master End
Timing Diagrams (Continued)
TL/H/11725 – 10
FIGURE 10. B Channel Interface Timing Details
8
Timing Diagrams (Continued)
TL/H/11725 – 11
TL/H/11725 – 12
FIGURE 11. D Channel Interface Timing (Master and Slave Modes, C1 e 0)
TL/H/11725 – 13
FIGURE 12. D Channel Interface Timing (Master Mode only, C1 e 1)
9
FIGURE 13. Control Interface Timing
TL/H/11725 – 14
Timing Diagrams (Continued)
10
Absolute Maximum Ratings
Storage Temperature Range
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
VCC to GND
Voltage at Li, Lo
Voltage at any Digital Input
b 65§ C to a 150§ C
Current at Lo
g 100 mA
Current at any Digital Output
Lead Temperature (Soldering, 10 sec.)
ESD (Human Body Model)
7V
VCC a 1V to VSSb1V
VCC a 1V to VSSb1V
g 50 mA
300§ C
2000V
Electrical Characteristics Unless otherwise noted, limits printed in bold characters are guaranteed for VCC e
5.0V g 5% and TA e 0§ C to a 70§ C by correlation with 100% electrical testing at VCC e 5.0V and TA e 25§ C. All other limits
are assured by correlation with other production tests and/or product design and characterization. Typical characteristics are
specified at VCC e 5.0V and TA e 25§ C. All digital signals are referenced to GND.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DIGITAL INTERFACES
VIL
Input Low Voltage
All Digital Inputs (not MCLK)
VIH
Input High Voltage
All Digital Inputs (not MCLK)
VOL
Output Low Voltage
IL e 1 mA
VOH
Output High Voltage
IL e b1 mA
IIM
Input Current at MBS/FSc
GND k VIN k VCC
II
Input Current
IOZ
Output Current in
High Impedance
State (TRI-STATEÉ)
0.7
2.2
V
V
0.4
V
b 600
10
mA
Any Other Digital Input, GND k VIN k VCC
b 10
10
mA
Br, INT, TSr, CO, Dr
GND k VOUT k VCC
b 10
10
mA
2.4
V
LINE INTERFACES
RLi
Input Resistance
0V k Li k 5.0V
CLLo
Load Capacitance
CLLo from Lo to GND.
50
RO
Output Resistance
at Lo
Load e 60X in Series with 2 mF to GND
VDC
Mean d.c. Voltage
at Lo
Load e 60X in Series with 2 mF to GND
kX
100
pF
3.0
X
2.0
V
POWER DISSIPATION
ICC0
Power Down Current
ICC1
Power Up Current (Activated)
1.3
Load at Lo e 200X in Series with 2 mF to
GND (in Master Mode)
2.5
mA
20
mA
TRANSMISSION PERFORMANCE
Transmit Pulse Amplitude at Lo
RL e 200X in Series with 2 mF to GND
Input Pulse Amplitude at Li
Timing Recovery Jitter
g 1.1
g 250
BCLK at Slave Relative to MCLK at Master
11
Vpk
mVpk
100
ns pk-pk
Timing Characteristics
Unless otherwise noted: VCC e a 5V g 5%, TA e 0§ C to 70§ C. Typical characteristics are specified at VCC e 5V, TA e 25§ C.
All signals are referenced to GND.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
MASTER CLOCK INPUT SPECIFICATIONS
FMCK
Master Clock Frequency
2.048
Master Clock Tolerance
Measured Relative to the Slave MCLK
Master Clock Input Jitter
2.048 MHz Input, 18 kHz k f k 200 kHz
tWMH,
tWML
Clock Pulse Width
Hi & Low for MCLK
VIH e VCC b 0.5V
VIL e 0.5V
tMR,
tMF
Rise and Fall Time
of MCLK
Used as a Logic Input
b 100
MHz
a 100
ppm
200
ns pk-pk
190
ns
15
ns
B CHANNEL INTERFACE (Figure 10)
FBCK
Bit Clock Frequency
Master Mode Only
tWBH,
tWBL
Clock Pulse Width
Hi & Low for BCLK
VIH e 2.2V
VIL e 0.7V
2.048
MHz
tBR,
tBF
Rise and Fall Time
of BCLK
Master Mode requirement for BCLK
Source
tSFB
Set-Up Time, FSa and
FSb to BCLK Low
Master Mode Only
tHCFL
Hold Time, BCLK Low to
FSa and FSb Low
Master Mode Only
tWBH
tWBL
Output Pulse Width
High and Low for BCLK
Slave Mode Only
Load e 2 LSTTL Inputs Plus 50 pF
tDCF
Delay Time, BCLK High to
FSa, FSb and FSc Transitions
Slave Mode Only
Load e 2 LSTTL Inputs Plus 50 pF
tSBC
Set Up Time, BX Valid
to BCLK Low
30
ns
tHCB
Hold Time, BCLK Low to
BX Invalid
50
ns
tDCB
Delay Time, BCLK High
to Br Valid
Load e 2 LSTTL Inputs Plus 100 pF
tDCBZ
Delay Time, BCLK Low to
Br High-Impedance
Slave Mode Only
tDCT
Delay Time, BCLK High
to TSr Low
Load e 2 LSTTL Inputs Plus 100 pF
tDCTZ
Delay Time, BCLK Low to
TSr High-Impedance
tSMBC
Set-Up Time, MBS
to BCLK Low (Note 1)
Master Mode Only
tWMBH
Width of MBS Input
High
Master Mode Only
190
ns
15
70
ns
100
ns
195
ns
115
60
60
Note 1: MBS transitions may occur anywhere in the Frame, and require no specific relationship to FSa or FSb.
12
ns
60
ns
160
ns
220
ns
180
ns
185
ns
ns
125
ms
Timing Characteristics (Continued)
Unless otherwise noted: VCC e a 5V g 5%, TA e 0§ C to 70§ C. Typical characteristics are specified at VCC e 5V, TA e 25§ C.
All signals are referenced to GND.
Symbol
Parameter
Conditions
Min
Max
Units
D CHANNEL INTERFACE (Figure 11 & 12)
tSDDC
Set Up Time, DX
Valid to DCLK Low
100
ns
tHCD
Hold Time, DCLK Low
to DX Invalid
100
ns
tDDCD
Delay Time, DCLK High to
Dr Data Valid
Load e 100 pF
a 2 LSTTL Inputs
tSDCB
Set-Up Time, DCLK
Transitions to BCLK High
Master Mode
Only
50
ns
tHBDC
Hold Time, BCLK High
to DCLK Transitions
Master Mode
Only
50
ns
tSDCF
Set-Up Time, DCLK
Transitions to FSa HIgh
Master Mode
Only
70
ns
tDDED
Delay Time, DEN High
to Dr Valid
Load e 100 pF a
2 LSTTL Inputs
tSDEB
Set-Up Time, DEN to
BCLK Low
tSDBC
220
200
ns
ns
100
ns
Set-Up Time, Dx
to BCLK Low
50
ns
tHBCD
Hold Time, BCLK
Low to Dx Invalid
50
ns
tDBCD
Delay Time, BCLK
High to Dr Valid
tDCDZ
Delay Time, DEN
Low to Dr High Impedance
Load e 100 pF
a 2 LSSTL Inputs
190
ns
140
ns
CONTROL INTERFACE (Figure 13)
tCH
CCLK High Duration
250
ns
tCL
CCLK Low Duration
250
ns
tSIC
Setup Time, CI
Valid to CCLK High
100
ns
tHCI
Hold Time, CCLK High
to CI Invalid
0
ns
tSSC
Setup Time from CS
Low to CCLK High
200
ns
tHCS
Hold Time from CCLK
Low to CS
10
ns
tDCO
Delay Time from CCLK Low
to C0 Data Valid
Load e 100 pF
a 2 LSTTL Inputs
tDSO
Delay Time from CS
Low to CO Valid
1st Bit Only
tDSZ
tDCI
150
ns
100
ns
Delay Time from CS High
to CO High Impedance
100
ns
Delay Time from CCLK1
High to INT High Impedance
120
ns
13
Definitions and Timing Conventions
DEFINITIONS
VIH
VIL
VIH is the d.c. input level above which
an input level is guaranteed to appear
as a logical one. This parameter is to
be measured by performing a functional test at reduced clock speeds and
nominal timing, (i.e. not minimum setup
and hold times or output strobes), with
the high level of all driving signals set
to VIH and maximum supply voltages
applied to the device.
VIL is the d.c. input level below which
an input level is guaranteed to appear
as a logical zero to the device. This parameter is measured in the same manner as VIH but with all driving signal low
levels set to VIL and minimum supply
voltages applied to the device.
VOH
VOH is the minimum d.c. output level to
which an output placed in a logical one
state will converge when loaded at the
maximum specified load current.
VOL
VOL is the maximum d.c. output level to
which an output placed in a logical zero
state will converge when loaded at the
maximum specified load current.
Threshold Region
The threshold region is the range of input voltages between VIL and VIH.
Valid Signal
A signal is Valid if it is in one of the
valid logic states, (i.e. above VIH or below VIL). In timing specifications, a signal is deemed valid at the instant it enters a valid state.
Invalid Signal
A signal is Invalid if it is not in a valid
logic state, i.e. when it is in the threshold region between VIL and VIH. In timing specifications, a signal is deemed
invalid at the instant it enters the
threshold region.
TIMING CONVENTIONS
For the purpose of this timing specification the following
conventions apply:
Input Signals
All input signals may be characterized
as: VL e 0.4V, VIH e 2.4V, tR k 10 ns,
tF k 10 ns.
Period
The period of clock signal is designated at tPxx where xx represents the
mnemonic of the clock signal being
specified.
14
Rise Time
Rise times are designated at tRyy,
where yy represents a mnemonic of
the signal whose rise time is being
specified. tRyy is measured from VIL to
VIH.
Fall Time
Fall times are designated as tFyy,
where yy represents a mnemonic of
the signal whose fall time is being
specified. tFyy is measured from VIH to
VIL.
Pulse Width High
The high width is designated as tWzzH,
where zz represents the mnemonic of
the input or output signal whose pulse
width is being specified. High pulse
widths are measured from VIH to VIH.
Pulse Width Low
The low pulse width is designed as
tWzzL, where zz represents the mnemonic of the input or output signal
whose pulse width is being specified.
Low pulse widths are measured from
VIL to VIL.
Setup Time
Setup times are designated as tSwwxx,
where ww represents the mnemonic of
the input signal whose setup time is being specified relative to a clock or
strobe input represented by mnemonic
xx. Setup times are measured from the
ww Valid to xx Invalid.
Hold Time
Hold times are designated as tHxxww,
where ww represents the mnemonic of
the input signal whose hold time is being specified relative to a clock or
strobe input represented by mnemonic
xx. Hold times are measured from xx
Valid to ww invalid.
Delay Time
Delay times are designated as tDxxyy [
lHlL], where xx represents the mnemonic of the input reference signal and
yy represents the mnemonic of the output signal whose timing is being specified relative to xx. The mnemonic may
optionally be terminated by an H or L to
specifiy the high going or low going
transition of the output signal. Maximum delay times are measured from xx
Valid to yy Valid. Minimum delay times
are measured from xx Valid to yy invalid. This parameter is tested under the
load conditions specified in the Conditions column of the Timing Specification section of this data sheet.
15
TP3406 DASL Digital Adapter for Subscriber Loops
Physical Dimensions inches (millimeters)
Plastic Chip Carrier (V)
Order Number TP3406V
NS Package Number V28A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
National Semiconductor
Corporation
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Europe
Fax: (a49) 0-180-530 85 86
Email: cnjwge @ tevm2.nsc.com
Deutsch Tel: (a49) 0-180-530 85 85
English Tel: (a49) 0-180-532 78 32
Fran3ais Tel: (a49) 0-180-532 93 58
Italiano Tel: (a49) 0-180-534 16 80
National Semiconductor
Hong Kong Ltd.
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
National Semiconductor
Japan Ltd.
Tel: 81-043-299-2309
Fax: 81-043-299-2408
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.